Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 1 | /************************************************************************** |
| 2 | * |
| 3 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 4 | * All Rights Reserved. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the |
| 8 | * "Software"), to deal in the Software without restriction, including |
| 9 | * without limitation the rights to use, copy, modify, merge, publish, |
| 10 | * distribute, sub license, and/or sell copies of the Software, and to |
| 11 | * permit persons to whom the Software is furnished to do so, subject to |
| 12 | * the following conditions: |
| 13 | * |
| 14 | * The above copyright notice and this permission notice (including the |
| 15 | * next paragraph) shall be included in all copies or substantial portions |
| 16 | * of the Software. |
| 17 | * |
| 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 19 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 20 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 21 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 22 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 23 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 24 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 25 | * |
| 26 | **************************************************************************/ |
| 27 | |
Brian Paul | ecadb51 | 2008-09-18 15:17:05 -0600 | [diff] [blame] | 28 | #include "glapi/glapi.h" |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 29 | |
| 30 | #include "i830_context.h" |
| 31 | #include "i830_reg.h" |
| 32 | #include "intel_batchbuffer.h" |
| 33 | #include "intel_regions.h" |
Dave Airlie | f75843a | 2008-08-24 17:59:10 +1000 | [diff] [blame] | 34 | #include "intel_tris.h" |
Eric Anholt | 2c30fd8 | 2009-04-09 18:30:12 -0700 | [diff] [blame] | 35 | #include "intel_fbo.h" |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 36 | #include "tnl/t_context.h" |
| 37 | #include "tnl/t_vertex.h" |
| 38 | |
| 39 | #define FILE_DEBUG_FLAG DEBUG_STATE |
| 40 | |
| 41 | static GLboolean i830_check_vertex_size(struct intel_context *intel, |
| 42 | GLuint expected); |
| 43 | |
| 44 | #define SZ_TO_HW(sz) ((sz-2)&0x3) |
| 45 | #define EMIT_SZ(sz) (EMIT_1F + (sz) - 1) |
| 46 | #define EMIT_ATTR( ATTR, STYLE, V0 ) \ |
| 47 | do { \ |
| 48 | intel->vertex_attrs[intel->vertex_attr_count].attrib = (ATTR); \ |
| 49 | intel->vertex_attrs[intel->vertex_attr_count].format = (STYLE); \ |
| 50 | intel->vertex_attr_count++; \ |
| 51 | v0 |= V0; \ |
| 52 | } while (0) |
| 53 | |
| 54 | #define EMIT_PAD( N ) \ |
| 55 | do { \ |
| 56 | intel->vertex_attrs[intel->vertex_attr_count].attrib = 0; \ |
| 57 | intel->vertex_attrs[intel->vertex_attr_count].format = EMIT_PAD; \ |
| 58 | intel->vertex_attrs[intel->vertex_attr_count].offset = (N); \ |
| 59 | intel->vertex_attr_count++; \ |
| 60 | } while (0) |
| 61 | |
| 62 | |
| 63 | #define VRTX_TEX_SET_FMT(n, x) ((x)<<((n)*2)) |
| 64 | #define TEXBIND_SET(n, x) ((x)<<((n)*4)) |
| 65 | |
| 66 | static void |
Roland Scheidegger | a188ba4 | 2007-07-29 18:04:28 +0200 | [diff] [blame] | 67 | i830_render_prevalidate(struct intel_context *intel) |
| 68 | { |
| 69 | } |
| 70 | |
| 71 | static void |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 72 | i830_render_start(struct intel_context *intel) |
| 73 | { |
| 74 | GLcontext *ctx = &intel->ctx; |
| 75 | struct i830_context *i830 = i830_context(ctx); |
| 76 | TNLcontext *tnl = TNL_CONTEXT(ctx); |
| 77 | struct vertex_buffer *VB = &tnl->vb; |
| 78 | DECLARE_RENDERINPUTS(index_bitset); |
| 79 | GLuint v0 = _3DSTATE_VFT0_CMD; |
| 80 | GLuint v2 = _3DSTATE_VFT1_CMD; |
| 81 | GLuint mcsb1 = 0; |
| 82 | |
| 83 | RENDERINPUTS_COPY(index_bitset, tnl->render_inputs_bitset); |
| 84 | |
| 85 | /* Important: |
| 86 | */ |
| 87 | VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr; |
| 88 | intel->vertex_attr_count = 0; |
| 89 | |
| 90 | /* EMIT_ATTR's must be in order as they tell t_vertex.c how to |
| 91 | * build up a hardware vertex. |
| 92 | */ |
| 93 | if (RENDERINPUTS_TEST_RANGE(index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX)) { |
| 94 | EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_4F_VIEWPORT, VFT0_XYZW); |
| 95 | intel->coloroffset = 4; |
| 96 | } |
| 97 | else { |
| 98 | EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_3F_VIEWPORT, VFT0_XYZ); |
| 99 | intel->coloroffset = 3; |
| 100 | } |
| 101 | |
| 102 | if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_POINTSIZE)) { |
| 103 | EMIT_ATTR(_TNL_ATTRIB_POINTSIZE, EMIT_1F, VFT0_POINT_WIDTH); |
| 104 | } |
| 105 | |
| 106 | EMIT_ATTR(_TNL_ATTRIB_COLOR0, EMIT_4UB_4F_BGRA, VFT0_DIFFUSE); |
| 107 | |
| 108 | intel->specoffset = 0; |
| 109 | if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_COLOR1) || |
| 110 | RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_FOG)) { |
| 111 | if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_COLOR1)) { |
| 112 | intel->specoffset = intel->coloroffset + 1; |
| 113 | EMIT_ATTR(_TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR, VFT0_SPEC); |
| 114 | } |
| 115 | else |
| 116 | EMIT_PAD(3); |
| 117 | |
| 118 | if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_FOG)) |
| 119 | EMIT_ATTR(_TNL_ATTRIB_FOG, EMIT_1UB_1F, VFT0_SPEC); |
| 120 | else |
| 121 | EMIT_PAD(1); |
| 122 | } |
| 123 | |
| 124 | if (RENDERINPUTS_TEST_RANGE(index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX)) { |
| 125 | int i, count = 0; |
| 126 | |
| 127 | for (i = 0; i < I830_TEX_UNITS; i++) { |
| 128 | if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_TEX(i))) { |
| 129 | GLuint sz = VB->TexCoordPtr[i]->size; |
| 130 | GLuint emit; |
| 131 | GLuint mcs = (i830->state.Tex[i][I830_TEXREG_MCS] & |
| 132 | ~TEXCOORDTYPE_MASK); |
| 133 | |
| 134 | switch (sz) { |
| 135 | case 1: |
| 136 | case 2: |
| 137 | emit = EMIT_2F; |
| 138 | sz = 2; |
| 139 | mcs |= TEXCOORDTYPE_CARTESIAN; |
| 140 | break; |
| 141 | case 3: |
| 142 | emit = EMIT_3F; |
| 143 | sz = 3; |
| 144 | mcs |= TEXCOORDTYPE_VECTOR; |
| 145 | break; |
| 146 | case 4: |
| 147 | emit = EMIT_3F_XYW; |
| 148 | sz = 3; |
| 149 | mcs |= TEXCOORDTYPE_HOMOGENEOUS; |
| 150 | break; |
| 151 | default: |
| 152 | continue; |
| 153 | }; |
| 154 | |
| 155 | |
| 156 | EMIT_ATTR(_TNL_ATTRIB_TEX0 + i, emit, 0); |
| 157 | v2 |= VRTX_TEX_SET_FMT(count, SZ_TO_HW(sz)); |
| 158 | mcsb1 |= (count + 8) << (i * 4); |
| 159 | |
| 160 | if (mcs != i830->state.Tex[i][I830_TEXREG_MCS]) { |
| 161 | I830_STATECHANGE(i830, I830_UPLOAD_TEX(i)); |
| 162 | i830->state.Tex[i][I830_TEXREG_MCS] = mcs; |
| 163 | } |
| 164 | |
| 165 | count++; |
| 166 | } |
| 167 | } |
| 168 | |
| 169 | v0 |= VFT0_TEX_COUNT(count); |
| 170 | } |
| 171 | |
| 172 | /* Only need to change the vertex emit code if there has been a |
| 173 | * statechange to a new hardware vertex format: |
| 174 | */ |
| 175 | if (v0 != i830->state.Ctx[I830_CTXREG_VF] || |
| 176 | v2 != i830->state.Ctx[I830_CTXREG_VF2] || |
| 177 | mcsb1 != i830->state.Ctx[I830_CTXREG_MCSB1] || |
| 178 | !RENDERINPUTS_EQUAL(index_bitset, i830->last_index_bitset)) { |
| 179 | int k; |
| 180 | |
| 181 | I830_STATECHANGE(i830, I830_UPLOAD_CTX); |
| 182 | |
| 183 | /* Must do this *after* statechange, so as not to affect |
| 184 | * buffered vertices reliant on the old state: |
| 185 | */ |
| 186 | intel->vertex_size = |
| 187 | _tnl_install_attrs(ctx, |
| 188 | intel->vertex_attrs, |
| 189 | intel->vertex_attr_count, |
| 190 | intel->ViewportMatrix.m, 0); |
| 191 | |
| 192 | intel->vertex_size >>= 2; |
| 193 | |
| 194 | i830->state.Ctx[I830_CTXREG_VF] = v0; |
| 195 | i830->state.Ctx[I830_CTXREG_VF2] = v2; |
| 196 | i830->state.Ctx[I830_CTXREG_MCSB1] = mcsb1; |
| 197 | RENDERINPUTS_COPY(i830->last_index_bitset, index_bitset); |
| 198 | |
| 199 | k = i830_check_vertex_size(intel, intel->vertex_size); |
| 200 | assert(k); |
| 201 | } |
| 202 | } |
| 203 | |
| 204 | static void |
| 205 | i830_reduced_primitive_state(struct intel_context *intel, GLenum rprim) |
| 206 | { |
| 207 | struct i830_context *i830 = i830_context(&intel->ctx); |
| 208 | GLuint st1 = i830->state.Stipple[I830_STPREG_ST1]; |
| 209 | |
| 210 | st1 &= ~ST1_ENABLE; |
| 211 | |
| 212 | switch (rprim) { |
| 213 | case GL_TRIANGLES: |
| 214 | if (intel->ctx.Polygon.StippleFlag && intel->hw_stipple) |
| 215 | st1 |= ST1_ENABLE; |
| 216 | break; |
| 217 | case GL_LINES: |
| 218 | case GL_POINTS: |
| 219 | default: |
| 220 | break; |
| 221 | } |
| 222 | |
| 223 | i830->intel.reduced_primitive = rprim; |
| 224 | |
| 225 | if (st1 != i830->state.Stipple[I830_STPREG_ST1]) { |
| 226 | INTEL_FIREVERTICES(intel); |
| 227 | |
| 228 | I830_STATECHANGE(i830, I830_UPLOAD_STIPPLE); |
| 229 | i830->state.Stipple[I830_STPREG_ST1] = st1; |
| 230 | } |
| 231 | } |
| 232 | |
| 233 | /* Pull apart the vertex format registers and figure out how large a |
| 234 | * vertex is supposed to be. |
| 235 | */ |
| 236 | static GLboolean |
| 237 | i830_check_vertex_size(struct intel_context *intel, GLuint expected) |
| 238 | { |
| 239 | struct i830_context *i830 = i830_context(&intel->ctx); |
| 240 | int vft0 = i830->current->Ctx[I830_CTXREG_VF]; |
| 241 | int vft1 = i830->current->Ctx[I830_CTXREG_VF2]; |
| 242 | int nrtex = (vft0 & VFT0_TEX_COUNT_MASK) >> VFT0_TEX_COUNT_SHIFT; |
| 243 | int i, sz = 0; |
| 244 | |
| 245 | switch (vft0 & VFT0_XYZW_MASK) { |
| 246 | case VFT0_XY: |
| 247 | sz = 2; |
| 248 | break; |
| 249 | case VFT0_XYZ: |
| 250 | sz = 3; |
| 251 | break; |
| 252 | case VFT0_XYW: |
| 253 | sz = 3; |
| 254 | break; |
| 255 | case VFT0_XYZW: |
| 256 | sz = 4; |
| 257 | break; |
| 258 | default: |
| 259 | fprintf(stderr, "no xyzw specified\n"); |
| 260 | return 0; |
| 261 | } |
| 262 | |
| 263 | if (vft0 & VFT0_SPEC) |
| 264 | sz++; |
| 265 | if (vft0 & VFT0_DIFFUSE) |
| 266 | sz++; |
| 267 | if (vft0 & VFT0_DEPTH_OFFSET) |
| 268 | sz++; |
| 269 | if (vft0 & VFT0_POINT_WIDTH) |
| 270 | sz++; |
| 271 | |
| 272 | for (i = 0; i < nrtex; i++) { |
| 273 | switch (vft1 & VFT1_TEX0_MASK) { |
| 274 | case TEXCOORDFMT_2D: |
| 275 | sz += 2; |
| 276 | break; |
| 277 | case TEXCOORDFMT_3D: |
| 278 | sz += 3; |
| 279 | break; |
| 280 | case TEXCOORDFMT_4D: |
| 281 | sz += 4; |
| 282 | break; |
| 283 | case TEXCOORDFMT_1D: |
| 284 | sz += 1; |
| 285 | break; |
| 286 | } |
| 287 | vft1 >>= VFT1_TEX1_SHIFT; |
| 288 | } |
| 289 | |
| 290 | if (sz != expected) |
| 291 | fprintf(stderr, "vertex size mismatch %d/%d\n", sz, expected); |
| 292 | |
| 293 | return sz == expected; |
| 294 | } |
| 295 | |
| 296 | static void |
| 297 | i830_emit_invarient_state(struct intel_context *intel) |
| 298 | { |
| 299 | BATCH_LOCALS; |
| 300 | |
Eric Anholt | de80eee | 2009-08-04 11:28:26 -0700 | [diff] [blame] | 301 | BEGIN_BATCH(29, IGNORE_CLIPRECTS); |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 302 | |
| 303 | OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD); |
| 304 | OUT_BATCH(0); |
| 305 | |
| 306 | OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD); |
| 307 | OUT_BATCH(0); |
| 308 | |
| 309 | OUT_BATCH(_3DSTATE_DFLT_Z_CMD); |
| 310 | OUT_BATCH(0); |
| 311 | |
| 312 | OUT_BATCH(_3DSTATE_FOG_MODE_CMD); |
| 313 | OUT_BATCH(FOGFUNC_ENABLE | |
| 314 | FOG_LINEAR_CONST | FOGSRC_INDEX_Z | ENABLE_FOG_DENSITY); |
| 315 | OUT_BATCH(0); |
| 316 | OUT_BATCH(0); |
| 317 | |
| 318 | |
| 319 | OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD | |
| 320 | MAP_UNIT(0) | |
| 321 | DISABLE_TEX_STREAM_BUMP | |
| 322 | ENABLE_TEX_STREAM_COORD_SET | |
| 323 | TEX_STREAM_COORD_SET(0) | |
| 324 | ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(0)); |
| 325 | OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD | |
| 326 | MAP_UNIT(1) | |
| 327 | DISABLE_TEX_STREAM_BUMP | |
| 328 | ENABLE_TEX_STREAM_COORD_SET | |
| 329 | TEX_STREAM_COORD_SET(1) | |
| 330 | ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(1)); |
| 331 | OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD | |
| 332 | MAP_UNIT(2) | |
| 333 | DISABLE_TEX_STREAM_BUMP | |
| 334 | ENABLE_TEX_STREAM_COORD_SET | |
| 335 | TEX_STREAM_COORD_SET(2) | |
| 336 | ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(2)); |
| 337 | OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD | |
| 338 | MAP_UNIT(3) | |
| 339 | DISABLE_TEX_STREAM_BUMP | |
| 340 | ENABLE_TEX_STREAM_COORD_SET | |
| 341 | TEX_STREAM_COORD_SET(3) | |
| 342 | ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(3)); |
| 343 | |
| 344 | OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM); |
| 345 | OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(0)); |
| 346 | OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM); |
| 347 | OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(1)); |
| 348 | OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM); |
| 349 | OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(2)); |
| 350 | OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM); |
| 351 | OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(3)); |
| 352 | |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 353 | OUT_BATCH(_3DSTATE_VERTEX_TRANSFORM); |
| 354 | OUT_BATCH(DISABLE_VIEWPORT_TRANSFORM | DISABLE_PERSPECTIVE_DIVIDE); |
| 355 | |
| 356 | OUT_BATCH(_3DSTATE_W_STATE_CMD); |
| 357 | OUT_BATCH(MAGIC_W_STATE_DWORD1); |
| 358 | OUT_BATCH(0x3f800000 /* 1.0 in IEEE float */ ); |
| 359 | |
| 360 | |
| 361 | OUT_BATCH(_3DSTATE_COLOR_FACTOR_CMD); |
| 362 | OUT_BATCH(0x80808080); /* .5 required in alpha for GL_DOT3_RGBA_EXT */ |
| 363 | |
| 364 | ADVANCE_BATCH(); |
| 365 | } |
| 366 | |
| 367 | |
| 368 | #define emit( intel, state, size ) \ |
Eric Anholt | a04b632 | 2008-01-10 10:48:05 -0800 | [diff] [blame] | 369 | intel_batchbuffer_data(intel->batch, state, size, IGNORE_CLIPRECTS ) |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 370 | |
| 371 | static GLuint |
Michel Dänzer | 2af613e | 2007-11-30 11:40:06 +0100 | [diff] [blame] | 372 | get_dirty(struct i830_hw_state *state) |
| 373 | { |
| 374 | return state->active & ~state->emitted; |
| 375 | } |
| 376 | |
| 377 | static GLuint |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 378 | get_state_size(struct i830_hw_state *state) |
| 379 | { |
Michel Dänzer | 2af613e | 2007-11-30 11:40:06 +0100 | [diff] [blame] | 380 | GLuint dirty = get_dirty(state); |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 381 | GLuint sz = 0; |
| 382 | GLuint i; |
| 383 | |
| 384 | if (dirty & I830_UPLOAD_INVARIENT) |
| 385 | sz += 40 * sizeof(int); |
| 386 | |
Eric Anholt | de80eee | 2009-08-04 11:28:26 -0700 | [diff] [blame] | 387 | if (dirty & I830_UPLOAD_RASTER_RULES) |
| 388 | sz += sizeof(state->RasterRules); |
| 389 | |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 390 | if (dirty & I830_UPLOAD_CTX) |
| 391 | sz += sizeof(state->Ctx); |
| 392 | |
| 393 | if (dirty & I830_UPLOAD_BUFFERS) |
| 394 | sz += sizeof(state->Buffer); |
| 395 | |
| 396 | if (dirty & I830_UPLOAD_STIPPLE) |
| 397 | sz += sizeof(state->Stipple); |
| 398 | |
| 399 | for (i = 0; i < I830_TEX_UNITS; i++) { |
| 400 | if ((dirty & I830_UPLOAD_TEX(i))) |
| 401 | sz += sizeof(state->Tex[i]); |
| 402 | |
| 403 | if (dirty & I830_UPLOAD_TEXBLEND(i)) |
| 404 | sz += state->TexBlendWordsUsed[i] * 4; |
| 405 | } |
| 406 | |
| 407 | return sz; |
| 408 | } |
| 409 | |
| 410 | |
| 411 | /* Push the state into the sarea and/or texture memory. |
| 412 | */ |
| 413 | static void |
Eric Anholt | 8517079 | 2008-01-14 11:03:05 -0800 | [diff] [blame] | 414 | i830_emit_state(struct intel_context *intel) |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 415 | { |
| 416 | struct i830_context *i830 = i830_context(&intel->ctx); |
| 417 | struct i830_hw_state *state = i830->current; |
Dave Airlie | f75843a | 2008-08-24 17:59:10 +1000 | [diff] [blame] | 418 | int i, count; |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 419 | GLuint dirty; |
Dave Airlie | f75843a | 2008-08-24 17:59:10 +1000 | [diff] [blame] | 420 | dri_bo *aper_array[3 + I830_TEX_UNITS]; |
| 421 | int aper_count; |
Brian Paul | 6b9c144 | 2009-03-12 17:13:00 -0600 | [diff] [blame] | 422 | GET_CURRENT_CONTEXT(ctx); |
| 423 | BATCH_LOCALS; |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 424 | |
| 425 | /* We don't hold the lock at this point, so want to make sure that |
Eric Anholt | 8517079 | 2008-01-14 11:03:05 -0800 | [diff] [blame] | 426 | * there won't be a buffer wrap between the state emits and the primitive |
| 427 | * emit header. |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 428 | * |
| 429 | * It might be better to talk about explicit places where |
| 430 | * scheduling is allowed, rather than assume that it is whenever a |
| 431 | * batchbuffer fills up. |
Michel Dänzer | 2af613e | 2007-11-30 11:40:06 +0100 | [diff] [blame] | 432 | * |
Eric Anholt | 8517079 | 2008-01-14 11:03:05 -0800 | [diff] [blame] | 433 | * Set the space as LOOP_CLIPRECTS now, since that's what our primitives |
| 434 | * will be emitted under. |
Michel Dänzer | 2af613e | 2007-11-30 11:40:06 +0100 | [diff] [blame] | 435 | */ |
Dave Airlie | f75843a | 2008-08-24 17:59:10 +1000 | [diff] [blame] | 436 | intel_batchbuffer_require_space(intel->batch, |
| 437 | get_state_size(state) + INTEL_PRIM_EMIT_SIZE, |
Eric Anholt | 8517079 | 2008-01-14 11:03:05 -0800 | [diff] [blame] | 438 | LOOP_CLIPRECTS); |
Dave Airlie | 96338dd | 2008-04-16 16:37:13 +1000 | [diff] [blame] | 439 | count = 0; |
| 440 | again: |
Dave Airlie | f75843a | 2008-08-24 17:59:10 +1000 | [diff] [blame] | 441 | aper_count = 0; |
Dave Airlie | 96338dd | 2008-04-16 16:37:13 +1000 | [diff] [blame] | 442 | dirty = get_dirty(state); |
| 443 | |
Dave Airlie | f75843a | 2008-08-24 17:59:10 +1000 | [diff] [blame] | 444 | aper_array[aper_count++] = intel->batch->buf; |
Dave Airlie | 96338dd | 2008-04-16 16:37:13 +1000 | [diff] [blame] | 445 | if (dirty & I830_UPLOAD_BUFFERS) { |
Dave Airlie | f75843a | 2008-08-24 17:59:10 +1000 | [diff] [blame] | 446 | aper_array[aper_count++] = state->draw_region->buffer; |
Xiang, Haihao | b4bf9ac | 2008-10-21 10:30:39 +0800 | [diff] [blame] | 447 | if (state->depth_region) |
| 448 | aper_array[aper_count++] = state->depth_region->buffer; |
Dave Airlie | 96338dd | 2008-04-16 16:37:13 +1000 | [diff] [blame] | 449 | } |
Dave Airlie | f75843a | 2008-08-24 17:59:10 +1000 | [diff] [blame] | 450 | |
Dave Airlie | 96338dd | 2008-04-16 16:37:13 +1000 | [diff] [blame] | 451 | for (i = 0; i < I830_TEX_UNITS; i++) |
| 452 | if (dirty & I830_UPLOAD_TEX(i)) { |
| 453 | if (state->tex_buffer[i]) { |
Dave Airlie | f75843a | 2008-08-24 17:59:10 +1000 | [diff] [blame] | 454 | aper_array[aper_count++] = state->tex_buffer[i]; |
Dave Airlie | 96338dd | 2008-04-16 16:37:13 +1000 | [diff] [blame] | 455 | } |
| 456 | } |
| 457 | |
Dave Airlie | f75843a | 2008-08-24 17:59:10 +1000 | [diff] [blame] | 458 | if (dri_bufmgr_check_aperture_space(aper_array, aper_count)) { |
Dave Airlie | 96338dd | 2008-04-16 16:37:13 +1000 | [diff] [blame] | 459 | if (count == 0) { |
| 460 | count++; |
| 461 | intel_batchbuffer_flush(intel->batch); |
| 462 | goto again; |
| 463 | } else { |
| 464 | _mesa_error(ctx, GL_OUT_OF_MEMORY, "i830 emit state"); |
| 465 | assert(0); |
| 466 | } |
| 467 | } |
| 468 | |
Michel Dänzer | 2af613e | 2007-11-30 11:40:06 +0100 | [diff] [blame] | 469 | |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 470 | /* Do this here as we may have flushed the batchbuffer above, |
| 471 | * causing more state to be dirty! |
| 472 | */ |
Michel Dänzer | 2af613e | 2007-11-30 11:40:06 +0100 | [diff] [blame] | 473 | dirty = get_dirty(state); |
| 474 | state->emitted |= dirty; |
| 475 | assert(get_dirty(state) == 0); |
| 476 | |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 477 | if (dirty & I830_UPLOAD_INVARIENT) { |
| 478 | DBG("I830_UPLOAD_INVARIENT:\n"); |
| 479 | i830_emit_invarient_state(intel); |
| 480 | } |
| 481 | |
Eric Anholt | de80eee | 2009-08-04 11:28:26 -0700 | [diff] [blame] | 482 | if (dirty & I830_UPLOAD_RASTER_RULES) { |
| 483 | DBG("I830_UPLOAD_RASTER_RULES:\n"); |
| 484 | emit(intel, state->RasterRules, sizeof(state->RasterRules)); |
| 485 | } |
| 486 | |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 487 | if (dirty & I830_UPLOAD_CTX) { |
| 488 | DBG("I830_UPLOAD_CTX:\n"); |
Eric Anholt | a04b632 | 2008-01-10 10:48:05 -0800 | [diff] [blame] | 489 | emit(intel, state->Ctx, sizeof(state->Ctx)); |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 490 | |
| 491 | } |
| 492 | |
| 493 | if (dirty & I830_UPLOAD_BUFFERS) { |
Xiang, Haihao | df73363 | 2008-12-18 10:07:45 +0800 | [diff] [blame] | 494 | GLuint count = 9; |
| 495 | |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 496 | DBG("I830_UPLOAD_BUFFERS:\n"); |
Xiang, Haihao | df73363 | 2008-12-18 10:07:45 +0800 | [diff] [blame] | 497 | |
| 498 | if (state->depth_region) |
| 499 | count += 3; |
| 500 | |
| 501 | if (intel->constant_cliprect) |
| 502 | count += 6; |
| 503 | |
| 504 | BEGIN_BATCH(count, IGNORE_CLIPRECTS); |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 505 | OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR0]); |
| 506 | OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR1]); |
| 507 | OUT_RELOC(state->draw_region->buffer, |
Dave Airlie | f75843a | 2008-08-24 17:59:10 +1000 | [diff] [blame] | 508 | I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, |
Dave Airlie | 50b3f56 | 2006-11-23 01:12:41 +0000 | [diff] [blame] | 509 | state->draw_region->draw_offset); |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 510 | |
| 511 | if (state->depth_region) { |
| 512 | OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR0]); |
| 513 | OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR1]); |
| 514 | OUT_RELOC(state->depth_region->buffer, |
Dave Airlie | f75843a | 2008-08-24 17:59:10 +1000 | [diff] [blame] | 515 | I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, |
Dave Airlie | 50b3f56 | 2006-11-23 01:12:41 +0000 | [diff] [blame] | 516 | state->depth_region->draw_offset); |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 517 | } |
| 518 | |
| 519 | OUT_BATCH(state->Buffer[I830_DESTREG_DV0]); |
| 520 | OUT_BATCH(state->Buffer[I830_DESTREG_DV1]); |
| 521 | OUT_BATCH(state->Buffer[I830_DESTREG_SENABLE]); |
| 522 | OUT_BATCH(state->Buffer[I830_DESTREG_SR0]); |
| 523 | OUT_BATCH(state->Buffer[I830_DESTREG_SR1]); |
| 524 | OUT_BATCH(state->Buffer[I830_DESTREG_SR2]); |
Eric Anholt | 0cade4d | 2008-10-19 17:46:41 -0700 | [diff] [blame] | 525 | |
| 526 | if (intel->constant_cliprect) { |
| 527 | assert(state->Buffer[I830_DESTREG_DRAWRECT0] != MI_NOOP); |
| 528 | OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT0]); |
| 529 | OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT1]); |
| 530 | OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT2]); |
| 531 | OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT3]); |
| 532 | OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT4]); |
| 533 | OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT5]); |
| 534 | } |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 535 | ADVANCE_BATCH(); |
| 536 | } |
Dave Airlie | 50b3f56 | 2006-11-23 01:12:41 +0000 | [diff] [blame] | 537 | |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 538 | if (dirty & I830_UPLOAD_STIPPLE) { |
| 539 | DBG("I830_UPLOAD_STIPPLE:\n"); |
Eric Anholt | a04b632 | 2008-01-10 10:48:05 -0800 | [diff] [blame] | 540 | emit(intel, state->Stipple, sizeof(state->Stipple)); |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 541 | } |
| 542 | |
| 543 | for (i = 0; i < I830_TEX_UNITS; i++) { |
| 544 | if ((dirty & I830_UPLOAD_TEX(i))) { |
| 545 | DBG("I830_UPLOAD_TEX(%d):\n", i); |
| 546 | |
Eric Anholt | a04b632 | 2008-01-10 10:48:05 -0800 | [diff] [blame] | 547 | BEGIN_BATCH(I830_TEX_SETUP_SIZE + 1, IGNORE_CLIPRECTS); |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 548 | OUT_BATCH(state->Tex[i][I830_TEXREG_TM0LI]); |
| 549 | |
| 550 | if (state->tex_buffer[i]) { |
| 551 | OUT_RELOC(state->tex_buffer[i], |
Dave Airlie | f75843a | 2008-08-24 17:59:10 +1000 | [diff] [blame] | 552 | I915_GEM_DOMAIN_SAMPLER, 0, |
Eric Anholt | 165ae5e | 2009-06-04 10:21:29 +0000 | [diff] [blame] | 553 | state->tex_offset[i]); |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 554 | } |
Michel Dänzer | 9cde7fb | 2007-06-15 15:24:35 +0200 | [diff] [blame] | 555 | else if (state == &i830->meta) { |
| 556 | assert(i == 0); |
| 557 | OUT_BATCH(0); |
| 558 | } |
| 559 | else { |
| 560 | OUT_BATCH(state->tex_offset[i]); |
| 561 | } |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 562 | |
| 563 | OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S1]); |
| 564 | OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S2]); |
| 565 | OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S3]); |
| 566 | OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S4]); |
| 567 | OUT_BATCH(state->Tex[i][I830_TEXREG_MCS]); |
| 568 | OUT_BATCH(state->Tex[i][I830_TEXREG_CUBE]); |
Xiang, Haihao | df73363 | 2008-12-18 10:07:45 +0800 | [diff] [blame] | 569 | |
| 570 | ADVANCE_BATCH(); |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 571 | } |
| 572 | |
| 573 | if (dirty & I830_UPLOAD_TEXBLEND(i)) { |
| 574 | DBG("I830_UPLOAD_TEXBLEND(%d): %d words\n", i, |
| 575 | state->TexBlendWordsUsed[i]); |
Eric Anholt | a04b632 | 2008-01-10 10:48:05 -0800 | [diff] [blame] | 576 | emit(intel, state->TexBlend[i], state->TexBlendWordsUsed[i] * 4); |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 577 | } |
| 578 | } |
| 579 | |
Michel Dänzer | 2af613e | 2007-11-30 11:40:06 +0100 | [diff] [blame] | 580 | intel->batch->dirty_state &= ~dirty; |
| 581 | assert(get_dirty(state) == 0); |
Michel Dänzer | 2af613e | 2007-11-30 11:40:06 +0100 | [diff] [blame] | 582 | assert((intel->batch->dirty_state & (1<<1)) == 0); |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 583 | } |
| 584 | |
| 585 | static void |
| 586 | i830_destroy_context(struct intel_context *intel) |
| 587 | { |
Michel Dänzer | 2193c4d | 2007-08-16 08:45:16 +0200 | [diff] [blame] | 588 | GLuint i; |
| 589 | struct i830_context *i830 = i830_context(&intel->ctx); |
| 590 | |
Eric Anholt | 7d99ddc | 2008-09-26 12:48:23 -0700 | [diff] [blame] | 591 | intel_region_release(&i830->state.draw_region); |
| 592 | intel_region_release(&i830->state.depth_region); |
| 593 | intel_region_release(&i830->meta.draw_region); |
| 594 | intel_region_release(&i830->meta.depth_region); |
| 595 | intel_region_release(&i830->initial.draw_region); |
| 596 | intel_region_release(&i830->initial.depth_region); |
| 597 | |
Michel Dänzer | 2193c4d | 2007-08-16 08:45:16 +0200 | [diff] [blame] | 598 | for (i = 0; i < I830_TEX_UNITS; i++) { |
| 599 | if (i830->state.tex_buffer[i] != NULL) { |
Eric Anholt | 4f1c9f7 | 2007-09-19 11:05:36 -0700 | [diff] [blame] | 600 | dri_bo_unreference(i830->state.tex_buffer[i]); |
Michel Dänzer | 2193c4d | 2007-08-16 08:45:16 +0200 | [diff] [blame] | 601 | i830->state.tex_buffer[i] = NULL; |
| 602 | } |
| 603 | } |
| 604 | |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 605 | _tnl_free_vertices(&intel->ctx); |
| 606 | } |
| 607 | |
Dave Airlie | d98e1f3 | 2006-11-23 00:09:16 +0000 | [diff] [blame] | 608 | |
| 609 | void |
| 610 | i830_state_draw_region(struct intel_context *intel, |
| 611 | struct i830_hw_state *state, |
| 612 | struct intel_region *color_region, |
| 613 | struct intel_region *depth_region) |
| 614 | { |
| 615 | struct i830_context *i830 = i830_context(&intel->ctx); |
Eric Anholt | 0cade4d | 2008-10-19 17:46:41 -0700 | [diff] [blame] | 616 | GLcontext *ctx = &intel->ctx; |
Eric Anholt | 2c30fd8 | 2009-04-09 18:30:12 -0700 | [diff] [blame] | 617 | struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0]; |
| 618 | struct intel_renderbuffer *irb = intel_renderbuffer(rb); |
Dave Airlie | d98e1f3 | 2006-11-23 00:09:16 +0000 | [diff] [blame] | 619 | GLuint value; |
| 620 | |
| 621 | ASSERT(state == &i830->state || state == &i830->meta); |
| 622 | |
| 623 | if (state->draw_region != color_region) { |
| 624 | intel_region_release(&state->draw_region); |
| 625 | intel_region_reference(&state->draw_region, color_region); |
| 626 | } |
| 627 | if (state->depth_region != depth_region) { |
| 628 | intel_region_release(&state->depth_region); |
| 629 | intel_region_reference(&state->depth_region, depth_region); |
| 630 | } |
| 631 | |
| 632 | /* |
| 633 | * Set stride/cpp values |
| 634 | */ |
Eric Anholt | 165ae5e | 2009-06-04 10:21:29 +0000 | [diff] [blame] | 635 | i915_set_buf_info_for_region(&state->Buffer[I830_DESTREG_CBUFADDR0], |
| 636 | color_region, BUF_3D_ID_COLOR_BACK); |
Dave Airlie | d98e1f3 | 2006-11-23 00:09:16 +0000 | [diff] [blame] | 637 | |
Eric Anholt | 165ae5e | 2009-06-04 10:21:29 +0000 | [diff] [blame] | 638 | i915_set_buf_info_for_region(&state->Buffer[I830_DESTREG_DBUFADDR0], |
| 639 | depth_region, BUF_3D_ID_DEPTH); |
Dave Airlie | d98e1f3 | 2006-11-23 00:09:16 +0000 | [diff] [blame] | 640 | |
| 641 | /* |
| 642 | * Compute/set I830_DESTREG_DV1 value |
| 643 | */ |
| 644 | value = (DSTORG_HORT_BIAS(0x8) | /* .5 */ |
| 645 | DSTORG_VERT_BIAS(0x8) | DEPTH_IS_Z); /* .5 */ |
Eric Anholt | 2c30fd8 | 2009-04-09 18:30:12 -0700 | [diff] [blame] | 646 | |
| 647 | if (irb != NULL) { |
Brian Paul | 1f7c914 | 2009-09-30 20:28:45 -0600 | [diff] [blame] | 648 | switch (irb->texformat) { |
Eric Anholt | 2c30fd8 | 2009-04-09 18:30:12 -0700 | [diff] [blame] | 649 | case MESA_FORMAT_ARGB8888: |
Brian Paul | 4a25343 | 2009-10-29 19:12:50 -0600 | [diff] [blame] | 650 | case MESA_FORMAT_XRGB8888: |
Eric Anholt | 2c30fd8 | 2009-04-09 18:30:12 -0700 | [diff] [blame] | 651 | value |= DV_PF_8888; |
| 652 | break; |
| 653 | case MESA_FORMAT_RGB565: |
| 654 | value |= DV_PF_565; |
| 655 | break; |
| 656 | case MESA_FORMAT_ARGB1555: |
| 657 | value |= DV_PF_1555; |
| 658 | break; |
| 659 | case MESA_FORMAT_ARGB4444: |
| 660 | value |= DV_PF_4444; |
| 661 | break; |
| 662 | default: |
| 663 | _mesa_problem(ctx, "Bad renderbuffer format: %d\n", |
Brian Paul | 1f7c914 | 2009-09-30 20:28:45 -0600 | [diff] [blame] | 664 | irb->texformat); |
Eric Anholt | 2c30fd8 | 2009-04-09 18:30:12 -0700 | [diff] [blame] | 665 | } |
Dave Airlie | d98e1f3 | 2006-11-23 00:09:16 +0000 | [diff] [blame] | 666 | } |
Eric Anholt | 2c30fd8 | 2009-04-09 18:30:12 -0700 | [diff] [blame] | 667 | |
Dave Airlie | d98e1f3 | 2006-11-23 00:09:16 +0000 | [diff] [blame] | 668 | if (depth_region && depth_region->cpp == 4) { |
| 669 | value |= DEPTH_FRMT_24_FIXED_8_OTHER; |
| 670 | } |
| 671 | else { |
| 672 | value |= DEPTH_FRMT_16_FIXED; |
| 673 | } |
| 674 | state->Buffer[I830_DESTREG_DV1] = value; |
| 675 | |
Eric Anholt | 0cade4d | 2008-10-19 17:46:41 -0700 | [diff] [blame] | 676 | if (intel->constant_cliprect) { |
| 677 | state->Buffer[I830_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO; |
| 678 | state->Buffer[I830_DESTREG_DRAWRECT1] = 0; |
| 679 | state->Buffer[I830_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */ |
| 680 | state->Buffer[I830_DESTREG_DRAWRECT3] = |
| 681 | (ctx->DrawBuffer->Width & 0xffff) | |
| 682 | (ctx->DrawBuffer->Height << 16); |
| 683 | state->Buffer[I830_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */ |
| 684 | state->Buffer[I830_DESTREG_DRAWRECT5] = 0; |
| 685 | } else { |
| 686 | state->Buffer[I830_DESTREG_DRAWRECT0] = MI_NOOP; |
| 687 | state->Buffer[I830_DESTREG_DRAWRECT1] = MI_NOOP; |
| 688 | state->Buffer[I830_DESTREG_DRAWRECT2] = MI_NOOP; |
| 689 | state->Buffer[I830_DESTREG_DRAWRECT3] = MI_NOOP; |
| 690 | state->Buffer[I830_DESTREG_DRAWRECT4] = MI_NOOP; |
| 691 | state->Buffer[I830_DESTREG_DRAWRECT5] = MI_NOOP; |
| 692 | } |
| 693 | |
Dave Airlie | d98e1f3 | 2006-11-23 00:09:16 +0000 | [diff] [blame] | 694 | I830_STATECHANGE(i830, I830_UPLOAD_BUFFERS); |
| 695 | |
| 696 | |
| 697 | } |
| 698 | |
| 699 | |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 700 | static void |
| 701 | i830_set_draw_region(struct intel_context *intel, |
Zou Nan hai | fcb7cb9 | 2008-03-13 14:46:38 +0800 | [diff] [blame] | 702 | struct intel_region *color_regions[], |
| 703 | struct intel_region *depth_region, |
| 704 | GLuint num_regions) |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 705 | { |
| 706 | struct i830_context *i830 = i830_context(&intel->ctx); |
Zou Nan hai | fcb7cb9 | 2008-03-13 14:46:38 +0800 | [diff] [blame] | 707 | i830_state_draw_region(intel, &i830->state, color_regions[0], depth_region); |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 708 | } |
| 709 | |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 710 | /* This isn't really handled at the moment. |
| 711 | */ |
| 712 | static void |
Eric Anholt | 5f86ae0 | 2008-01-09 13:40:40 -0800 | [diff] [blame] | 713 | i830_new_batch(struct intel_context *intel) |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 714 | { |
| 715 | struct i830_context *i830 = i830_context(&intel->ctx); |
| 716 | i830->state.emitted = 0; |
Eric Anholt | 8517079 | 2008-01-14 11:03:05 -0800 | [diff] [blame] | 717 | |
| 718 | /* Check that we didn't just wrap our batchbuffer at a bad time. */ |
| 719 | assert(!intel->no_batch_wrap); |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 720 | } |
| 721 | |
| 722 | |
| 723 | |
| 724 | static GLuint |
| 725 | i830_flush_cmd(void) |
| 726 | { |
| 727 | return MI_FLUSH | FLUSH_MAP_CACHE; |
| 728 | } |
| 729 | |
| 730 | |
| 731 | static void |
| 732 | i830_assert_not_dirty( struct intel_context *intel ) |
| 733 | { |
| 734 | struct i830_context *i830 = i830_context(&intel->ctx); |
| 735 | struct i830_hw_state *state = i830->current; |
Michel Dänzer | 2af613e | 2007-11-30 11:40:06 +0100 | [diff] [blame] | 736 | assert(!get_dirty(state)); |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 737 | } |
| 738 | |
Eric Anholt | de80eee | 2009-08-04 11:28:26 -0700 | [diff] [blame] | 739 | static void |
| 740 | i830_invalidate_state(struct intel_context *intel, GLuint new_state) |
| 741 | { |
| 742 | if (new_state & _NEW_LIGHT) |
| 743 | i830_update_provoking_vertex(&intel->ctx); |
| 744 | } |
| 745 | |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 746 | void |
| 747 | i830InitVtbl(struct i830_context *i830) |
| 748 | { |
| 749 | i830->intel.vtbl.check_vertex_size = i830_check_vertex_size; |
| 750 | i830->intel.vtbl.destroy = i830_destroy_context; |
| 751 | i830->intel.vtbl.emit_state = i830_emit_state; |
Eric Anholt | 5f86ae0 | 2008-01-09 13:40:40 -0800 | [diff] [blame] | 752 | i830->intel.vtbl.new_batch = i830_new_batch; |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 753 | i830->intel.vtbl.reduced_primitive_state = i830_reduced_primitive_state; |
| 754 | i830->intel.vtbl.set_draw_region = i830_set_draw_region; |
| 755 | i830->intel.vtbl.update_texture_state = i830UpdateTextureState; |
| 756 | i830->intel.vtbl.flush_cmd = i830_flush_cmd; |
| 757 | i830->intel.vtbl.render_start = i830_render_start; |
Roland Scheidegger | a188ba4 | 2007-07-29 18:04:28 +0200 | [diff] [blame] | 758 | i830->intel.vtbl.render_prevalidate = i830_render_prevalidate; |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 759 | i830->intel.vtbl.assert_not_dirty = i830_assert_not_dirty; |
Dave Airlie | f75843a | 2008-08-24 17:59:10 +1000 | [diff] [blame] | 760 | i830->intel.vtbl.finish_batch = intel_finish_vb; |
Eric Anholt | de80eee | 2009-08-04 11:28:26 -0700 | [diff] [blame] | 761 | i830->intel.vtbl.invalidate_state = i830_invalidate_state; |
Keith Whitwell | 6b9e31f | 2006-11-01 12:03:11 +0000 | [diff] [blame] | 762 | } |