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gerrit-public.fairphone.software / fp2-dev / platform / external / oprofile / 219a1d03a9de33ae62abdb0cf5c45126940d0ace / . / daemon / opd_ibs.h
blob: 9ccc4824bcafa81e83a336def408e0a4d84c71a9 [file] [log] [blame]
Ben Cheng5a4eb4e2009-09-14 16:00:41 -0700[diff] [blame]1/**
2 * @file daemon/opd_ibs.h
3 * AMD Family10h Instruction Based Sampling (IBS) handling.
4 *
5 * @remark Copyright 2008 OProfile authors
6 * @remark Read the file COPYING
7 *
8 * @author Jason Yeh <jason.yeh@amd.com>
9 * @author Paul Drongowski <paul.drongowski@amd.com>
10 * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
11 * Copyright (c) 2008 Advanced Micro Devices, Inc.
12 */
13
14#ifndef OPD_IBS_H
15#define OPD_IBS_H
16
17#include <stdint.h>
18
19#include "opd_ibs_macro.h"
20
21struct transient;
22struct opd_event;
23
24/**
25 * IBS information is processed in two steps. The first step decodes
26 * hardware-level IBS information and saves it in decoded form. The
27 * second step translates the decoded IBS information into IBS derived
28 * events. IBS information is tallied and is reported as derived events.
29 */
30
31struct ibs_sample {
32 struct ibs_fetch_sample * fetch;
33 struct ibs_op_sample * op;
34};
35
36/**
37 * This struct represents the hardware-level IBS fetch information.
38 * Each field corresponds to a model-specific register (MSR.) See the
39 * BIOS and Kernel Developer's Guide for AMD Model Family 10h Processors
40 * for further details.
41 */
42struct ibs_fetch_sample {
43 unsigned long int rip;
44 /* MSRC001_1030 IBS Fetch Control Register */
45 unsigned int ibs_fetch_ctl_low;
46 unsigned int ibs_fetch_ctl_high;
47 /* MSRC001_1031 IBS Fetch Linear Address Register */
48 unsigned int ibs_fetch_lin_addr_low;
49 unsigned int ibs_fetch_lin_addr_high;
50 /* MSRC001_1032 IBS Fetch Physical Address Register */
51 unsigned int ibs_fetch_phys_addr_low;
52 unsigned int ibs_fetch_phys_addr_high;
53 unsigned int dummy_event;
54};
55
56
57
58/** This struct represents the hardware-level IBS op information. */
59struct ibs_op_sample {
60 unsigned long int rip;
61 /* MSRC001_1034 IBS Op Logical Address Register */
62 unsigned int ibs_op_lin_addr_low;
63 unsigned int ibs_op_lin_addr_high;
64 /* MSRC001_1035 IBS Op Data Register */
65 unsigned int ibs_op_data1_low;
66 unsigned int ibs_op_data1_high;
67 /* MSRC001_1036 IBS Op Data 2 Register */
68 unsigned int ibs_op_data2_low;
69 unsigned int ibs_op_data2_high;
70 /* MSRC001_1037 IBS Op Data 3 Register */
71 unsigned int ibs_op_data3_low;
72 unsigned int ibs_op_data3_high;
73 unsigned int ibs_op_ldst_linaddr_low;
74 unsigned int ibs_op_ldst_linaddr_high;
75 unsigned int ibs_op_phys_addr_low;
76 unsigned int ibs_op_phys_addr_high;
77};
78
79
80enum IBSL1PAGESIZE {
81 L1TLB4K = 0,
82 L1TLB2M,
83 L1TLB1G,
84 L1TLB_INVALID
85};
86
87
88/**
89 * Handle an IBS fetch sample escape code sequence. An IBS fetch sample
90 * is represented as an escape code sequence. (See the comment for the
91 * function code_ibs_op_sample() for the sequence of entries in the event
92 * buffer.) When this function is called, the ESCAPE_CODE and IBS_FETCH_CODE
93 * have already been removed from the event buffer. Thus, 7 more event buffer
94 * entries are needed in order to process a complete IBS fetch sample.
95 */
96extern void code_ibs_fetch_sample(struct transient * trans);
97
98/**
99 * Handle an IBS op sample escape code sequence. An IBS op sample
100 * is represented as an escape code sequence:
101 *
102 * IBS fetch IBS op
103 * --------------- ----------------
104 * ESCAPE_CODE ESCAPE_CODE
105 * IBS_FETCH_CODE IBS_OP_CODE
106 * Offset Offset
107 * IbsFetchLinAd low IbsOpRip low <-- Logical (virtual) RIP
108 * IbsFetchLinAd high IbsOpRip high <-- Logical (virtual) RIP
109 * IbsFetchCtl low IbsOpData low
110 * IbsFetchCtl high IbsOpData high
111 * IbsFetchPhysAd low IbsOpData2 low
112 * IbsFetchPhysAd high IbsOpData2 high
113 * IbsOpData3 low
114 * IbsOpData3 high
115 * IbsDcLinAd low
116 * IbsDcLinAd high
117 * IbsDcPhysAd low
118 * IbsDcPhysAd high
119 *
120 * When this function is called, the ESCAPE_CODE and IBS_OP_CODE have
121 * already been removed from the event buffer. Thus, 13 more event buffer
122 * entries are needed to process a complete IBS op sample.
123 *
124 * The IbsFetchLinAd and IbsOpRip are the linear (virtual) addresses
125 * that were generated by the IBS hardware. These addresses are mapped
126 * into the offset.
127 */
128extern void code_ibs_op_sample(struct transient * trans);
129
130/** Log the specified IBS derived event. */
131extern void opd_log_ibs_event(unsigned int event, struct transient * trans);
132
133/** Log the specified IBS cycle count. */
134extern void opd_log_ibs_count(unsigned int event, struct transient * trans, unsigned int count);
135
136
137#endif /*OPD_IBS_H*/