blob: ef3a6df1a03b4e07b811f3c877a321aba0e33c38 [file] [log] [blame]
Paul Lind73f45fe2013-03-04 17:10:49 -08001// events from file events/mips/74K/events
2 {0x0, CTR(0) | CTR(1) | CTR(2) | CTR(3), 0, "CYCLES",
3 "0-0 Cycles"},
4 {0x1, CTR(0) | CTR(1) | CTR(2) | CTR(3), 0, "INSTRUCTIONS",
5 "1-0 Instructions graduated"},
6 {0x2, CTR(0) | CTR(2), 0, "PREDICTED_JR_31",
7 "2-0 JR $31 (return) instructions predicted including speculative instructions"},
8 {0x3, CTR(0) | CTR(2), 0, "REDIRECT_STALLS",
9 "3-0 Stall cycles due to register indirect jumps (including non-predicted JR $31), ERET/WAIT instructions, and IFU determined exception"},
10 {0x4, CTR(0) | CTR(2), 0, "ITLB_ACCESSES",
11 "4-0 Instruction micro-TLB accesses"},
12 {0x6, CTR(0) | CTR(2), 0, "ICACHE_ACCESSES",
13 "6-0 Instruction cache accesses including speculative instructions"},
14 {0x7, CTR(0) | CTR(2), 0, "ICACHE_MISS_STALLS",
15 "7-0 Instruction cache miss stall cycles"},
16 {0x8, CTR(0) | CTR(2), 0, "UNCACHED_IFETCH_STALLS",
17 "8-0 Uncached instruction fetch stall cycles"},
18 {0x9, CTR(0) | CTR(2), 0, "IFU_REPLAYS",
19 "9-0 Replays within the IFU due to full Instruction Buffer"},
20 {0xb, CTR(0) | CTR(2), 0, "IFU_IDU_MISS_PRED_UPSTREAM_CYCLES",
21 "11-0 Cycles IFU-IDU gate is closed (to prevent upstream from getting ahead) due to mispredicted branch"},
22 {0xc, CTR(0) | CTR(2), 0, "IFU_IDU_CLOGED_DOWNSTREAM_CYCLES",
23 "12-0 Cycles IFU-IDU gate is closed (waiting for downstream to unclog) due to MTC0/MFC0 sequence in pipe, EHB, or blocked DD, DR, or DS"},
24 {0xd, CTR(0) | CTR(2), 0, "DDQ0_FULL_DR_STALLS",
25 "13-0 DR stage stall cycles due to DDQ0 (ALU out-of-order dispatch queue) full"},
26 {0xe, CTR(0) | CTR(2), 0, "ALCB_FULL_DR_STALLS",
27 "14-0 DR stage stall cycles due to ALCB (ALU completion buffers) full"},
28 {0xf, CTR(0) | CTR(2), 0, "CLDQ_FULL_DR_STALLS",
29 "15-0 DR stage stall cycles due to CLDQ (data comming back from FPU) full"},
30 {0x10, CTR(0) | CTR(2), 0, "ALU_EMPTY_CYCLES",
31 "16-0 DDQ0 (ALU out-of-order dispatch queue) empty cycles"},
32 {0x11, CTR(0) | CTR(2), 0, "ALU_OPERANDS_NOT_READY_CYCLES",
33 "17-0 DDQ0 (ALU out-of-order dispatch queue) no issue cycles with valid instructions but operands not ready"},
34 {0x12, CTR(0) | CTR(2), 0, "ALU_NO_ISSUES_CYCLES",
35 "18-0 DDQ0 (ALU out-of-order dispatch queue) no issue cycles with valid instructions due to operand(s) not available, MDU busy, or CorExt resource busy"},
36 {0x13, CTR(0) | CTR(2), 0, "ALU_BUBBLE_CYCLES",
37 "19-0 DDQ0 (ALU out-of-order dispatch queue) bubbles due to MFC1 data write"},
38 {0x14, CTR(0) | CTR(2), 0, "SINGLE_ISSUE_CYCLES",
39 "20-0 Either DDQ0 (ALU out-of-order dispatch queue) or DDQ1 (AGEN out-of-order dispatch queue) valid instruction issue cycles"},
40 {0x15, CTR(0) | CTR(2), 0, "OOO_ALU_ISSUE_CYCLES",
41 "21-0 Out-of-order ALU issue cycles (issued instruction is not the oldest in the pool)"},
42 {0x16, CTR(0) | CTR(2), 0, "JALR_JALR_HB_INSNS",
43 "22-0 Graduated JALR/JALR.HB instructions"},
44 {0x17, CTR(0) | CTR(2), 0, "DCACHE_LOAD_ACCESSES",
45 "23-0 Counts all accesses to the data cache caused by load instructions"},
46 {0x18, CTR(0) | CTR(2), 0, "DCACHE_WRITEBACKS",
47 "24-0 Data cache writebacks"},
48 {0x19, CTR(0) | CTR(2), 0, "JTLB_DATA_ACCESSES",
49 "25-0 Joint TLB data (non-instruction) accesses"},
50 {0x1a, CTR(0) | CTR(2), 0, "LOAD_STORE_REPLAYS",
51 "26-0 Load/store generated replays - load/store follows too closely a matching CACHEOP"},
52 {0x1b, CTR(0) | CTR(2), 0, "LOAD_STORE_BLOCKED_CYCLES",
53 "27-0 Load/store graduation blocked cycles due to CP1/2 store data not ready, SYNC/SYNCI/SC/CACHEOP at the head, or FSB/LDQ/WBB/ITU FIFO full"},
54 {0x1c, CTR(0) | CTR(2), 0, "L2_CACHE_WRITEBACKS",
55 "28-0 L2 Cache Writebacks"},
56 {0x1d, CTR(0) | CTR(2), 0, "L2_CACHE_MISSES",
57 "29-0 L2 Cache Misses"},
58 {0x1e, CTR(0) | CTR(2), 0, "FSB_FULL_STALLS",
59 "30-0 Pipe stall cycles due to FSB full"},
60 {0x1f, CTR(0) | CTR(2), 0, "LDQ_FULL_STALLS",
61 "31-0 Pipe stall cycles due to LDQ full"},
62 {0x20, CTR(0) | CTR(2), 0, "WBB_FULL_STALLS",
63 "32-0 Pipe stall cycles due to WBB full"},
64 {0x23, CTR(0) | CTR(2), 0, "LOAD_MISS_CONSUMER_REPLAYS",
65 "35-0 Replays following optimistic issue of instruction dependent on load which missed, counted only when the dependent instruction graduates"},
66 {0x24, CTR(0) | CTR(2), 0, "JR_NON_31_INSNS",
67 "36-0 jr $xx (not $31) instructions graduated (at same cost as a mispredict)"},
68 {0x25, CTR(0) | CTR(2), 0, "BRANCH_INSNS",
69 "37-0 Branch instructions graduated, excluding CP1/CP2 conditional branches"},
70 {0x26, CTR(0) | CTR(2), 0, "BRANCH_LIKELY_INSNS",
71 "38-0 Branch likely instructions graduated including CP1 and CP2 branch likely instructions"},
72 {0x27, CTR(0) | CTR(2), 0, "COND_BRANCH_INSNS",
73 "39-0 Conditional branches graduated"},
74 {0x28, CTR(0) | CTR(2), 0, "INTEGER_INSNS",
75 "40-0 Integer instructions graduated including NOP, SSNOP, MOVCI, and EHB"},
76 {0x29, CTR(0) | CTR(2), 0, "LOAD_INSNS",
77 "41-0 Loads graduated including CP1 ans CP2 loads"},
78 {0x2a, CTR(0) | CTR(2), 0, "J_JAL_INSNS",
79 "42-0 J/JAL graduated"},
80 {0x2b, CTR(0) | CTR(2), 0, "NOP_INSNS",
81 "43-0 NOP instructions graduated - SLL 0, NOP, SSNOP, and EHB"},
82 {0x2c, CTR(0) | CTR(2), 0, "DSP_INSNS",
83 "44-0 DSP instructions graduated"},
84 {0x2d, CTR(0) | CTR(2), 0, "DSP_BRANCH_INSNS",
85 "45-0 DSP branch instructions graduated"},
86 {0x2e, CTR(0) | CTR(2), 0, "UNCACHED_LOAD_INSNS",
87 "46-0 Uncached loads graduated"},
88 {0x31, CTR(0) | CTR(2), 0, "EJTAG_INSN_TRIGGERS",
89 "49-0 EJTAG instruction triggerpoints"},
90 {0x32, CTR(0) | CTR(2), 0, "CP1_BRANCH_MISPREDICTIONS",
91 "50-0 CP1 branches mispredicted"},
92 {0x33, CTR(0) | CTR(2), 0, "SC_INSNS",
93 "51-0 SC instructions graduated"},
94 {0x34, CTR(0) | CTR(2), 0, "PREFETCH_INSNS",
95 "52-0 Prefetch instructions graduated"},
96 {0x35, CTR(0) | CTR(2), 0, "NO_INSN_CYCLES",
97 "53-0 No instructions graduated cycles"},
98 {0x36, CTR(0) | CTR(2), 0, "ONE_INSN_CYCLES",
99 "54-0 One instruction graduated cycles"},
100 {0x37, CTR(0) | CTR(2), 0, "GFIFO_BLOCKED_CYCLES",
101 "55-0 GFIFO blocked cycles"},
102 {0x38, CTR(0) | CTR(2), 0, "MISPREDICTION_STALLS",
103 "56-0 Cycles from the time of a pipe kill due to mispredict until the first new instruction graduates"},
104 {0x39, CTR(0) | CTR(2), 0, "MISPREDICTED_BRANCH_INSNS_CYCLES",
105 "57-0 Mispredicted branch instruction graduation cycles without the delay slot"},
106 {0x3a, CTR(0) | CTR(2), 0, "EXCEPTIONS_TAKEN",
107 "58-0 Exceptions taken"},
108 {0x3b, CTR(0) | CTR(2), 0, "COREEXTEND_EVENTS",
109 "59-0 Implementation specific CorExtend events"},
110 {0x3e, CTR(0) | CTR(2), 0, "ISPRAM_EVENTS",
111 "62-0 Implementation specific ISPRAM events"},
112 {0x3f, CTR(0) | CTR(2), 0, "L2_CACHE_SINGLE_BIT_ERRORS",
113 "63-0 Single bit errors corrected in L2"},
114 {0x40, CTR(0) | CTR(2), 0, "SYSTEM_EVENT_0",
115 "64-0 Implementation specific system event 0"},
116 {0x41, CTR(0) | CTR(2), 0, "SYSTEM_EVENT_2",
117 "65-0 Implementation specific system event 2"},
118 {0x42, CTR(0) | CTR(2), 0, "SYSTEM_EVENT_4",
119 "66-0 Implementation specific system event 4"},
120 {0x43, CTR(0) | CTR(2), 0, "SYSTEM_EVENT_6",
121 "67-0 Implementation specific system event 6"},
122 {0x44, CTR(0) | CTR(2), 0, "OCP_ALL_REQUESTS",
123 "68-0 All OCP requests accepted"},
124 {0x45, CTR(0) | CTR(2), 0, "OCP_READ_REQUESTS",
125 "69-0 OCP read requests accepted"},
126 {0x46, CTR(0) | CTR(2), 0, "OCP_WRITE_REQUESTS",
127 "70-0 OCP write requests accepted"},
128 {0x4a, CTR(0) | CTR(2), 0, "FSB_LESS_25_FULL",
129 "74-0 FSB < 25% full"},
130 {0x4b, CTR(0) | CTR(2), 0, "LDQ_LESS_25_FULL",
131 "75-0 LDQ < 25% full"},
132 {0x4c, CTR(0) | CTR(2), 0, "WBB_LESS_25_FULL",
133 "76-0 WBB < 25% full"},
134 {0x402, CTR(1) | CTR(3), 0, "JR_31_MISPREDICTIONS",
135 "2-1 JR $31 (return) instructions mispredicted"},
136 {0x403, CTR(1) | CTR(3), 0, "JR_31_NO_PREDICTIONS",
137 "3-1 JR $31 (return) instructions not predicted"},
138 {0x404, CTR(1) | CTR(3), 0, "ITLB_MISSES",
139 "4-1 Instruction micro-TLB misses"},
140 {0x405, CTR(1) | CTR(3), 0, "JTLB_INSN_MISSES",
141 "5-1 Joint TLB instruction misses"},
142 {0x406, CTR(1) | CTR(3), 0, "ICACHE_MISSES",
143 "6-1 Instruction cache misses, includes misses from fetch-ahead and speculation"},
144 {0x408, CTR(1) | CTR(3), 0, "PDTRACE_BACK_STALLS",
145 "8-1 PDtrace back stalls"},
146 {0x409, CTR(1) | CTR(3), 0, "KILLED_FETCH_SLOTS",
147 "9-1 Valid fetch slots killed due to taken branches/jumps or stalling instructions"},
148 {0x40b, CTR(1) | CTR(3), 0, "IFU_IDU_NO_FETCH_CYCLES",
149 "11-1 Cycles IFU-IDU gate open but no instructions fetched by IFU"},
150 {0x40d, CTR(1) | CTR(3), 0, "DDQ1_FULL_DR_STALLS",
151 "13-1 DR stage stall cycles due to DDQ1 (AGEN out-of-order dispatch queue) full"},
152 {0x40e, CTR(1) | CTR(3), 0, "AGCB_FULL_DR_STALLS",
153 "14-1 DR stage stall cycles due to AGCB (AGEN completion buffers) full"},
154 {0x40f, CTR(1) | CTR(3), 0, "IODQ_FULL_DR_STALLS",
155 "15-1 DR stage stall cycles due to IODQ (data comming back from IO) full"},
156 {0x410, CTR(1) | CTR(3), 0, "AGEN_EMPTY_CYCLES",
157 "16-1 DDQ1 (AGEN out-of-order dispatch queue) empty cycles"},
158 {0x411, CTR(1) | CTR(3), 0, "AGEN_OPERANDS_NOT_READY_CYCLES",
159 "17-1 DDQ1 (AGEN out-of-order dispatch queue) no issue cycles with valid instructions but operands not ready"},
160 {0x412, CTR(1) | CTR(3), 0, "AGEN_NO_ISSUES_CYCLES",
161 "18-1 DDQ1 (AGEN out-of-order dispatch queue) no issue cycles with valid instructions due to operand(s) not available, non-issued stores blocking ready to issue loads, or non-issued CACHEOPs blocking ready to issue loads"},
162 {0x413, CTR(1) | CTR(3), 0, "AGEN_BUBBLE_CYCLES",
163 "19-1 DDQ1 (AGEN out-of-order dispatch queue) bubbles due to MFC2 data write or cache access from FSB"},
164 {0x414, CTR(1) | CTR(3), 0, "DUAL_ISSUE_CYCLES",
165 "20-1 Both DDQ0 (ALU out-of-order dispatch queue) and DDQ1 (AGEN out-of-order dispatch queue) valid instruction issue cycles"},
166 {0x415, CTR(1) | CTR(3), 0, "OOO_AGEN_ISSUE_CYCLES",
167 "21-1 Out-of-order AGEN issue cycles (issued instruction is not the oldest in the pool)"},
168 {0x416, CTR(1) | CTR(3), 0, "DCACHE_LINE_REFILL_REQUESTS",
169 "22-1 Data cache line loads (line refill requests)"},
170 {0x417, CTR(1) | CTR(3), 0, "DCACHE_ACCESSES",
171 "23-1 Data cache accesses"},
172 {0x418, CTR(1) | CTR(3), 0, "DCACHE_MISSES",
173 "24-1 Data cache misses"},
174 {0x419, CTR(1) | CTR(3), 0, "JTLB_DATA_MISSES",
175 "25-1 Joint TLB data (non-instruction) misses"},
176 {0x41a, CTR(1) | CTR(3), 0, "VA_TRANSALTION_CORNER_CASES",
177 "26-1 Virtual memory address translation synonyms, homonyms, and aliases (loads/stores treated as miss in the cache)"},
178 {0x41b, CTR(1) | CTR(3), 0, "LOAD_STORE_NO_FILL_REQUESTS",
179 "27-1 Load/store graduations not resulting in a bus request because misses at integer pipe graduation turn into hit or merge with outstanding fill request"},
180 {0x41c, CTR(1) | CTR(3), 0, "L2_CACHE_ACCESSES",
181 "28-1 Accesses to the L2 cache"},
182 {0x41d, CTR(1) | CTR(3), 0, "L2_CACHE_MISS_CYCLES",
183 "29-1 Cycles a L2 miss is outstanding, but not necessarily stalling the pipeline"},
184 {0x41e, CTR(1) | CTR(3), 0, "FSB_OVER_50_FULL",
185 "30-1 FSB > 50% full"},
186 {0x41f, CTR(1) | CTR(3), 0, "LDQ_OVER_50_FULL",
187 "31-1 LDQ > 50% full"},
188 {0x420, CTR(1) | CTR(3), 0, "WBB_OVER_50_FULL",
189 "32-1 WBB > 50% full"},
190 {0x423, CTR(1) | CTR(3), 0, "CP1_CP2_LOAD_INSNS",
191 "35-1 CP1/CP2 load instructions graduated"},
192 {0x424, CTR(1) | CTR(3), 0, "MISPREDICTED_JR_31_INSNS",
193 "36-1 jr $31 instructions graduated after mispredict"},
194 {0x425, CTR(1) | CTR(3), 0, "CP1_CP2_COND_BRANCH_INSNS",
195 "37-1 CP1/CP2 conditional branch instructions graduated"},
196 {0x426, CTR(1) | CTR(3), 0, "MISPREDICTED_BRANCH_LIKELY_INSNS",
197 "38-1 Mispredicted branch likely instructions graduated"},
198 {0x427, CTR(1) | CTR(3), 0, "MISPREDICTED_BRANCH_INSNS",
199 "39-1 Mispredicted branches graduated"},
200 {0x428, CTR(1) | CTR(3), 0, "FPU_INSNS",
201 "40-1 FPU instructions graduated"},
202 {0x429, CTR(1) | CTR(3), 0, "STORE_INSNS",
203 "41-1 Store instructions graduated including CP1 ans CP2 stores"},
204 {0x42a, CTR(1) | CTR(3), 0, "MIPS16_INSNS",
205 "42-1 MIPS16 instructions graduated"},
206 {0x42b, CTR(1) | CTR(3), 0, "NT_MUL_DIV_INSNS",
207 "43-1 Integer multiply/divide instructions graduated"},
208 {0x42c, CTR(1) | CTR(3), 0, "ALU_DSP_SATURATION_INSNS",
209 "44-1 ALU-DSP graduated, result was saturated"},
210 {0x42d, CTR(1) | CTR(3), 0, "MDU_DSP_SATURATION_INSNS",
211 "45-1 MDU-DSP graduated, result was saturated"},
212 {0x42e, CTR(1) | CTR(3), 0, "UNCACHED_STORE_INSNS",
213 "46-1 Uncached stores graduated"},
214 {0x433, CTR(1) | CTR(3), 0, "FAILED_SC_INSNS",
215 "51-1 SC instructions failed"},
216 {0x434, CTR(1) | CTR(3), 0, "CACHE_HIT_PREFETCH_INSNS",
217 "52-1 PREFETCH instructions which did nothing, because they hit in the cache"},
218 {0x435, CTR(1) | CTR(3), 0, "LOAD_MISS_INSNS",
219 "53-1 Cacheable load instructions that miss in the cache graduated"},
220 {0x436, CTR(1) | CTR(3), 0, "TWO_INSNS_CYCLES",
221 "54-1 Two instructions graduated cycles"},
222 {0x437, CTR(1) | CTR(3), 0, "CP1_CP2_STORE_INSNS",
223 "55-1 CP1/CP2 Store graduated"},
224 {0x43a, CTR(1) | CTR(3), 0, "GRADUATION_REPLAYS",
225 "58-1 Replays initiated from graduation"},
226 {0x43e, CTR(1) | CTR(3), 0, "DSPRAM_EVENTS",
227 "62-1 Implementation specific events from the DSPRAM block"},
228 {0x440, CTR(0) | CTR(2), 0, "SYSTEM_EVENT_1",
229 "64-1 Implementation specific system event 1"},
230 {0x441, CTR(0) | CTR(2), 0, "SYSTEM_EVENT_3",
231 "65-1 Implementation specific system event 3"},
232 {0x442, CTR(0) | CTR(2), 0, "SYSTEM_EVENT_5",
233 "66-1 Implementation specific system event 5"},
234 {0x443, CTR(0) | CTR(2), 0, "SYSTEM_EVENT_7",
235 "67-1 Implementation specific system event 7"},
236 {0x444, CTR(0) | CTR(2), 0, "OCP_ALL_CACHEABLE_REQUESTS",
237 "68-1 All OCP cacheable requests accepted"},
238 {0x445, CTR(0) | CTR(2), 0, "OCP_READ_CACHEABLE_REQUESTS",
239 "69-1 OCP cacheable read request accepted"},
240 {0x446, CTR(0) | CTR(2), 0, "OCP_WRITE_CACHEABLE_REQUESTS",
241 "70-1 OCP cacheable write request accepted"},
242 {0x44a, CTR(0) | CTR(2), 0, "FSB_25_50_FULL",
243 "74-1 FSB 25-50% full"},
244 {0x44b, CTR(0) | CTR(2), 0, "LDQ_25_50_FULL",
245 "75-1 LDQ 25-50% full"},
246 {0x44c, CTR(0) | CTR(2), 0, "WBB_25_50_FULL",
247 "76-1 WBB 25-50% full"},