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gerrit-public.fairphone.software / fp2-dev / platform / external / oprofile / 751a4435c3ef705b0e31faa14c75b9e2fd859959 / . / daemon / opd_ibs_trans.c
blob: 3b2c2f8c49f015e95c8c72a80a3cdcfb0500fbf8 [file] [log] [blame]
Ben Cheng5a4eb4e2009-09-14 16:00:41 -0700[diff] [blame]1/**
2 * @file daemon/opd_ibs_trans.c
3 * AMD Family10h Instruction Based Sampling (IBS) translation.
4 *
5 * @remark Copyright 2008 OProfile authors
6 * @remark Read the file COPYING
7 *
8 * @author Jason Yeh <jason.yeh@amd.com>
9 * @author Paul Drongowski <paul.drongowski@amd.com>
10 * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
11 * Copyright (c) 2008 Advanced Micro Devices, Inc.
12 */
13
14#include "opd_ibs.h"
15#include "opd_ibs_macro.h"
16#include "opd_ibs_trans.h"
17#include "opd_trans.h"
18#include "opd_printf.h"
19
20#include <stdlib.h>
21#include <stdio.h>
22
23#define MAX_EVENTS_PER_GROUP 32
24
25/*
26 * --------------------- OP DERIVED FUNCTION
27 */
28void trans_ibs_fetch (struct transient * trans, unsigned int selected_flag, unsigned int size)
29{
30 struct ibs_fetch_sample * trans_fetch = ((struct ibs_sample*)(trans->ext))->fetch;
31 unsigned int i, j, mask = 1;
32
33 for (i = IBS_FETCH_BASE, j =0 ; i <= IBS_FETCH_END && j < size ; i++, mask = mask << 1) {
34
35 if ((selected_flag & mask) == 0)
36 continue;
37
38 j++;
39
40 switch (i) {
41
42 case DE_IBS_FETCH_ALL:
43 /* IBS all fetch samples (kills + attempts) */
44 AGG_IBS_EVENT(DE_IBS_FETCH_ALL);
45 break;
46
47 case DE_IBS_FETCH_KILLED:
48 /* IBS killed fetches ("case 0") -- All interesting event
49 * flags are clear */
50 if (IBS_FETCH_KILLED(trans_fetch))
51 AGG_IBS_EVENT(DE_IBS_FETCH_KILLED);
52 break;
53
54 case DE_IBS_FETCH_ATTEMPTED:
55 /* Any non-killed fetch is an attempted fetch */
56 AGG_IBS_EVENT(DE_IBS_FETCH_ATTEMPTED);
57 break;
58
59 case DE_IBS_FETCH_COMPLETED:
60 if (IBS_FETCH_FETCH_COMPLETION(trans_fetch))
61 /* IBS Fetch Completed */
62 AGG_IBS_EVENT(DE_IBS_FETCH_COMPLETED);
63 break;
64
65 case DE_IBS_FETCH_ABORTED:
66 if (!IBS_FETCH_FETCH_COMPLETION(trans_fetch))
67 /* IBS Fetch Aborted */
68 AGG_IBS_EVENT(DE_IBS_FETCH_ABORTED);
69 break;
70
71 case DE_IBS_L1_ITLB_HIT:
72 /* IBS L1 ITLB hit */
73 if (IBS_FETCH_L1_TLB_HIT(trans_fetch))
74 AGG_IBS_EVENT(DE_IBS_L1_ITLB_HIT);
75 break;
76
77 case DE_IBS_ITLB_L1M_L2H:
78 /* IBS L1 ITLB miss and L2 ITLB hit */
79 if (IBS_FETCH_ITLB_L1M_L2H(trans_fetch))
80 AGG_IBS_EVENT(DE_IBS_ITLB_L1M_L2H);
81 break;
82
83 case DE_IBS_ITLB_L1M_L2M:
84 /* IBS L1 & L2 ITLB miss; complete ITLB miss */
85 if (IBS_FETCH_ITLB_L1M_L2M(trans_fetch))
86 AGG_IBS_EVENT(DE_IBS_ITLB_L1M_L2M);
87 break;
88
89 case DE_IBS_IC_MISS:
90 /* IBS instruction cache miss */
91 if (IBS_FETCH_INST_CACHE_MISS(trans_fetch))
92 AGG_IBS_EVENT(DE_IBS_IC_MISS);
93 break;
94
95 case DE_IBS_IC_HIT:
96 /* IBS instruction cache hit */
97 if (IBS_FETCH_INST_CACHE_HIT(trans_fetch))
98 AGG_IBS_EVENT(DE_IBS_IC_HIT);
99 break;
100
101 case DE_IBS_FETCH_4K_PAGE:
102 if (IBS_FETCH_PHYS_ADDR_VALID(trans_fetch)
103 && IBS_FETCH_TLB_PAGE_SIZE(trans_fetch) == L1TLB4K)
104 AGG_IBS_EVENT(DE_IBS_FETCH_4K_PAGE);
105 break;
106
107 case DE_IBS_FETCH_2M_PAGE:
108 if (IBS_FETCH_PHYS_ADDR_VALID(trans_fetch)
109 && IBS_FETCH_TLB_PAGE_SIZE(trans_fetch) == L1TLB2M)
110 AGG_IBS_EVENT(DE_IBS_FETCH_2M_PAGE);
111 break;
112
113 case DE_IBS_FETCH_1G_PAGE:
114 if (IBS_FETCH_PHYS_ADDR_VALID(trans_fetch)
115 && IBS_FETCH_TLB_PAGE_SIZE(trans_fetch) == L1TLB1G)
116 AGG_IBS_EVENT(DE_IBS_FETCH_1G_PAGE);
117 break;
118
119 case DE_IBS_FETCH_XX_PAGE:
120 break;
121
122 case DE_IBS_FETCH_LATENCY:
123 if (IBS_FETCH_FETCH_LATENCY(trans_fetch))
124 AGG_IBS_COUNT(DE_IBS_FETCH_LATENCY,
125 IBS_FETCH_FETCH_LATENCY(trans_fetch));
126 break;
127 default:
128 break;
129 }
130 }
131}
132
133/*
134 * --------------------- OP DERIVED FUNCTION
135 */
136void trans_ibs_op (struct transient * trans, unsigned int selected_flag, unsigned int size)
137{
138 struct ibs_op_sample * trans_op = ((struct ibs_sample*)(trans->ext))->op;
139 unsigned int i, j, mask = 1;
140
141 for (i = IBS_OP_BASE, j =0 ; i <= IBS_OP_END && j < size ; i++, mask = mask << 1) {
142
143 if ((selected_flag & mask) == 0)
144 continue;
145
146 j++;
147
148 switch (i) {
149
150 case DE_IBS_OP_ALL:
151 /* All IBS op samples */
152 AGG_IBS_EVENT(DE_IBS_OP_ALL);
153 break;
154
155 case DE_IBS_OP_TAG_TO_RETIRE:
156 /* Tally retire cycle counts for all sampled macro-ops
157 * IBS tag to retire cycles */
158 if (IBS_OP_TAG_TO_RETIRE_CYCLES(trans_op))
159 AGG_IBS_COUNT(DE_IBS_OP_TAG_TO_RETIRE,
160 IBS_OP_TAG_TO_RETIRE_CYCLES(trans_op));
161 break;
162
163 case DE_IBS_OP_COMP_TO_RETIRE:
164 /* IBS completion to retire cycles */
165 if (IBS_OP_COM_TO_RETIRE_CYCLES(trans_op))
166 AGG_IBS_COUNT(DE_IBS_OP_COMP_TO_RETIRE,
167 IBS_OP_COM_TO_RETIRE_CYCLES(trans_op));
168 break;
169
170 case DE_IBS_BRANCH_RETIRED:
171 if (IBS_OP_OP_BRANCH_RETIRED(trans_op))
172 /* IBS Branch retired op */
173 AGG_IBS_EVENT(DE_IBS_BRANCH_RETIRED) ;
174 break;
175
176 case DE_IBS_BRANCH_MISP:
177 if (IBS_OP_OP_BRANCH_RETIRED(trans_op)
178 /* Test branch-specific event flags */
179 /* IBS mispredicted Branch op */
180 && IBS_OP_OP_BRANCH_MISPREDICT(trans_op))
181 AGG_IBS_EVENT(DE_IBS_BRANCH_MISP) ;
182 break;
183
184 case DE_IBS_BRANCH_TAKEN:
185 if (IBS_OP_OP_BRANCH_RETIRED(trans_op)
186 /* IBS taken Branch op */
187 && IBS_OP_OP_BRANCH_TAKEN(trans_op))
188 AGG_IBS_EVENT(DE_IBS_BRANCH_TAKEN);
189 break;
190
191 case DE_IBS_BRANCH_MISP_TAKEN:
192 if (IBS_OP_OP_BRANCH_RETIRED(trans_op)
193 /* IBS mispredicted taken branch op */
194 && IBS_OP_OP_BRANCH_TAKEN(trans_op)
195 && IBS_OP_OP_BRANCH_MISPREDICT(trans_op))
196 AGG_IBS_EVENT(DE_IBS_BRANCH_MISP_TAKEN);
197 break;
198
199 case DE_IBS_RETURN:
200 if (IBS_OP_OP_BRANCH_RETIRED(trans_op)
201 /* IBS return op */
202 && IBS_OP_OP_RETURN(trans_op))
203 AGG_IBS_EVENT(DE_IBS_RETURN);
204 break;
205
206 case DE_IBS_RETURN_MISP:
207 if (IBS_OP_OP_BRANCH_RETIRED(trans_op)
208 /* IBS mispredicted return op */
209 && IBS_OP_OP_RETURN(trans_op)
210 && IBS_OP_OP_BRANCH_MISPREDICT(trans_op))
211 AGG_IBS_EVENT(DE_IBS_RETURN_MISP);
212 break;
213
214 case DE_IBS_RESYNC:
215 /* Test for a resync macro-op */
216 if (IBS_OP_OP_BRANCH_RESYNC(trans_op))
217 AGG_IBS_EVENT(DE_IBS_RESYNC);
218 break;
219 default:
220 break;
221 }
222 }
223}
224
225
226/*
227 * --------------------- OP LS DERIVED FUNCTION
228 */
229void trans_ibs_op_ls (struct transient * trans, unsigned int selected_flag, unsigned int size)
230{
231 struct ibs_op_sample * trans_op = ((struct ibs_sample*)(trans->ext))->op;
232 unsigned int i, j, mask = 1;
233
234 /* Preliminary check */
235 if (!IBS_OP_IBS_LD_OP(trans_op) && !IBS_OP_IBS_ST_OP(trans_op))
236 return;
237
238
239 for (i = IBS_OP_LS_BASE, j =0 ; i <= IBS_OP_LS_END && j < size ; i++, mask = mask << 1) {
240
241 if ((selected_flag & mask) == 0)
242 continue;
243
244 j++;
245
246 switch (i) {
247
248 case DE_IBS_LS_ALL_OP:
249 /* Count the number of LS op samples */
250 AGG_IBS_EVENT(DE_IBS_LS_ALL_OP) ;
251 break;
252
253 case DE_IBS_LS_LOAD_OP:
254 if (IBS_OP_IBS_LD_OP(trans_op))
255 /* TALLy an IBS load derived event */
256 AGG_IBS_EVENT(DE_IBS_LS_LOAD_OP) ;
257 break;
258
259 case DE_IBS_LS_STORE_OP:
260 if (IBS_OP_IBS_ST_OP(trans_op))
261 /* Count and handle store operations */
262 AGG_IBS_EVENT(DE_IBS_LS_STORE_OP);
263 break;
264
265 case DE_IBS_LS_DTLB_L1H:
266 if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
267 && !IBS_OP_IBS_DC_L1_TLB_MISS(trans_op))
268 /* L1 DTLB hit -- This is the most frequent case */
269 AGG_IBS_EVENT(DE_IBS_LS_DTLB_L1H);
270 break;
271
272 case DE_IBS_LS_DTLB_L1M_L2H:
273 /* l2_translation_size = 1 */
274 if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
275 && IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)
276 && !IBS_OP_IBS_DC_L2_TLB_MISS(trans_op))
277 /* L1 DTLB miss, L2 DTLB hit */
278 AGG_IBS_EVENT(DE_IBS_LS_DTLB_L1M_L2H);
279 break;
280
281 case DE_IBS_LS_DTLB_L1M_L2M:
282 if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
283 && IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)
284 && IBS_OP_IBS_DC_L2_TLB_MISS(trans_op))
285 /* L1 DTLB miss, L2 DTLB miss */
286 AGG_IBS_EVENT(DE_IBS_LS_DTLB_L1M_L2M);
287 break;
288
289 case DE_IBS_LS_DC_MISS:
290 if (IBS_OP_IBS_DC_MISS(trans_op))
291 AGG_IBS_EVENT(DE_IBS_LS_DC_MISS);
292 break;
293
294 case DE_IBS_LS_DC_HIT:
295 if (!IBS_OP_IBS_DC_MISS(trans_op))
296 AGG_IBS_EVENT(DE_IBS_LS_DC_HIT);
297 break;
298
299 case DE_IBS_LS_MISALIGNED:
300 if (IBS_OP_IBS_DC_MISS_ACC(trans_op))
301 AGG_IBS_EVENT(DE_IBS_LS_MISALIGNED);
302 break;
303
304 case DE_IBS_LS_BNK_CONF_LOAD:
305 if (IBS_OP_IBS_DC_LD_BNK_CON(trans_op))
306 AGG_IBS_EVENT(DE_IBS_LS_BNK_CONF_LOAD);
307 break;
308
309 case DE_IBS_LS_BNK_CONF_STORE:
310 if (IBS_OP_IBS_DC_ST_BNK_CON(trans_op))
311 AGG_IBS_EVENT(DE_IBS_LS_BNK_CONF_STORE);
312 break;
313
314 case DE_IBS_LS_STL_FORWARDED:
315 if (IBS_OP_IBS_LD_OP(trans_op)
316 /* Data forwarding info are valid only for load ops */
317 && IBS_OP_IBS_DC_ST_TO_LD_FWD(trans_op))
318 AGG_IBS_EVENT(DE_IBS_LS_STL_FORWARDED) ;
319 break;
320
321 case DE_IBS_LS_STL_CANCELLED:
322 if (IBS_OP_IBS_LD_OP(trans_op))
323 if (IBS_OP_IBS_DC_ST_TO_LD_CAN(trans_op))
324 AGG_IBS_EVENT(DE_IBS_LS_STL_CANCELLED) ;
325 break;
326
327 case DE_IBS_LS_UC_MEM_ACCESS:
328 if (IBS_OP_IBS_DC_UC_MEM_ACC(trans_op))
329 AGG_IBS_EVENT(DE_IBS_LS_UC_MEM_ACCESS);
330 break;
331
332 case DE_IBS_LS_WC_MEM_ACCESS:
333 if (IBS_OP_IBS_DC_WC_MEM_ACC(trans_op))
334 AGG_IBS_EVENT(DE_IBS_LS_WC_MEM_ACCESS);
335 break;
336
337 case DE_IBS_LS_LOCKED_OP:
338 if (IBS_OP_IBS_LOCKED_OP(trans_op))
339 AGG_IBS_EVENT(DE_IBS_LS_LOCKED_OP);
340 break;
341
342 case DE_IBS_LS_MAB_HIT:
343 if (IBS_OP_IBS_DC_MAB_HIT(trans_op))
344 AGG_IBS_EVENT(DE_IBS_LS_MAB_HIT);
345 break;
346
347 case DE_IBS_LS_L1_DTLB_4K:
348 /* l1_translation */
349 if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
350 && !IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)
351
352 && !IBS_OP_IBS_DC_L1_TLB_HIT_2MB(trans_op)
353 && !IBS_OP_IBS_DC_L1_TLB_HIT_1GB(trans_op))
354 /* This is the most common case, unfortunately */
355 AGG_IBS_EVENT(DE_IBS_LS_L1_DTLB_4K) ;
356 break;
357
358 case DE_IBS_LS_L1_DTLB_2M:
359 /* l1_translation */
360 if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
361 && !IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)
362
363 && IBS_OP_IBS_DC_L1_TLB_HIT_2MB(trans_op))
364 /* 2M L1 DTLB page translation */
365 AGG_IBS_EVENT(DE_IBS_LS_L1_DTLB_2M);
366 break;
367
368 case DE_IBS_LS_L1_DTLB_1G:
369 /* l1_translation */
370 if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
371 && !IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)
372
373 && !IBS_OP_IBS_DC_L1_TLB_HIT_2MB(trans_op)
374 && IBS_OP_IBS_DC_L1_TLB_HIT_1GB(trans_op))
375 /* 1G L1 DTLB page translation */
376 AGG_IBS_EVENT(DE_IBS_LS_L1_DTLB_1G);
377 break;
378
379 case DE_IBS_LS_L1_DTLB_RES:
380 break;
381
382 case DE_IBS_LS_L2_DTLB_4K:
383 /* l2_translation_size = 1 */
384 if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
385 && IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)
386 && !IBS_OP_IBS_DC_L2_TLB_MISS(trans_op)
387
388 /* L2 DTLB page translation */
389 && !IBS_OP_IBS_DC_L2_TLB_HIT_2MB(trans_op)
390 && !IBS_OP_IBS_DC_L2_TLB_HIT_1GB(trans_op))
391 /* 4K L2 DTLB page translation */
392 AGG_IBS_EVENT(DE_IBS_LS_L2_DTLB_4K);
393 break;
394
395 case DE_IBS_LS_L2_DTLB_2M:
396 /* l2_translation_size = 1 */
397 if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
398 && IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)
399 && !IBS_OP_IBS_DC_L2_TLB_MISS(trans_op)
400
401 /* L2 DTLB page translation */
402 && IBS_OP_IBS_DC_L2_TLB_HIT_2MB(trans_op)
403 && !IBS_OP_IBS_DC_L2_TLB_HIT_1GB(trans_op))
404 /* 2M L2 DTLB page translation */
405 AGG_IBS_EVENT(DE_IBS_LS_L2_DTLB_2M);
406 break;
407
408 case DE_IBS_LS_L2_DTLB_1G:
409 /* l2_translation_size = 1 */
410 if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
411 && IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)
412 && !IBS_OP_IBS_DC_L2_TLB_MISS(trans_op)
413
414 /* L2 DTLB page translation */
415 && !IBS_OP_IBS_DC_L2_TLB_HIT_2MB(trans_op)
416 && IBS_OP_IBS_DC_L2_TLB_HIT_1GB(trans_op))
417 /* 2M L2 DTLB page translation */
418 AGG_IBS_EVENT(DE_IBS_LS_L2_DTLB_1G);
419 break;
420
421 case DE_IBS_LS_L2_DTLB_RES2:
422 break;
423
424 case DE_IBS_LS_DC_LOAD_LAT:
425 if (IBS_OP_IBS_LD_OP(trans_op)
426 /* If the load missed in DC, tally the DC load miss latency */
427 && IBS_OP_IBS_DC_MISS(trans_op))
428 /* DC load miss latency is only reliable for load ops */
429 AGG_IBS_COUNT(DE_IBS_LS_DC_LOAD_LAT,
430 IBS_OP_DC_MISS_LATENCY(trans_op)) ;
431 break;
432
433 default:
434 break;
435 }
436 }
437}
438
439/*
440 * --------------------- OP NB DERIVED FUNCTION
441 *
442 * NB data is only guaranteed reliable for load operations
443 * that miss in L1 and L2 cache. NB data arrives too late
444 * to be reliable for store operations
445 */
446void trans_ibs_op_nb (struct transient * trans, unsigned int selected_flag, unsigned int size)
447{
448 struct ibs_op_sample * trans_op = ((struct ibs_sample*)(trans->ext))->op;
449 unsigned int i, j, mask = 1;
450
451 /* Preliminary check */
452 if (!IBS_OP_IBS_LD_OP(trans_op))
453 return;
454
455 if (!IBS_OP_IBS_DC_MISS(trans_op))
456 return;
457
458 if (IBS_OP_NB_IBS_REQ_SRC(trans_op) == 0)
459 return;
460
461 for (i = IBS_OP_NB_BASE, j =0 ; i <= IBS_OP_NB_END && j < size ; i++, mask = mask << 1) {
462
463 if ((selected_flag & mask) == 0)
464 continue;
465
466 j++;
467
468 switch (i) {
469
470 case DE_IBS_NB_LOCAL:
471 if (!IBS_OP_NB_IBS_REQ_DST_PROC(trans_op))
472 /* Request was serviced by local processor */
473 AGG_IBS_EVENT(DE_IBS_NB_LOCAL) ;
474 break;
475
476 case DE_IBS_NB_REMOTE:
477 if (IBS_OP_NB_IBS_REQ_DST_PROC(trans_op))
478 /* Request was serviced by remote processor */
479 AGG_IBS_EVENT(DE_IBS_NB_REMOTE) ;
480 break;
481
482 case DE_IBS_NB_LOCAL_L3:
483 if (!IBS_OP_NB_IBS_REQ_DST_PROC(trans_op)
484 && (IBS_OP_NB_IBS_REQ_SRC(trans_op) == 0x1))
485 AGG_IBS_EVENT(DE_IBS_NB_LOCAL_L3);
486 break;
487
488 case DE_IBS_NB_LOCAL_CACHE:
489 if (!IBS_OP_NB_IBS_REQ_DST_PROC(trans_op)
490 && (IBS_OP_NB_IBS_REQ_SRC(trans_op) == 0x2))
491 AGG_IBS_EVENT(DE_IBS_NB_LOCAL_CACHE);
492 break;
493
494 case DE_IBS_NB_REMOTE_CACHE:
495 if (IBS_OP_NB_IBS_REQ_DST_PROC(trans_op)
496 && (IBS_OP_NB_IBS_REQ_SRC(trans_op) == 0x2))
497 AGG_IBS_EVENT(DE_IBS_NB_REMOTE_CACHE) ;
498 break;
499
500 case DE_IBS_NB_LOCAL_DRAM:
501 if (!IBS_OP_NB_IBS_REQ_DST_PROC(trans_op)
502 && (IBS_OP_NB_IBS_REQ_SRC(trans_op) == 0x3))
503 AGG_IBS_EVENT(DE_IBS_NB_LOCAL_DRAM);
504 break;
505
506 case DE_IBS_NB_REMOTE_DRAM:
507 if (IBS_OP_NB_IBS_REQ_DST_PROC(trans_op)
508 && (IBS_OP_NB_IBS_REQ_SRC(trans_op) == 0x3))
509 AGG_IBS_EVENT(DE_IBS_NB_REMOTE_DRAM) ;
510 break;
511
512 case DE_IBS_NB_LOCAL_OTHER:
513 if (!IBS_OP_NB_IBS_REQ_DST_PROC(trans_op)
514 && (IBS_OP_NB_IBS_REQ_SRC(trans_op) == 0x7))
515 AGG_IBS_EVENT(DE_IBS_NB_LOCAL_OTHER);
516 break;
517
518 case DE_IBS_NB_REMOTE_OTHER:
519 if (IBS_OP_NB_IBS_REQ_DST_PROC(trans_op)
520 && (IBS_OP_NB_IBS_REQ_SRC(trans_op) == 0x7))
521 AGG_IBS_EVENT(DE_IBS_NB_REMOTE_OTHER) ;
522 break;
523
524 case DE_IBS_NB_CACHE_STATE_M:
525 if ((IBS_OP_NB_IBS_REQ_SRC(trans_op) == 0x2)
526 && !IBS_OP_NB_IBS_CACHE_HIT_ST(trans_op))
527 AGG_IBS_EVENT(DE_IBS_NB_CACHE_STATE_M) ;
528 break;
529
530 case DE_IBS_NB_CACHE_STATE_O:
531 if ((IBS_OP_NB_IBS_REQ_SRC(trans_op) == 0x2)
532 && IBS_OP_NB_IBS_CACHE_HIT_ST(trans_op))
533 AGG_IBS_EVENT(DE_IBS_NB_CACHE_STATE_O) ;
534 break;
535
536 case DE_IBS_NB_LOCAL_LATENCY:
537 if (!IBS_OP_NB_IBS_REQ_DST_PROC(trans_op))
538 /* Request was serviced by local processor */
539 AGG_IBS_COUNT(DE_IBS_NB_LOCAL_LATENCY,
540 IBS_OP_DC_MISS_LATENCY(trans_op));
541 break;
542
543 case DE_IBS_NB_REMOTE_LATENCY:
544 if (IBS_OP_NB_IBS_REQ_DST_PROC(trans_op))
545 /* Request was serviced by remote processor */
546 AGG_IBS_COUNT(DE_IBS_NB_REMOTE_LATENCY,
547 IBS_OP_DC_MISS_LATENCY(trans_op));
548 break;
549
550 default:
551 break;
552 }
553 }
554}