Upstream | cc2ee17 | 1970-01-12 13:46:40 +0000 | [diff] [blame^] | 1 | # Pentium II events |
| 2 | # |
| 3 | event:0x79 counters:0,1 um:zero minimum:6000 name:CPU_CLK_UNHALTED : clocks processor is not halted |
| 4 | event:0x43 counters:0,1 um:zero minimum:500 name:DATA_MEM_REFS : all memory references, cachable and non |
| 5 | event:0x45 counters:0,1 um:zero minimum:500 name:DCU_LINES_IN : total lines allocated in the DCU |
| 6 | event:0x46 counters:0,1 um:zero minimum:500 name:DCU_M_LINES_IN : number of M state lines allocated in DCU |
| 7 | event:0x47 counters:0,1 um:zero minimum:500 name:DCU_M_LINES_OUT : number of M lines evicted from the DCU |
| 8 | event:0x48 counters:0,1 um:zero minimum:500 name:DCU_MISS_OUTSTANDING : number of cycles while DCU miss outstanding |
| 9 | event:0x80 counters:0,1 um:zero minimum:500 name:IFU_IFETCH : number of non/cachable instruction fetches |
| 10 | event:0x81 counters:0,1 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses |
| 11 | event:0x85 counters:0,1 um:zero minimum:500 name:ITLB_MISS : number of ITLB misses |
| 12 | event:0x86 counters:0,1 um:zero minimum:500 name:IFU_MEM_STALL : cycles instruction fetch pipe is stalled |
| 13 | event:0x87 counters:0,1 um:zero minimum:500 name:ILD_STALL : cycles instruction length decoder is stalled |
| 14 | event:0x28 counters:0,1 um:mesi minimum:500 name:L2_IFETCH : number of L2 instruction fetches |
| 15 | event:0x29 counters:0,1 um:mesi minimum:500 name:L2_LD : number of L2 data loads |
| 16 | event:0x2a counters:0,1 um:mesi minimum:500 name:L2_ST : number of L2 data stores |
| 17 | event:0x24 counters:0,1 um:zero minimum:500 name:L2_LINES_IN : number of allocated lines in L2 |
| 18 | event:0x26 counters:0,1 um:zero minimum:500 name:L2_LINES_OUT : number of recovered lines from L2 |
| 19 | event:0x25 counters:0,1 um:zero minimum:500 name:L2_M_LINES_INM : number of modified lines allocated in L2 |
| 20 | event:0x27 counters:0,1 um:zero minimum:500 name:L2_M_LINES_OUTM : number of modified lines removed from L2 |
| 21 | event:0x2e counters:0,1 um:mesi minimum:500 name:L2_RQSTS : number of L2 requests |
| 22 | event:0x21 counters:0,1 um:zero minimum:500 name:L2_ADS : number of L2 address strobes |
| 23 | event:0x22 counters:0,1 um:zero minimum:500 name:L2_DBUS_BUSY : number of cycles data bus was busy |
| 24 | event:0x23 counters:0,1 um:zero minimum:500 name:L2_DBUS_BUSY_RD : cycles data bus was busy in xfer from L2 to CPU |
| 25 | event:0x62 counters:0,1 um:ebl minimum:500 name:BUS_DRDY_CLOCKS : number of clocks DRDY is asserted |
| 26 | event:0x63 counters:0,1 um:ebl minimum:500 name:BUS_LOCK_CLOCKS : number of clocks LOCK is asserted |
| 27 | event:0x60 counters:0,1 um:zero minimum:500 name:BUS_REQ_OUTSTANDING : number of outstanding bus requests |
| 28 | event:0x65 counters:0,1 um:ebl minimum:500 name:BUS_TRAN_BRD : number of burst read transactions |
| 29 | event:0x66 counters:0,1 um:ebl minimum:500 name:BUS_TRAN_RFO : number of read for ownership transactions |
| 30 | event:0x67 counters:0,1 um:ebl minimum:500 name:BUS_TRANS_WB : number of write back transactions |
| 31 | event:0x68 counters:0,1 um:ebl minimum:500 name:BUS_TRAN_IFETCH : number of instruction fetch transactions |
| 32 | event:0x69 counters:0,1 um:ebl minimum:500 name:BUS_TRAN_INVAL : number of invalidate transactions |
| 33 | event:0x6a counters:0,1 um:ebl minimum:500 name:BUS_TRAN_PWR : number of partial write transactions |
| 34 | event:0x6b counters:0,1 um:ebl minimum:500 name:BUS_TRANS_P : number of partial transactions |
| 35 | event:0x6c counters:0,1 um:ebl minimum:500 name:BUS_TRANS_IO : number of I/O transactions |
| 36 | event:0x6d counters:0,1 um:ebl minimum:500 name:BUS_TRANS_DEF : number of deferred transactions |
| 37 | event:0x6e counters:0,1 um:ebl minimum:500 name:BUS_TRAN_BURST : number of burst transactions |
| 38 | event:0x70 counters:0,1 um:ebl minimum:500 name:BUS_TRAN_ANY : number of all transactions |
| 39 | event:0x6f counters:0,1 um:ebl minimum:500 name:BUS_TRAN_MEM : number of memory transactions |
| 40 | event:0x64 counters:0,1 um:zero minimum:500 name:BUS_DATA_RCV : bus cycles this processor is receiving data |
| 41 | event:0x61 counters:0,1 um:zero minimum:500 name:BUS_BNR_DRV : bus cycles this processor is driving BNR pin |
| 42 | event:0x7a counters:0,1 um:zero minimum:500 name:BUS_HIT_DRV : bus cycles this processor is driving HIT pin |
| 43 | event:0x7b counters:0,1 um:zero minimum:500 name:BUS_HITM_DRV : bus cycles this processor is driving HITM pin |
| 44 | event:0x7e counters:0,1 um:zero minimum:500 name:BUS_SNOOP_STALL : cycles during bus snoop stall |
| 45 | event:0xc1 counters:0 um:zero minimum:3000 name:COMP_FLOP_RET : number of computational FP operations retired |
| 46 | event:0x10 counters:0 um:zero minimum:3000 name:FLOPS : number of computational FP operations executed |
| 47 | event:0x11 counters:1 um:zero minimum:500 name:FP_ASSIST : number of FP exceptions handled by microcode |
| 48 | event:0x12 counters:1 um:zero minimum:1000 name:MUL : number of multiplies |
| 49 | event:0x13 counters:1 um:zero minimum:500 name:DIV : number of divides |
| 50 | event:0x14 counters:0 um:zero minimum:1000 name:CYCLES_DIV_BUSY : cycles divider is busy |
| 51 | event:0x03 counters:0,1 um:zero minimum:500 name:LD_BLOCKS : number of store buffer blocks |
| 52 | event:0x04 counters:0,1 um:zero minimum:500 name:SB_DRAINS : number of store buffer drain cycles |
| 53 | event:0x05 counters:0,1 um:zero minimum:500 name:MISALIGN_MEM_REF : number of misaligned data memory references |
| 54 | event:0xc0 counters:0,1 um:zero minimum:6000 name:INST_RETIRED : number of instructions retired |
| 55 | event:0xc2 counters:0,1 um:zero minimum:6000 name:UOPS_RETIRED : number of UOPs retired |
| 56 | event:0xd0 counters:0,1 um:zero minimum:6000 name:INST_DECODED : number of instructions decoded |
| 57 | event:0xc8 counters:0,1 um:zero minimum:500 name:HW_INT_RX : number of hardware interrupts received |
| 58 | event:0xc6 counters:0,1 um:zero minimum:500 name:CYCLES_INT_MASKED : cycles interrupts are disabled |
| 59 | event:0xc7 counters:0,1 um:zero minimum:500 name:CYCLES_INT_PENDING_AND_MASKED : cycles interrupts are disabled with pending interrupts |
| 60 | event:0xc4 counters:0,1 um:zero minimum:500 name:BR_INST_RETIRED : number of branch instructions retired |
| 61 | event:0xc5 counters:0,1 um:zero minimum:500 name:BR_MISS_PRED_RETIRED : number of mispredicted branches retired |
| 62 | event:0xc9 counters:0,1 um:zero minimum:500 name:BR_TAKEN_RETIRED : number of taken branches retired |
| 63 | event:0xca counters:0,1 um:zero minimum:500 name:BR_MISS_PRED_TAKEN_RET : number of taken mispredictions branches retired |
| 64 | event:0xe0 counters:0,1 um:zero minimum:500 name:BR_INST_DECODED : number of branch instructions decoded |
| 65 | event:0xe2 counters:0,1 um:zero minimum:500 name:BTB_MISSES : number of branches that miss the BTB |
| 66 | event:0xe4 counters:0,1 um:zero minimum:500 name:BR_BOGUS : number of bogus branches |
| 67 | event:0xe6 counters:0,1 um:zero minimum:500 name:BACLEARS : number of times BACLEAR is asserted |
| 68 | event:0xa2 counters:0,1 um:zero minimum:500 name:RESOURCE_STALLS : cycles during resource related stalls |
| 69 | event:0xd2 counters:0,1 um:zero minimum:500 name:PARTIAL_RAT_STALLS : cycles or events for partial stalls |
| 70 | event:0x06 counters:0,1 um:zero minimum:500 name:SEGMENT_REG_LOADS : number of segment register loads |
| 71 | event:0xb0 counters:0,1 um:zero minimum:3000 name:MMX_INSTR_EXEC : number of MMX instructions executed |
| 72 | event:0xb1 counters:0,1 um:zero minimum:3000 name:MMX_SAT_INSTR_EXEC : number of MMX saturating instructions executed |
| 73 | event:0xb2 counters:0,1 um:mmx_uops minimum:3000 name:MMX_UOPS_EXEC : number of MMX UOPS executed |
| 74 | event:0xb3 counters:0,1 um:mmx_instr_type_exec minimum:3000 name:MMX_INSTR_TYPE_EXEC : number of MMX packing instructions |
| 75 | event:0xcc counters:0,1 um:mmx_trans minimum:3000 name:FP_MMX_TRANS : MMX-floating point transitions |
| 76 | event:0xcd counters:0,1 um:zero minimum:500 name:MMX_ASSIST : number of EMMS instructions executed |
| 77 | event:0xce counters:0,1 um:zero minimum:3000 name:MMX_INSTR_RET : number of MMX instructions retired |
| 78 | event:0xd4 counters:0,1 um:seg_rename minimum:500 name:SEG_RENAME_STALLS : number of segment register renaming stalls |
| 79 | event:0xd5 counters:0,1 um:seg_rename minimum:500 name:SEG_REG_RENAMES : number of segment register renames |
| 80 | event:0xd6 counters:0,1 um:zero minimum:500 name:RET_SEG_RENAMES : number of segment register rename events retired |