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gerrit-public.fairphone.software / fp2-dev / platform / external / oprofile / refs/heads/fp2-sibon / . / daemon / opd_ibs.h
blob: 6f0fd64238c125ec46777b2c4809d67aef36cab6 [file] [log] [blame]
Ben Cheng5a4eb4e2009-09-14 16:00:41 -0700[diff] [blame]1/**
2 * @file daemon/opd_ibs.h
3 * AMD Family10h Instruction Based Sampling (IBS) handling.
4 *
Jeff Brown7a33c862011-02-02 14:00:44 -0800[diff] [blame]5 * @remark Copyright 2008-2010 OProfile authors
Ben Cheng5a4eb4e2009-09-14 16:00:41 -0700[diff] [blame]6 * @remark Read the file COPYING
7 *
8 * @author Jason Yeh <jason.yeh@amd.com>
9 * @author Paul Drongowski <paul.drongowski@amd.com>
10 * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
11 * Copyright (c) 2008 Advanced Micro Devices, Inc.
12 */
13
14#ifndef OPD_IBS_H
15#define OPD_IBS_H
16
17#include <stdint.h>
18
19#include "opd_ibs_macro.h"
20
21struct transient;
22struct opd_event;
23
24/**
25 * IBS information is processed in two steps. The first step decodes
26 * hardware-level IBS information and saves it in decoded form. The
27 * second step translates the decoded IBS information into IBS derived
28 * events. IBS information is tallied and is reported as derived events.
29 */
30
31struct ibs_sample {
32 struct ibs_fetch_sample * fetch;
33 struct ibs_op_sample * op;
34};
35
36/**
37 * This struct represents the hardware-level IBS fetch information.
38 * Each field corresponds to a model-specific register (MSR.) See the
39 * BIOS and Kernel Developer's Guide for AMD Model Family 10h Processors
40 * for further details.
41 */
42struct ibs_fetch_sample {
43 unsigned long int rip;
44 /* MSRC001_1030 IBS Fetch Control Register */
45 unsigned int ibs_fetch_ctl_low;
46 unsigned int ibs_fetch_ctl_high;
47 /* MSRC001_1031 IBS Fetch Linear Address Register */
48 unsigned int ibs_fetch_lin_addr_low;
49 unsigned int ibs_fetch_lin_addr_high;
50 /* MSRC001_1032 IBS Fetch Physical Address Register */
51 unsigned int ibs_fetch_phys_addr_low;
52 unsigned int ibs_fetch_phys_addr_high;
53 unsigned int dummy_event;
54};
55
56
57
58/** This struct represents the hardware-level IBS op information. */
59struct ibs_op_sample {
60 unsigned long int rip;
61 /* MSRC001_1034 IBS Op Logical Address Register */
62 unsigned int ibs_op_lin_addr_low;
63 unsigned int ibs_op_lin_addr_high;
64 /* MSRC001_1035 IBS Op Data Register */
65 unsigned int ibs_op_data1_low;
66 unsigned int ibs_op_data1_high;
67 /* MSRC001_1036 IBS Op Data 2 Register */
68 unsigned int ibs_op_data2_low;
69 unsigned int ibs_op_data2_high;
70 /* MSRC001_1037 IBS Op Data 3 Register */
71 unsigned int ibs_op_data3_low;
72 unsigned int ibs_op_data3_high;
Jeff Brown7a33c862011-02-02 14:00:44 -0800[diff] [blame]73 /* MSRC001_1038 IBS DC Linear Address */
Ben Cheng5a4eb4e2009-09-14 16:00:41 -0700[diff] [blame]74 unsigned int ibs_op_ldst_linaddr_low;
75 unsigned int ibs_op_ldst_linaddr_high;
Jeff Brown7a33c862011-02-02 14:00:44 -0800[diff] [blame]76 /* MSRC001_1039 IBS DC Physical Address */
Ben Cheng5a4eb4e2009-09-14 16:00:41 -0700[diff] [blame]77 unsigned int ibs_op_phys_addr_low;
78 unsigned int ibs_op_phys_addr_high;
Jeff Brown7a33c862011-02-02 14:00:44 -0800[diff] [blame]79 /* MSRC001_103B IBS Branch Target Address */
80 unsigned long ibs_op_brtgt_addr;
Ben Cheng5a4eb4e2009-09-14 16:00:41 -0700[diff] [blame]81};
82
83
84/**
85 * Handle an IBS fetch sample escape code sequence. An IBS fetch sample
86 * is represented as an escape code sequence. (See the comment for the
87 * function code_ibs_op_sample() for the sequence of entries in the event
88 * buffer.) When this function is called, the ESCAPE_CODE and IBS_FETCH_CODE
89 * have already been removed from the event buffer. Thus, 7 more event buffer
90 * entries are needed in order to process a complete IBS fetch sample.
91 */
92extern void code_ibs_fetch_sample(struct transient * trans);
93
94/**
95 * Handle an IBS op sample escape code sequence. An IBS op sample
96 * is represented as an escape code sequence:
97 *
98 * IBS fetch IBS op
99 * --------------- ----------------
100 * ESCAPE_CODE ESCAPE_CODE
101 * IBS_FETCH_CODE IBS_OP_CODE
102 * Offset Offset
103 * IbsFetchLinAd low IbsOpRip low <-- Logical (virtual) RIP
104 * IbsFetchLinAd high IbsOpRip high <-- Logical (virtual) RIP
105 * IbsFetchCtl low IbsOpData low
106 * IbsFetchCtl high IbsOpData high
107 * IbsFetchPhysAd low IbsOpData2 low
108 * IbsFetchPhysAd high IbsOpData2 high
109 * IbsOpData3 low
110 * IbsOpData3 high
111 * IbsDcLinAd low
112 * IbsDcLinAd high
113 * IbsDcPhysAd low
114 * IbsDcPhysAd high
115 *
116 * When this function is called, the ESCAPE_CODE and IBS_OP_CODE have
117 * already been removed from the event buffer. Thus, 13 more event buffer
118 * entries are needed to process a complete IBS op sample.
119 *
120 * The IbsFetchLinAd and IbsOpRip are the linear (virtual) addresses
121 * that were generated by the IBS hardware. These addresses are mapped
122 * into the offset.
123 */
124extern void code_ibs_op_sample(struct transient * trans);
125
126/** Log the specified IBS derived event. */
127extern void opd_log_ibs_event(unsigned int event, struct transient * trans);
128
129/** Log the specified IBS cycle count. */
130extern void opd_log_ibs_count(unsigned int event, struct transient * trans, unsigned int count);
131
132
133#endif /*OPD_IBS_H*/