The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 1 | /* |
| 2 | * ARM virtual CPU header |
| 3 | * |
| 4 | * Copyright (c) 2003 Fabrice Bellard |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
David Turner | 6a9ef17 | 2010-09-09 22:54:36 +0200 | [diff] [blame^] | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 18 | */ |
| 19 | #ifndef CPU_ARM_H |
| 20 | #define CPU_ARM_H |
| 21 | |
| 22 | #define TARGET_LONG_BITS 32 |
| 23 | |
| 24 | #define ELF_MACHINE EM_ARM |
| 25 | |
David 'Digit' Turner | 5d8f37a | 2009-09-14 14:32:27 -0700 | [diff] [blame] | 26 | #define CPUState struct CPUARMState |
| 27 | |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 28 | #include "cpu-defs.h" |
| 29 | |
| 30 | #include "softfloat.h" |
| 31 | |
| 32 | #define TARGET_HAS_ICE 1 |
| 33 | |
| 34 | #define EXCP_UDEF 1 /* undefined instruction */ |
| 35 | #define EXCP_SWI 2 /* software interrupt */ |
| 36 | #define EXCP_PREFETCH_ABORT 3 |
| 37 | #define EXCP_DATA_ABORT 4 |
| 38 | #define EXCP_IRQ 5 |
| 39 | #define EXCP_FIQ 6 |
| 40 | #define EXCP_BKPT 7 |
| 41 | #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ |
| 42 | #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ |
David Turner | 6a9ef17 | 2010-09-09 22:54:36 +0200 | [diff] [blame^] | 43 | #define EXCP_STREX 10 |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 44 | |
| 45 | #define ARMV7M_EXCP_RESET 1 |
| 46 | #define ARMV7M_EXCP_NMI 2 |
| 47 | #define ARMV7M_EXCP_HARD 3 |
| 48 | #define ARMV7M_EXCP_MEM 4 |
| 49 | #define ARMV7M_EXCP_BUS 5 |
| 50 | #define ARMV7M_EXCP_USAGE 6 |
| 51 | #define ARMV7M_EXCP_SVC 11 |
| 52 | #define ARMV7M_EXCP_DEBUG 12 |
| 53 | #define ARMV7M_EXCP_PENDSV 14 |
| 54 | #define ARMV7M_EXCP_SYSTICK 15 |
| 55 | |
| 56 | typedef void ARMWriteCPFunc(void *opaque, int cp_info, |
| 57 | int srcreg, int operand, uint32_t value); |
| 58 | typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info, |
| 59 | int dstreg, int operand); |
| 60 | |
| 61 | struct arm_boot_info; |
| 62 | |
| 63 | #define NB_MMU_MODES 2 |
| 64 | |
| 65 | /* We currently assume float and double are IEEE single and double |
| 66 | precision respectively. |
| 67 | Doing runtime conversions is tricky because VFP registers may contain |
| 68 | integer values (eg. as the result of a FTOSI instruction). |
| 69 | s<2n> maps to the least significant half of d<n> |
| 70 | s<2n+1> maps to the most significant half of d<n> |
| 71 | */ |
| 72 | |
| 73 | typedef struct CPUARMState { |
| 74 | /* Regs for current mode. */ |
| 75 | uint32_t regs[16]; |
| 76 | /* Frequently accessed CPSR bits are stored separately for efficiently. |
| 77 | This contains all the other bits. Use cpsr_{read,write} to access |
| 78 | the whole CPSR. */ |
| 79 | uint32_t uncached_cpsr; |
| 80 | uint32_t spsr; |
| 81 | |
| 82 | /* Banked registers. */ |
| 83 | uint32_t banked_spsr[6]; |
| 84 | uint32_t banked_r13[6]; |
| 85 | uint32_t banked_r14[6]; |
| 86 | |
| 87 | /* These hold r8-r12. */ |
| 88 | uint32_t usr_regs[5]; |
| 89 | uint32_t fiq_regs[5]; |
| 90 | |
| 91 | /* cpsr flag cache for faster execution */ |
| 92 | uint32_t CF; /* 0 or 1 */ |
| 93 | uint32_t VF; /* V is the bit 31. All other bits are undefined */ |
| 94 | uint32_t NF; /* N is bit 31. All other bits are undefined. */ |
| 95 | uint32_t ZF; /* Z set if zero. */ |
| 96 | uint32_t QF; /* 0 or 1 */ |
| 97 | uint32_t GE; /* cpsr[19:16] */ |
| 98 | uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ |
| 99 | uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ |
| 100 | |
| 101 | /* System control coprocessor (cp15) */ |
| 102 | struct { |
| 103 | uint32_t c0_cpuid; |
| 104 | uint32_t c0_cachetype; |
David 'Digit' Turner | 5d8f37a | 2009-09-14 14:32:27 -0700 | [diff] [blame] | 105 | uint32_t c0_ccsid[16]; /* Cache size. */ |
| 106 | uint32_t c0_clid; /* Cache level. */ |
| 107 | uint32_t c0_cssel; /* Cache size selection. */ |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 108 | uint32_t c0_c1[8]; /* Feature registers. */ |
| 109 | uint32_t c0_c2[8]; /* Instruction set registers. */ |
| 110 | uint32_t c1_sys; /* System control register. */ |
| 111 | uint32_t c1_coproc; /* Coprocessor access register. */ |
| 112 | uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ |
| 113 | uint32_t c2_base0; /* MMU translation table base 0. */ |
| 114 | uint32_t c2_base1; /* MMU translation table base 1. */ |
David 'Digit' Turner | 5d8f37a | 2009-09-14 14:32:27 -0700 | [diff] [blame] | 115 | uint32_t c2_control; /* MMU translation table base control. */ |
| 116 | uint32_t c2_mask; /* MMU translation table base selection mask. */ |
| 117 | uint32_t c2_base_mask; /* MMU translation table base 0 mask. */ |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 118 | uint32_t c2_data; /* MPU data cachable bits. */ |
| 119 | uint32_t c2_insn; /* MPU instruction cachable bits. */ |
| 120 | uint32_t c3; /* MMU domain access control register |
| 121 | MPU write buffer control. */ |
| 122 | uint32_t c5_insn; /* Fault status registers. */ |
| 123 | uint32_t c5_data; |
| 124 | uint32_t c6_region[8]; /* MPU base/size registers. */ |
| 125 | uint32_t c6_insn; /* Fault address registers. */ |
| 126 | uint32_t c6_data; |
| 127 | uint32_t c9_insn; /* Cache lockdown registers. */ |
| 128 | uint32_t c9_data; |
| 129 | uint32_t c13_fcse; /* FCSE PID. */ |
| 130 | uint32_t c13_context; /* Context ID. */ |
| 131 | uint32_t c13_tls1; /* User RW Thread register. */ |
| 132 | uint32_t c13_tls2; /* User RO Thread register. */ |
| 133 | uint32_t c13_tls3; /* Privileged Thread register. */ |
| 134 | uint32_t c15_cpar; /* XScale Coprocessor Access Register */ |
| 135 | uint32_t c15_ticonfig; /* TI925T configuration byte. */ |
| 136 | uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ |
| 137 | uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ |
| 138 | uint32_t c15_threadid; /* TI debugger thread-ID. */ |
| 139 | } cp15; |
| 140 | |
| 141 | struct { |
| 142 | uint32_t other_sp; |
| 143 | uint32_t vecbase; |
| 144 | uint32_t basepri; |
| 145 | uint32_t control; |
| 146 | int current_sp; |
| 147 | int exception; |
| 148 | int pending_exception; |
| 149 | void *nvic; |
| 150 | } v7m; |
| 151 | |
| 152 | /* Coprocessor IO used by peripherals */ |
| 153 | struct { |
| 154 | ARMReadCPFunc *cp_read; |
| 155 | ARMWriteCPFunc *cp_write; |
| 156 | void *opaque; |
| 157 | } cp[15]; |
| 158 | |
David 'Digit' Turner | 5d8f37a | 2009-09-14 14:32:27 -0700 | [diff] [blame] | 159 | /* Thumb-2 EE state. */ |
| 160 | uint32_t teecr; |
| 161 | uint32_t teehbr; |
| 162 | |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 163 | /* Internal CPU feature flags. */ |
| 164 | uint32_t features; |
| 165 | |
| 166 | /* Callback for vectored interrupt controller. */ |
| 167 | int (*get_irq_vector)(struct CPUARMState *); |
| 168 | void *irq_opaque; |
| 169 | |
| 170 | /* VFP coprocessor state. */ |
| 171 | struct { |
| 172 | float64 regs[32]; |
| 173 | |
| 174 | uint32_t xregs[16]; |
| 175 | /* We store these fpcsr fields separately for convenience. */ |
| 176 | int vec_len; |
| 177 | int vec_stride; |
| 178 | |
| 179 | /* scratch space when Tn are not sufficient. */ |
| 180 | uint32_t scratch[8]; |
| 181 | |
| 182 | float_status fp_status; |
| 183 | } vfp; |
| 184 | #if defined(CONFIG_USER_ONLY) |
| 185 | struct mmon_state *mmon_entry; |
| 186 | #else |
| 187 | uint32_t mmon_addr; |
| 188 | #endif |
| 189 | |
| 190 | /* iwMMXt coprocessor state. */ |
| 191 | struct { |
| 192 | uint64_t regs[16]; |
| 193 | uint64_t val; |
| 194 | |
| 195 | uint32_t cregs[16]; |
| 196 | } iwmmxt; |
| 197 | |
| 198 | #if defined(CONFIG_USER_ONLY) |
| 199 | /* For usermode syscall translation. */ |
| 200 | int eabi; |
| 201 | #endif |
| 202 | |
| 203 | CPU_COMMON |
| 204 | |
| 205 | /* These fields after the common ones so they are preserved on reset. */ |
| 206 | struct arm_boot_info *boot_info; |
| 207 | } CPUARMState; |
| 208 | |
| 209 | CPUARMState *cpu_arm_init(const char *cpu_model); |
| 210 | void arm_translate_init(void); |
| 211 | int cpu_arm_exec(CPUARMState *s); |
| 212 | void cpu_arm_close(CPUARMState *s); |
| 213 | void do_interrupt(CPUARMState *); |
| 214 | void switch_mode(CPUARMState *, int); |
| 215 | uint32_t do_arm_semihosting(CPUARMState *env); |
| 216 | |
| 217 | /* you can call this signal handler from your SIGBUS and SIGSEGV |
| 218 | signal handlers to inform the virtual CPU of exceptions. non zero |
| 219 | is returned if the signal was handled by the virtual CPU. */ |
| 220 | int cpu_arm_signal_handler(int host_signum, void *pinfo, |
| 221 | void *puc); |
David 'Digit' Turner | 5d8f37a | 2009-09-14 14:32:27 -0700 | [diff] [blame] | 222 | int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw, |
| 223 | int mmu_idx, int is_softmuu); |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 224 | |
| 225 | void cpu_lock(void); |
| 226 | void cpu_unlock(void); |
| 227 | static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls) |
| 228 | { |
| 229 | env->cp15.c13_tls2 = newtls; |
| 230 | } |
| 231 | |
| 232 | #define CPSR_M (0x1f) |
| 233 | #define CPSR_T (1 << 5) |
| 234 | #define CPSR_F (1 << 6) |
| 235 | #define CPSR_I (1 << 7) |
| 236 | #define CPSR_A (1 << 8) |
| 237 | #define CPSR_E (1 << 9) |
| 238 | #define CPSR_IT_2_7 (0xfc00) |
| 239 | #define CPSR_GE (0xf << 16) |
| 240 | #define CPSR_RESERVED (0xf << 20) |
| 241 | #define CPSR_J (1 << 24) |
| 242 | #define CPSR_IT_0_1 (3 << 25) |
| 243 | #define CPSR_Q (1 << 27) |
| 244 | #define CPSR_V (1 << 28) |
| 245 | #define CPSR_C (1 << 29) |
| 246 | #define CPSR_Z (1 << 30) |
| 247 | #define CPSR_N (1 << 31) |
| 248 | #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) |
| 249 | |
| 250 | #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) |
| 251 | #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV) |
| 252 | /* Bits writable in user mode. */ |
| 253 | #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) |
| 254 | /* Execution state bits. MRS read as zero, MSR writes ignored. */ |
| 255 | #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J) |
| 256 | |
| 257 | /* Return the current CPSR value. */ |
| 258 | uint32_t cpsr_read(CPUARMState *env); |
| 259 | /* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */ |
| 260 | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask); |
| 261 | |
| 262 | /* Return the current xPSR value. */ |
| 263 | static inline uint32_t xpsr_read(CPUARMState *env) |
| 264 | { |
| 265 | int ZF; |
| 266 | ZF = (env->ZF == 0); |
| 267 | return (env->NF & 0x80000000) | (ZF << 30) |
| 268 | | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
| 269 | | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) |
| 270 | | ((env->condexec_bits & 0xfc) << 8) |
| 271 | | env->v7m.exception; |
| 272 | } |
| 273 | |
| 274 | /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ |
| 275 | static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) |
| 276 | { |
| 277 | if (mask & CPSR_NZCV) { |
| 278 | env->ZF = (~val) & CPSR_Z; |
| 279 | env->NF = val; |
| 280 | env->CF = (val >> 29) & 1; |
| 281 | env->VF = (val << 3) & 0x80000000; |
| 282 | } |
| 283 | if (mask & CPSR_Q) |
| 284 | env->QF = ((val & CPSR_Q) != 0); |
| 285 | if (mask & (1 << 24)) |
| 286 | env->thumb = ((val & (1 << 24)) != 0); |
| 287 | if (mask & CPSR_IT_0_1) { |
| 288 | env->condexec_bits &= ~3; |
| 289 | env->condexec_bits |= (val >> 25) & 3; |
| 290 | } |
| 291 | if (mask & CPSR_IT_2_7) { |
| 292 | env->condexec_bits &= 3; |
| 293 | env->condexec_bits |= (val >> 8) & 0xfc; |
| 294 | } |
| 295 | if (mask & 0x1ff) { |
| 296 | env->v7m.exception = val & 0x1ff; |
| 297 | } |
| 298 | } |
| 299 | |
| 300 | enum arm_cpu_mode { |
| 301 | ARM_CPU_MODE_USR = 0x10, |
| 302 | ARM_CPU_MODE_FIQ = 0x11, |
| 303 | ARM_CPU_MODE_IRQ = 0x12, |
| 304 | ARM_CPU_MODE_SVC = 0x13, |
| 305 | ARM_CPU_MODE_ABT = 0x17, |
| 306 | ARM_CPU_MODE_UND = 0x1b, |
| 307 | ARM_CPU_MODE_SYS = 0x1f |
| 308 | }; |
| 309 | |
| 310 | /* VFP system registers. */ |
| 311 | #define ARM_VFP_FPSID 0 |
| 312 | #define ARM_VFP_FPSCR 1 |
| 313 | #define ARM_VFP_MVFR1 6 |
| 314 | #define ARM_VFP_MVFR0 7 |
| 315 | #define ARM_VFP_FPEXC 8 |
| 316 | #define ARM_VFP_FPINST 9 |
| 317 | #define ARM_VFP_FPINST2 10 |
| 318 | |
| 319 | /* iwMMXt coprocessor control registers. */ |
| 320 | #define ARM_IWMMXT_wCID 0 |
| 321 | #define ARM_IWMMXT_wCon 1 |
| 322 | #define ARM_IWMMXT_wCSSF 2 |
| 323 | #define ARM_IWMMXT_wCASF 3 |
| 324 | #define ARM_IWMMXT_wCGR0 8 |
| 325 | #define ARM_IWMMXT_wCGR1 9 |
| 326 | #define ARM_IWMMXT_wCGR2 10 |
| 327 | #define ARM_IWMMXT_wCGR3 11 |
| 328 | |
| 329 | enum arm_features { |
| 330 | ARM_FEATURE_VFP, |
| 331 | ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ |
| 332 | ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ |
| 333 | ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ |
| 334 | ARM_FEATURE_V6, |
| 335 | ARM_FEATURE_V6K, |
| 336 | ARM_FEATURE_V7, |
| 337 | ARM_FEATURE_THUMB2, |
| 338 | ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */ |
| 339 | ARM_FEATURE_VFP3, |
| 340 | ARM_FEATURE_NEON, |
| 341 | ARM_FEATURE_DIV, |
| 342 | ARM_FEATURE_M, /* Microcontroller profile. */ |
David 'Digit' Turner | 5d8f37a | 2009-09-14 14:32:27 -0700 | [diff] [blame] | 343 | ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ |
| 344 | ARM_FEATURE_THUMB2EE |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 345 | }; |
| 346 | |
| 347 | static inline int arm_feature(CPUARMState *env, int feature) |
| 348 | { |
| 349 | return (env->features & (1u << feature)) != 0; |
| 350 | } |
| 351 | |
| 352 | void arm_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
| 353 | |
| 354 | /* Interface between CPU and Interrupt controller. */ |
| 355 | void armv7m_nvic_set_pending(void *opaque, int irq); |
| 356 | int armv7m_nvic_acknowledge_irq(void *opaque); |
| 357 | void armv7m_nvic_complete_irq(void *opaque, int irq); |
| 358 | |
| 359 | void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, |
| 360 | ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write, |
| 361 | void *opaque); |
| 362 | |
| 363 | /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3. |
| 364 | Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are |
| 365 | conventional cores (ie. Application or Realtime profile). */ |
| 366 | |
| 367 | #define IS_M(env) arm_feature(env, ARM_FEATURE_M) |
| 368 | #define ARM_CPUID(env) (env->cp15.c0_cpuid) |
| 369 | |
| 370 | #define ARM_CPUID_ARM1026 0x4106a262 |
| 371 | #define ARM_CPUID_ARM926 0x41069265 |
| 372 | #define ARM_CPUID_ARM946 0x41059461 |
| 373 | #define ARM_CPUID_TI915T 0x54029152 |
| 374 | #define ARM_CPUID_TI925T 0x54029252 |
| 375 | #define ARM_CPUID_PXA250 0x69052100 |
| 376 | #define ARM_CPUID_PXA255 0x69052d00 |
| 377 | #define ARM_CPUID_PXA260 0x69052903 |
| 378 | #define ARM_CPUID_PXA261 0x69052d05 |
| 379 | #define ARM_CPUID_PXA262 0x69052d06 |
| 380 | #define ARM_CPUID_PXA270 0x69054110 |
| 381 | #define ARM_CPUID_PXA270_A0 0x69054110 |
| 382 | #define ARM_CPUID_PXA270_A1 0x69054111 |
| 383 | #define ARM_CPUID_PXA270_B0 0x69054112 |
| 384 | #define ARM_CPUID_PXA270_B1 0x69054113 |
| 385 | #define ARM_CPUID_PXA270_C0 0x69054114 |
| 386 | #define ARM_CPUID_PXA270_C5 0x69054117 |
| 387 | #define ARM_CPUID_ARM1136 0x4117b363 |
| 388 | #define ARM_CPUID_ARM1136_R2 0x4107b362 |
| 389 | #define ARM_CPUID_ARM11MPCORE 0x410fb022 |
| 390 | #define ARM_CPUID_CORTEXA8 0x410fc080 |
David Turner | 6a9ef17 | 2010-09-09 22:54:36 +0200 | [diff] [blame^] | 391 | #define ARM_CPUID_CORTEXA9 0x410fc090 |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 392 | #define ARM_CPUID_CORTEXM3 0x410fc231 |
| 393 | #define ARM_CPUID_ANY 0xffffffff |
| 394 | |
| 395 | #if defined(CONFIG_USER_ONLY) |
| 396 | #define TARGET_PAGE_BITS 12 |
| 397 | #else |
| 398 | /* The ARM MMU allows 1k pages. */ |
| 399 | /* ??? Linux doesn't actually use these, and they're deprecated in recent |
| 400 | architecture revisions. Maybe a configure option to disable them. */ |
| 401 | #define TARGET_PAGE_BITS 10 |
| 402 | #endif |
| 403 | |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 404 | #define cpu_init cpu_arm_init |
| 405 | #define cpu_exec cpu_arm_exec |
| 406 | #define cpu_gen_code cpu_arm_gen_code |
| 407 | #define cpu_signal_handler cpu_arm_signal_handler |
| 408 | #define cpu_list arm_cpu_list |
| 409 | |
| 410 | #define CPU_SAVE_VERSION 1 |
| 411 | |
| 412 | /* MMU modes definitions */ |
| 413 | #define MMU_MODE0_SUFFIX _kernel |
| 414 | #define MMU_MODE1_SUFFIX _user |
| 415 | #define MMU_USER_IDX 1 |
| 416 | static inline int cpu_mmu_index (CPUState *env) |
| 417 | { |
| 418 | return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0; |
| 419 | } |
| 420 | |
Vladimir Chtchetkine | 5389aa1 | 2010-02-16 10:38:35 -0800 | [diff] [blame] | 421 | static inline int is_cpu_user (CPUState *env) |
| 422 | { |
| 423 | #ifdef CONFIG_USER_ONLY |
| 424 | return 1; |
| 425 | #else |
| 426 | return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR; |
| 427 | #endif // CONFIG_USER_ONLY |
| 428 | } |
| 429 | |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 430 | #if defined(CONFIG_USER_ONLY) |
| 431 | static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) |
| 432 | { |
| 433 | if (newsp) |
| 434 | env->regs[13] = newsp; |
| 435 | env->regs[0] = 0; |
| 436 | } |
| 437 | #endif |
| 438 | |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 439 | #include "cpu-all.h" |
David 'Digit' Turner | 5d8f37a | 2009-09-14 14:32:27 -0700 | [diff] [blame] | 440 | #include "exec-all.h" |
| 441 | |
| 442 | static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) |
| 443 | { |
| 444 | env->regs[15] = tb->pc; |
| 445 | } |
| 446 | |
| 447 | static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
| 448 | target_ulong *cs_base, int *flags) |
| 449 | { |
| 450 | *pc = env->regs[15]; |
| 451 | *cs_base = 0; |
| 452 | *flags = env->thumb | (env->vfp.vec_len << 1) |
| 453 | | (env->vfp.vec_stride << 4) | (env->condexec_bits << 8); |
| 454 | if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) |
| 455 | *flags |= (1 << 6); |
| 456 | if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) |
| 457 | *flags |= (1 << 7); |
| 458 | } |
The Android Open Source Project | 8b23a6c | 2009-03-03 19:30:32 -0800 | [diff] [blame] | 459 | |
| 460 | #endif |