Bhanu Chetlapalli | 409c7b6 | 2012-01-31 16:25:04 -0800 | [diff] [blame] | 1 | #if !defined (__MIPS_CPU_H__) |
| 2 | #define __MIPS_CPU_H__ |
| 3 | |
David 'Digit' Turner | 26a8fb6 | 2014-01-15 14:37:21 +0100 | [diff] [blame] | 4 | //#define DEBUG_OP |
| 5 | |
Bhanu Chetlapalli | 409c7b6 | 2012-01-31 16:25:04 -0800 | [diff] [blame] | 6 | #define TARGET_HAS_ICE 1 |
| 7 | |
| 8 | #define ELF_MACHINE EM_MIPS |
| 9 | |
David 'Digit' Turner | 26a8fb6 | 2014-01-15 14:37:21 +0100 | [diff] [blame] | 10 | // TODO(digit): Remove this define. |
David 'Digit' Turner | e2678e1 | 2014-01-16 15:56:43 +0100 | [diff] [blame] | 11 | #define CPUOldState struct CPUMIPSState |
Bhanu Chetlapalli | 409c7b6 | 2012-01-31 16:25:04 -0800 | [diff] [blame] | 12 | |
David 'Digit' Turner | 26a8fb6 | 2014-01-15 14:37:21 +0100 | [diff] [blame] | 13 | #define CPUArchState struct CPUMIPSState |
| 14 | |
Bhanu Chetlapalli | 409c7b6 | 2012-01-31 16:25:04 -0800 | [diff] [blame] | 15 | #include "config.h" |
David 'Digit' Turner | 26a8fb6 | 2014-01-15 14:37:21 +0100 | [diff] [blame] | 16 | #include "qemu-common.h" |
Bhanu Chetlapalli | 409c7b6 | 2012-01-31 16:25:04 -0800 | [diff] [blame] | 17 | #include "mips-defs.h" |
David 'Digit' Turner | 852088c | 2013-12-14 23:04:12 +0100 | [diff] [blame] | 18 | #include "exec/cpu-defs.h" |
David 'Digit' Turner | 5425d40 | 2013-12-15 00:28:46 +0100 | [diff] [blame] | 19 | #include "fpu/softfloat.h" |
Bhanu Chetlapalli | 409c7b6 | 2012-01-31 16:25:04 -0800 | [diff] [blame] | 20 | |
| 21 | // uint_fast8_t and uint_fast16_t not in <sys/int_types.h> |
| 22 | // XXX: move that elsewhere |
| 23 | #if defined(CONFIG_SOLARIS) && CONFIG_SOLARIS_VERSION < 10 |
| 24 | typedef unsigned char uint_fast8_t; |
| 25 | typedef unsigned int uint_fast16_t; |
| 26 | #endif |
| 27 | |
| 28 | struct CPUMIPSState; |
| 29 | |
| 30 | typedef struct r4k_tlb_t r4k_tlb_t; |
| 31 | struct r4k_tlb_t { |
| 32 | target_ulong VPN; |
| 33 | uint32_t PageMask; |
| 34 | uint_fast8_t ASID; |
| 35 | uint_fast16_t G:1; |
| 36 | uint_fast16_t C0:3; |
| 37 | uint_fast16_t C1:3; |
| 38 | uint_fast16_t V0:1; |
| 39 | uint_fast16_t V1:1; |
| 40 | uint_fast16_t D0:1; |
| 41 | uint_fast16_t D1:1; |
| 42 | target_ulong PFN[2]; |
| 43 | }; |
| 44 | |
David 'Digit' Turner | 26a8fb6 | 2014-01-15 14:37:21 +0100 | [diff] [blame] | 45 | #if !defined(CONFIG_USER_ONLY) |
Bhanu Chetlapalli | 409c7b6 | 2012-01-31 16:25:04 -0800 | [diff] [blame] | 46 | typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; |
| 47 | struct CPUMIPSTLBContext { |
| 48 | uint32_t nb_tlb; |
David 'Digit' Turner | bcde109 | 2014-01-09 23:19:19 +0100 | [diff] [blame] | 49 | int (*map_address) (struct CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int access_type); |
David 'Digit' Turner | 758fa08 | 2014-04-03 12:29:21 +0200 | [diff] [blame] | 50 | void (*helper_tlbwi)(struct CPUMIPSState *env); |
| 51 | void (*helper_tlbwr)(struct CPUMIPSState *env); |
| 52 | void (*helper_tlbp)(struct CPUMIPSState *env); |
| 53 | void (*helper_tlbr)(struct CPUMIPSState *env); |
Bhanu Chetlapalli | 409c7b6 | 2012-01-31 16:25:04 -0800 | [diff] [blame] | 54 | union { |
| 55 | struct { |
| 56 | r4k_tlb_t tlb[MIPS_TLB_MAX]; |
| 57 | } r4k; |
| 58 | } mmu; |
| 59 | }; |
David 'Digit' Turner | 26a8fb6 | 2014-01-15 14:37:21 +0100 | [diff] [blame] | 60 | #endif |
Bhanu Chetlapalli | 409c7b6 | 2012-01-31 16:25:04 -0800 | [diff] [blame] | 61 | |
| 62 | typedef union fpr_t fpr_t; |
| 63 | union fpr_t { |
| 64 | float64 fd; /* ieee double precision */ |
| 65 | float32 fs[2];/* ieee single precision */ |
| 66 | uint64_t d; /* binary double fixed-point */ |
| 67 | uint32_t w[2]; /* binary single fixed-point */ |
| 68 | }; |
| 69 | /* define FP_ENDIAN_IDX to access the same location |
David 'Digit' Turner | 26a8fb6 | 2014-01-15 14:37:21 +0100 | [diff] [blame] | 70 | * in the fpr_t union regardless of the host endianness |
Bhanu Chetlapalli | 409c7b6 | 2012-01-31 16:25:04 -0800 | [diff] [blame] | 71 | */ |
| 72 | #if defined(HOST_WORDS_BIGENDIAN) |
| 73 | # define FP_ENDIAN_IDX 1 |
| 74 | #else |
| 75 | # define FP_ENDIAN_IDX 0 |
| 76 | #endif |
| 77 | |
| 78 | typedef struct CPUMIPSFPUContext CPUMIPSFPUContext; |
| 79 | struct CPUMIPSFPUContext { |
| 80 | /* Floating point registers */ |
| 81 | fpr_t fpr[32]; |
| 82 | float_status fp_status; |
| 83 | /* fpu implementation/revision register (fir) */ |
| 84 | uint32_t fcr0; |
| 85 | #define FCR0_F64 22 |
| 86 | #define FCR0_L 21 |
| 87 | #define FCR0_W 20 |
| 88 | #define FCR0_3D 19 |
| 89 | #define FCR0_PS 18 |
| 90 | #define FCR0_D 17 |
| 91 | #define FCR0_S 16 |
| 92 | #define FCR0_PRID 8 |
| 93 | #define FCR0_REV 0 |
| 94 | /* fcsr */ |
| 95 | uint32_t fcr31; |
| 96 | #define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) |
| 97 | #define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) |
| 98 | #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1)) |
| 99 | #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) |
| 100 | #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) |
| 101 | #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) |
| 102 | #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0) |
| 103 | #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0) |
| 104 | #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0) |
| 105 | #define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0) |
| 106 | #define FP_INEXACT 1 |
| 107 | #define FP_UNDERFLOW 2 |
| 108 | #define FP_OVERFLOW 4 |
| 109 | #define FP_DIV0 8 |
| 110 | #define FP_INVALID 16 |
| 111 | #define FP_UNIMPLEMENTED 32 |
| 112 | }; |
| 113 | |
| 114 | #define NB_MMU_MODES 3 |
| 115 | |
| 116 | typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; |
| 117 | struct CPUMIPSMVPContext { |
| 118 | int32_t CP0_MVPControl; |
| 119 | #define CP0MVPCo_CPA 3 |
| 120 | #define CP0MVPCo_STLB 2 |
| 121 | #define CP0MVPCo_VPC 1 |
| 122 | #define CP0MVPCo_EVP 0 |
| 123 | int32_t CP0_MVPConf0; |
| 124 | #define CP0MVPC0_M 31 |
| 125 | #define CP0MVPC0_TLBS 29 |
| 126 | #define CP0MVPC0_GS 28 |
| 127 | #define CP0MVPC0_PCP 27 |
| 128 | #define CP0MVPC0_PTLBE 16 |
| 129 | #define CP0MVPC0_TCA 15 |
| 130 | #define CP0MVPC0_PVPE 10 |
| 131 | #define CP0MVPC0_PTC 0 |
| 132 | int32_t CP0_MVPConf1; |
| 133 | #define CP0MVPC1_CIM 31 |
| 134 | #define CP0MVPC1_CIF 30 |
| 135 | #define CP0MVPC1_PCX 20 |
| 136 | #define CP0MVPC1_PCP2 10 |
| 137 | #define CP0MVPC1_PCP1 0 |
| 138 | }; |
| 139 | |
| 140 | typedef struct mips_def_t mips_def_t; |
| 141 | |
| 142 | #define MIPS_SHADOW_SET_MAX 16 |
| 143 | #define MIPS_TC_MAX 5 |
| 144 | #define MIPS_FPU_MAX 1 |
| 145 | #define MIPS_DSP_ACC 4 |
| 146 | |
| 147 | typedef struct TCState TCState; |
| 148 | struct TCState { |
| 149 | target_ulong gpr[32]; |
| 150 | target_ulong PC; |
| 151 | target_ulong HI[MIPS_DSP_ACC]; |
| 152 | target_ulong LO[MIPS_DSP_ACC]; |
| 153 | target_ulong ACX[MIPS_DSP_ACC]; |
| 154 | target_ulong DSPControl; |
| 155 | int32_t CP0_TCStatus; |
| 156 | #define CP0TCSt_TCU3 31 |
| 157 | #define CP0TCSt_TCU2 30 |
| 158 | #define CP0TCSt_TCU1 29 |
| 159 | #define CP0TCSt_TCU0 28 |
| 160 | #define CP0TCSt_TMX 27 |
| 161 | #define CP0TCSt_RNST 23 |
| 162 | #define CP0TCSt_TDS 21 |
| 163 | #define CP0TCSt_DT 20 |
| 164 | #define CP0TCSt_DA 15 |
| 165 | #define CP0TCSt_A 13 |
| 166 | #define CP0TCSt_TKSU 11 |
| 167 | #define CP0TCSt_IXMT 10 |
| 168 | #define CP0TCSt_TASID 0 |
| 169 | int32_t CP0_TCBind; |
| 170 | #define CP0TCBd_CurTC 21 |
| 171 | #define CP0TCBd_TBE 17 |
| 172 | #define CP0TCBd_CurVPE 0 |
| 173 | target_ulong CP0_TCHalt; |
| 174 | target_ulong CP0_TCContext; |
| 175 | target_ulong CP0_TCSchedule; |
| 176 | target_ulong CP0_TCScheFBack; |
| 177 | int32_t CP0_Debug_tcstatus; |
| 178 | }; |
| 179 | |
| 180 | typedef struct CPUMIPSState CPUMIPSState; |
| 181 | struct CPUMIPSState { |
| 182 | TCState active_tc; |
| 183 | CPUMIPSFPUContext active_fpu; |
| 184 | |
| 185 | uint32_t current_tc; |
| 186 | uint32_t current_fpu; |
| 187 | |
| 188 | uint32_t SEGBITS; |
| 189 | uint32_t PABITS; |
| 190 | target_ulong SEGMask; |
| 191 | target_ulong PAMask; |
| 192 | |
| 193 | int32_t CP0_Index; |
| 194 | /* CP0_MVP* are per MVP registers. */ |
| 195 | int32_t CP0_Random; |
| 196 | int32_t CP0_VPEControl; |
| 197 | #define CP0VPECo_YSI 21 |
| 198 | #define CP0VPECo_GSI 20 |
| 199 | #define CP0VPECo_EXCPT 16 |
| 200 | #define CP0VPECo_TE 15 |
| 201 | #define CP0VPECo_TargTC 0 |
| 202 | int32_t CP0_VPEConf0; |
| 203 | #define CP0VPEC0_M 31 |
| 204 | #define CP0VPEC0_XTC 21 |
| 205 | #define CP0VPEC0_TCS 19 |
| 206 | #define CP0VPEC0_SCS 18 |
| 207 | #define CP0VPEC0_DSC 17 |
| 208 | #define CP0VPEC0_ICS 16 |
| 209 | #define CP0VPEC0_MVP 1 |
| 210 | #define CP0VPEC0_VPA 0 |
| 211 | int32_t CP0_VPEConf1; |
| 212 | #define CP0VPEC1_NCX 20 |
| 213 | #define CP0VPEC1_NCP2 10 |
| 214 | #define CP0VPEC1_NCP1 0 |
| 215 | target_ulong CP0_YQMask; |
| 216 | target_ulong CP0_VPESchedule; |
| 217 | target_ulong CP0_VPEScheFBack; |
| 218 | int32_t CP0_VPEOpt; |
| 219 | #define CP0VPEOpt_IWX7 15 |
| 220 | #define CP0VPEOpt_IWX6 14 |
| 221 | #define CP0VPEOpt_IWX5 13 |
| 222 | #define CP0VPEOpt_IWX4 12 |
| 223 | #define CP0VPEOpt_IWX3 11 |
| 224 | #define CP0VPEOpt_IWX2 10 |
| 225 | #define CP0VPEOpt_IWX1 9 |
| 226 | #define CP0VPEOpt_IWX0 8 |
| 227 | #define CP0VPEOpt_DWX7 7 |
| 228 | #define CP0VPEOpt_DWX6 6 |
| 229 | #define CP0VPEOpt_DWX5 5 |
| 230 | #define CP0VPEOpt_DWX4 4 |
| 231 | #define CP0VPEOpt_DWX3 3 |
| 232 | #define CP0VPEOpt_DWX2 2 |
| 233 | #define CP0VPEOpt_DWX1 1 |
| 234 | #define CP0VPEOpt_DWX0 0 |
| 235 | target_ulong CP0_EntryLo0; |
| 236 | target_ulong CP0_EntryLo1; |
| 237 | target_ulong CP0_Context; |
| 238 | int32_t CP0_PageMask; |
| 239 | int32_t CP0_PageGrain; |
| 240 | int32_t CP0_Wired; |
| 241 | int32_t CP0_SRSConf0_rw_bitmask; |
| 242 | int32_t CP0_SRSConf0; |
| 243 | #define CP0SRSC0_M 31 |
| 244 | #define CP0SRSC0_SRS3 20 |
| 245 | #define CP0SRSC0_SRS2 10 |
| 246 | #define CP0SRSC0_SRS1 0 |
| 247 | int32_t CP0_SRSConf1_rw_bitmask; |
| 248 | int32_t CP0_SRSConf1; |
| 249 | #define CP0SRSC1_M 31 |
| 250 | #define CP0SRSC1_SRS6 20 |
| 251 | #define CP0SRSC1_SRS5 10 |
| 252 | #define CP0SRSC1_SRS4 0 |
| 253 | int32_t CP0_SRSConf2_rw_bitmask; |
| 254 | int32_t CP0_SRSConf2; |
| 255 | #define CP0SRSC2_M 31 |
| 256 | #define CP0SRSC2_SRS9 20 |
| 257 | #define CP0SRSC2_SRS8 10 |
| 258 | #define CP0SRSC2_SRS7 0 |
| 259 | int32_t CP0_SRSConf3_rw_bitmask; |
| 260 | int32_t CP0_SRSConf3; |
| 261 | #define CP0SRSC3_M 31 |
| 262 | #define CP0SRSC3_SRS12 20 |
| 263 | #define CP0SRSC3_SRS11 10 |
| 264 | #define CP0SRSC3_SRS10 0 |
| 265 | int32_t CP0_SRSConf4_rw_bitmask; |
| 266 | int32_t CP0_SRSConf4; |
| 267 | #define CP0SRSC4_SRS15 20 |
| 268 | #define CP0SRSC4_SRS14 10 |
| 269 | #define CP0SRSC4_SRS13 0 |
| 270 | int32_t CP0_HWREna; |
| 271 | target_ulong CP0_BadVAddr; |
| 272 | int32_t CP0_Count; |
| 273 | target_ulong CP0_EntryHi; |
| 274 | int32_t CP0_Compare; |
| 275 | int32_t CP0_Status; |
| 276 | #define CP0St_CU3 31 |
| 277 | #define CP0St_CU2 30 |
| 278 | #define CP0St_CU1 29 |
| 279 | #define CP0St_CU0 28 |
| 280 | #define CP0St_RP 27 |
| 281 | #define CP0St_FR 26 |
| 282 | #define CP0St_RE 25 |
| 283 | #define CP0St_MX 24 |
| 284 | #define CP0St_PX 23 |
| 285 | #define CP0St_BEV 22 |
| 286 | #define CP0St_TS 21 |
| 287 | #define CP0St_SR 20 |
| 288 | #define CP0St_NMI 19 |
| 289 | #define CP0St_IM 8 |
| 290 | #define CP0St_KX 7 |
| 291 | #define CP0St_SX 6 |
| 292 | #define CP0St_UX 5 |
| 293 | #define CP0St_KSU 3 |
| 294 | #define CP0St_ERL 2 |
| 295 | #define CP0St_EXL 1 |
| 296 | #define CP0St_IE 0 |
| 297 | int32_t CP0_IntCtl; |
| 298 | #define CP0IntCtl_IPTI 29 |
| 299 | #define CP0IntCtl_IPPC1 26 |
| 300 | #define CP0IntCtl_VS 5 |
| 301 | int32_t CP0_SRSCtl; |
| 302 | #define CP0SRSCtl_HSS 26 |
| 303 | #define CP0SRSCtl_EICSS 18 |
| 304 | #define CP0SRSCtl_ESS 12 |
| 305 | #define CP0SRSCtl_PSS 6 |
| 306 | #define CP0SRSCtl_CSS 0 |
| 307 | int32_t CP0_SRSMap; |
| 308 | #define CP0SRSMap_SSV7 28 |
| 309 | #define CP0SRSMap_SSV6 24 |
| 310 | #define CP0SRSMap_SSV5 20 |
| 311 | #define CP0SRSMap_SSV4 16 |
| 312 | #define CP0SRSMap_SSV3 12 |
| 313 | #define CP0SRSMap_SSV2 8 |
| 314 | #define CP0SRSMap_SSV1 4 |
| 315 | #define CP0SRSMap_SSV0 0 |
| 316 | int32_t CP0_Cause; |
| 317 | #define CP0Ca_BD 31 |
| 318 | #define CP0Ca_TI 30 |
| 319 | #define CP0Ca_CE 28 |
| 320 | #define CP0Ca_DC 27 |
| 321 | #define CP0Ca_PCI 26 |
| 322 | #define CP0Ca_IV 23 |
| 323 | #define CP0Ca_WP 22 |
| 324 | #define CP0Ca_IP 8 |
| 325 | #define CP0Ca_IP_mask 0x0000FF00 |
| 326 | #define CP0Ca_EC 2 |
| 327 | target_ulong CP0_EPC; |
| 328 | int32_t CP0_PRid; |
| 329 | int32_t CP0_EBase; |
| 330 | int32_t CP0_Config0; |
| 331 | #define CP0C0_M 31 |
| 332 | #define CP0C0_K23 28 |
| 333 | #define CP0C0_KU 25 |
| 334 | #define CP0C0_MDU 20 |
| 335 | #define CP0C0_MM 17 |
| 336 | #define CP0C0_BM 16 |
| 337 | #define CP0C0_BE 15 |
| 338 | #define CP0C0_AT 13 |
| 339 | #define CP0C0_AR 10 |
| 340 | #define CP0C0_MT 7 |
| 341 | #define CP0C0_VI 3 |
| 342 | #define CP0C0_K0 0 |
| 343 | int32_t CP0_Config1; |
| 344 | #define CP0C1_M 31 |
| 345 | #define CP0C1_MMU 25 |
| 346 | #define CP0C1_IS 22 |
| 347 | #define CP0C1_IL 19 |
| 348 | #define CP0C1_IA 16 |
| 349 | #define CP0C1_DS 13 |
| 350 | #define CP0C1_DL 10 |
| 351 | #define CP0C1_DA 7 |
| 352 | #define CP0C1_C2 6 |
| 353 | #define CP0C1_MD 5 |
| 354 | #define CP0C1_PC 4 |
| 355 | #define CP0C1_WR 3 |
| 356 | #define CP0C1_CA 2 |
| 357 | #define CP0C1_EP 1 |
| 358 | #define CP0C1_FP 0 |
| 359 | int32_t CP0_Config2; |
| 360 | #define CP0C2_M 31 |
| 361 | #define CP0C2_TU 28 |
| 362 | #define CP0C2_TS 24 |
| 363 | #define CP0C2_TL 20 |
| 364 | #define CP0C2_TA 16 |
| 365 | #define CP0C2_SU 12 |
| 366 | #define CP0C2_SS 8 |
| 367 | #define CP0C2_SL 4 |
| 368 | #define CP0C2_SA 0 |
| 369 | int32_t CP0_Config3; |
| 370 | #define CP0C3_M 31 |
David 'Digit' Turner | 26a8fb6 | 2014-01-15 14:37:21 +0100 | [diff] [blame] | 371 | #define CP0C3_ISA_ON_EXC 16 |
Bhanu Chetlapalli | 409c7b6 | 2012-01-31 16:25:04 -0800 | [diff] [blame] | 372 | #define CP0C3_DSPP 10 |
| 373 | #define CP0C3_LPA 7 |
| 374 | #define CP0C3_VEIC 6 |
| 375 | #define CP0C3_VInt 5 |
| 376 | #define CP0C3_SP 4 |
| 377 | #define CP0C3_MT 2 |
| 378 | #define CP0C3_SM 1 |
| 379 | #define CP0C3_TL 0 |
| 380 | int32_t CP0_Config6; |
| 381 | int32_t CP0_Config7; |
| 382 | /* XXX: Maybe make LLAddr per-TC? */ |
| 383 | target_ulong lladdr; |
| 384 | target_ulong llval; |
| 385 | target_ulong llnewval; |
| 386 | target_ulong llreg; |
| 387 | target_ulong CP0_LLAddr_rw_bitmask; |
| 388 | int CP0_LLAddr_shift; |
| 389 | target_ulong CP0_WatchLo[8]; |
| 390 | int32_t CP0_WatchHi[8]; |
| 391 | target_ulong CP0_XContext; |
| 392 | int32_t CP0_Framemask; |
| 393 | int32_t CP0_Debug; |
| 394 | #define CP0DB_DBD 31 |
| 395 | #define CP0DB_DM 30 |
| 396 | #define CP0DB_LSNM 28 |
| 397 | #define CP0DB_Doze 27 |
| 398 | #define CP0DB_Halt 26 |
| 399 | #define CP0DB_CNT 25 |
| 400 | #define CP0DB_IBEP 24 |
| 401 | #define CP0DB_DBEP 21 |
| 402 | #define CP0DB_IEXI 20 |
| 403 | #define CP0DB_VER 15 |
| 404 | #define CP0DB_DEC 10 |
| 405 | #define CP0DB_SSt 8 |
| 406 | #define CP0DB_DINT 5 |
| 407 | #define CP0DB_DIB 4 |
| 408 | #define CP0DB_DDBS 3 |
| 409 | #define CP0DB_DDBL 2 |
| 410 | #define CP0DB_DBp 1 |
| 411 | #define CP0DB_DSS 0 |
| 412 | target_ulong CP0_DEPC; |
| 413 | int32_t CP0_Performance0; |
| 414 | int32_t CP0_TagLo; |
| 415 | int32_t CP0_DataLo; |
| 416 | int32_t CP0_TagHi; |
| 417 | int32_t CP0_DataHi; |
| 418 | target_ulong CP0_ErrorEPC; |
| 419 | int32_t CP0_DESAVE; |
| 420 | /* We waste some space so we can handle shadow registers like TCs. */ |
| 421 | TCState tcs[MIPS_SHADOW_SET_MAX]; |
| 422 | CPUMIPSFPUContext fpus[MIPS_FPU_MAX]; |
David 'Digit' Turner | 26a8fb6 | 2014-01-15 14:37:21 +0100 | [diff] [blame] | 423 | /* QEMU */ |
Bhanu Chetlapalli | 409c7b6 | 2012-01-31 16:25:04 -0800 | [diff] [blame] | 424 | int error_code; |
| 425 | uint32_t hflags; /* CPU State */ |
| 426 | /* TMASK defines different execution modes */ |
| 427 | #define MIPS_HFLAG_TMASK 0x03FF |
| 428 | #define MIPS_HFLAG_MODE 0x0007 /* execution modes */ |
| 429 | /* The KSU flags must be the lowest bits in hflags. The flag order |
| 430 | must be the same as defined for CP0 Status. This allows to use |
| 431 | the bits as the value of mmu_idx. */ |
| 432 | #define MIPS_HFLAG_KSU 0x0003 /* kernel/supervisor/user mode mask */ |
| 433 | #define MIPS_HFLAG_UM 0x0002 /* user mode flag */ |
| 434 | #define MIPS_HFLAG_SM 0x0001 /* supervisor mode flag */ |
| 435 | #define MIPS_HFLAG_KM 0x0000 /* kernel mode flag */ |
| 436 | #define MIPS_HFLAG_DM 0x0004 /* Debug mode */ |
| 437 | #define MIPS_HFLAG_64 0x0008 /* 64-bit instructions enabled */ |
| 438 | #define MIPS_HFLAG_CP0 0x0010 /* CP0 enabled */ |
| 439 | #define MIPS_HFLAG_FPU 0x0020 /* FPU enabled */ |
| 440 | #define MIPS_HFLAG_F64 0x0040 /* 64-bit FPU enabled */ |
| 441 | /* True if the MIPS IV COP1X instructions can be used. This also |
| 442 | controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S |
| 443 | and RSQRT.D. */ |
| 444 | #define MIPS_HFLAG_COP1X 0x0080 /* COP1X instructions enabled */ |
| 445 | #define MIPS_HFLAG_RE 0x0100 /* Reversed endianness */ |
| 446 | #define MIPS_HFLAG_UX 0x0200 /* 64-bit user mode */ |
| 447 | /* If translation is interrupted between the branch instruction and |
| 448 | * the delay slot, record what type of branch it is so that we can |
| 449 | * resume translation properly. It might be possible to reduce |
| 450 | * this from three bits to two. */ |
| 451 | #define MIPS_HFLAG_BMASK 0x1C00 |
| 452 | #define MIPS_HFLAG_B 0x0400 /* Unconditional branch */ |
| 453 | #define MIPS_HFLAG_BC 0x0800 /* Conditional branch */ |
| 454 | #define MIPS_HFLAG_BL 0x0C00 /* Likely branch */ |
| 455 | #define MIPS_HFLAG_BR 0x1000 /* branch to register (can't link TB) */ |
| 456 | target_ulong btarget; /* Jump / branch target */ |
| 457 | target_ulong bcond; /* Branch condition (if needed) */ |
| 458 | |
| 459 | int SYNCI_Step; /* Address step size for SYNCI */ |
| 460 | int CCRes; /* Cycle count resolution/divisor */ |
| 461 | uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ |
| 462 | uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ |
| 463 | int insn_flags; /* Supported instruction set */ |
| 464 | |
| 465 | target_ulong tls_value; /* For usermode emulation */ |
| 466 | |
| 467 | CPU_COMMON |
| 468 | |
| 469 | CPUMIPSMVPContext *mvp; |
David 'Digit' Turner | 26a8fb6 | 2014-01-15 14:37:21 +0100 | [diff] [blame] | 470 | #if !defined(CONFIG_USER_ONLY) |
Bhanu Chetlapalli | 409c7b6 | 2012-01-31 16:25:04 -0800 | [diff] [blame] | 471 | CPUMIPSTLBContext *tlb; |
David 'Digit' Turner | 26a8fb6 | 2014-01-15 14:37:21 +0100 | [diff] [blame] | 472 | #endif |
Bhanu Chetlapalli | 409c7b6 | 2012-01-31 16:25:04 -0800 | [diff] [blame] | 473 | |
| 474 | const mips_def_t *cpu_model; |
| 475 | void *irq[8]; |
| 476 | struct QEMUTimer *timer; /* Internal timer */ |
| 477 | }; |
| 478 | |
David 'Digit' Turner | 6657678 | 2014-03-24 16:57:57 +0100 | [diff] [blame] | 479 | #include "cpu-qom.h" |
| 480 | |
David 'Digit' Turner | bcde109 | 2014-01-09 23:19:19 +0100 | [diff] [blame] | 481 | int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, |
Bhanu Chetlapalli | 409c7b6 | 2012-01-31 16:25:04 -0800 | [diff] [blame] | 482 | target_ulong address, int rw, int access_type); |
David 'Digit' Turner | bcde109 | 2014-01-09 23:19:19 +0100 | [diff] [blame] | 483 | int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, |
Bhanu Chetlapalli | 409c7b6 | 2012-01-31 16:25:04 -0800 | [diff] [blame] | 484 | target_ulong address, int rw, int access_type); |
David 'Digit' Turner | bcde109 | 2014-01-09 23:19:19 +0100 | [diff] [blame] | 485 | int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, |
Bhanu Chetlapalli | 409c7b6 | 2012-01-31 16:25:04 -0800 | [diff] [blame] | 486 | target_ulong address, int rw, int access_type); |
David 'Digit' Turner | 758fa08 | 2014-04-03 12:29:21 +0200 | [diff] [blame] | 487 | void r4k_helper_tlbwi(CPUMIPSState *env); |
| 488 | void r4k_helper_tlbwr(CPUMIPSState *env); |
| 489 | void r4k_helper_tlbp(CPUMIPSState *env); |
| 490 | void r4k_helper_tlbr(CPUMIPSState *env); |
Bhanu Chetlapalli | 409c7b6 | 2012-01-31 16:25:04 -0800 | [diff] [blame] | 491 | void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
| 492 | |
David 'Digit' Turner | 6cf763a | 2014-03-14 13:25:11 +0100 | [diff] [blame] | 493 | void cpu_unassigned_access(CPUArchState* env, hwaddr addr, |
| 494 | int is_write, int is_exec, int unused, int size); |
Bhanu Chetlapalli | 409c7b6 | 2012-01-31 16:25:04 -0800 | [diff] [blame] | 495 | |
| 496 | #define cpu_init cpu_mips_init |
| 497 | #define cpu_exec cpu_mips_exec |
| 498 | #define cpu_gen_code cpu_mips_gen_code |
| 499 | #define cpu_signal_handler cpu_mips_signal_handler |
| 500 | #define cpu_list mips_cpu_list |
| 501 | |
| 502 | #define CPU_SAVE_VERSION 3 |
| 503 | |
David 'Digit' Turner | 26a8fb6 | 2014-01-15 14:37:21 +0100 | [diff] [blame] | 504 | // NOTE(digit): Came from cpu-all.h, to be removed later. |
| 505 | #define CPU_INTERRUPT_TIMER 0x08 /* internal timer exception pending */ |
| 506 | |
Bhanu Chetlapalli | 409c7b6 | 2012-01-31 16:25:04 -0800 | [diff] [blame] | 507 | /* MMU modes definitions. We carefully match the indices with our |
| 508 | hflags layout. */ |
| 509 | #define MMU_MODE0_SUFFIX _kernel |
| 510 | #define MMU_MODE1_SUFFIX _super |
| 511 | #define MMU_MODE2_SUFFIX _user |
| 512 | #define MMU_USER_IDX 2 |
David 'Digit' Turner | 26a8fb6 | 2014-01-15 14:37:21 +0100 | [diff] [blame] | 513 | static inline int cpu_mmu_index (CPUMIPSState *env) |
Bhanu Chetlapalli | 409c7b6 | 2012-01-31 16:25:04 -0800 | [diff] [blame] | 514 | { |
| 515 | return env->hflags & MIPS_HFLAG_KSU; |
| 516 | } |
| 517 | |
David 'Digit' Turner | 26a8fb6 | 2014-01-15 14:37:21 +0100 | [diff] [blame] | 518 | static inline int is_cpu_user (CPUMIPSState *env) |
Bhanu Chetlapalli | 325e19d | 2012-01-31 16:26:04 -0800 | [diff] [blame] | 519 | { |
| 520 | #ifdef CONFIG_USER_ONLY |
| 521 | return 1; |
| 522 | #else |
| 523 | return ((env->CP0_Status & |
| 524 | ((3 << CP0St_KSU) | (1 << CP0St_ERL) | (1 << CP0St_EXL))) == (3 << CP0St_KSU)); |
| 525 | #endif // CONFIG_USER_ONLY |
| 526 | } |
| 527 | |
David 'Digit' Turner | e2678e1 | 2014-01-16 15:56:43 +0100 | [diff] [blame] | 528 | static inline void cpu_clone_regs(CPUMIPSState *env, target_ulong newsp) |
Bhanu Chetlapalli | 409c7b6 | 2012-01-31 16:25:04 -0800 | [diff] [blame] | 529 | { |
| 530 | if (newsp) |
| 531 | env->active_tc.gpr[29] = newsp; |
| 532 | env->active_tc.gpr[7] = 0; |
| 533 | env->active_tc.gpr[2] = 0; |
| 534 | } |
| 535 | |
David 'Digit' Turner | e2678e1 | 2014-01-16 15:56:43 +0100 | [diff] [blame] | 536 | static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env) |
Bhanu Chetlapalli | 741dc13 | 2012-05-08 17:16:03 -0700 | [diff] [blame] | 537 | { |
| 538 | int32_t pending; |
| 539 | int32_t status; |
| 540 | int r; |
| 541 | |
| 542 | if (!(env->CP0_Status & (1 << CP0St_IE)) || |
| 543 | (env->CP0_Status & (1 << CP0St_EXL)) || |
| 544 | (env->CP0_Status & (1 << CP0St_ERL)) || |
| 545 | (env->hflags & MIPS_HFLAG_DM)) { |
| 546 | /* Interrupts are disabled */ |
| 547 | return 0; |
| 548 | } |
| 549 | |
| 550 | pending = env->CP0_Cause & CP0Ca_IP_mask; |
| 551 | status = env->CP0_Status & CP0Ca_IP_mask; |
| 552 | |
| 553 | if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { |
| 554 | /* A MIPS configured with a vectorizing external interrupt controller |
| 555 | will feed a vector into the Cause pending lines. The core treats |
| 556 | the status lines as a vector level, not as indiviual masks. */ |
| 557 | r = pending > status; |
| 558 | } else { |
| 559 | /* A MIPS configured with compatibility or VInt (Vectored Interrupts) |
| 560 | treats the pending lines as individual interrupt lines, the status |
| 561 | lines are individual masks. */ |
| 562 | r = pending & status; |
| 563 | } |
| 564 | return r; |
| 565 | } |
| 566 | |
David 'Digit' Turner | 852088c | 2013-12-14 23:04:12 +0100 | [diff] [blame] | 567 | #include "exec/cpu-all.h" |
| 568 | #include "exec/exec-all.h" |
Bhanu Chetlapalli | 409c7b6 | 2012-01-31 16:25:04 -0800 | [diff] [blame] | 569 | |
| 570 | /* Memory access type : |
| 571 | * may be needed for precise access rights control and precise exceptions. |
| 572 | */ |
| 573 | enum { |
| 574 | /* 1 bit to define user level / supervisor access */ |
| 575 | ACCESS_USER = 0x00, |
| 576 | ACCESS_SUPER = 0x01, |
| 577 | /* 1 bit to indicate direction */ |
| 578 | ACCESS_STORE = 0x02, |
| 579 | /* Type of instruction that generated the access */ |
| 580 | ACCESS_CODE = 0x10, /* Code fetch access */ |
| 581 | ACCESS_INT = 0x20, /* Integer load/store access */ |
| 582 | ACCESS_FLOAT = 0x30, /* floating point load/store access */ |
| 583 | }; |
| 584 | |
| 585 | /* Exceptions */ |
| 586 | enum { |
| 587 | EXCP_NONE = -1, |
| 588 | EXCP_RESET = 0, |
| 589 | EXCP_SRESET, |
| 590 | EXCP_DSS, |
| 591 | EXCP_DINT, |
| 592 | EXCP_DDBL, |
| 593 | EXCP_DDBS, |
| 594 | EXCP_NMI, |
| 595 | EXCP_MCHECK, |
| 596 | EXCP_EXT_INTERRUPT, /* 8 */ |
| 597 | EXCP_DFWATCH, |
| 598 | EXCP_DIB, |
| 599 | EXCP_IWATCH, |
| 600 | EXCP_AdEL, |
| 601 | EXCP_AdES, |
| 602 | EXCP_TLBF, |
| 603 | EXCP_IBE, |
| 604 | EXCP_DBp, /* 16 */ |
| 605 | EXCP_SYSCALL, |
| 606 | EXCP_BREAK, |
| 607 | EXCP_CpU, |
| 608 | EXCP_RI, |
| 609 | EXCP_OVERFLOW, |
| 610 | EXCP_TRAP, |
| 611 | EXCP_FPE, |
| 612 | EXCP_DWATCH, /* 24 */ |
| 613 | EXCP_LTLBL, |
| 614 | EXCP_TLBL, |
| 615 | EXCP_TLBS, |
| 616 | EXCP_DBE, |
| 617 | EXCP_THREAD, |
| 618 | EXCP_MDMX, |
| 619 | EXCP_C2E, |
| 620 | EXCP_CACHE, /* 32 */ |
| 621 | |
| 622 | EXCP_LAST = EXCP_CACHE, |
| 623 | }; |
| 624 | /* Dummy exception for conditional stores. */ |
| 625 | #define EXCP_SC 0x100 |
| 626 | |
David 'Digit' Turner | 26a8fb6 | 2014-01-15 14:37:21 +0100 | [diff] [blame] | 627 | /* |
| 628 | * This is an interrnally generated WAKE request line. |
| 629 | * It is driven by the CPU itself. Raised when the MT |
| 630 | * block wants to wake a VPE from an inactive state and |
| 631 | * cleared when VPE goes from active to inactive. |
| 632 | */ |
| 633 | #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0 |
| 634 | |
Bhanu Chetlapalli | 409c7b6 | 2012-01-31 16:25:04 -0800 | [diff] [blame] | 635 | int cpu_mips_exec(CPUMIPSState *s); |
| 636 | CPUMIPSState *cpu_mips_init(const char *cpu_model); |
| 637 | //~ uint32_t cpu_mips_get_clock (void); |
| 638 | int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); |
| 639 | |
| 640 | /* mips_timer.c */ |
David 'Digit' Turner | e2678e1 | 2014-01-16 15:56:43 +0100 | [diff] [blame] | 641 | uint32_t cpu_mips_get_random (CPUMIPSState *env); |
| 642 | uint32_t cpu_mips_get_count (CPUMIPSState *env); |
| 643 | void cpu_mips_store_count (CPUMIPSState *env, uint32_t value); |
| 644 | void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value); |
| 645 | void cpu_mips_start_count(CPUMIPSState *env); |
| 646 | void cpu_mips_stop_count(CPUMIPSState *env); |
Bhanu Chetlapalli | 409c7b6 | 2012-01-31 16:25:04 -0800 | [diff] [blame] | 647 | |
| 648 | /* mips_int.c */ |
David 'Digit' Turner | e2678e1 | 2014-01-16 15:56:43 +0100 | [diff] [blame] | 649 | void cpu_mips_update_irq (CPUMIPSState *env); |
Bhanu Chetlapalli | 409c7b6 | 2012-01-31 16:25:04 -0800 | [diff] [blame] | 650 | |
| 651 | /* helper.c */ |
David 'Digit' Turner | e2678e1 | 2014-01-16 15:56:43 +0100 | [diff] [blame] | 652 | int cpu_mips_handle_mmu_fault (CPUMIPSState *env, target_ulong address, int rw, |
David 'Digit' Turner | 0d8b235 | 2014-03-20 17:13:13 +0100 | [diff] [blame] | 653 | int mmu_idx); |
Bhanu Chetlapalli | 409c7b6 | 2012-01-31 16:25:04 -0800 | [diff] [blame] | 654 | #define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault |
David 'Digit' Turner | e2678e1 | 2014-01-16 15:56:43 +0100 | [diff] [blame] | 655 | void do_interrupt (CPUMIPSState *env); |
| 656 | hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address, |
Bhanu Chetlapalli | 409c7b6 | 2012-01-31 16:25:04 -0800 | [diff] [blame] | 657 | int rw); |
| 658 | |
David 'Digit' Turner | e2678e1 | 2014-01-16 15:56:43 +0100 | [diff] [blame] | 659 | static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc, |
Bhanu Chetlapalli | 409c7b6 | 2012-01-31 16:25:04 -0800 | [diff] [blame] | 660 | target_ulong *cs_base, int *flags) |
| 661 | { |
| 662 | *pc = env->active_tc.PC; |
| 663 | *cs_base = 0; |
| 664 | *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK); |
| 665 | } |
| 666 | |
David 'Digit' Turner | e2678e1 | 2014-01-16 15:56:43 +0100 | [diff] [blame] | 667 | static inline void cpu_set_tls(CPUMIPSState *env, target_ulong newtls) |
Bhanu Chetlapalli | 409c7b6 | 2012-01-31 16:25:04 -0800 | [diff] [blame] | 668 | { |
| 669 | env->tls_value = newtls; |
| 670 | } |
| 671 | |
David 'Digit' Turner | 6657678 | 2014-03-24 16:57:57 +0100 | [diff] [blame] | 672 | static inline bool cpu_has_work(CPUState *cpu) |
David 'Digit' Turner | 93949dc | 2014-03-18 15:00:37 +0100 | [diff] [blame] | 673 | { |
| 674 | int has_work = 0; |
| 675 | |
| 676 | /* It is implementation dependent if non-enabled interrupts |
| 677 | wake-up the CPU, however most of the implementations only |
| 678 | check for interrupts that can be taken. */ |
David 'Digit' Turner | 6657678 | 2014-03-24 16:57:57 +0100 | [diff] [blame] | 679 | if ((cpu->interrupt_request & CPU_INTERRUPT_HARD) && |
| 680 | cpu_mips_hw_interrupts_pending(cpu->env_ptr)) { |
David 'Digit' Turner | 93949dc | 2014-03-18 15:00:37 +0100 | [diff] [blame] | 681 | has_work = 1; |
| 682 | } |
| 683 | |
David 'Digit' Turner | 6657678 | 2014-03-24 16:57:57 +0100 | [diff] [blame] | 684 | if (cpu->interrupt_request & CPU_INTERRUPT_TIMER) { |
David 'Digit' Turner | 93949dc | 2014-03-18 15:00:37 +0100 | [diff] [blame] | 685 | has_work = 1; |
| 686 | } |
| 687 | |
| 688 | return has_work; |
| 689 | } |
| 690 | |
| 691 | static inline void cpu_pc_from_tb(CPUMIPSState *env, TranslationBlock *tb) |
| 692 | { |
| 693 | env->active_tc.PC = tb->pc; |
| 694 | env->hflags &= ~MIPS_HFLAG_BMASK; |
| 695 | env->hflags |= tb->flags & MIPS_HFLAG_BMASK; |
| 696 | } |
| 697 | |
Bhanu Chetlapalli | 409c7b6 | 2012-01-31 16:25:04 -0800 | [diff] [blame] | 698 | #endif /* !defined (__MIPS_CPU_H__) */ |