Merge "Disable clang assembler, to fix asm code later."
diff --git a/Android.libv8.mk b/Android.libv8.mk
index 255bad7..13bb088 100644
--- a/Android.libv8.mk
+++ b/Android.libv8.mk
@@ -111,7 +111,7 @@
-Umips \
-finline-limit=64 \
-fno-strict-aliasing
-LOCAL_CLFAGS_mips64 += -DV8_TARGET_ARCH_MIPS64 \
+LOCAL_CFLAGS_mips64 += -DV8_TARGET_ARCH_MIPS64 \
-Umips \
-finline-limit=64 \
-fno-strict-aliasing
diff --git a/Android.mksnapshot.mk b/Android.mksnapshot.mk
index 0eab005..200f6d9 100644
--- a/Android.mksnapshot.mk
+++ b/Android.mksnapshot.mk
@@ -93,7 +93,7 @@
-finline-limit=64 \
-fno-strict-aliasing
-LOCAL_CLFAGS_v8_target_mips64 += -DV8_TARGET_ARCH_MIPS64 \
+LOCAL_CFLAGS_v8_target_mips64 += -DV8_TARGET_ARCH_MIPS64 \
-Umips \
-finline-limit=64 \
-fno-strict-aliasing
diff --git a/V8_MERGE_REVISION b/V8_MERGE_REVISION
index 37ec723..fd6b1b2 100644
--- a/V8_MERGE_REVISION
+++ b/V8_MERGE_REVISION
@@ -1,2 +1,2 @@
-V8 3.9.24.30
-http://v8.googlecode.com/svn/branches/3.9@11743
+v8 3.29.88.18
+https://chromium.googlesource.com/v8/v8/+/f0158730a3b758d746287cacc315ae262b83232d
diff --git a/build/standalone.gypi b/build/standalone.gypi
index b09122b..32ad028 100644
--- a/build/standalone.gypi
+++ b/build/standalone.gypi
@@ -127,6 +127,16 @@
'arm_fpu%': 'vfpv3',
'arm_float_abi%': 'default',
'arm_thumb': 'default',
+
+ # Default MIPS variable settings.
+ 'mips_arch_variant%': 'r2',
+ # Possible values fp32, fp64, fpxx.
+ # fp32 - 32 32-bit FPU registers are available, doubles are placed in
+ # register pairs.
+ # fp64 - 32 64-bit FPU registers are available.
+ # fpxx - compatibility mode, it chooses fp32 or fp64 depending on runtime
+ # detection
+ 'mips_fpu_mode%': 'fp32',
},
'target_defaults': {
'variables': {
diff --git a/build/toolchain.gypi b/build/toolchain.gypi
index 7f3b9e5..38c9aee 100644
--- a/build/toolchain.gypi
+++ b/build/toolchain.gypi
@@ -55,17 +55,6 @@
# Similar to the ARM hard float ABI but on MIPS.
'v8_use_mips_abi_hardfloat%': 'true',
- # Default arch variant for MIPS.
- 'mips_arch_variant%': 'r2',
-
- # Possible values fp32, fp64, fpxx.
- # fp32 - 32 32-bit FPU registers are available, doubles are placed in
- # register pairs.
- # fp64 - 32 64-bit FPU registers are available.
- # fpxx - compatibility mode, it chooses fp32 or fp64 depending on runtime
- # detection
- 'mips_fpu_mode%': 'fp32',
-
'v8_enable_backtrace%': 0,
# Enable profiling support. Only required on Windows.
@@ -278,10 +267,27 @@
'V8_TARGET_ARCH_MIPS',
],
'conditions': [
- ['v8_target_arch==target_arch and android_webview_build==0', {
- # Target built with a Mips CXX compiler.
- 'target_conditions': [
- ['_toolset=="target"', {
+ [ 'v8_can_use_fpu_instructions=="true"', {
+ 'defines': [
+ 'CAN_USE_FPU_INSTRUCTIONS',
+ ],
+ }],
+ [ 'v8_use_mips_abi_hardfloat=="true"', {
+ 'defines': [
+ '__mips_hard_float=1',
+ 'CAN_USE_FPU_INSTRUCTIONS',
+ ],
+ }, {
+ 'defines': [
+ '__mips_soft_float=1'
+ ]
+ }],
+ ],
+ 'target_conditions': [
+ ['_toolset=="target"', {
+ 'conditions': [
+ ['v8_target_arch==target_arch and android_webview_build==0', {
+ # Target built with a Mips CXX compiler.
'cflags': ['-EB'],
'ldflags': ['-EB'],
'conditions': [
@@ -292,17 +298,12 @@
'cflags': ['-msoft-float'],
'ldflags': ['-msoft-float'],
}],
- ['mips_fpu_mode=="fp64"', {
- 'cflags': ['-mfp64'],
- }],
- ['mips_fpu_mode=="fpxx"', {
- 'cflags': ['-mfpxx'],
- }],
- ['mips_fpu_mode=="fp32"', {
- 'cflags': ['-mfp32'],
- }],
['mips_arch_variant=="r6"', {
- 'cflags!': ['-mfp32'],
+ 'defines': [
+ '_MIPS_ARCH_MIPS32R6',
+ 'FPU_MODE_FP64',
+ ],
+ 'cflags!': ['-mfp32', '-mfpxx'],
'cflags': ['-mips32r6', '-Wa,-mips32r6'],
'ldflags': [
'-mips32r6',
@@ -311,20 +312,145 @@
],
}],
['mips_arch_variant=="r2"', {
+ 'conditions': [
+ [ 'mips_fpu_mode=="fp64"', {
+ 'defines': [
+ '_MIPS_ARCH_MIPS32R2',
+ 'FPU_MODE_FP64',
+ ],
+ 'cflags': ['-mfp64'],
+ }],
+ ['mips_fpu_mode=="fpxx"', {
+ 'defines': [
+ '_MIPS_ARCH_MIPS32R2',
+ 'FPU_MODE_FPXX',
+ ],
+ 'cflags': ['-mfpxx'],
+ }],
+ ['mips_fpu_mode=="fp32"', {
+ 'defines': [
+ '_MIPS_ARCH_MIPS32R2',
+ 'FPU_MODE_FP32',
+ ],
+ 'cflags': ['-mfp32'],
+ }],
+ ],
'cflags': ['-mips32r2', '-Wa,-mips32r2'],
+ 'ldflags': ['-mips32r2'],
}],
['mips_arch_variant=="r1"', {
- 'cflags!': ['-mfp64'],
+ 'defines': [
+ 'FPU_MODE_FP32',
+ ],
+ 'cflags!': ['-mfp64', '-mfpxx'],
'cflags': ['-mips32', '-Wa,-mips32'],
+ 'ldflags': ['-mips32'],
}],
['mips_arch_variant=="rx"', {
- 'cflags!': ['-mfp64'],
- 'cflags': ['-mips32', '-Wa,-mips32'],
+ 'defines': [
+ '_MIPS_ARCH_MIPS32RX',
+ 'FPU_MODE_FPXX',
+ ],
+ 'cflags!': ['-mfp64', '-mfp32'],
+ 'cflags': ['-mips32', '-Wa,-mips32', '-mfpxx'],
+ 'ldflags': ['-mips32'],
+ }],
+ ],
+ }, {
+ # 'v8_target_arch!=target_arch'
+ # Target not built with an MIPS CXX compiler (simulator build).
+ 'conditions': [
+ ['mips_arch_variant=="r6"', {
+ 'defines': [
+ '_MIPS_ARCH_MIPS32R6',
+ 'FPU_MODE_FP64',
+ ],
+ }],
+ ['mips_arch_variant=="r2"', {
+ 'conditions': [
+ [ 'mips_fpu_mode=="fp64"', {
+ 'defines': [
+ '_MIPS_ARCH_MIPS32R2',
+ 'FPU_MODE_FP64',
+ ],
+ }],
+ ['mips_fpu_mode=="fpxx"', {
+ 'defines': [
+ '_MIPS_ARCH_MIPS32R2',
+ 'FPU_MODE_FPXX',
+ ],
+ }],
+ ['mips_fpu_mode=="fp32"', {
+ 'defines': [
+ '_MIPS_ARCH_MIPS32R2',
+ 'FPU_MODE_FP32',
+ ],
+ }],
+ ],
+ }],
+ ['mips_arch_variant=="r1"', {
+ 'defines': [
+ 'FPU_MODE_FP32',
+ ],
+ }],
+ ['mips_arch_variant=="rx"', {
+ 'defines': [
+ '_MIPS_ARCH_MIPS32RX',
+ 'FPU_MODE_FPXX',
+ ],
}],
],
}],
],
- }],
+ }], #_toolset=="target"
+ ['_toolset=="host"', {
+ 'conditions': [
+ ['mips_arch_variant=="rx"', {
+ 'defines': [
+ '_MIPS_ARCH_MIPS32RX',
+ 'FPU_MODE_FPXX',
+ ],
+ }],
+ ['mips_arch_variant=="r6"', {
+ 'defines': [
+ '_MIPS_ARCH_MIPS32R6',
+ 'FPU_MODE_FP64',
+ ],
+ }],
+ ['mips_arch_variant=="r2"', {
+ 'conditions': [
+ ['mips_fpu_mode=="fp64"', {
+ 'defines': [
+ '_MIPS_ARCH_MIPS32R2',
+ 'FPU_MODE_FP64',
+ ],
+ }],
+ ['mips_fpu_mode=="fpxx"', {
+ 'defines': [
+ '_MIPS_ARCH_MIPS32R2',
+ 'FPU_MODE_FPXX',
+ ],
+ }],
+ ['mips_fpu_mode=="fp32"', {
+ 'defines': [
+ '_MIPS_ARCH_MIPS32R2',
+ 'FPU_MODE_FP32'
+ ],
+ }],
+ ],
+ }],
+ ['mips_arch_variant=="r1"', {
+ 'defines': ['FPU_MODE_FP32',],
+ }],
+ ]
+ }], #_toolset=="host"
+ ],
+ }], # v8_target_arch=="mips"
+ ['v8_target_arch=="mipsel"', {
+ 'defines': [
+ 'V8_TARGET_ARCH_MIPS',
+ ],
+ 'conditions': [
[ 'v8_can_use_fpu_instructions=="true"', {
'defines': [
'CAN_USE_FPU_INSTRUCTIONS',
@@ -340,46 +466,12 @@
'__mips_soft_float=1'
],
}],
- ['mips_arch_variant=="rx"', {
- 'defines': [
- '_MIPS_ARCH_MIPS32RX',
- 'FPU_MODE_FPXX',
- ],
- }],
- ['mips_arch_variant=="r6"', {
- 'defines': [
- '_MIPS_ARCH_MIPS32R6',
- 'FPU_MODE_FP64',
- ],
- }],
- ['mips_arch_variant=="r2"', {
- 'defines': ['_MIPS_ARCH_MIPS32R2',],
+ ],
+ 'target_conditions': [
+ ['_toolset=="target"', {
'conditions': [
- ['mips_fpu_mode=="fp64"', {
- 'defines': ['FPU_MODE_FP64',],
- }],
- ['mips_fpu_mode=="fpxx"', {
- 'defines': ['FPU_MODE_FPXX',],
- }],
- ['mips_fpu_mode=="fp32"', {
- 'defines': ['FPU_MODE_FP32',],
- }],
- ],
- }],
- ['mips_arch_variant=="r1"', {
- 'defines': ['FPU_MODE_FP32',],
- }],
- ],
- }], # v8_target_arch=="mips"
- ['v8_target_arch=="mipsel"', {
- 'defines': [
- 'V8_TARGET_ARCH_MIPS',
- ],
- 'conditions': [
- ['v8_target_arch==target_arch and android_webview_build==0', {
- # Target built with a Mips CXX compiler.
- 'target_conditions': [
- ['_toolset=="target"', {
+ ['v8_target_arch==target_arch and android_webview_build==0', {
+ # Target built with a Mips CXX compiler.
'cflags': ['-EL'],
'ldflags': ['-EL'],
'conditions': [
@@ -390,17 +482,12 @@
'cflags': ['-msoft-float'],
'ldflags': ['-msoft-float'],
}],
- ['mips_fpu_mode=="fp64"', {
- 'cflags': ['-mfp64'],
- }],
- ['mips_fpu_mode=="fpxx"', {
- 'cflags': ['-mfpxx'],
- }],
- ['mips_fpu_mode=="fp32"', {
- 'cflags': ['-mfp32'],
- }],
['mips_arch_variant=="r6"', {
- 'cflags!': ['-mfp32'],
+ 'defines': [
+ '_MIPS_ARCH_MIPS32R6',
+ 'FPU_MODE_FP64',
+ ],
+ 'cflags!': ['-mfp32', '-mfpxx'],
'cflags': ['-mips32r6', '-Wa,-mips32r6'],
'ldflags': [
'-mips32r6',
@@ -409,73 +496,154 @@
],
}],
['mips_arch_variant=="r2"', {
+ 'conditions': [
+ [ 'mips_fpu_mode=="fp64"', {
+ 'defines': [
+ '_MIPS_ARCH_MIPS32R2',
+ 'FPU_MODE_FP64',
+ ],
+ 'cflags': ['-mfp64'],
+ }],
+ ['mips_fpu_mode=="fpxx"', {
+ 'defines': [
+ '_MIPS_ARCH_MIPS32R2',
+ 'FPU_MODE_FPXX',
+ ],
+ 'cflags': ['-mfpxx'],
+ }],
+ ['mips_fpu_mode=="fp32"', {
+ 'defines': [
+ '_MIPS_ARCH_MIPS32R2',
+ 'FPU_MODE_FP32',
+ ],
+ 'cflags': ['-mfp32'],
+ }],
+ ],
'cflags': ['-mips32r2', '-Wa,-mips32r2'],
+ 'ldflags': ['-mips32r2'],
}],
['mips_arch_variant=="r1"', {
- 'cflags!': ['-mfp64'],
+ 'cflags!': ['-mfp64', '-mfpxx'],
'cflags': ['-mips32', '-Wa,-mips32'],
+ 'ldflags': ['-mips32'],
}],
['mips_arch_variant=="rx"', {
- 'cflags!': ['-mfp64'],
- 'cflags': ['-mips32', '-Wa,-mips32'],
+ 'defines': [
+ '_MIPS_ARCH_MIPS32RX',
+ 'FPU_MODE_FPXX',
+ ],
+ 'cflags!': ['-mfp64', '-mfp32'],
+ 'cflags': ['-mips32', '-Wa,-mips32', '-mfpxx'],
+ 'ldflags': ['-mips32'],
}],
['mips_arch_variant=="loongson"', {
- 'cflags!': ['-mfp64'],
+ 'defines': [
+ '_MIPS_ARCH_LOONGSON',
+ 'FPU_MODE_FP32',
+ ],
+ 'cflags!': ['-mfp64', '-mfp32', '-mfpxx'],
'cflags': ['-mips3', '-Wa,-mips3'],
}],
],
+ }, {
+ # 'v8_target_arch!=target_arch'
+ # Target not built with an MIPS CXX compiler (simulator build).
+ 'conditions': [
+ ['mips_arch_variant=="r6"', {
+ 'defines': [
+ '_MIPS_ARCH_MIPS32R6',
+ 'FPU_MODE_FP64',
+ ],
+ }],
+ ['mips_arch_variant=="r2"', {
+ 'conditions': [
+ [ 'mips_fpu_mode=="fp64"', {
+ 'defines': [
+ '_MIPS_ARCH_MIPS32R2',
+ 'FPU_MODE_FP64',
+ ],
+ }],
+ ['mips_fpu_mode=="fpxx"', {
+ 'defines': [
+ '_MIPS_ARCH_MIPS32R2',
+ 'FPU_MODE_FPXX',
+ ],
+ }],
+ ['mips_fpu_mode=="fp32"', {
+ 'defines': [
+ '_MIPS_ARCH_MIPS32R2',
+ 'FPU_MODE_FP32',
+ ],
+ }],
+ ],
+ }],
+ ['mips_arch_variant=="r1"', {
+ 'defines': [
+ 'FPU_MODE_FP32',
+ ],
+ }],
+ ['mips_arch_variant=="rx"', {
+ 'defines': [
+ '_MIPS_ARCH_MIPS32RX',
+ 'FPU_MODE_FPXX',
+ ],
+ }],
+ ['mips_arch_variant=="loongson"', {
+ 'defines': [
+ '_MIPS_ARCH_LOONGSON',
+ 'FPU_MODE_FP32',
+ ],
+ }],
+ ],
}],
],
- }],
- [ 'v8_can_use_fpu_instructions=="true"', {
- 'defines': [
- 'CAN_USE_FPU_INSTRUCTIONS',
- ],
- }],
- [ 'v8_use_mips_abi_hardfloat=="true"', {
- 'defines': [
- '__mips_hard_float=1',
- 'CAN_USE_FPU_INSTRUCTIONS',
- ],
- }, {
- 'defines': [
- '__mips_soft_float=1'
- ],
- }],
- ['mips_arch_variant=="rx"', {
- 'defines': [
- '_MIPS_ARCH_MIPS32RX',
- 'FPU_MODE_FPXX',
- ],
- }],
- ['mips_arch_variant=="r6"', {
- 'defines': [
- '_MIPS_ARCH_MIPS32R6',
- 'FPU_MODE_FP64',
- ],
- }],
- ['mips_arch_variant=="r2"', {
- 'defines': ['_MIPS_ARCH_MIPS32R2',],
+ }], #_toolset=="target
+ ['_toolset=="host"', {
'conditions': [
- ['mips_fpu_mode=="fp64"', {
- 'defines': ['FPU_MODE_FP64',],
+ ['mips_arch_variant=="rx"', {
+ 'defines': [
+ '_MIPS_ARCH_MIPS32RX',
+ 'FPU_MODE_FPXX',
+ ],
}],
- ['mips_fpu_mode=="fpxx"', {
- 'defines': ['FPU_MODE_FPXX',],
+ ['mips_arch_variant=="r6"', {
+ 'defines': [
+ '_MIPS_ARCH_MIPS32R6',
+ 'FPU_MODE_FP64',
+ ],
}],
- ['mips_fpu_mode=="fp32"', {
+ ['mips_arch_variant=="r2"', {
+ 'conditions': [
+ ['mips_fpu_mode=="fp64"', {
+ 'defines': [
+ '_MIPS_ARCH_MIPS32R2',
+ 'FPU_MODE_FP64',
+ ],
+ }],
+ ['mips_fpu_mode=="fpxx"', {
+ 'defines': [
+ '_MIPS_ARCH_MIPS32R2',
+ 'FPU_MODE_FPXX',
+ ],
+ }],
+ ['mips_fpu_mode=="fp32"', {
+ 'defines': [
+ '_MIPS_ARCH_MIPS32R2',
+ 'FPU_MODE_FP32'
+ ],
+ }],
+ ],
+ }],
+ ['mips_arch_variant=="r1"', {
'defines': ['FPU_MODE_FP32',],
}],
- ],
- }],
- ['mips_arch_variant=="r1"', {
- 'defines': ['FPU_MODE_FP32',],
- }],
- ['mips_arch_variant=="loongson"', {
- 'defines': [
- '_MIPS_ARCH_LOONGSON',
- 'FPU_MODE_FP32',
- ],
+ ['mips_arch_variant=="loongson"', {
+ 'defines': [
+ '_MIPS_ARCH_LOONGSON',
+ 'FPU_MODE_FP32',
+ ],
+ }],
+ ]
}],
],
}], # v8_target_arch=="mipsel"
@@ -484,40 +652,6 @@
'V8_TARGET_ARCH_MIPS64',
],
'conditions': [
- ['v8_target_arch==target_arch and android_webview_build==0', {
- # Target built with a Mips CXX compiler.
- 'target_conditions': [
- ['_toolset=="target"', {
- 'cflags': ['-EL'],
- 'ldflags': ['-EL'],
- 'conditions': [
- [ 'v8_use_mips_abi_hardfloat=="true"', {
- 'cflags': ['-mhard-float'],
- 'ldflags': ['-mhard-float'],
- }, {
- 'cflags': ['-msoft-float'],
- 'ldflags': ['-msoft-float'],
- }],
- ['mips_arch_variant=="r6"', {
- 'cflags': ['-mips64r6', '-mabi=64', '-Wa,-mips64r6'],
- 'ldflags': [
- '-mips64r6', '-mabi=64',
- '-Wl,--dynamic-linker=$(LDSO_PATH)',
- '-Wl,--rpath=$(LD_R_PATH)',
- ],
- }],
- ['mips_arch_variant=="r2"', {
- 'cflags': ['-mips64r2', '-mabi=64', '-Wa,-mips64r2'],
- 'ldflags': [
- '-mips64r2', '-mabi=64',
- '-Wl,--dynamic-linker=$(LDSO_PATH)',
- '-Wl,--rpath=$(LD_R_PATH)',
- ],
- }],
- ],
- }],
- ],
- }],
[ 'v8_can_use_fpu_instructions=="true"', {
'defines': [
'CAN_USE_FPU_INSTRUCTIONS',
@@ -533,12 +667,64 @@
'__mips_soft_float=1'
],
}],
- ['mips_arch_variant=="r6"', {
- 'defines': ['_MIPS_ARCH_MIPS64R6',],
- }],
- ['mips_arch_variant=="r2"', {
- 'defines': ['_MIPS_ARCH_MIPS64R2',],
- }],
+ ],
+ 'target_conditions': [
+ ['_toolset=="target"', {
+ 'conditions': [
+ ['v8_target_arch==target_arch and android_webview_build==0', {
+ 'cflags': ['-EL'],
+ 'ldflags': ['-EL'],
+ 'conditions': [
+ [ 'v8_use_mips_abi_hardfloat=="true"', {
+ 'cflags': ['-mhard-float'],
+ 'ldflags': ['-mhard-float'],
+ }, {
+ 'cflags': ['-msoft-float'],
+ 'ldflags': ['-msoft-float'],
+ }],
+ ['mips_arch_variant=="r6"', {
+ 'defines': ['_MIPS_ARCH_MIPS64R6',],
+ 'cflags': ['-mips64r6', '-mabi=64', '-Wa,-mips64r6'],
+ 'ldflags': [
+ '-mips64r6', '-mabi=64',
+ '-Wl,--dynamic-linker=$(LDSO_PATH)',
+ '-Wl,--rpath=$(LD_R_PATH)',
+ ],
+ }],
+ ['mips_arch_variant=="r2"', {
+ 'defines': ['_MIPS_ARCH_MIPS64R2',],
+ 'cflags': ['-mips64r2', '-mabi=64', '-Wa,-mips64r2'],
+ 'ldflags': [
+ '-mips64r2', '-mabi=64',
+ '-Wl,--dynamic-linker=$(LDSO_PATH)',
+ '-Wl,--rpath=$(LD_R_PATH)',
+ ],
+ }],
+ ],
+ }, {
+ # 'v8_target_arch!=target_arch'
+ # Target not built with an MIPS CXX compiler (simulator build).
+ 'conditions': [
+ ['mips_arch_variant=="r6"', {
+ 'defines': ['_MIPS_ARCH_MIPS64R6',],
+ }],
+ ['mips_arch_variant=="r2"', {
+ 'defines': ['_MIPS_ARCH_MIPS64R2',],
+ }],
+ ],
+ }],
+ ],
+ }], #'_toolset=="target"
+ ['_toolset=="host"', {
+ 'conditions': [
+ ['mips_arch_variant=="r6"', {
+ 'defines': ['_MIPS_ARCH_MIPS64R6',],
+ }],
+ ['mips_arch_variant=="r2"', {
+ 'defines': ['_MIPS_ARCH_MIPS64R2',],
+ }],
+ ],
+ }], #'_toolset=="host"
],
}], # v8_target_arch=="mips64el"
['v8_target_arch=="x64"', {
diff --git a/src/base/cpu.cc b/src/base/cpu.cc
index fbfbcf6..cd40d4f 100644
--- a/src/base/cpu.cc
+++ b/src/base/cpu.cc
@@ -119,13 +119,18 @@
int __detect_fp64_mode(void) {
double result = 0;
// Bit representation of (double)1 is 0x3FF0000000000000.
- asm(
- "lui $t0, 0x3FF0\n\t"
- "ldc1 $f0, %0\n\t"
- "mtc1 $t0, $f1\n\t"
- "sdc1 $f0, %0\n\t"
- : "+m" (result)
- : : "t0", "$f0", "$f1", "memory");
+ __asm__ volatile(
+ ".set push\n\t"
+ ".set noreorder\n\t"
+ ".set oddspreg\n\t"
+ "lui $t0, 0x3FF0\n\t"
+ "ldc1 $f0, %0\n\t"
+ "mtc1 $t0, $f1\n\t"
+ "sdc1 $f0, %0\n\t"
+ ".set pop\n\t"
+ : "+m"(result)
+ :
+ : "t0", "$f0", "$f1", "memory");
return !(result == 1);
}
@@ -133,9 +138,22 @@
int __detect_mips_arch_revision(void) {
// TODO(dusmil): Do the specific syscall as soon as it is implemented in mips
- // kernel. Currently fail-back to the least common denominator which is
- // mips32 revision 1.
- return 1;
+ // kernel.
+ uint32_t result = 0;
+ __asm__ volatile(
+ "move $v0, $zero\n\t"
+ // Encoding for "addi $v0, $v0, 1" on non-r6,
+ // which is encoding for "bovc $v0, %v0, 1" on r6.
+ // Use machine code directly to avoid compilation errors with different
+ // toolchains and maintain compatibility.
+ ".word 0x20420001\n\t"
+ "sw $v0, %0\n\t"
+ : "=m"(result)
+ :
+ : "v0", "memory");
+ // Result is 0 on r6 architectures, 1 on other architecture revisions.
+ // Fall-back to the least common denominator which is mips32 revision 1.
+ return result ? 1 : 6;
}
#endif
diff --git a/src/mips/constants-mips.h b/src/mips/constants-mips.h
index 5ead110..c2eb4ca 100644
--- a/src/mips/constants-mips.h
+++ b/src/mips/constants-mips.h
@@ -105,7 +105,7 @@
(kArchVariant == check)
#else
#define IsMipsArchVariant(check) \
- (CpuFeatures::IsSupported(check))
+ (CpuFeatures::IsSupported(static_cast<CpuFeature>(check)))
#endif
diff --git a/src/version.cc b/src/version.cc
index a6c529e..0502ba1 100644
--- a/src/version.cc
+++ b/src/version.cc
@@ -35,7 +35,7 @@
#define MAJOR_VERSION 3
#define MINOR_VERSION 29
#define BUILD_NUMBER 88
-#define PATCH_LEVEL 17
+#define PATCH_LEVEL 18
// Use 1 for candidates and 0 otherwise.
// (Boolean macro values are not supported by all preprocessors.)
#define IS_CANDIDATE_VERSION 0