Update V8 to r5901 as required by WebKit r73109
Change-Id: Ic48c5b085ce90e0151e2e7e58c4c5afe87fce9d1
diff --git a/src/arm/assembler-arm.cc b/src/arm/assembler-arm.cc
index 4cb421c..cfdd164 100644
--- a/src/arm/assembler-arm.cc
+++ b/src/arm/assembler-arm.cc
@@ -397,13 +397,6 @@
}
-bool Assembler::IsNop(Instr instr, int type) {
- // Check for mov rx, rx.
- ASSERT(0 <= type && type <= 14); // mov pc, pc is not a nop.
- return instr == (al | 13*B21 | type*B12 | type);
-}
-
-
bool Assembler::IsBranch(Instr instr) {
return (instr & (B27 | B25)) == (B27 | B25);
}
@@ -510,6 +503,13 @@
}
+bool Assembler::IsLdrPcImmediateOffset(Instr instr) {
+ // Check the instruction is indeed a
+ // ldr<cond> <Rd>, [pc +/- offset_12].
+ return (instr & 0x0f7f0000) == 0x051f0000;
+}
+
+
// Labels refer to positions in the (to be) generated code.
// There are bound, linked, and unused labels.
//
@@ -1113,8 +1113,8 @@
positions_recorder()->WriteRecordedPositions();
}
// Don't allow nop instructions in the form mov rn, rn to be generated using
- // the mov instruction. They must be generated using nop(int)
- // pseudo instructions.
+ // the mov instruction. They must be generated using nop(int/NopMarkerTypes)
+ // or MarkCode(int/NopMarkerTypes) pseudo instructions.
ASSERT(!(src.is_reg() && src.rm().is(dst) && s == LeaveCC && cond == al));
addrmod1(cond | 13*B21 | s, r0, dst, src);
}
@@ -2376,6 +2376,13 @@
}
+bool Assembler::IsNop(Instr instr, int type) {
+ // Check for mov rx, rx.
+ ASSERT(0 <= type && type <= 14); // mov pc, pc is not a nop.
+ return instr == (al | 13*B21 | type*B12 | type);
+}
+
+
bool Assembler::ImmediateFitsAddrMode1Instruction(int32_t imm32) {
uint32_t dummy1;
uint32_t dummy2;