Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1 | // Copyright (c) 1994-2006 Sun Microsystems Inc. |
| 2 | // All Rights Reserved. |
| 3 | // |
| 4 | // Redistribution and use in source and binary forms, with or without |
| 5 | // modification, are permitted provided that the following conditions |
| 6 | // are met: |
| 7 | // |
| 8 | // - Redistributions of source code must retain the above copyright notice, |
| 9 | // this list of conditions and the following disclaimer. |
| 10 | // |
| 11 | // - Redistribution in binary form must reproduce the above copyright |
| 12 | // notice, this list of conditions and the following disclaimer in the |
| 13 | // documentation and/or other materials provided with the |
| 14 | // distribution. |
| 15 | // |
| 16 | // - Neither the name of Sun Microsystems or the names of contributors may |
| 17 | // be used to endorse or promote products derived from this software without |
| 18 | // specific prior written permission. |
| 19 | // |
| 20 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 21 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 22 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 23 | // FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 24 | // COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 25 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 26 | // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| 27 | // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 28 | // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
| 29 | // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 30 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED |
| 31 | // OF THE POSSIBILITY OF SUCH DAMAGE. |
| 32 | |
Leon Clarke | d91b9f7 | 2010-01-27 17:25:45 +0000 | [diff] [blame] | 33 | // The original source code covered by the above license above has been |
| 34 | // modified significantly by Google Inc. |
| 35 | // Copyright 2010 the V8 project authors. All rights reserved. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 36 | |
| 37 | #include "v8.h" |
| 38 | |
Leon Clarke | f7060e2 | 2010-06-03 12:02:55 +0100 | [diff] [blame] | 39 | #if defined(V8_TARGET_ARCH_ARM) |
| 40 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 41 | #include "arm/assembler-arm-inl.h" |
| 42 | #include "serialize.h" |
| 43 | |
| 44 | namespace v8 { |
| 45 | namespace internal { |
| 46 | |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 47 | // Safe default is no features. |
| 48 | unsigned CpuFeatures::supported_ = 0; |
| 49 | unsigned CpuFeatures::enabled_ = 0; |
| 50 | unsigned CpuFeatures::found_by_runtime_probing_ = 0; |
| 51 | |
Andrei Popescu | 402d937 | 2010-02-26 13:31:12 +0000 | [diff] [blame] | 52 | |
| 53 | #ifdef __arm__ |
| 54 | static uint64_t CpuFeaturesImpliedByCompiler() { |
| 55 | uint64_t answer = 0; |
| 56 | #ifdef CAN_USE_ARMV7_INSTRUCTIONS |
| 57 | answer |= 1u << ARMv7; |
| 58 | #endif // def CAN_USE_ARMV7_INSTRUCTIONS |
| 59 | // If the compiler is allowed to use VFP then we can use VFP too in our code |
| 60 | // generation even when generating snapshots. This won't work for cross |
| 61 | // compilation. |
| 62 | #if defined(__VFP_FP__) && !defined(__SOFTFP__) |
| 63 | answer |= 1u << VFP3; |
| 64 | #endif // defined(__VFP_FP__) && !defined(__SOFTFP__) |
| 65 | #ifdef CAN_USE_VFP_INSTRUCTIONS |
| 66 | answer |= 1u << VFP3; |
| 67 | #endif // def CAN_USE_VFP_INSTRUCTIONS |
| 68 | return answer; |
| 69 | } |
| 70 | #endif // def __arm__ |
| 71 | |
| 72 | |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 73 | void CpuFeatures::Probe() { |
Andrei Popescu | 402d937 | 2010-02-26 13:31:12 +0000 | [diff] [blame] | 74 | #ifndef __arm__ |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 75 | // For the simulator=arm build, use VFP when FLAG_enable_vfp3 is enabled. |
| 76 | if (FLAG_enable_vfp3) { |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 77 | supported_ |= 1u << VFP3; |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 78 | } |
| 79 | // For the simulator=arm build, use ARMv7 when FLAG_enable_armv7 is enabled |
| 80 | if (FLAG_enable_armv7) { |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 81 | supported_ |= 1u << ARMv7; |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 82 | } |
Andrei Popescu | 402d937 | 2010-02-26 13:31:12 +0000 | [diff] [blame] | 83 | #else // def __arm__ |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 84 | if (Serializer::enabled()) { |
Andrei Popescu | 402d937 | 2010-02-26 13:31:12 +0000 | [diff] [blame] | 85 | supported_ |= OS::CpuFeaturesImpliedByPlatform(); |
| 86 | supported_ |= CpuFeaturesImpliedByCompiler(); |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 87 | return; // No features if we might serialize. |
| 88 | } |
| 89 | |
| 90 | if (OS::ArmCpuHasFeature(VFP3)) { |
| 91 | // This implementation also sets the VFP flags if |
| 92 | // runtime detection of VFP returns true. |
| 93 | supported_ |= 1u << VFP3; |
| 94 | found_by_runtime_probing_ |= 1u << VFP3; |
| 95 | } |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 96 | |
| 97 | if (OS::ArmCpuHasFeature(ARMv7)) { |
| 98 | supported_ |= 1u << ARMv7; |
| 99 | found_by_runtime_probing_ |= 1u << ARMv7; |
| 100 | } |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 101 | #endif |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 102 | } |
| 103 | |
| 104 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 105 | // ----------------------------------------------------------------------------- |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 106 | // Implementation of RelocInfo |
| 107 | |
| 108 | const int RelocInfo::kApplyMask = 0; |
| 109 | |
| 110 | |
Leon Clarke | f7060e2 | 2010-06-03 12:02:55 +0100 | [diff] [blame] | 111 | bool RelocInfo::IsCodedSpecially() { |
| 112 | // The deserializer needs to know whether a pointer is specially coded. Being |
| 113 | // specially coded on ARM means that it is a movw/movt instruction. We don't |
| 114 | // generate those yet. |
| 115 | return false; |
| 116 | } |
| 117 | |
| 118 | |
| 119 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 120 | void RelocInfo::PatchCode(byte* instructions, int instruction_count) { |
| 121 | // Patch the code at the current address with the supplied instructions. |
| 122 | Instr* pc = reinterpret_cast<Instr*>(pc_); |
| 123 | Instr* instr = reinterpret_cast<Instr*>(instructions); |
| 124 | for (int i = 0; i < instruction_count; i++) { |
| 125 | *(pc + i) = *(instr + i); |
| 126 | } |
| 127 | |
| 128 | // Indicate that code has changed. |
| 129 | CPU::FlushICache(pc_, instruction_count * Assembler::kInstrSize); |
| 130 | } |
| 131 | |
| 132 | |
| 133 | // Patch the code at the current PC with a call to the target address. |
| 134 | // Additional guard instructions can be added if required. |
| 135 | void RelocInfo::PatchCodeWithCall(Address target, int guard_bytes) { |
| 136 | // Patch the code at the current address with a call to the target. |
| 137 | UNIMPLEMENTED(); |
| 138 | } |
| 139 | |
| 140 | |
| 141 | // ----------------------------------------------------------------------------- |
| 142 | // Implementation of Operand and MemOperand |
| 143 | // See assembler-arm-inl.h for inlined constructors |
| 144 | |
| 145 | Operand::Operand(Handle<Object> handle) { |
| 146 | rm_ = no_reg; |
| 147 | // Verify all Objects referred by code are NOT in new space. |
| 148 | Object* obj = *handle; |
| 149 | ASSERT(!Heap::InNewSpace(obj)); |
| 150 | if (obj->IsHeapObject()) { |
| 151 | imm32_ = reinterpret_cast<intptr_t>(handle.location()); |
| 152 | rmode_ = RelocInfo::EMBEDDED_OBJECT; |
| 153 | } else { |
| 154 | // no relocation needed |
| 155 | imm32_ = reinterpret_cast<intptr_t>(obj); |
| 156 | rmode_ = RelocInfo::NONE; |
| 157 | } |
| 158 | } |
| 159 | |
| 160 | |
| 161 | Operand::Operand(Register rm, ShiftOp shift_op, int shift_imm) { |
| 162 | ASSERT(is_uint5(shift_imm)); |
| 163 | ASSERT(shift_op != ROR || shift_imm != 0); // use RRX if you mean it |
| 164 | rm_ = rm; |
| 165 | rs_ = no_reg; |
| 166 | shift_op_ = shift_op; |
| 167 | shift_imm_ = shift_imm & 31; |
| 168 | if (shift_op == RRX) { |
| 169 | // encoded as ROR with shift_imm == 0 |
| 170 | ASSERT(shift_imm == 0); |
| 171 | shift_op_ = ROR; |
| 172 | shift_imm_ = 0; |
| 173 | } |
| 174 | } |
| 175 | |
| 176 | |
| 177 | Operand::Operand(Register rm, ShiftOp shift_op, Register rs) { |
| 178 | ASSERT(shift_op != RRX); |
| 179 | rm_ = rm; |
| 180 | rs_ = no_reg; |
| 181 | shift_op_ = shift_op; |
| 182 | rs_ = rs; |
| 183 | } |
| 184 | |
| 185 | |
| 186 | MemOperand::MemOperand(Register rn, int32_t offset, AddrMode am) { |
| 187 | rn_ = rn; |
| 188 | rm_ = no_reg; |
| 189 | offset_ = offset; |
| 190 | am_ = am; |
| 191 | } |
| 192 | |
| 193 | MemOperand::MemOperand(Register rn, Register rm, AddrMode am) { |
| 194 | rn_ = rn; |
| 195 | rm_ = rm; |
| 196 | shift_op_ = LSL; |
| 197 | shift_imm_ = 0; |
| 198 | am_ = am; |
| 199 | } |
| 200 | |
| 201 | |
| 202 | MemOperand::MemOperand(Register rn, Register rm, |
| 203 | ShiftOp shift_op, int shift_imm, AddrMode am) { |
| 204 | ASSERT(is_uint5(shift_imm)); |
| 205 | rn_ = rn; |
| 206 | rm_ = rm; |
| 207 | shift_op_ = shift_op; |
| 208 | shift_imm_ = shift_imm & 31; |
| 209 | am_ = am; |
| 210 | } |
| 211 | |
| 212 | |
| 213 | // ----------------------------------------------------------------------------- |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 214 | // Implementation of Assembler. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 215 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 216 | // Instruction encoding bits. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 217 | enum { |
| 218 | H = 1 << 5, // halfword (or byte) |
| 219 | S6 = 1 << 6, // signed (or unsigned) |
| 220 | L = 1 << 20, // load (or store) |
| 221 | S = 1 << 20, // set condition code (or leave unchanged) |
| 222 | W = 1 << 21, // writeback base register (or leave unchanged) |
| 223 | A = 1 << 21, // accumulate in multiply instruction (or not) |
| 224 | B = 1 << 22, // unsigned byte (or word) |
| 225 | N = 1 << 22, // long (or short) |
| 226 | U = 1 << 23, // positive (or negative) offset/index |
| 227 | P = 1 << 24, // offset/pre-indexed addressing (or post-indexed addressing) |
| 228 | I = 1 << 25, // immediate shifter operand (or not) |
| 229 | |
| 230 | B4 = 1 << 4, |
| 231 | B5 = 1 << 5, |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 232 | B6 = 1 << 6, |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 233 | B7 = 1 << 7, |
| 234 | B8 = 1 << 8, |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 235 | B9 = 1 << 9, |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 236 | B12 = 1 << 12, |
| 237 | B16 = 1 << 16, |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 238 | B18 = 1 << 18, |
| 239 | B19 = 1 << 19, |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 240 | B20 = 1 << 20, |
| 241 | B21 = 1 << 21, |
| 242 | B22 = 1 << 22, |
| 243 | B23 = 1 << 23, |
| 244 | B24 = 1 << 24, |
| 245 | B25 = 1 << 25, |
| 246 | B26 = 1 << 26, |
| 247 | B27 = 1 << 27, |
| 248 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 249 | // Instruction bit masks. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 250 | RdMask = 15 << 12, // in str instruction |
| 251 | CondMask = 15 << 28, |
| 252 | CoprocessorMask = 15 << 8, |
| 253 | OpCodeMask = 15 << 21, // in data-processing instructions |
| 254 | Imm24Mask = (1 << 24) - 1, |
| 255 | Off12Mask = (1 << 12) - 1, |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 256 | // Reserved condition. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 257 | nv = 15 << 28 |
| 258 | }; |
| 259 | |
| 260 | |
| 261 | // add(sp, sp, 4) instruction (aka Pop()) |
| 262 | static const Instr kPopInstruction = |
| 263 | al | 4 * B21 | 4 | LeaveCC | I | sp.code() * B16 | sp.code() * B12; |
| 264 | // str(r, MemOperand(sp, 4, NegPreIndex), al) instruction (aka push(r)) |
| 265 | // register r is not encoded. |
| 266 | static const Instr kPushRegPattern = |
| 267 | al | B26 | 4 | NegPreIndex | sp.code() * B16; |
| 268 | // ldr(r, MemOperand(sp, 4, PostIndex), al) instruction (aka pop(r)) |
| 269 | // register r is not encoded. |
| 270 | static const Instr kPopRegPattern = |
| 271 | al | B26 | L | 4 | PostIndex | sp.code() * B16; |
| 272 | // mov lr, pc |
| 273 | const Instr kMovLrPc = al | 13*B21 | pc.code() | lr.code() * B12; |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 274 | // ldr rd, [pc, #offset] |
| 275 | const Instr kLdrPCMask = CondMask | 15 * B24 | 7 * B20 | 15 * B16; |
| 276 | const Instr kLdrPCPattern = al | 5 * B24 | L | pc.code() * B16; |
| 277 | // blxcc rm |
| 278 | const Instr kBlxRegMask = |
| 279 | 15 * B24 | 15 * B20 | 15 * B16 | 15 * B12 | 15 * B8 | 15 * B4; |
| 280 | const Instr kBlxRegPattern = |
| 281 | B24 | B21 | 15 * B16 | 15 * B12 | 15 * B8 | 3 * B4; |
Kristian Monsen | 9dcf7e2 | 2010-06-28 14:14:28 +0100 | [diff] [blame] | 282 | const Instr kMovMvnMask = 0x6d * B21 | 0xf * B16; |
| 283 | const Instr kMovMvnPattern = 0xd * B21; |
| 284 | const Instr kMovMvnFlip = B22; |
| 285 | const Instr kMovLeaveCCMask = 0xdff * B16; |
| 286 | const Instr kMovLeaveCCPattern = 0x1a0 * B16; |
| 287 | const Instr kMovwMask = 0xff * B20; |
| 288 | const Instr kMovwPattern = 0x30 * B20; |
| 289 | const Instr kMovwLeaveCCFlip = 0x5 * B21; |
| 290 | const Instr kCmpCmnMask = 0xdd * B20 | 0xf * B12; |
| 291 | const Instr kCmpCmnPattern = 0x15 * B20; |
| 292 | const Instr kCmpCmnFlip = B21; |
| 293 | const Instr kALUMask = 0x6f * B21; |
| 294 | const Instr kAddPattern = 0x4 * B21; |
| 295 | const Instr kSubPattern = 0x2 * B21; |
| 296 | const Instr kBicPattern = 0xe * B21; |
| 297 | const Instr kAndPattern = 0x0 * B21; |
| 298 | const Instr kAddSubFlip = 0x6 * B21; |
| 299 | const Instr kAndBicFlip = 0xe * B21; |
| 300 | |
Leon Clarke | f7060e2 | 2010-06-03 12:02:55 +0100 | [diff] [blame] | 301 | // A mask for the Rd register for push, pop, ldr, str instructions. |
| 302 | const Instr kRdMask = 0x0000f000; |
| 303 | static const int kRdShift = 12; |
| 304 | static const Instr kLdrRegFpOffsetPattern = |
| 305 | al | B26 | L | Offset | fp.code() * B16; |
| 306 | static const Instr kStrRegFpOffsetPattern = |
| 307 | al | B26 | Offset | fp.code() * B16; |
| 308 | static const Instr kLdrRegFpNegOffsetPattern = |
| 309 | al | B26 | L | NegOffset | fp.code() * B16; |
| 310 | static const Instr kStrRegFpNegOffsetPattern = |
| 311 | al | B26 | NegOffset | fp.code() * B16; |
| 312 | static const Instr kLdrStrInstrTypeMask = 0xffff0000; |
| 313 | static const Instr kLdrStrInstrArgumentMask = 0x0000ffff; |
| 314 | static const Instr kLdrStrOffsetMask = 0x00000fff; |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 315 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 316 | // Spare buffer. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 317 | static const int kMinimalBufferSize = 4*KB; |
| 318 | static byte* spare_buffer_ = NULL; |
| 319 | |
Teng-Hui Zhu | 3e5fa29 | 2010-11-09 16:16:48 -0800 | [diff] [blame] | 320 | Assembler::Assembler(void* buffer, int buffer_size) |
| 321 | : positions_recorder_(this) { |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 322 | if (buffer == NULL) { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 323 | // Do our own buffer management. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 324 | if (buffer_size <= kMinimalBufferSize) { |
| 325 | buffer_size = kMinimalBufferSize; |
| 326 | |
| 327 | if (spare_buffer_ != NULL) { |
| 328 | buffer = spare_buffer_; |
| 329 | spare_buffer_ = NULL; |
| 330 | } |
| 331 | } |
| 332 | if (buffer == NULL) { |
| 333 | buffer_ = NewArray<byte>(buffer_size); |
| 334 | } else { |
| 335 | buffer_ = static_cast<byte*>(buffer); |
| 336 | } |
| 337 | buffer_size_ = buffer_size; |
| 338 | own_buffer_ = true; |
| 339 | |
| 340 | } else { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 341 | // Use externally provided buffer instead. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 342 | ASSERT(buffer_size > 0); |
| 343 | buffer_ = static_cast<byte*>(buffer); |
| 344 | buffer_size_ = buffer_size; |
| 345 | own_buffer_ = false; |
| 346 | } |
| 347 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 348 | // Setup buffer pointers. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 349 | ASSERT(buffer_ != NULL); |
| 350 | pc_ = buffer_; |
| 351 | reloc_info_writer.Reposition(buffer_ + buffer_size, pc_); |
| 352 | num_prinfo_ = 0; |
| 353 | next_buffer_check_ = 0; |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 354 | const_pool_blocked_nesting_ = 0; |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 355 | no_const_pool_before_ = 0; |
| 356 | last_const_pool_end_ = 0; |
| 357 | last_bound_pos_ = 0; |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 358 | } |
| 359 | |
| 360 | |
| 361 | Assembler::~Assembler() { |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 362 | ASSERT(const_pool_blocked_nesting_ == 0); |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 363 | if (own_buffer_) { |
| 364 | if (spare_buffer_ == NULL && buffer_size_ == kMinimalBufferSize) { |
| 365 | spare_buffer_ = buffer_; |
| 366 | } else { |
| 367 | DeleteArray(buffer_); |
| 368 | } |
| 369 | } |
| 370 | } |
| 371 | |
| 372 | |
| 373 | void Assembler::GetCode(CodeDesc* desc) { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 374 | // Emit constant pool if necessary. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 375 | CheckConstPool(true, false); |
| 376 | ASSERT(num_prinfo_ == 0); |
| 377 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 378 | // Setup code descriptor. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 379 | desc->buffer = buffer_; |
| 380 | desc->buffer_size = buffer_size_; |
| 381 | desc->instr_size = pc_offset(); |
| 382 | desc->reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos(); |
| 383 | } |
| 384 | |
| 385 | |
| 386 | void Assembler::Align(int m) { |
| 387 | ASSERT(m >= 4 && IsPowerOf2(m)); |
| 388 | while ((pc_offset() & (m - 1)) != 0) { |
| 389 | nop(); |
| 390 | } |
| 391 | } |
| 392 | |
| 393 | |
Kristian Monsen | 9dcf7e2 | 2010-06-28 14:14:28 +0100 | [diff] [blame] | 394 | void Assembler::CodeTargetAlign() { |
| 395 | // Preferred alignment of jump targets on some ARM chips. |
| 396 | Align(8); |
| 397 | } |
| 398 | |
| 399 | |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 400 | bool Assembler::IsNop(Instr instr, int type) { |
| 401 | // Check for mov rx, rx. |
| 402 | ASSERT(0 <= type && type <= 14); // mov pc, pc is not a nop. |
| 403 | return instr == (al | 13*B21 | type*B12 | type); |
| 404 | } |
| 405 | |
| 406 | |
| 407 | bool Assembler::IsBranch(Instr instr) { |
| 408 | return (instr & (B27 | B25)) == (B27 | B25); |
| 409 | } |
| 410 | |
| 411 | |
| 412 | int Assembler::GetBranchOffset(Instr instr) { |
| 413 | ASSERT(IsBranch(instr)); |
| 414 | // Take the jump offset in the lower 24 bits, sign extend it and multiply it |
| 415 | // with 4 to get the offset in bytes. |
| 416 | return ((instr & Imm24Mask) << 8) >> 6; |
| 417 | } |
| 418 | |
| 419 | |
| 420 | bool Assembler::IsLdrRegisterImmediate(Instr instr) { |
| 421 | return (instr & (B27 | B26 | B25 | B22 | B20)) == (B26 | B20); |
| 422 | } |
| 423 | |
| 424 | |
| 425 | int Assembler::GetLdrRegisterImmediateOffset(Instr instr) { |
| 426 | ASSERT(IsLdrRegisterImmediate(instr)); |
| 427 | bool positive = (instr & B23) == B23; |
| 428 | int offset = instr & Off12Mask; // Zero extended offset. |
| 429 | return positive ? offset : -offset; |
| 430 | } |
| 431 | |
| 432 | |
| 433 | Instr Assembler::SetLdrRegisterImmediateOffset(Instr instr, int offset) { |
| 434 | ASSERT(IsLdrRegisterImmediate(instr)); |
| 435 | bool positive = offset >= 0; |
| 436 | if (!positive) offset = -offset; |
| 437 | ASSERT(is_uint12(offset)); |
| 438 | // Set bit indicating whether the offset should be added. |
| 439 | instr = (instr & ~B23) | (positive ? B23 : 0); |
| 440 | // Set the actual offset. |
| 441 | return (instr & ~Off12Mask) | offset; |
| 442 | } |
| 443 | |
| 444 | |
Kristian Monsen | 50ef84f | 2010-07-29 15:18:00 +0100 | [diff] [blame] | 445 | bool Assembler::IsStrRegisterImmediate(Instr instr) { |
| 446 | return (instr & (B27 | B26 | B25 | B22 | B20)) == B26; |
| 447 | } |
| 448 | |
| 449 | |
| 450 | Instr Assembler::SetStrRegisterImmediateOffset(Instr instr, int offset) { |
| 451 | ASSERT(IsStrRegisterImmediate(instr)); |
| 452 | bool positive = offset >= 0; |
| 453 | if (!positive) offset = -offset; |
| 454 | ASSERT(is_uint12(offset)); |
| 455 | // Set bit indicating whether the offset should be added. |
| 456 | instr = (instr & ~B23) | (positive ? B23 : 0); |
| 457 | // Set the actual offset. |
| 458 | return (instr & ~Off12Mask) | offset; |
| 459 | } |
| 460 | |
| 461 | |
| 462 | bool Assembler::IsAddRegisterImmediate(Instr instr) { |
| 463 | return (instr & (B27 | B26 | B25 | B24 | B23 | B22 | B21)) == (B25 | B23); |
| 464 | } |
| 465 | |
| 466 | |
| 467 | Instr Assembler::SetAddRegisterImmediateOffset(Instr instr, int offset) { |
| 468 | ASSERT(IsAddRegisterImmediate(instr)); |
| 469 | ASSERT(offset >= 0); |
| 470 | ASSERT(is_uint12(offset)); |
| 471 | // Set the offset. |
| 472 | return (instr & ~Off12Mask) | offset; |
| 473 | } |
| 474 | |
| 475 | |
Leon Clarke | f7060e2 | 2010-06-03 12:02:55 +0100 | [diff] [blame] | 476 | Register Assembler::GetRd(Instr instr) { |
| 477 | Register reg; |
| 478 | reg.code_ = ((instr & kRdMask) >> kRdShift); |
| 479 | return reg; |
| 480 | } |
| 481 | |
| 482 | |
| 483 | bool Assembler::IsPush(Instr instr) { |
| 484 | return ((instr & ~kRdMask) == kPushRegPattern); |
| 485 | } |
| 486 | |
| 487 | |
| 488 | bool Assembler::IsPop(Instr instr) { |
| 489 | return ((instr & ~kRdMask) == kPopRegPattern); |
| 490 | } |
| 491 | |
| 492 | |
| 493 | bool Assembler::IsStrRegFpOffset(Instr instr) { |
| 494 | return ((instr & kLdrStrInstrTypeMask) == kStrRegFpOffsetPattern); |
| 495 | } |
| 496 | |
| 497 | |
| 498 | bool Assembler::IsLdrRegFpOffset(Instr instr) { |
| 499 | return ((instr & kLdrStrInstrTypeMask) == kLdrRegFpOffsetPattern); |
| 500 | } |
| 501 | |
| 502 | |
| 503 | bool Assembler::IsStrRegFpNegOffset(Instr instr) { |
| 504 | return ((instr & kLdrStrInstrTypeMask) == kStrRegFpNegOffsetPattern); |
| 505 | } |
| 506 | |
| 507 | |
| 508 | bool Assembler::IsLdrRegFpNegOffset(Instr instr) { |
| 509 | return ((instr & kLdrStrInstrTypeMask) == kLdrRegFpNegOffsetPattern); |
| 510 | } |
| 511 | |
| 512 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 513 | // Labels refer to positions in the (to be) generated code. |
| 514 | // There are bound, linked, and unused labels. |
| 515 | // |
| 516 | // Bound labels refer to known positions in the already |
| 517 | // generated code. pos() is the position the label refers to. |
| 518 | // |
| 519 | // Linked labels refer to unknown positions in the code |
| 520 | // to be generated; pos() is the position of the last |
| 521 | // instruction using the label. |
| 522 | |
| 523 | |
| 524 | // The link chain is terminated by a negative code position (must be aligned) |
| 525 | const int kEndOfChain = -4; |
| 526 | |
| 527 | |
| 528 | int Assembler::target_at(int pos) { |
| 529 | Instr instr = instr_at(pos); |
| 530 | if ((instr & ~Imm24Mask) == 0) { |
| 531 | // Emitted label constant, not part of a branch. |
| 532 | return instr - (Code::kHeaderSize - kHeapObjectTag); |
| 533 | } |
| 534 | ASSERT((instr & 7*B25) == 5*B25); // b, bl, or blx imm24 |
| 535 | int imm26 = ((instr & Imm24Mask) << 8) >> 6; |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 536 | if ((instr & CondMask) == nv && (instr & B24) != 0) { |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 537 | // blx uses bit 24 to encode bit 2 of imm26 |
| 538 | imm26 += 2; |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 539 | } |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 540 | return pos + kPcLoadDelta + imm26; |
| 541 | } |
| 542 | |
| 543 | |
| 544 | void Assembler::target_at_put(int pos, int target_pos) { |
| 545 | Instr instr = instr_at(pos); |
| 546 | if ((instr & ~Imm24Mask) == 0) { |
| 547 | ASSERT(target_pos == kEndOfChain || target_pos >= 0); |
| 548 | // Emitted label constant, not part of a branch. |
| 549 | // Make label relative to Code* of generated Code object. |
| 550 | instr_at_put(pos, target_pos + (Code::kHeaderSize - kHeapObjectTag)); |
| 551 | return; |
| 552 | } |
| 553 | int imm26 = target_pos - (pos + kPcLoadDelta); |
| 554 | ASSERT((instr & 7*B25) == 5*B25); // b, bl, or blx imm24 |
| 555 | if ((instr & CondMask) == nv) { |
| 556 | // blx uses bit 24 to encode bit 2 of imm26 |
| 557 | ASSERT((imm26 & 1) == 0); |
| 558 | instr = (instr & ~(B24 | Imm24Mask)) | ((imm26 & 2) >> 1)*B24; |
| 559 | } else { |
| 560 | ASSERT((imm26 & 3) == 0); |
| 561 | instr &= ~Imm24Mask; |
| 562 | } |
| 563 | int imm24 = imm26 >> 2; |
| 564 | ASSERT(is_int24(imm24)); |
| 565 | instr_at_put(pos, instr | (imm24 & Imm24Mask)); |
| 566 | } |
| 567 | |
| 568 | |
| 569 | void Assembler::print(Label* L) { |
| 570 | if (L->is_unused()) { |
| 571 | PrintF("unused label\n"); |
| 572 | } else if (L->is_bound()) { |
| 573 | PrintF("bound label to %d\n", L->pos()); |
| 574 | } else if (L->is_linked()) { |
| 575 | Label l = *L; |
| 576 | PrintF("unbound label"); |
| 577 | while (l.is_linked()) { |
| 578 | PrintF("@ %d ", l.pos()); |
| 579 | Instr instr = instr_at(l.pos()); |
| 580 | if ((instr & ~Imm24Mask) == 0) { |
| 581 | PrintF("value\n"); |
| 582 | } else { |
| 583 | ASSERT((instr & 7*B25) == 5*B25); // b, bl, or blx |
| 584 | int cond = instr & CondMask; |
| 585 | const char* b; |
| 586 | const char* c; |
| 587 | if (cond == nv) { |
| 588 | b = "blx"; |
| 589 | c = ""; |
| 590 | } else { |
| 591 | if ((instr & B24) != 0) |
| 592 | b = "bl"; |
| 593 | else |
| 594 | b = "b"; |
| 595 | |
| 596 | switch (cond) { |
| 597 | case eq: c = "eq"; break; |
| 598 | case ne: c = "ne"; break; |
| 599 | case hs: c = "hs"; break; |
| 600 | case lo: c = "lo"; break; |
| 601 | case mi: c = "mi"; break; |
| 602 | case pl: c = "pl"; break; |
| 603 | case vs: c = "vs"; break; |
| 604 | case vc: c = "vc"; break; |
| 605 | case hi: c = "hi"; break; |
| 606 | case ls: c = "ls"; break; |
| 607 | case ge: c = "ge"; break; |
| 608 | case lt: c = "lt"; break; |
| 609 | case gt: c = "gt"; break; |
| 610 | case le: c = "le"; break; |
| 611 | case al: c = ""; break; |
| 612 | default: |
| 613 | c = ""; |
| 614 | UNREACHABLE(); |
| 615 | } |
| 616 | } |
| 617 | PrintF("%s%s\n", b, c); |
| 618 | } |
| 619 | next(&l); |
| 620 | } |
| 621 | } else { |
| 622 | PrintF("label in inconsistent state (pos = %d)\n", L->pos_); |
| 623 | } |
| 624 | } |
| 625 | |
| 626 | |
| 627 | void Assembler::bind_to(Label* L, int pos) { |
| 628 | ASSERT(0 <= pos && pos <= pc_offset()); // must have a valid binding position |
| 629 | while (L->is_linked()) { |
| 630 | int fixup_pos = L->pos(); |
| 631 | next(L); // call next before overwriting link with target at fixup_pos |
| 632 | target_at_put(fixup_pos, pos); |
| 633 | } |
| 634 | L->bind_to(pos); |
| 635 | |
| 636 | // Keep track of the last bound label so we don't eliminate any instructions |
| 637 | // before a bound label. |
| 638 | if (pos > last_bound_pos_) |
| 639 | last_bound_pos_ = pos; |
| 640 | } |
| 641 | |
| 642 | |
| 643 | void Assembler::link_to(Label* L, Label* appendix) { |
| 644 | if (appendix->is_linked()) { |
| 645 | if (L->is_linked()) { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 646 | // Append appendix to L's list. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 647 | int fixup_pos; |
| 648 | int link = L->pos(); |
| 649 | do { |
| 650 | fixup_pos = link; |
| 651 | link = target_at(fixup_pos); |
| 652 | } while (link > 0); |
| 653 | ASSERT(link == kEndOfChain); |
| 654 | target_at_put(fixup_pos, appendix->pos()); |
| 655 | } else { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 656 | // L is empty, simply use appendix. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 657 | *L = *appendix; |
| 658 | } |
| 659 | } |
| 660 | appendix->Unuse(); // appendix should not be used anymore |
| 661 | } |
| 662 | |
| 663 | |
| 664 | void Assembler::bind(Label* L) { |
| 665 | ASSERT(!L->is_bound()); // label can only be bound once |
| 666 | bind_to(L, pc_offset()); |
| 667 | } |
| 668 | |
| 669 | |
| 670 | void Assembler::next(Label* L) { |
| 671 | ASSERT(L->is_linked()); |
| 672 | int link = target_at(L->pos()); |
| 673 | if (link > 0) { |
| 674 | L->link_to(link); |
| 675 | } else { |
| 676 | ASSERT(link == kEndOfChain); |
| 677 | L->Unuse(); |
| 678 | } |
| 679 | } |
| 680 | |
| 681 | |
Kristian Monsen | 9dcf7e2 | 2010-06-28 14:14:28 +0100 | [diff] [blame] | 682 | static Instr EncodeMovwImmediate(uint32_t immediate) { |
| 683 | ASSERT(immediate < 0x10000); |
| 684 | return ((immediate & 0xf000) << 4) | (immediate & 0xfff); |
| 685 | } |
| 686 | |
| 687 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 688 | // Low-level code emission routines depending on the addressing mode. |
Kristian Monsen | 9dcf7e2 | 2010-06-28 14:14:28 +0100 | [diff] [blame] | 689 | // If this returns true then you have to use the rotate_imm and immed_8 |
| 690 | // that it returns, because it may have already changed the instruction |
| 691 | // to match them! |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 692 | static bool fits_shifter(uint32_t imm32, |
| 693 | uint32_t* rotate_imm, |
| 694 | uint32_t* immed_8, |
| 695 | Instr* instr) { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 696 | // imm32 must be unsigned. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 697 | for (int rot = 0; rot < 16; rot++) { |
| 698 | uint32_t imm8 = (imm32 << 2*rot) | (imm32 >> (32 - 2*rot)); |
| 699 | if ((imm8 <= 0xff)) { |
| 700 | *rotate_imm = rot; |
| 701 | *immed_8 = imm8; |
| 702 | return true; |
| 703 | } |
| 704 | } |
Kristian Monsen | 9dcf7e2 | 2010-06-28 14:14:28 +0100 | [diff] [blame] | 705 | // If the opcode is one with a complementary version and the complementary |
| 706 | // immediate fits, change the opcode. |
| 707 | if (instr != NULL) { |
| 708 | if ((*instr & kMovMvnMask) == kMovMvnPattern) { |
| 709 | if (fits_shifter(~imm32, rotate_imm, immed_8, NULL)) { |
| 710 | *instr ^= kMovMvnFlip; |
| 711 | return true; |
| 712 | } else if ((*instr & kMovLeaveCCMask) == kMovLeaveCCPattern) { |
| 713 | if (CpuFeatures::IsSupported(ARMv7)) { |
| 714 | if (imm32 < 0x10000) { |
| 715 | *instr ^= kMovwLeaveCCFlip; |
| 716 | *instr |= EncodeMovwImmediate(imm32); |
| 717 | *rotate_imm = *immed_8 = 0; // Not used for movw. |
| 718 | return true; |
| 719 | } |
| 720 | } |
| 721 | } |
| 722 | } else if ((*instr & kCmpCmnMask) == kCmpCmnPattern) { |
| 723 | if (fits_shifter(-imm32, rotate_imm, immed_8, NULL)) { |
| 724 | *instr ^= kCmpCmnFlip; |
| 725 | return true; |
| 726 | } |
| 727 | } else { |
| 728 | Instr alu_insn = (*instr & kALUMask); |
| 729 | if (alu_insn == kAddPattern || |
| 730 | alu_insn == kSubPattern) { |
| 731 | if (fits_shifter(-imm32, rotate_imm, immed_8, NULL)) { |
| 732 | *instr ^= kAddSubFlip; |
| 733 | return true; |
| 734 | } |
| 735 | } else if (alu_insn == kAndPattern || |
| 736 | alu_insn == kBicPattern) { |
| 737 | if (fits_shifter(~imm32, rotate_imm, immed_8, NULL)) { |
| 738 | *instr ^= kAndBicFlip; |
| 739 | return true; |
| 740 | } |
| 741 | } |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 742 | } |
| 743 | } |
| 744 | return false; |
| 745 | } |
| 746 | |
| 747 | |
| 748 | // We have to use the temporary register for things that can be relocated even |
| 749 | // if they can be encoded in the ARM's 12 bits of immediate-offset instruction |
| 750 | // space. There is no guarantee that the relocated location can be similarly |
| 751 | // encoded. |
Teng-Hui Zhu | 3e5fa29 | 2010-11-09 16:16:48 -0800 | [diff] [blame] | 752 | bool Operand::must_use_constant_pool() const { |
| 753 | if (rmode_ == RelocInfo::EXTERNAL_REFERENCE) { |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 754 | #ifdef DEBUG |
| 755 | if (!Serializer::enabled()) { |
| 756 | Serializer::TooLateToEnableNow(); |
| 757 | } |
Andrei Popescu | 402d937 | 2010-02-26 13:31:12 +0000 | [diff] [blame] | 758 | #endif // def DEBUG |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 759 | return Serializer::enabled(); |
Teng-Hui Zhu | 3e5fa29 | 2010-11-09 16:16:48 -0800 | [diff] [blame] | 760 | } else if (rmode_ == RelocInfo::NONE) { |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 761 | return false; |
| 762 | } |
| 763 | return true; |
| 764 | } |
| 765 | |
| 766 | |
Kristian Monsen | 9dcf7e2 | 2010-06-28 14:14:28 +0100 | [diff] [blame] | 767 | bool Operand::is_single_instruction() const { |
| 768 | if (rm_.is_valid()) return true; |
Teng-Hui Zhu | 3e5fa29 | 2010-11-09 16:16:48 -0800 | [diff] [blame] | 769 | if (must_use_constant_pool()) return false; |
Kristian Monsen | 9dcf7e2 | 2010-06-28 14:14:28 +0100 | [diff] [blame] | 770 | uint32_t dummy1, dummy2; |
| 771 | return fits_shifter(imm32_, &dummy1, &dummy2, NULL); |
| 772 | } |
| 773 | |
| 774 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 775 | void Assembler::addrmod1(Instr instr, |
| 776 | Register rn, |
| 777 | Register rd, |
| 778 | const Operand& x) { |
| 779 | CheckBuffer(); |
| 780 | ASSERT((instr & ~(CondMask | OpCodeMask | S)) == 0); |
| 781 | if (!x.rm_.is_valid()) { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 782 | // Immediate. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 783 | uint32_t rotate_imm; |
| 784 | uint32_t immed_8; |
Teng-Hui Zhu | 3e5fa29 | 2010-11-09 16:16:48 -0800 | [diff] [blame] | 785 | if (x.must_use_constant_pool() || |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 786 | !fits_shifter(x.imm32_, &rotate_imm, &immed_8, &instr)) { |
| 787 | // The immediate operand cannot be encoded as a shifter operand, so load |
| 788 | // it first to register ip and change the original instruction to use ip. |
| 789 | // However, if the original instruction is a 'mov rd, x' (not setting the |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 790 | // condition code), then replace it with a 'ldr rd, [pc]'. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 791 | CHECK(!rn.is(ip)); // rn should never be ip, or will be trashed |
| 792 | Condition cond = static_cast<Condition>(instr & CondMask); |
| 793 | if ((instr & ~CondMask) == 13*B21) { // mov, S not set |
Teng-Hui Zhu | 3e5fa29 | 2010-11-09 16:16:48 -0800 | [diff] [blame] | 794 | if (x.must_use_constant_pool() || !CpuFeatures::IsSupported(ARMv7)) { |
Kristian Monsen | 9dcf7e2 | 2010-06-28 14:14:28 +0100 | [diff] [blame] | 795 | RecordRelocInfo(x.rmode_, x.imm32_); |
| 796 | ldr(rd, MemOperand(pc, 0), cond); |
| 797 | } else { |
| 798 | // Will probably use movw, will certainly not use constant pool. |
| 799 | mov(rd, Operand(x.imm32_ & 0xffff), LeaveCC, cond); |
| 800 | movt(rd, static_cast<uint32_t>(x.imm32_) >> 16, cond); |
| 801 | } |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 802 | } else { |
Kristian Monsen | 9dcf7e2 | 2010-06-28 14:14:28 +0100 | [diff] [blame] | 803 | // If this is not a mov or mvn instruction we may still be able to avoid |
| 804 | // a constant pool entry by using mvn or movw. |
Teng-Hui Zhu | 3e5fa29 | 2010-11-09 16:16:48 -0800 | [diff] [blame] | 805 | if (!x.must_use_constant_pool() && |
Kristian Monsen | 9dcf7e2 | 2010-06-28 14:14:28 +0100 | [diff] [blame] | 806 | (instr & kMovMvnMask) != kMovMvnPattern) { |
| 807 | mov(ip, x, LeaveCC, cond); |
| 808 | } else { |
| 809 | RecordRelocInfo(x.rmode_, x.imm32_); |
| 810 | ldr(ip, MemOperand(pc, 0), cond); |
| 811 | } |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 812 | addrmod1(instr, rn, rd, Operand(ip)); |
| 813 | } |
| 814 | return; |
| 815 | } |
| 816 | instr |= I | rotate_imm*B8 | immed_8; |
| 817 | } else if (!x.rs_.is_valid()) { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 818 | // Immediate shift. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 819 | instr |= x.shift_imm_*B7 | x.shift_op_ | x.rm_.code(); |
| 820 | } else { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 821 | // Register shift. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 822 | ASSERT(!rn.is(pc) && !rd.is(pc) && !x.rm_.is(pc) && !x.rs_.is(pc)); |
| 823 | instr |= x.rs_.code()*B8 | x.shift_op_ | B4 | x.rm_.code(); |
| 824 | } |
| 825 | emit(instr | rn.code()*B16 | rd.code()*B12); |
Kristian Monsen | 50ef84f | 2010-07-29 15:18:00 +0100 | [diff] [blame] | 826 | if (rn.is(pc) || x.rm_.is(pc)) { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 827 | // Block constant pool emission for one instruction after reading pc. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 828 | BlockConstPoolBefore(pc_offset() + kInstrSize); |
Kristian Monsen | 50ef84f | 2010-07-29 15:18:00 +0100 | [diff] [blame] | 829 | } |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 830 | } |
| 831 | |
| 832 | |
| 833 | void Assembler::addrmod2(Instr instr, Register rd, const MemOperand& x) { |
| 834 | ASSERT((instr & ~(CondMask | B | L)) == B26); |
| 835 | int am = x.am_; |
| 836 | if (!x.rm_.is_valid()) { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 837 | // Immediate offset. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 838 | int offset_12 = x.offset_; |
| 839 | if (offset_12 < 0) { |
| 840 | offset_12 = -offset_12; |
| 841 | am ^= U; |
| 842 | } |
| 843 | if (!is_uint12(offset_12)) { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 844 | // Immediate offset cannot be encoded, load it first to register ip |
| 845 | // rn (and rd in a load) should never be ip, or will be trashed. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 846 | ASSERT(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip))); |
| 847 | mov(ip, Operand(x.offset_), LeaveCC, |
| 848 | static_cast<Condition>(instr & CondMask)); |
| 849 | addrmod2(instr, rd, MemOperand(x.rn_, ip, x.am_)); |
| 850 | return; |
| 851 | } |
| 852 | ASSERT(offset_12 >= 0); // no masking needed |
| 853 | instr |= offset_12; |
| 854 | } else { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 855 | // Register offset (shift_imm_ and shift_op_ are 0) or scaled |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 856 | // register offset the constructors make sure than both shift_imm_ |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 857 | // and shift_op_ are initialized. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 858 | ASSERT(!x.rm_.is(pc)); |
| 859 | instr |= B25 | x.shift_imm_*B7 | x.shift_op_ | x.rm_.code(); |
| 860 | } |
| 861 | ASSERT((am & (P|W)) == P || !x.rn_.is(pc)); // no pc base with writeback |
| 862 | emit(instr | am | x.rn_.code()*B16 | rd.code()*B12); |
| 863 | } |
| 864 | |
| 865 | |
| 866 | void Assembler::addrmod3(Instr instr, Register rd, const MemOperand& x) { |
| 867 | ASSERT((instr & ~(CondMask | L | S6 | H)) == (B4 | B7)); |
| 868 | ASSERT(x.rn_.is_valid()); |
| 869 | int am = x.am_; |
| 870 | if (!x.rm_.is_valid()) { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 871 | // Immediate offset. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 872 | int offset_8 = x.offset_; |
| 873 | if (offset_8 < 0) { |
| 874 | offset_8 = -offset_8; |
| 875 | am ^= U; |
| 876 | } |
| 877 | if (!is_uint8(offset_8)) { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 878 | // Immediate offset cannot be encoded, load it first to register ip |
| 879 | // rn (and rd in a load) should never be ip, or will be trashed. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 880 | ASSERT(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip))); |
| 881 | mov(ip, Operand(x.offset_), LeaveCC, |
| 882 | static_cast<Condition>(instr & CondMask)); |
| 883 | addrmod3(instr, rd, MemOperand(x.rn_, ip, x.am_)); |
| 884 | return; |
| 885 | } |
| 886 | ASSERT(offset_8 >= 0); // no masking needed |
| 887 | instr |= B | (offset_8 >> 4)*B8 | (offset_8 & 0xf); |
| 888 | } else if (x.shift_imm_ != 0) { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 889 | // Scaled register offset not supported, load index first |
| 890 | // rn (and rd in a load) should never be ip, or will be trashed. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 891 | ASSERT(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip))); |
| 892 | mov(ip, Operand(x.rm_, x.shift_op_, x.shift_imm_), LeaveCC, |
| 893 | static_cast<Condition>(instr & CondMask)); |
| 894 | addrmod3(instr, rd, MemOperand(x.rn_, ip, x.am_)); |
| 895 | return; |
| 896 | } else { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 897 | // Register offset. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 898 | ASSERT((am & (P|W)) == P || !x.rm_.is(pc)); // no pc index with writeback |
| 899 | instr |= x.rm_.code(); |
| 900 | } |
| 901 | ASSERT((am & (P|W)) == P || !x.rn_.is(pc)); // no pc base with writeback |
| 902 | emit(instr | am | x.rn_.code()*B16 | rd.code()*B12); |
| 903 | } |
| 904 | |
| 905 | |
| 906 | void Assembler::addrmod4(Instr instr, Register rn, RegList rl) { |
| 907 | ASSERT((instr & ~(CondMask | P | U | W | L)) == B27); |
| 908 | ASSERT(rl != 0); |
| 909 | ASSERT(!rn.is(pc)); |
| 910 | emit(instr | rn.code()*B16 | rl); |
| 911 | } |
| 912 | |
| 913 | |
| 914 | void Assembler::addrmod5(Instr instr, CRegister crd, const MemOperand& x) { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 915 | // Unindexed addressing is not encoded by this function. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 916 | ASSERT_EQ((B27 | B26), |
| 917 | (instr & ~(CondMask | CoprocessorMask | P | U | N | W | L))); |
| 918 | ASSERT(x.rn_.is_valid() && !x.rm_.is_valid()); |
| 919 | int am = x.am_; |
| 920 | int offset_8 = x.offset_; |
| 921 | ASSERT((offset_8 & 3) == 0); // offset must be an aligned word offset |
| 922 | offset_8 >>= 2; |
| 923 | if (offset_8 < 0) { |
| 924 | offset_8 = -offset_8; |
| 925 | am ^= U; |
| 926 | } |
| 927 | ASSERT(is_uint8(offset_8)); // unsigned word offset must fit in a byte |
| 928 | ASSERT((am & (P|W)) == P || !x.rn_.is(pc)); // no pc base with writeback |
| 929 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 930 | // Post-indexed addressing requires W == 1; different than in addrmod2/3. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 931 | if ((am & P) == 0) |
| 932 | am |= W; |
| 933 | |
| 934 | ASSERT(offset_8 >= 0); // no masking needed |
| 935 | emit(instr | am | x.rn_.code()*B16 | crd.code()*B12 | offset_8); |
| 936 | } |
| 937 | |
| 938 | |
| 939 | int Assembler::branch_offset(Label* L, bool jump_elimination_allowed) { |
| 940 | int target_pos; |
| 941 | if (L->is_bound()) { |
| 942 | target_pos = L->pos(); |
| 943 | } else { |
| 944 | if (L->is_linked()) { |
| 945 | target_pos = L->pos(); // L's link |
| 946 | } else { |
| 947 | target_pos = kEndOfChain; |
| 948 | } |
| 949 | L->link_to(pc_offset()); |
| 950 | } |
| 951 | |
| 952 | // Block the emission of the constant pool, since the branch instruction must |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 953 | // be emitted at the pc offset recorded by the label. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 954 | BlockConstPoolBefore(pc_offset() + kInstrSize); |
| 955 | return target_pos - (pc_offset() + kPcLoadDelta); |
| 956 | } |
| 957 | |
| 958 | |
| 959 | void Assembler::label_at_put(Label* L, int at_offset) { |
| 960 | int target_pos; |
| 961 | if (L->is_bound()) { |
| 962 | target_pos = L->pos(); |
| 963 | } else { |
| 964 | if (L->is_linked()) { |
| 965 | target_pos = L->pos(); // L's link |
| 966 | } else { |
| 967 | target_pos = kEndOfChain; |
| 968 | } |
| 969 | L->link_to(at_offset); |
| 970 | instr_at_put(at_offset, target_pos + (Code::kHeaderSize - kHeapObjectTag)); |
| 971 | } |
| 972 | } |
| 973 | |
| 974 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 975 | // Branch instructions. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 976 | void Assembler::b(int branch_offset, Condition cond) { |
| 977 | ASSERT((branch_offset & 3) == 0); |
| 978 | int imm24 = branch_offset >> 2; |
| 979 | ASSERT(is_int24(imm24)); |
| 980 | emit(cond | B27 | B25 | (imm24 & Imm24Mask)); |
| 981 | |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 982 | if (cond == al) { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 983 | // Dead code is a good location to emit the constant pool. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 984 | CheckConstPool(false, false); |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 985 | } |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 986 | } |
| 987 | |
| 988 | |
| 989 | void Assembler::bl(int branch_offset, Condition cond) { |
| 990 | ASSERT((branch_offset & 3) == 0); |
| 991 | int imm24 = branch_offset >> 2; |
| 992 | ASSERT(is_int24(imm24)); |
| 993 | emit(cond | B27 | B25 | B24 | (imm24 & Imm24Mask)); |
| 994 | } |
| 995 | |
| 996 | |
| 997 | void Assembler::blx(int branch_offset) { // v5 and above |
Teng-Hui Zhu | 3e5fa29 | 2010-11-09 16:16:48 -0800 | [diff] [blame] | 998 | positions_recorder()->WriteRecordedPositions(); |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 999 | ASSERT((branch_offset & 1) == 0); |
| 1000 | int h = ((branch_offset & 2) >> 1)*B24; |
| 1001 | int imm24 = branch_offset >> 2; |
| 1002 | ASSERT(is_int24(imm24)); |
Teng-Hui Zhu | 3e5fa29 | 2010-11-09 16:16:48 -0800 | [diff] [blame] | 1003 | emit(nv | B27 | B25 | h | (imm24 & Imm24Mask)); |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1004 | } |
| 1005 | |
| 1006 | |
| 1007 | void Assembler::blx(Register target, Condition cond) { // v5 and above |
Teng-Hui Zhu | 3e5fa29 | 2010-11-09 16:16:48 -0800 | [diff] [blame] | 1008 | positions_recorder()->WriteRecordedPositions(); |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1009 | ASSERT(!target.is(pc)); |
| 1010 | emit(cond | B24 | B21 | 15*B16 | 15*B12 | 15*B8 | 3*B4 | target.code()); |
| 1011 | } |
| 1012 | |
| 1013 | |
| 1014 | void Assembler::bx(Register target, Condition cond) { // v5 and above, plus v4t |
Teng-Hui Zhu | 3e5fa29 | 2010-11-09 16:16:48 -0800 | [diff] [blame] | 1015 | positions_recorder()->WriteRecordedPositions(); |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1016 | ASSERT(!target.is(pc)); // use of pc is actually allowed, but discouraged |
| 1017 | emit(cond | B24 | B21 | 15*B16 | 15*B12 | 15*B8 | B4 | target.code()); |
| 1018 | } |
| 1019 | |
| 1020 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1021 | // Data-processing instructions. |
| 1022 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1023 | void Assembler::and_(Register dst, Register src1, const Operand& src2, |
| 1024 | SBit s, Condition cond) { |
| 1025 | addrmod1(cond | 0*B21 | s, src1, dst, src2); |
| 1026 | } |
| 1027 | |
| 1028 | |
| 1029 | void Assembler::eor(Register dst, Register src1, const Operand& src2, |
| 1030 | SBit s, Condition cond) { |
| 1031 | addrmod1(cond | 1*B21 | s, src1, dst, src2); |
| 1032 | } |
| 1033 | |
| 1034 | |
| 1035 | void Assembler::sub(Register dst, Register src1, const Operand& src2, |
| 1036 | SBit s, Condition cond) { |
| 1037 | addrmod1(cond | 2*B21 | s, src1, dst, src2); |
| 1038 | } |
| 1039 | |
| 1040 | |
| 1041 | void Assembler::rsb(Register dst, Register src1, const Operand& src2, |
| 1042 | SBit s, Condition cond) { |
| 1043 | addrmod1(cond | 3*B21 | s, src1, dst, src2); |
| 1044 | } |
| 1045 | |
| 1046 | |
| 1047 | void Assembler::add(Register dst, Register src1, const Operand& src2, |
| 1048 | SBit s, Condition cond) { |
| 1049 | addrmod1(cond | 4*B21 | s, src1, dst, src2); |
| 1050 | |
| 1051 | // Eliminate pattern: push(r), pop() |
| 1052 | // str(src, MemOperand(sp, 4, NegPreIndex), al); |
| 1053 | // add(sp, sp, Operand(kPointerSize)); |
| 1054 | // Both instructions can be eliminated. |
Leon Clarke | f7060e2 | 2010-06-03 12:02:55 +0100 | [diff] [blame] | 1055 | if (can_peephole_optimize(2) && |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1056 | // Pattern. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1057 | instr_at(pc_ - 1 * kInstrSize) == kPopInstruction && |
| 1058 | (instr_at(pc_ - 2 * kInstrSize) & ~RdMask) == kPushRegPattern) { |
| 1059 | pc_ -= 2 * kInstrSize; |
Leon Clarke | f7060e2 | 2010-06-03 12:02:55 +0100 | [diff] [blame] | 1060 | if (FLAG_print_peephole_optimization) { |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1061 | PrintF("%x push(reg)/pop() eliminated\n", pc_offset()); |
| 1062 | } |
| 1063 | } |
| 1064 | } |
| 1065 | |
| 1066 | |
| 1067 | void Assembler::adc(Register dst, Register src1, const Operand& src2, |
| 1068 | SBit s, Condition cond) { |
| 1069 | addrmod1(cond | 5*B21 | s, src1, dst, src2); |
| 1070 | } |
| 1071 | |
| 1072 | |
| 1073 | void Assembler::sbc(Register dst, Register src1, const Operand& src2, |
| 1074 | SBit s, Condition cond) { |
| 1075 | addrmod1(cond | 6*B21 | s, src1, dst, src2); |
| 1076 | } |
| 1077 | |
| 1078 | |
| 1079 | void Assembler::rsc(Register dst, Register src1, const Operand& src2, |
| 1080 | SBit s, Condition cond) { |
| 1081 | addrmod1(cond | 7*B21 | s, src1, dst, src2); |
| 1082 | } |
| 1083 | |
| 1084 | |
| 1085 | void Assembler::tst(Register src1, const Operand& src2, Condition cond) { |
| 1086 | addrmod1(cond | 8*B21 | S, src1, r0, src2); |
| 1087 | } |
| 1088 | |
| 1089 | |
| 1090 | void Assembler::teq(Register src1, const Operand& src2, Condition cond) { |
| 1091 | addrmod1(cond | 9*B21 | S, src1, r0, src2); |
| 1092 | } |
| 1093 | |
| 1094 | |
| 1095 | void Assembler::cmp(Register src1, const Operand& src2, Condition cond) { |
| 1096 | addrmod1(cond | 10*B21 | S, src1, r0, src2); |
| 1097 | } |
| 1098 | |
| 1099 | |
| 1100 | void Assembler::cmn(Register src1, const Operand& src2, Condition cond) { |
| 1101 | addrmod1(cond | 11*B21 | S, src1, r0, src2); |
| 1102 | } |
| 1103 | |
| 1104 | |
| 1105 | void Assembler::orr(Register dst, Register src1, const Operand& src2, |
| 1106 | SBit s, Condition cond) { |
| 1107 | addrmod1(cond | 12*B21 | s, src1, dst, src2); |
| 1108 | } |
| 1109 | |
| 1110 | |
| 1111 | void Assembler::mov(Register dst, const Operand& src, SBit s, Condition cond) { |
| 1112 | if (dst.is(pc)) { |
Teng-Hui Zhu | 3e5fa29 | 2010-11-09 16:16:48 -0800 | [diff] [blame] | 1113 | positions_recorder()->WriteRecordedPositions(); |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1114 | } |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 1115 | // Don't allow nop instructions in the form mov rn, rn to be generated using |
| 1116 | // the mov instruction. They must be generated using nop(int) |
| 1117 | // pseudo instructions. |
| 1118 | ASSERT(!(src.is_reg() && src.rm().is(dst) && s == LeaveCC && cond == al)); |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1119 | addrmod1(cond | 13*B21 | s, r0, dst, src); |
| 1120 | } |
| 1121 | |
| 1122 | |
Kristian Monsen | 9dcf7e2 | 2010-06-28 14:14:28 +0100 | [diff] [blame] | 1123 | void Assembler::movw(Register reg, uint32_t immediate, Condition cond) { |
| 1124 | ASSERT(immediate < 0x10000); |
| 1125 | mov(reg, Operand(immediate), LeaveCC, cond); |
| 1126 | } |
| 1127 | |
| 1128 | |
| 1129 | void Assembler::movt(Register reg, uint32_t immediate, Condition cond) { |
| 1130 | emit(cond | 0x34*B20 | reg.code()*B12 | EncodeMovwImmediate(immediate)); |
| 1131 | } |
| 1132 | |
| 1133 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1134 | void Assembler::bic(Register dst, Register src1, const Operand& src2, |
| 1135 | SBit s, Condition cond) { |
| 1136 | addrmod1(cond | 14*B21 | s, src1, dst, src2); |
| 1137 | } |
| 1138 | |
| 1139 | |
| 1140 | void Assembler::mvn(Register dst, const Operand& src, SBit s, Condition cond) { |
| 1141 | addrmod1(cond | 15*B21 | s, r0, dst, src); |
| 1142 | } |
| 1143 | |
| 1144 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1145 | // Multiply instructions. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1146 | void Assembler::mla(Register dst, Register src1, Register src2, Register srcA, |
| 1147 | SBit s, Condition cond) { |
| 1148 | ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc)); |
| 1149 | emit(cond | A | s | dst.code()*B16 | srcA.code()*B12 | |
| 1150 | src2.code()*B8 | B7 | B4 | src1.code()); |
| 1151 | } |
| 1152 | |
| 1153 | |
| 1154 | void Assembler::mul(Register dst, Register src1, Register src2, |
| 1155 | SBit s, Condition cond) { |
| 1156 | ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc)); |
| 1157 | // dst goes in bits 16-19 for this instruction! |
| 1158 | emit(cond | s | dst.code()*B16 | src2.code()*B8 | B7 | B4 | src1.code()); |
| 1159 | } |
| 1160 | |
| 1161 | |
| 1162 | void Assembler::smlal(Register dstL, |
| 1163 | Register dstH, |
| 1164 | Register src1, |
| 1165 | Register src2, |
| 1166 | SBit s, |
| 1167 | Condition cond) { |
| 1168 | ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc)); |
| 1169 | ASSERT(!dstL.is(dstH)); |
| 1170 | emit(cond | B23 | B22 | A | s | dstH.code()*B16 | dstL.code()*B12 | |
| 1171 | src2.code()*B8 | B7 | B4 | src1.code()); |
| 1172 | } |
| 1173 | |
| 1174 | |
| 1175 | void Assembler::smull(Register dstL, |
| 1176 | Register dstH, |
| 1177 | Register src1, |
| 1178 | Register src2, |
| 1179 | SBit s, |
| 1180 | Condition cond) { |
| 1181 | ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc)); |
| 1182 | ASSERT(!dstL.is(dstH)); |
| 1183 | emit(cond | B23 | B22 | s | dstH.code()*B16 | dstL.code()*B12 | |
| 1184 | src2.code()*B8 | B7 | B4 | src1.code()); |
| 1185 | } |
| 1186 | |
| 1187 | |
| 1188 | void Assembler::umlal(Register dstL, |
| 1189 | Register dstH, |
| 1190 | Register src1, |
| 1191 | Register src2, |
| 1192 | SBit s, |
| 1193 | Condition cond) { |
| 1194 | ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc)); |
| 1195 | ASSERT(!dstL.is(dstH)); |
| 1196 | emit(cond | B23 | A | s | dstH.code()*B16 | dstL.code()*B12 | |
| 1197 | src2.code()*B8 | B7 | B4 | src1.code()); |
| 1198 | } |
| 1199 | |
| 1200 | |
| 1201 | void Assembler::umull(Register dstL, |
| 1202 | Register dstH, |
| 1203 | Register src1, |
| 1204 | Register src2, |
| 1205 | SBit s, |
| 1206 | Condition cond) { |
| 1207 | ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc)); |
| 1208 | ASSERT(!dstL.is(dstH)); |
| 1209 | emit(cond | B23 | s | dstH.code()*B16 | dstL.code()*B12 | |
| 1210 | src2.code()*B8 | B7 | B4 | src1.code()); |
| 1211 | } |
| 1212 | |
| 1213 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1214 | // Miscellaneous arithmetic instructions. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1215 | void Assembler::clz(Register dst, Register src, Condition cond) { |
| 1216 | // v5 and above. |
| 1217 | ASSERT(!dst.is(pc) && !src.is(pc)); |
| 1218 | emit(cond | B24 | B22 | B21 | 15*B16 | dst.code()*B12 | |
| 1219 | 15*B8 | B4 | src.code()); |
| 1220 | } |
| 1221 | |
| 1222 | |
Kristian Monsen | 50ef84f | 2010-07-29 15:18:00 +0100 | [diff] [blame] | 1223 | // Saturating instructions. |
| 1224 | |
| 1225 | // Unsigned saturate. |
| 1226 | void Assembler::usat(Register dst, |
| 1227 | int satpos, |
| 1228 | const Operand& src, |
| 1229 | Condition cond) { |
| 1230 | // v6 and above. |
| 1231 | ASSERT(CpuFeatures::IsSupported(ARMv7)); |
| 1232 | ASSERT(!dst.is(pc) && !src.rm_.is(pc)); |
| 1233 | ASSERT((satpos >= 0) && (satpos <= 31)); |
| 1234 | ASSERT((src.shift_op_ == ASR) || (src.shift_op_ == LSL)); |
| 1235 | ASSERT(src.rs_.is(no_reg)); |
| 1236 | |
| 1237 | int sh = 0; |
| 1238 | if (src.shift_op_ == ASR) { |
| 1239 | sh = 1; |
| 1240 | } |
| 1241 | |
| 1242 | emit(cond | 0x6*B24 | 0xe*B20 | satpos*B16 | dst.code()*B12 | |
| 1243 | src.shift_imm_*B7 | sh*B6 | 0x1*B4 | src.rm_.code()); |
| 1244 | } |
| 1245 | |
| 1246 | |
Ben Murdoch | 7f4d5bd | 2010-06-15 11:15:29 +0100 | [diff] [blame] | 1247 | // Bitfield manipulation instructions. |
| 1248 | |
| 1249 | // Unsigned bit field extract. |
| 1250 | // Extracts #width adjacent bits from position #lsb in a register, and |
| 1251 | // writes them to the low bits of a destination register. |
| 1252 | // ubfx dst, src, #lsb, #width |
| 1253 | void Assembler::ubfx(Register dst, |
| 1254 | Register src, |
| 1255 | int lsb, |
| 1256 | int width, |
| 1257 | Condition cond) { |
| 1258 | // v7 and above. |
| 1259 | ASSERT(CpuFeatures::IsSupported(ARMv7)); |
| 1260 | ASSERT(!dst.is(pc) && !src.is(pc)); |
| 1261 | ASSERT((lsb >= 0) && (lsb <= 31)); |
| 1262 | ASSERT((width >= 1) && (width <= (32 - lsb))); |
| 1263 | emit(cond | 0xf*B23 | B22 | B21 | (width - 1)*B16 | dst.code()*B12 | |
| 1264 | lsb*B7 | B6 | B4 | src.code()); |
| 1265 | } |
| 1266 | |
| 1267 | |
| 1268 | // Signed bit field extract. |
| 1269 | // Extracts #width adjacent bits from position #lsb in a register, and |
| 1270 | // writes them to the low bits of a destination register. The extracted |
| 1271 | // value is sign extended to fill the destination register. |
| 1272 | // sbfx dst, src, #lsb, #width |
| 1273 | void Assembler::sbfx(Register dst, |
| 1274 | Register src, |
| 1275 | int lsb, |
| 1276 | int width, |
| 1277 | Condition cond) { |
| 1278 | // v7 and above. |
| 1279 | ASSERT(CpuFeatures::IsSupported(ARMv7)); |
| 1280 | ASSERT(!dst.is(pc) && !src.is(pc)); |
| 1281 | ASSERT((lsb >= 0) && (lsb <= 31)); |
| 1282 | ASSERT((width >= 1) && (width <= (32 - lsb))); |
| 1283 | emit(cond | 0xf*B23 | B21 | (width - 1)*B16 | dst.code()*B12 | |
| 1284 | lsb*B7 | B6 | B4 | src.code()); |
| 1285 | } |
| 1286 | |
| 1287 | |
| 1288 | // Bit field clear. |
| 1289 | // Sets #width adjacent bits at position #lsb in the destination register |
| 1290 | // to zero, preserving the value of the other bits. |
| 1291 | // bfc dst, #lsb, #width |
| 1292 | void Assembler::bfc(Register dst, int lsb, int width, Condition cond) { |
| 1293 | // v7 and above. |
| 1294 | ASSERT(CpuFeatures::IsSupported(ARMv7)); |
| 1295 | ASSERT(!dst.is(pc)); |
| 1296 | ASSERT((lsb >= 0) && (lsb <= 31)); |
| 1297 | ASSERT((width >= 1) && (width <= (32 - lsb))); |
| 1298 | int msb = lsb + width - 1; |
| 1299 | emit(cond | 0x1f*B22 | msb*B16 | dst.code()*B12 | lsb*B7 | B4 | 0xf); |
| 1300 | } |
| 1301 | |
| 1302 | |
| 1303 | // Bit field insert. |
| 1304 | // Inserts #width adjacent bits from the low bits of the source register |
| 1305 | // into position #lsb of the destination register. |
| 1306 | // bfi dst, src, #lsb, #width |
| 1307 | void Assembler::bfi(Register dst, |
| 1308 | Register src, |
| 1309 | int lsb, |
| 1310 | int width, |
| 1311 | Condition cond) { |
| 1312 | // v7 and above. |
| 1313 | ASSERT(CpuFeatures::IsSupported(ARMv7)); |
| 1314 | ASSERT(!dst.is(pc) && !src.is(pc)); |
| 1315 | ASSERT((lsb >= 0) && (lsb <= 31)); |
| 1316 | ASSERT((width >= 1) && (width <= (32 - lsb))); |
| 1317 | int msb = lsb + width - 1; |
| 1318 | emit(cond | 0x1f*B22 | msb*B16 | dst.code()*B12 | lsb*B7 | B4 | |
| 1319 | src.code()); |
| 1320 | } |
| 1321 | |
| 1322 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1323 | // Status register access instructions. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1324 | void Assembler::mrs(Register dst, SRegister s, Condition cond) { |
| 1325 | ASSERT(!dst.is(pc)); |
| 1326 | emit(cond | B24 | s | 15*B16 | dst.code()*B12); |
| 1327 | } |
| 1328 | |
| 1329 | |
| 1330 | void Assembler::msr(SRegisterFieldMask fields, const Operand& src, |
| 1331 | Condition cond) { |
| 1332 | ASSERT(fields >= B16 && fields < B20); // at least one field set |
| 1333 | Instr instr; |
| 1334 | if (!src.rm_.is_valid()) { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1335 | // Immediate. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1336 | uint32_t rotate_imm; |
| 1337 | uint32_t immed_8; |
Teng-Hui Zhu | 3e5fa29 | 2010-11-09 16:16:48 -0800 | [diff] [blame] | 1338 | if (src.must_use_constant_pool() || |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1339 | !fits_shifter(src.imm32_, &rotate_imm, &immed_8, NULL)) { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1340 | // Immediate operand cannot be encoded, load it first to register ip. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1341 | RecordRelocInfo(src.rmode_, src.imm32_); |
| 1342 | ldr(ip, MemOperand(pc, 0), cond); |
| 1343 | msr(fields, Operand(ip), cond); |
| 1344 | return; |
| 1345 | } |
| 1346 | instr = I | rotate_imm*B8 | immed_8; |
| 1347 | } else { |
| 1348 | ASSERT(!src.rs_.is_valid() && src.shift_imm_ == 0); // only rm allowed |
| 1349 | instr = src.rm_.code(); |
| 1350 | } |
| 1351 | emit(cond | instr | B24 | B21 | fields | 15*B12); |
| 1352 | } |
| 1353 | |
| 1354 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1355 | // Load/Store instructions. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1356 | void Assembler::ldr(Register dst, const MemOperand& src, Condition cond) { |
| 1357 | if (dst.is(pc)) { |
Teng-Hui Zhu | 3e5fa29 | 2010-11-09 16:16:48 -0800 | [diff] [blame] | 1358 | positions_recorder()->WriteRecordedPositions(); |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1359 | } |
| 1360 | addrmod2(cond | B26 | L, dst, src); |
| 1361 | |
Leon Clarke | f7060e2 | 2010-06-03 12:02:55 +0100 | [diff] [blame] | 1362 | // Eliminate pattern: push(ry), pop(rx) |
| 1363 | // str(ry, MemOperand(sp, 4, NegPreIndex), al) |
| 1364 | // ldr(rx, MemOperand(sp, 4, PostIndex), al) |
| 1365 | // Both instructions can be eliminated if ry = rx. |
| 1366 | // If ry != rx, a register copy from ry to rx is inserted |
| 1367 | // after eliminating the push and the pop instructions. |
Ben Murdoch | 7f4d5bd | 2010-06-15 11:15:29 +0100 | [diff] [blame] | 1368 | if (can_peephole_optimize(2)) { |
| 1369 | Instr push_instr = instr_at(pc_ - 2 * kInstrSize); |
| 1370 | Instr pop_instr = instr_at(pc_ - 1 * kInstrSize); |
Leon Clarke | f7060e2 | 2010-06-03 12:02:55 +0100 | [diff] [blame] | 1371 | |
Ben Murdoch | 7f4d5bd | 2010-06-15 11:15:29 +0100 | [diff] [blame] | 1372 | if (IsPush(push_instr) && IsPop(pop_instr)) { |
| 1373 | if ((pop_instr & kRdMask) != (push_instr & kRdMask)) { |
| 1374 | // For consecutive push and pop on different registers, |
| 1375 | // we delete both the push & pop and insert a register move. |
| 1376 | // push ry, pop rx --> mov rx, ry |
| 1377 | Register reg_pushed, reg_popped; |
| 1378 | reg_pushed = GetRd(push_instr); |
| 1379 | reg_popped = GetRd(pop_instr); |
| 1380 | pc_ -= 2 * kInstrSize; |
| 1381 | // Insert a mov instruction, which is better than a pair of push & pop |
| 1382 | mov(reg_popped, reg_pushed); |
| 1383 | if (FLAG_print_peephole_optimization) { |
| 1384 | PrintF("%x push/pop (diff reg) replaced by a reg move\n", |
| 1385 | pc_offset()); |
| 1386 | } |
| 1387 | } else { |
| 1388 | // For consecutive push and pop on the same register, |
| 1389 | // both the push and the pop can be deleted. |
| 1390 | pc_ -= 2 * kInstrSize; |
| 1391 | if (FLAG_print_peephole_optimization) { |
| 1392 | PrintF("%x push/pop (same reg) eliminated\n", pc_offset()); |
| 1393 | } |
Leon Clarke | f7060e2 | 2010-06-03 12:02:55 +0100 | [diff] [blame] | 1394 | } |
| 1395 | } |
| 1396 | } |
| 1397 | |
| 1398 | if (can_peephole_optimize(2)) { |
| 1399 | Instr str_instr = instr_at(pc_ - 2 * kInstrSize); |
| 1400 | Instr ldr_instr = instr_at(pc_ - 1 * kInstrSize); |
| 1401 | |
| 1402 | if ((IsStrRegFpOffset(str_instr) && |
| 1403 | IsLdrRegFpOffset(ldr_instr)) || |
| 1404 | (IsStrRegFpNegOffset(str_instr) && |
| 1405 | IsLdrRegFpNegOffset(ldr_instr))) { |
| 1406 | if ((ldr_instr & kLdrStrInstrArgumentMask) == |
| 1407 | (str_instr & kLdrStrInstrArgumentMask)) { |
| 1408 | // Pattern: Ldr/str same fp+offset, same register. |
| 1409 | // |
| 1410 | // The following: |
| 1411 | // str rx, [fp, #-12] |
| 1412 | // ldr rx, [fp, #-12] |
| 1413 | // |
| 1414 | // Becomes: |
| 1415 | // str rx, [fp, #-12] |
| 1416 | |
| 1417 | pc_ -= 1 * kInstrSize; |
| 1418 | if (FLAG_print_peephole_optimization) { |
| 1419 | PrintF("%x str/ldr (fp + same offset), same reg\n", pc_offset()); |
| 1420 | } |
| 1421 | } else if ((ldr_instr & kLdrStrOffsetMask) == |
| 1422 | (str_instr & kLdrStrOffsetMask)) { |
| 1423 | // Pattern: Ldr/str same fp+offset, different register. |
| 1424 | // |
| 1425 | // The following: |
| 1426 | // str rx, [fp, #-12] |
| 1427 | // ldr ry, [fp, #-12] |
| 1428 | // |
| 1429 | // Becomes: |
| 1430 | // str rx, [fp, #-12] |
| 1431 | // mov ry, rx |
| 1432 | |
| 1433 | Register reg_stored, reg_loaded; |
| 1434 | reg_stored = GetRd(str_instr); |
| 1435 | reg_loaded = GetRd(ldr_instr); |
| 1436 | pc_ -= 1 * kInstrSize; |
| 1437 | // Insert a mov instruction, which is better than ldr. |
| 1438 | mov(reg_loaded, reg_stored); |
| 1439 | if (FLAG_print_peephole_optimization) { |
| 1440 | PrintF("%x str/ldr (fp + same offset), diff reg \n", pc_offset()); |
| 1441 | } |
| 1442 | } |
| 1443 | } |
| 1444 | } |
| 1445 | |
| 1446 | if (can_peephole_optimize(3)) { |
| 1447 | Instr mem_write_instr = instr_at(pc_ - 3 * kInstrSize); |
| 1448 | Instr ldr_instr = instr_at(pc_ - 2 * kInstrSize); |
| 1449 | Instr mem_read_instr = instr_at(pc_ - 1 * kInstrSize); |
| 1450 | if (IsPush(mem_write_instr) && |
| 1451 | IsPop(mem_read_instr)) { |
| 1452 | if ((IsLdrRegFpOffset(ldr_instr) || |
| 1453 | IsLdrRegFpNegOffset(ldr_instr))) { |
| 1454 | if ((mem_write_instr & kRdMask) == |
| 1455 | (mem_read_instr & kRdMask)) { |
| 1456 | // Pattern: push & pop from/to same register, |
| 1457 | // with a fp+offset ldr in between |
| 1458 | // |
| 1459 | // The following: |
| 1460 | // str rx, [sp, #-4]! |
| 1461 | // ldr rz, [fp, #-24] |
| 1462 | // ldr rx, [sp], #+4 |
| 1463 | // |
| 1464 | // Becomes: |
| 1465 | // if(rx == rz) |
| 1466 | // delete all |
| 1467 | // else |
| 1468 | // ldr rz, [fp, #-24] |
| 1469 | |
| 1470 | if ((mem_write_instr & kRdMask) == (ldr_instr & kRdMask)) { |
| 1471 | pc_ -= 3 * kInstrSize; |
| 1472 | } else { |
| 1473 | pc_ -= 3 * kInstrSize; |
| 1474 | // Reinsert back the ldr rz. |
| 1475 | emit(ldr_instr); |
| 1476 | } |
| 1477 | if (FLAG_print_peephole_optimization) { |
| 1478 | PrintF("%x push/pop -dead ldr fp+offset in middle\n", pc_offset()); |
| 1479 | } |
| 1480 | } else { |
| 1481 | // Pattern: push & pop from/to different registers |
| 1482 | // with a fp+offset ldr in between |
| 1483 | // |
| 1484 | // The following: |
| 1485 | // str rx, [sp, #-4]! |
| 1486 | // ldr rz, [fp, #-24] |
| 1487 | // ldr ry, [sp], #+4 |
| 1488 | // |
| 1489 | // Becomes: |
| 1490 | // if(ry == rz) |
| 1491 | // mov ry, rx; |
| 1492 | // else if(rx != rz) |
| 1493 | // ldr rz, [fp, #-24] |
| 1494 | // mov ry, rx |
| 1495 | // else if((ry != rz) || (rx == rz)) becomes: |
| 1496 | // mov ry, rx |
| 1497 | // ldr rz, [fp, #-24] |
| 1498 | |
| 1499 | Register reg_pushed, reg_popped; |
| 1500 | if ((mem_read_instr & kRdMask) == (ldr_instr & kRdMask)) { |
| 1501 | reg_pushed = GetRd(mem_write_instr); |
| 1502 | reg_popped = GetRd(mem_read_instr); |
| 1503 | pc_ -= 3 * kInstrSize; |
| 1504 | mov(reg_popped, reg_pushed); |
| 1505 | } else if ((mem_write_instr & kRdMask) |
| 1506 | != (ldr_instr & kRdMask)) { |
| 1507 | reg_pushed = GetRd(mem_write_instr); |
| 1508 | reg_popped = GetRd(mem_read_instr); |
| 1509 | pc_ -= 3 * kInstrSize; |
| 1510 | emit(ldr_instr); |
| 1511 | mov(reg_popped, reg_pushed); |
| 1512 | } else if (((mem_read_instr & kRdMask) |
| 1513 | != (ldr_instr & kRdMask)) || |
| 1514 | ((mem_write_instr & kRdMask) |
| 1515 | == (ldr_instr & kRdMask)) ) { |
| 1516 | reg_pushed = GetRd(mem_write_instr); |
| 1517 | reg_popped = GetRd(mem_read_instr); |
| 1518 | pc_ -= 3 * kInstrSize; |
| 1519 | mov(reg_popped, reg_pushed); |
| 1520 | emit(ldr_instr); |
| 1521 | } |
| 1522 | if (FLAG_print_peephole_optimization) { |
| 1523 | PrintF("%x push/pop (ldr fp+off in middle)\n", pc_offset()); |
| 1524 | } |
| 1525 | } |
| 1526 | } |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1527 | } |
| 1528 | } |
| 1529 | } |
| 1530 | |
| 1531 | |
| 1532 | void Assembler::str(Register src, const MemOperand& dst, Condition cond) { |
| 1533 | addrmod2(cond | B26, src, dst); |
| 1534 | |
| 1535 | // Eliminate pattern: pop(), push(r) |
| 1536 | // add sp, sp, #4 LeaveCC, al; str r, [sp, #-4], al |
| 1537 | // -> str r, [sp, 0], al |
Leon Clarke | f7060e2 | 2010-06-03 12:02:55 +0100 | [diff] [blame] | 1538 | if (can_peephole_optimize(2) && |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1539 | // Pattern. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1540 | instr_at(pc_ - 1 * kInstrSize) == (kPushRegPattern | src.code() * B12) && |
| 1541 | instr_at(pc_ - 2 * kInstrSize) == kPopInstruction) { |
| 1542 | pc_ -= 2 * kInstrSize; |
| 1543 | emit(al | B26 | 0 | Offset | sp.code() * B16 | src.code() * B12); |
Leon Clarke | f7060e2 | 2010-06-03 12:02:55 +0100 | [diff] [blame] | 1544 | if (FLAG_print_peephole_optimization) { |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1545 | PrintF("%x pop()/push(reg) eliminated\n", pc_offset()); |
| 1546 | } |
| 1547 | } |
| 1548 | } |
| 1549 | |
| 1550 | |
| 1551 | void Assembler::ldrb(Register dst, const MemOperand& src, Condition cond) { |
| 1552 | addrmod2(cond | B26 | B | L, dst, src); |
| 1553 | } |
| 1554 | |
| 1555 | |
| 1556 | void Assembler::strb(Register src, const MemOperand& dst, Condition cond) { |
| 1557 | addrmod2(cond | B26 | B, src, dst); |
| 1558 | } |
| 1559 | |
| 1560 | |
| 1561 | void Assembler::ldrh(Register dst, const MemOperand& src, Condition cond) { |
| 1562 | addrmod3(cond | L | B7 | H | B4, dst, src); |
| 1563 | } |
| 1564 | |
| 1565 | |
| 1566 | void Assembler::strh(Register src, const MemOperand& dst, Condition cond) { |
| 1567 | addrmod3(cond | B7 | H | B4, src, dst); |
| 1568 | } |
| 1569 | |
| 1570 | |
| 1571 | void Assembler::ldrsb(Register dst, const MemOperand& src, Condition cond) { |
| 1572 | addrmod3(cond | L | B7 | S6 | B4, dst, src); |
| 1573 | } |
| 1574 | |
| 1575 | |
| 1576 | void Assembler::ldrsh(Register dst, const MemOperand& src, Condition cond) { |
| 1577 | addrmod3(cond | L | B7 | S6 | H | B4, dst, src); |
| 1578 | } |
| 1579 | |
| 1580 | |
Leon Clarke | f7060e2 | 2010-06-03 12:02:55 +0100 | [diff] [blame] | 1581 | void Assembler::ldrd(Register dst1, Register dst2, |
| 1582 | const MemOperand& src, Condition cond) { |
| 1583 | ASSERT(CpuFeatures::IsEnabled(ARMv7)); |
Kristian Monsen | 25f6136 | 2010-05-21 11:50:48 +0100 | [diff] [blame] | 1584 | ASSERT(src.rm().is(no_reg)); |
Leon Clarke | f7060e2 | 2010-06-03 12:02:55 +0100 | [diff] [blame] | 1585 | ASSERT(!dst1.is(lr)); // r14. |
| 1586 | ASSERT_EQ(0, dst1.code() % 2); |
| 1587 | ASSERT_EQ(dst1.code() + 1, dst2.code()); |
| 1588 | addrmod3(cond | B7 | B6 | B4, dst1, src); |
Kristian Monsen | 25f6136 | 2010-05-21 11:50:48 +0100 | [diff] [blame] | 1589 | } |
| 1590 | |
| 1591 | |
Leon Clarke | f7060e2 | 2010-06-03 12:02:55 +0100 | [diff] [blame] | 1592 | void Assembler::strd(Register src1, Register src2, |
| 1593 | const MemOperand& dst, Condition cond) { |
Kristian Monsen | 25f6136 | 2010-05-21 11:50:48 +0100 | [diff] [blame] | 1594 | ASSERT(dst.rm().is(no_reg)); |
Leon Clarke | f7060e2 | 2010-06-03 12:02:55 +0100 | [diff] [blame] | 1595 | ASSERT(!src1.is(lr)); // r14. |
| 1596 | ASSERT_EQ(0, src1.code() % 2); |
| 1597 | ASSERT_EQ(src1.code() + 1, src2.code()); |
| 1598 | ASSERT(CpuFeatures::IsEnabled(ARMv7)); |
| 1599 | addrmod3(cond | B7 | B6 | B5 | B4, src1, dst); |
Kristian Monsen | 25f6136 | 2010-05-21 11:50:48 +0100 | [diff] [blame] | 1600 | } |
| 1601 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1602 | // Load/Store multiple instructions. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1603 | void Assembler::ldm(BlockAddrMode am, |
| 1604 | Register base, |
| 1605 | RegList dst, |
| 1606 | Condition cond) { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1607 | // ABI stack constraint: ldmxx base, {..sp..} base != sp is not restartable. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1608 | ASSERT(base.is(sp) || (dst & sp.bit()) == 0); |
| 1609 | |
| 1610 | addrmod4(cond | B27 | am | L, base, dst); |
| 1611 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1612 | // Emit the constant pool after a function return implemented by ldm ..{..pc}. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1613 | if (cond == al && (dst & pc.bit()) != 0) { |
| 1614 | // There is a slight chance that the ldm instruction was actually a call, |
| 1615 | // in which case it would be wrong to return into the constant pool; we |
| 1616 | // recognize this case by checking if the emission of the pool was blocked |
| 1617 | // at the pc of the ldm instruction by a mov lr, pc instruction; if this is |
| 1618 | // the case, we emit a jump over the pool. |
| 1619 | CheckConstPool(true, no_const_pool_before_ == pc_offset() - kInstrSize); |
| 1620 | } |
| 1621 | } |
| 1622 | |
| 1623 | |
| 1624 | void Assembler::stm(BlockAddrMode am, |
| 1625 | Register base, |
| 1626 | RegList src, |
| 1627 | Condition cond) { |
| 1628 | addrmod4(cond | B27 | am, base, src); |
| 1629 | } |
| 1630 | |
| 1631 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1632 | // Exception-generating instructions and debugging support. |
Teng-Hui Zhu | 3e5fa29 | 2010-11-09 16:16:48 -0800 | [diff] [blame] | 1633 | // Stops with a non-negative code less than kNumOfWatchedStops support |
| 1634 | // enabling/disabling and a counter feature. See simulator-arm.h . |
| 1635 | void Assembler::stop(const char* msg, Condition cond, int32_t code) { |
Andrei Popescu | 402d937 | 2010-02-26 13:31:12 +0000 | [diff] [blame] | 1636 | #ifndef __arm__ |
Teng-Hui Zhu | 3e5fa29 | 2010-11-09 16:16:48 -0800 | [diff] [blame] | 1637 | // See constants-arm.h SoftwareInterruptCodes. Unluckily the Assembler and |
| 1638 | // Simulator do not share constants declaration. |
| 1639 | ASSERT(code >= kDefaultStopCode); |
| 1640 | static const uint32_t kStopInterruptCode = 1 << 23; |
| 1641 | static const uint32_t kMaxStopCode = kStopInterruptCode - 1; |
| 1642 | // The Simulator will handle the stop instruction and get the message address. |
| 1643 | // It expects to find the address just after the svc instruction. |
| 1644 | BlockConstPoolFor(2); |
| 1645 | if (code >= 0) { |
| 1646 | svc(kStopInterruptCode + code, cond); |
| 1647 | } else { |
| 1648 | svc(kStopInterruptCode + kMaxStopCode, cond); |
| 1649 | } |
| 1650 | emit(reinterpret_cast<Instr>(msg)); |
Andrei Popescu | 402d937 | 2010-02-26 13:31:12 +0000 | [diff] [blame] | 1651 | #else // def __arm__ |
| 1652 | #ifdef CAN_USE_ARMV5_INSTRUCTIONS |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1653 | bkpt(0); |
Andrei Popescu | 402d937 | 2010-02-26 13:31:12 +0000 | [diff] [blame] | 1654 | #else // ndef CAN_USE_ARMV5_INSTRUCTIONS |
Teng-Hui Zhu | 3e5fa29 | 2010-11-09 16:16:48 -0800 | [diff] [blame] | 1655 | svc(0x9f0001); |
Andrei Popescu | 402d937 | 2010-02-26 13:31:12 +0000 | [diff] [blame] | 1656 | #endif // ndef CAN_USE_ARMV5_INSTRUCTIONS |
| 1657 | #endif // def __arm__ |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1658 | } |
| 1659 | |
| 1660 | |
| 1661 | void Assembler::bkpt(uint32_t imm16) { // v5 and above |
| 1662 | ASSERT(is_uint16(imm16)); |
| 1663 | emit(al | B24 | B21 | (imm16 >> 4)*B8 | 7*B4 | (imm16 & 0xf)); |
| 1664 | } |
| 1665 | |
| 1666 | |
Teng-Hui Zhu | 3e5fa29 | 2010-11-09 16:16:48 -0800 | [diff] [blame] | 1667 | void Assembler::svc(uint32_t imm24, Condition cond) { |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1668 | ASSERT(is_uint24(imm24)); |
| 1669 | emit(cond | 15*B24 | imm24); |
| 1670 | } |
| 1671 | |
| 1672 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1673 | // Coprocessor instructions. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1674 | void Assembler::cdp(Coprocessor coproc, |
| 1675 | int opcode_1, |
| 1676 | CRegister crd, |
| 1677 | CRegister crn, |
| 1678 | CRegister crm, |
| 1679 | int opcode_2, |
| 1680 | Condition cond) { |
| 1681 | ASSERT(is_uint4(opcode_1) && is_uint3(opcode_2)); |
| 1682 | emit(cond | B27 | B26 | B25 | (opcode_1 & 15)*B20 | crn.code()*B16 | |
| 1683 | crd.code()*B12 | coproc*B8 | (opcode_2 & 7)*B5 | crm.code()); |
| 1684 | } |
| 1685 | |
| 1686 | |
| 1687 | void Assembler::cdp2(Coprocessor coproc, |
| 1688 | int opcode_1, |
| 1689 | CRegister crd, |
| 1690 | CRegister crn, |
| 1691 | CRegister crm, |
| 1692 | int opcode_2) { // v5 and above |
| 1693 | cdp(coproc, opcode_1, crd, crn, crm, opcode_2, static_cast<Condition>(nv)); |
| 1694 | } |
| 1695 | |
| 1696 | |
| 1697 | void Assembler::mcr(Coprocessor coproc, |
| 1698 | int opcode_1, |
| 1699 | Register rd, |
| 1700 | CRegister crn, |
| 1701 | CRegister crm, |
| 1702 | int opcode_2, |
| 1703 | Condition cond) { |
| 1704 | ASSERT(is_uint3(opcode_1) && is_uint3(opcode_2)); |
| 1705 | emit(cond | B27 | B26 | B25 | (opcode_1 & 7)*B21 | crn.code()*B16 | |
| 1706 | rd.code()*B12 | coproc*B8 | (opcode_2 & 7)*B5 | B4 | crm.code()); |
| 1707 | } |
| 1708 | |
| 1709 | |
| 1710 | void Assembler::mcr2(Coprocessor coproc, |
| 1711 | int opcode_1, |
| 1712 | Register rd, |
| 1713 | CRegister crn, |
| 1714 | CRegister crm, |
| 1715 | int opcode_2) { // v5 and above |
| 1716 | mcr(coproc, opcode_1, rd, crn, crm, opcode_2, static_cast<Condition>(nv)); |
| 1717 | } |
| 1718 | |
| 1719 | |
| 1720 | void Assembler::mrc(Coprocessor coproc, |
| 1721 | int opcode_1, |
| 1722 | Register rd, |
| 1723 | CRegister crn, |
| 1724 | CRegister crm, |
| 1725 | int opcode_2, |
| 1726 | Condition cond) { |
| 1727 | ASSERT(is_uint3(opcode_1) && is_uint3(opcode_2)); |
| 1728 | emit(cond | B27 | B26 | B25 | (opcode_1 & 7)*B21 | L | crn.code()*B16 | |
| 1729 | rd.code()*B12 | coproc*B8 | (opcode_2 & 7)*B5 | B4 | crm.code()); |
| 1730 | } |
| 1731 | |
| 1732 | |
| 1733 | void Assembler::mrc2(Coprocessor coproc, |
| 1734 | int opcode_1, |
| 1735 | Register rd, |
| 1736 | CRegister crn, |
| 1737 | CRegister crm, |
| 1738 | int opcode_2) { // v5 and above |
| 1739 | mrc(coproc, opcode_1, rd, crn, crm, opcode_2, static_cast<Condition>(nv)); |
| 1740 | } |
| 1741 | |
| 1742 | |
| 1743 | void Assembler::ldc(Coprocessor coproc, |
| 1744 | CRegister crd, |
| 1745 | const MemOperand& src, |
| 1746 | LFlag l, |
| 1747 | Condition cond) { |
| 1748 | addrmod5(cond | B27 | B26 | l | L | coproc*B8, crd, src); |
| 1749 | } |
| 1750 | |
| 1751 | |
| 1752 | void Assembler::ldc(Coprocessor coproc, |
| 1753 | CRegister crd, |
| 1754 | Register rn, |
| 1755 | int option, |
| 1756 | LFlag l, |
| 1757 | Condition cond) { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1758 | // Unindexed addressing. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1759 | ASSERT(is_uint8(option)); |
| 1760 | emit(cond | B27 | B26 | U | l | L | rn.code()*B16 | crd.code()*B12 | |
| 1761 | coproc*B8 | (option & 255)); |
| 1762 | } |
| 1763 | |
| 1764 | |
| 1765 | void Assembler::ldc2(Coprocessor coproc, |
| 1766 | CRegister crd, |
| 1767 | const MemOperand& src, |
| 1768 | LFlag l) { // v5 and above |
| 1769 | ldc(coproc, crd, src, l, static_cast<Condition>(nv)); |
| 1770 | } |
| 1771 | |
| 1772 | |
| 1773 | void Assembler::ldc2(Coprocessor coproc, |
| 1774 | CRegister crd, |
| 1775 | Register rn, |
| 1776 | int option, |
| 1777 | LFlag l) { // v5 and above |
| 1778 | ldc(coproc, crd, rn, option, l, static_cast<Condition>(nv)); |
| 1779 | } |
| 1780 | |
| 1781 | |
| 1782 | void Assembler::stc(Coprocessor coproc, |
| 1783 | CRegister crd, |
| 1784 | const MemOperand& dst, |
| 1785 | LFlag l, |
| 1786 | Condition cond) { |
| 1787 | addrmod5(cond | B27 | B26 | l | coproc*B8, crd, dst); |
| 1788 | } |
| 1789 | |
| 1790 | |
| 1791 | void Assembler::stc(Coprocessor coproc, |
| 1792 | CRegister crd, |
| 1793 | Register rn, |
| 1794 | int option, |
| 1795 | LFlag l, |
| 1796 | Condition cond) { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1797 | // Unindexed addressing. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1798 | ASSERT(is_uint8(option)); |
| 1799 | emit(cond | B27 | B26 | U | l | rn.code()*B16 | crd.code()*B12 | |
| 1800 | coproc*B8 | (option & 255)); |
| 1801 | } |
| 1802 | |
| 1803 | |
| 1804 | void Assembler::stc2(Coprocessor |
| 1805 | coproc, CRegister crd, |
| 1806 | const MemOperand& dst, |
| 1807 | LFlag l) { // v5 and above |
| 1808 | stc(coproc, crd, dst, l, static_cast<Condition>(nv)); |
| 1809 | } |
| 1810 | |
| 1811 | |
| 1812 | void Assembler::stc2(Coprocessor coproc, |
| 1813 | CRegister crd, |
| 1814 | Register rn, |
| 1815 | int option, |
| 1816 | LFlag l) { // v5 and above |
| 1817 | stc(coproc, crd, rn, option, l, static_cast<Condition>(nv)); |
| 1818 | } |
| 1819 | |
| 1820 | |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 1821 | // Support for VFP. |
Kristian Monsen | 80d68ea | 2010-09-08 11:05:35 +0100 | [diff] [blame] | 1822 | |
Leon Clarke | d91b9f7 | 2010-01-27 17:25:45 +0000 | [diff] [blame] | 1823 | void Assembler::vldr(const DwVfpRegister dst, |
| 1824 | const Register base, |
| 1825 | int offset, |
| 1826 | const Condition cond) { |
| 1827 | // Ddst = MEM(Rbase + offset). |
| 1828 | // Instruction details available in ARM DDI 0406A, A8-628. |
| 1829 | // cond(31-28) | 1101(27-24)| 1001(23-20) | Rbase(19-16) | |
| 1830 | // Vdst(15-12) | 1011(11-8) | offset |
| 1831 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
| 1832 | ASSERT(offset % 4 == 0); |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 1833 | ASSERT((offset / 4) < 256); |
Iain Merrick | 7568138 | 2010-08-19 15:07:18 +0100 | [diff] [blame] | 1834 | ASSERT(offset >= 0); |
Leon Clarke | d91b9f7 | 2010-01-27 17:25:45 +0000 | [diff] [blame] | 1835 | emit(cond | 0xD9*B20 | base.code()*B16 | dst.code()*B12 | |
| 1836 | 0xB*B8 | ((offset / 4) & 255)); |
| 1837 | } |
| 1838 | |
| 1839 | |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 1840 | void Assembler::vldr(const SwVfpRegister dst, |
| 1841 | const Register base, |
| 1842 | int offset, |
| 1843 | const Condition cond) { |
| 1844 | // Sdst = MEM(Rbase + offset). |
| 1845 | // Instruction details available in ARM DDI 0406A, A8-628. |
| 1846 | // cond(31-28) | 1101(27-24)| 1001(23-20) | Rbase(19-16) | |
| 1847 | // Vdst(15-12) | 1010(11-8) | offset |
| 1848 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
| 1849 | ASSERT(offset % 4 == 0); |
| 1850 | ASSERT((offset / 4) < 256); |
Iain Merrick | 7568138 | 2010-08-19 15:07:18 +0100 | [diff] [blame] | 1851 | ASSERT(offset >= 0); |
Kristian Monsen | 80d68ea | 2010-09-08 11:05:35 +0100 | [diff] [blame] | 1852 | int sd, d; |
| 1853 | dst.split_code(&sd, &d); |
| 1854 | emit(cond | d*B22 | 0xD9*B20 | base.code()*B16 | sd*B12 | |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 1855 | 0xA*B8 | ((offset / 4) & 255)); |
| 1856 | } |
| 1857 | |
| 1858 | |
Leon Clarke | d91b9f7 | 2010-01-27 17:25:45 +0000 | [diff] [blame] | 1859 | void Assembler::vstr(const DwVfpRegister src, |
| 1860 | const Register base, |
| 1861 | int offset, |
| 1862 | const Condition cond) { |
| 1863 | // MEM(Rbase + offset) = Dsrc. |
| 1864 | // Instruction details available in ARM DDI 0406A, A8-786. |
| 1865 | // cond(31-28) | 1101(27-24)| 1000(23-20) | | Rbase(19-16) | |
| 1866 | // Vsrc(15-12) | 1011(11-8) | (offset/4) |
| 1867 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
| 1868 | ASSERT(offset % 4 == 0); |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 1869 | ASSERT((offset / 4) < 256); |
Iain Merrick | 7568138 | 2010-08-19 15:07:18 +0100 | [diff] [blame] | 1870 | ASSERT(offset >= 0); |
Leon Clarke | d91b9f7 | 2010-01-27 17:25:45 +0000 | [diff] [blame] | 1871 | emit(cond | 0xD8*B20 | base.code()*B16 | src.code()*B12 | |
| 1872 | 0xB*B8 | ((offset / 4) & 255)); |
| 1873 | } |
| 1874 | |
| 1875 | |
Iain Merrick | 7568138 | 2010-08-19 15:07:18 +0100 | [diff] [blame] | 1876 | void Assembler::vstr(const SwVfpRegister src, |
| 1877 | const Register base, |
| 1878 | int offset, |
| 1879 | const Condition cond) { |
| 1880 | // MEM(Rbase + offset) = SSrc. |
| 1881 | // Instruction details available in ARM DDI 0406A, A8-786. |
| 1882 | // cond(31-28) | 1101(27-24)| 1000(23-20) | Rbase(19-16) | |
| 1883 | // Vdst(15-12) | 1010(11-8) | (offset/4) |
| 1884 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
| 1885 | ASSERT(offset % 4 == 0); |
| 1886 | ASSERT((offset / 4) < 256); |
| 1887 | ASSERT(offset >= 0); |
Kristian Monsen | 80d68ea | 2010-09-08 11:05:35 +0100 | [diff] [blame] | 1888 | int sd, d; |
| 1889 | src.split_code(&sd, &d); |
| 1890 | emit(cond | d*B22 | 0xD8*B20 | base.code()*B16 | sd*B12 | |
Iain Merrick | 7568138 | 2010-08-19 15:07:18 +0100 | [diff] [blame] | 1891 | 0xA*B8 | ((offset / 4) & 255)); |
| 1892 | } |
| 1893 | |
| 1894 | |
Ben Murdoch | 3bec4d2 | 2010-07-22 14:51:16 +0100 | [diff] [blame] | 1895 | static void DoubleAsTwoUInt32(double d, uint32_t* lo, uint32_t* hi) { |
| 1896 | uint64_t i; |
| 1897 | memcpy(&i, &d, 8); |
| 1898 | |
| 1899 | *lo = i & 0xffffffff; |
| 1900 | *hi = i >> 32; |
| 1901 | } |
| 1902 | |
| 1903 | // Only works for little endian floating point formats. |
| 1904 | // We don't support VFP on the mixed endian floating point platform. |
| 1905 | static bool FitsVMOVDoubleImmediate(double d, uint32_t *encoding) { |
| 1906 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
| 1907 | |
| 1908 | // VMOV can accept an immediate of the form: |
| 1909 | // |
| 1910 | // +/- m * 2^(-n) where 16 <= m <= 31 and 0 <= n <= 7 |
| 1911 | // |
| 1912 | // The immediate is encoded using an 8-bit quantity, comprised of two |
| 1913 | // 4-bit fields. For an 8-bit immediate of the form: |
| 1914 | // |
| 1915 | // [abcdefgh] |
| 1916 | // |
| 1917 | // where a is the MSB and h is the LSB, an immediate 64-bit double can be |
| 1918 | // created of the form: |
| 1919 | // |
| 1920 | // [aBbbbbbb,bbcdefgh,00000000,00000000, |
| 1921 | // 00000000,00000000,00000000,00000000] |
| 1922 | // |
| 1923 | // where B = ~b. |
| 1924 | // |
| 1925 | |
| 1926 | uint32_t lo, hi; |
| 1927 | DoubleAsTwoUInt32(d, &lo, &hi); |
| 1928 | |
| 1929 | // The most obvious constraint is the long block of zeroes. |
| 1930 | if ((lo != 0) || ((hi & 0xffff) != 0)) { |
| 1931 | return false; |
| 1932 | } |
| 1933 | |
| 1934 | // Bits 62:55 must be all clear or all set. |
| 1935 | if (((hi & 0x3fc00000) != 0) && ((hi & 0x3fc00000) != 0x3fc00000)) { |
| 1936 | return false; |
| 1937 | } |
| 1938 | |
| 1939 | // Bit 63 must be NOT bit 62. |
| 1940 | if (((hi ^ (hi << 1)) & (0x40000000)) == 0) { |
| 1941 | return false; |
| 1942 | } |
| 1943 | |
| 1944 | // Create the encoded immediate in the form: |
| 1945 | // [00000000,0000abcd,00000000,0000efgh] |
| 1946 | *encoding = (hi >> 16) & 0xf; // Low nybble. |
| 1947 | *encoding |= (hi >> 4) & 0x70000; // Low three bits of the high nybble. |
| 1948 | *encoding |= (hi >> 12) & 0x80000; // Top bit of the high nybble. |
| 1949 | |
| 1950 | return true; |
| 1951 | } |
| 1952 | |
| 1953 | |
| 1954 | void Assembler::vmov(const DwVfpRegister dst, |
| 1955 | double imm, |
| 1956 | const Condition cond) { |
| 1957 | // Dd = immediate |
| 1958 | // Instruction details available in ARM DDI 0406B, A8-640. |
| 1959 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
| 1960 | |
| 1961 | uint32_t enc; |
| 1962 | if (FitsVMOVDoubleImmediate(imm, &enc)) { |
| 1963 | // The double can be encoded in the instruction. |
| 1964 | emit(cond | 0xE*B24 | 0xB*B20 | dst.code()*B12 | 0xB*B8 | enc); |
| 1965 | } else { |
| 1966 | // Synthesise the double from ARM immediates. This could be implemented |
| 1967 | // using vldr from a constant pool. |
| 1968 | uint32_t lo, hi; |
| 1969 | DoubleAsTwoUInt32(imm, &lo, &hi); |
| 1970 | |
| 1971 | if (lo == hi) { |
| 1972 | // If the lo and hi parts of the double are equal, the literal is easier |
| 1973 | // to create. This is the case with 0.0. |
| 1974 | mov(ip, Operand(lo)); |
| 1975 | vmov(dst, ip, ip); |
| 1976 | } else { |
| 1977 | // Move the low part of the double into the lower of the corresponsing S |
| 1978 | // registers of D register dst. |
| 1979 | mov(ip, Operand(lo)); |
| 1980 | vmov(dst.low(), ip, cond); |
| 1981 | |
| 1982 | // Move the high part of the double into the higher of the corresponsing S |
| 1983 | // registers of D register dst. |
| 1984 | mov(ip, Operand(hi)); |
| 1985 | vmov(dst.high(), ip, cond); |
| 1986 | } |
| 1987 | } |
| 1988 | } |
| 1989 | |
| 1990 | |
| 1991 | void Assembler::vmov(const SwVfpRegister dst, |
| 1992 | const SwVfpRegister src, |
| 1993 | const Condition cond) { |
| 1994 | // Sd = Sm |
| 1995 | // Instruction details available in ARM DDI 0406B, A8-642. |
| 1996 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
Kristian Monsen | 80d68ea | 2010-09-08 11:05:35 +0100 | [diff] [blame] | 1997 | int sd, d, sm, m; |
| 1998 | dst.split_code(&sd, &d); |
| 1999 | src.split_code(&sm, &m); |
| 2000 | emit(cond | 0xE*B24 | d*B22 | 0xB*B20 | sd*B12 | 0xA*B8 | B6 | m*B5 | sm); |
Ben Murdoch | 3bec4d2 | 2010-07-22 14:51:16 +0100 | [diff] [blame] | 2001 | } |
| 2002 | |
| 2003 | |
Leon Clarke | e46be81 | 2010-01-19 14:06:41 +0000 | [diff] [blame] | 2004 | void Assembler::vmov(const DwVfpRegister dst, |
Steve Block | 8defd9f | 2010-07-08 12:39:36 +0100 | [diff] [blame] | 2005 | const DwVfpRegister src, |
| 2006 | const Condition cond) { |
| 2007 | // Dd = Dm |
| 2008 | // Instruction details available in ARM DDI 0406B, A8-642. |
Ben Murdoch | 3bec4d2 | 2010-07-22 14:51:16 +0100 | [diff] [blame] | 2009 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
Steve Block | 8defd9f | 2010-07-08 12:39:36 +0100 | [diff] [blame] | 2010 | emit(cond | 0xE*B24 | 0xB*B20 | |
| 2011 | dst.code()*B12 | 0x5*B9 | B8 | B6 | src.code()); |
| 2012 | } |
| 2013 | |
| 2014 | |
| 2015 | void Assembler::vmov(const DwVfpRegister dst, |
Leon Clarke | e46be81 | 2010-01-19 14:06:41 +0000 | [diff] [blame] | 2016 | const Register src1, |
| 2017 | const Register src2, |
| 2018 | const Condition cond) { |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 2019 | // Dm = <Rt,Rt2>. |
| 2020 | // Instruction details available in ARM DDI 0406A, A8-646. |
| 2021 | // cond(31-28) | 1100(27-24)| 010(23-21) | op=0(20) | Rt2(19-16) | |
| 2022 | // Rt(15-12) | 1011(11-8) | 00(7-6) | M(5) | 1(4) | Vm |
| 2023 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
| 2024 | ASSERT(!src1.is(pc) && !src2.is(pc)); |
| 2025 | emit(cond | 0xC*B24 | B22 | src2.code()*B16 | |
| 2026 | src1.code()*B12 | 0xB*B8 | B4 | dst.code()); |
| 2027 | } |
| 2028 | |
| 2029 | |
Leon Clarke | e46be81 | 2010-01-19 14:06:41 +0000 | [diff] [blame] | 2030 | void Assembler::vmov(const Register dst1, |
| 2031 | const Register dst2, |
| 2032 | const DwVfpRegister src, |
| 2033 | const Condition cond) { |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 2034 | // <Rt,Rt2> = Dm. |
| 2035 | // Instruction details available in ARM DDI 0406A, A8-646. |
| 2036 | // cond(31-28) | 1100(27-24)| 010(23-21) | op=1(20) | Rt2(19-16) | |
| 2037 | // Rt(15-12) | 1011(11-8) | 00(7-6) | M(5) | 1(4) | Vm |
| 2038 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
| 2039 | ASSERT(!dst1.is(pc) && !dst2.is(pc)); |
| 2040 | emit(cond | 0xC*B24 | B22 | B20 | dst2.code()*B16 | |
| 2041 | dst1.code()*B12 | 0xB*B8 | B4 | src.code()); |
| 2042 | } |
| 2043 | |
| 2044 | |
Leon Clarke | e46be81 | 2010-01-19 14:06:41 +0000 | [diff] [blame] | 2045 | void Assembler::vmov(const SwVfpRegister dst, |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 2046 | const Register src, |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 2047 | const Condition cond) { |
| 2048 | // Sn = Rt. |
| 2049 | // Instruction details available in ARM DDI 0406A, A8-642. |
| 2050 | // cond(31-28) | 1110(27-24)| 000(23-21) | op=0(20) | Vn(19-16) | |
| 2051 | // Rt(15-12) | 1010(11-8) | N(7)=0 | 00(6-5) | 1(4) | 0000(3-0) |
| 2052 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
| 2053 | ASSERT(!src.is(pc)); |
Kristian Monsen | 80d68ea | 2010-09-08 11:05:35 +0100 | [diff] [blame] | 2054 | int sn, n; |
| 2055 | dst.split_code(&sn, &n); |
| 2056 | emit(cond | 0xE*B24 | sn*B16 | src.code()*B12 | 0xA*B8 | n*B7 | B4); |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 2057 | } |
| 2058 | |
| 2059 | |
Leon Clarke | e46be81 | 2010-01-19 14:06:41 +0000 | [diff] [blame] | 2060 | void Assembler::vmov(const Register dst, |
| 2061 | const SwVfpRegister src, |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 2062 | const Condition cond) { |
| 2063 | // Rt = Sn. |
| 2064 | // Instruction details available in ARM DDI 0406A, A8-642. |
| 2065 | // cond(31-28) | 1110(27-24)| 000(23-21) | op=1(20) | Vn(19-16) | |
| 2066 | // Rt(15-12) | 1010(11-8) | N(7)=0 | 00(6-5) | 1(4) | 0000(3-0) |
| 2067 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
| 2068 | ASSERT(!dst.is(pc)); |
Kristian Monsen | 80d68ea | 2010-09-08 11:05:35 +0100 | [diff] [blame] | 2069 | int sn, n; |
| 2070 | src.split_code(&sn, &n); |
| 2071 | emit(cond | 0xE*B24 | B20 | sn*B16 | dst.code()*B12 | 0xA*B8 | n*B7 | B4); |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 2072 | } |
| 2073 | |
| 2074 | |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 2075 | // Type of data to read from or write to VFP register. |
| 2076 | // Used as specifier in generic vcvt instruction. |
| 2077 | enum VFPType { S32, U32, F32, F64 }; |
| 2078 | |
| 2079 | |
| 2080 | static bool IsSignedVFPType(VFPType type) { |
| 2081 | switch (type) { |
| 2082 | case S32: |
| 2083 | return true; |
| 2084 | case U32: |
| 2085 | return false; |
| 2086 | default: |
| 2087 | UNREACHABLE(); |
| 2088 | return false; |
| 2089 | } |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 2090 | } |
| 2091 | |
| 2092 | |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 2093 | static bool IsIntegerVFPType(VFPType type) { |
| 2094 | switch (type) { |
| 2095 | case S32: |
| 2096 | case U32: |
| 2097 | return true; |
| 2098 | case F32: |
| 2099 | case F64: |
| 2100 | return false; |
| 2101 | default: |
| 2102 | UNREACHABLE(); |
| 2103 | return false; |
| 2104 | } |
| 2105 | } |
| 2106 | |
| 2107 | |
| 2108 | static bool IsDoubleVFPType(VFPType type) { |
| 2109 | switch (type) { |
| 2110 | case F32: |
| 2111 | return false; |
| 2112 | case F64: |
| 2113 | return true; |
| 2114 | default: |
| 2115 | UNREACHABLE(); |
| 2116 | return false; |
| 2117 | } |
| 2118 | } |
| 2119 | |
| 2120 | |
Kristian Monsen | 80d68ea | 2010-09-08 11:05:35 +0100 | [diff] [blame] | 2121 | // Split five bit reg_code based on size of reg_type. |
| 2122 | // 32-bit register codes are Vm:M |
| 2123 | // 64-bit register codes are M:Vm |
| 2124 | // where Vm is four bits, and M is a single bit. |
| 2125 | static void SplitRegCode(VFPType reg_type, |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 2126 | int reg_code, |
| 2127 | int* vm, |
| 2128 | int* m) { |
Kristian Monsen | 80d68ea | 2010-09-08 11:05:35 +0100 | [diff] [blame] | 2129 | ASSERT((reg_code >= 0) && (reg_code <= 31)); |
| 2130 | if (IsIntegerVFPType(reg_type) || !IsDoubleVFPType(reg_type)) { |
| 2131 | // 32 bit type. |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 2132 | *m = reg_code & 0x1; |
| 2133 | *vm = reg_code >> 1; |
| 2134 | } else { |
Kristian Monsen | 80d68ea | 2010-09-08 11:05:35 +0100 | [diff] [blame] | 2135 | // 64 bit type. |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 2136 | *m = (reg_code & 0x10) >> 4; |
| 2137 | *vm = reg_code & 0x0F; |
| 2138 | } |
| 2139 | } |
| 2140 | |
| 2141 | |
| 2142 | // Encode vcvt.src_type.dst_type instruction. |
| 2143 | static Instr EncodeVCVT(const VFPType dst_type, |
| 2144 | const int dst_code, |
| 2145 | const VFPType src_type, |
| 2146 | const int src_code, |
Russell Brenner | 90bac25 | 2010-11-18 13:33:46 -0800 | [diff] [blame^] | 2147 | Assembler::ConversionMode mode, |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 2148 | const Condition cond) { |
Kristian Monsen | 80d68ea | 2010-09-08 11:05:35 +0100 | [diff] [blame] | 2149 | ASSERT(src_type != dst_type); |
| 2150 | int D, Vd, M, Vm; |
| 2151 | SplitRegCode(src_type, src_code, &Vm, &M); |
| 2152 | SplitRegCode(dst_type, dst_code, &Vd, &D); |
| 2153 | |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 2154 | if (IsIntegerVFPType(dst_type) || IsIntegerVFPType(src_type)) { |
| 2155 | // Conversion between IEEE floating point and 32-bit integer. |
| 2156 | // Instruction details available in ARM DDI 0406B, A8.6.295. |
| 2157 | // cond(31-28) | 11101(27-23)| D(22) | 11(21-20) | 1(19) | opc2(18-16) | |
| 2158 | // Vd(15-12) | 101(11-9) | sz(8) | op(7) | 1(6) | M(5) | 0(4) | Vm(3-0) |
| 2159 | ASSERT(!IsIntegerVFPType(dst_type) || !IsIntegerVFPType(src_type)); |
| 2160 | |
Kristian Monsen | 80d68ea | 2010-09-08 11:05:35 +0100 | [diff] [blame] | 2161 | int sz, opc2, op; |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 2162 | |
| 2163 | if (IsIntegerVFPType(dst_type)) { |
| 2164 | opc2 = IsSignedVFPType(dst_type) ? 0x5 : 0x4; |
| 2165 | sz = IsDoubleVFPType(src_type) ? 0x1 : 0x0; |
Russell Brenner | 90bac25 | 2010-11-18 13:33:46 -0800 | [diff] [blame^] | 2166 | op = mode; |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 2167 | } else { |
| 2168 | ASSERT(IsIntegerVFPType(src_type)); |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 2169 | opc2 = 0x0; |
| 2170 | sz = IsDoubleVFPType(dst_type) ? 0x1 : 0x0; |
| 2171 | op = IsSignedVFPType(src_type) ? 0x1 : 0x0; |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 2172 | } |
| 2173 | |
| 2174 | return (cond | 0xE*B24 | B23 | D*B22 | 0x3*B20 | B19 | opc2*B16 | |
| 2175 | Vd*B12 | 0x5*B9 | sz*B8 | op*B7 | B6 | M*B5 | Vm); |
| 2176 | } else { |
| 2177 | // Conversion between IEEE double and single precision. |
| 2178 | // Instruction details available in ARM DDI 0406B, A8.6.298. |
| 2179 | // cond(31-28) | 11101(27-23)| D(22) | 11(21-20) | 0111(19-16) | |
| 2180 | // Vd(15-12) | 101(11-9) | sz(8) | 1(7) | 1(6) | M(5) | 0(4) | Vm(3-0) |
Kristian Monsen | 80d68ea | 2010-09-08 11:05:35 +0100 | [diff] [blame] | 2181 | int sz = IsDoubleVFPType(src_type) ? 0x1 : 0x0; |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 2182 | return (cond | 0xE*B24 | B23 | D*B22 | 0x3*B20 | 0x7*B16 | |
| 2183 | Vd*B12 | 0x5*B9 | sz*B8 | B7 | B6 | M*B5 | Vm); |
| 2184 | } |
| 2185 | } |
| 2186 | |
| 2187 | |
| 2188 | void Assembler::vcvt_f64_s32(const DwVfpRegister dst, |
| 2189 | const SwVfpRegister src, |
Russell Brenner | 90bac25 | 2010-11-18 13:33:46 -0800 | [diff] [blame^] | 2190 | ConversionMode mode, |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 2191 | const Condition cond) { |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 2192 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
Russell Brenner | 90bac25 | 2010-11-18 13:33:46 -0800 | [diff] [blame^] | 2193 | emit(EncodeVCVT(F64, dst.code(), S32, src.code(), mode, cond)); |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 2194 | } |
| 2195 | |
| 2196 | |
| 2197 | void Assembler::vcvt_f32_s32(const SwVfpRegister dst, |
| 2198 | const SwVfpRegister src, |
Russell Brenner | 90bac25 | 2010-11-18 13:33:46 -0800 | [diff] [blame^] | 2199 | ConversionMode mode, |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 2200 | const Condition cond) { |
| 2201 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
Russell Brenner | 90bac25 | 2010-11-18 13:33:46 -0800 | [diff] [blame^] | 2202 | emit(EncodeVCVT(F32, dst.code(), S32, src.code(), mode, cond)); |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 2203 | } |
| 2204 | |
| 2205 | |
| 2206 | void Assembler::vcvt_f64_u32(const DwVfpRegister dst, |
| 2207 | const SwVfpRegister src, |
Russell Brenner | 90bac25 | 2010-11-18 13:33:46 -0800 | [diff] [blame^] | 2208 | ConversionMode mode, |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 2209 | const Condition cond) { |
| 2210 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
Russell Brenner | 90bac25 | 2010-11-18 13:33:46 -0800 | [diff] [blame^] | 2211 | emit(EncodeVCVT(F64, dst.code(), U32, src.code(), mode, cond)); |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 2212 | } |
| 2213 | |
| 2214 | |
| 2215 | void Assembler::vcvt_s32_f64(const SwVfpRegister dst, |
| 2216 | const DwVfpRegister src, |
Russell Brenner | 90bac25 | 2010-11-18 13:33:46 -0800 | [diff] [blame^] | 2217 | ConversionMode mode, |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 2218 | const Condition cond) { |
| 2219 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
Russell Brenner | 90bac25 | 2010-11-18 13:33:46 -0800 | [diff] [blame^] | 2220 | emit(EncodeVCVT(S32, dst.code(), F64, src.code(), mode, cond)); |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 2221 | } |
| 2222 | |
| 2223 | |
| 2224 | void Assembler::vcvt_u32_f64(const SwVfpRegister dst, |
| 2225 | const DwVfpRegister src, |
Russell Brenner | 90bac25 | 2010-11-18 13:33:46 -0800 | [diff] [blame^] | 2226 | ConversionMode mode, |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 2227 | const Condition cond) { |
| 2228 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
Russell Brenner | 90bac25 | 2010-11-18 13:33:46 -0800 | [diff] [blame^] | 2229 | emit(EncodeVCVT(U32, dst.code(), F64, src.code(), mode, cond)); |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 2230 | } |
| 2231 | |
| 2232 | |
| 2233 | void Assembler::vcvt_f64_f32(const DwVfpRegister dst, |
| 2234 | const SwVfpRegister src, |
Russell Brenner | 90bac25 | 2010-11-18 13:33:46 -0800 | [diff] [blame^] | 2235 | ConversionMode mode, |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 2236 | const Condition cond) { |
| 2237 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
Russell Brenner | 90bac25 | 2010-11-18 13:33:46 -0800 | [diff] [blame^] | 2238 | emit(EncodeVCVT(F64, dst.code(), F32, src.code(), mode, cond)); |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 2239 | } |
| 2240 | |
| 2241 | |
| 2242 | void Assembler::vcvt_f32_f64(const SwVfpRegister dst, |
| 2243 | const DwVfpRegister src, |
Russell Brenner | 90bac25 | 2010-11-18 13:33:46 -0800 | [diff] [blame^] | 2244 | ConversionMode mode, |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 2245 | const Condition cond) { |
| 2246 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
Russell Brenner | 90bac25 | 2010-11-18 13:33:46 -0800 | [diff] [blame^] | 2247 | emit(EncodeVCVT(F32, dst.code(), F64, src.code(), mode, cond)); |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 2248 | } |
| 2249 | |
| 2250 | |
Leon Clarke | e46be81 | 2010-01-19 14:06:41 +0000 | [diff] [blame] | 2251 | void Assembler::vadd(const DwVfpRegister dst, |
| 2252 | const DwVfpRegister src1, |
| 2253 | const DwVfpRegister src2, |
| 2254 | const Condition cond) { |
| 2255 | // Dd = vadd(Dn, Dm) double precision floating point addition. |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 2256 | // Dd = D:Vd; Dm=M:Vm; Dn=N:Vm. |
| 2257 | // Instruction details available in ARM DDI 0406A, A8-536. |
| 2258 | // cond(31-28) | 11100(27-23)| D=?(22) | 11(21-20) | Vn(19-16) | |
| 2259 | // Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=0 | 0(6) | M=?(5) | 0(4) | Vm(3-0) |
| 2260 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
| 2261 | emit(cond | 0xE*B24 | 0x3*B20 | src1.code()*B16 | |
| 2262 | dst.code()*B12 | 0x5*B9 | B8 | src2.code()); |
| 2263 | } |
| 2264 | |
| 2265 | |
Leon Clarke | e46be81 | 2010-01-19 14:06:41 +0000 | [diff] [blame] | 2266 | void Assembler::vsub(const DwVfpRegister dst, |
| 2267 | const DwVfpRegister src1, |
| 2268 | const DwVfpRegister src2, |
| 2269 | const Condition cond) { |
| 2270 | // Dd = vsub(Dn, Dm) double precision floating point subtraction. |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 2271 | // Dd = D:Vd; Dm=M:Vm; Dn=N:Vm. |
| 2272 | // Instruction details available in ARM DDI 0406A, A8-784. |
| 2273 | // cond(31-28) | 11100(27-23)| D=?(22) | 11(21-20) | Vn(19-16) | |
| 2274 | // Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=0 | 1(6) | M=?(5) | 0(4) | Vm(3-0) |
| 2275 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
| 2276 | emit(cond | 0xE*B24 | 0x3*B20 | src1.code()*B16 | |
| 2277 | dst.code()*B12 | 0x5*B9 | B8 | B6 | src2.code()); |
| 2278 | } |
| 2279 | |
| 2280 | |
Leon Clarke | e46be81 | 2010-01-19 14:06:41 +0000 | [diff] [blame] | 2281 | void Assembler::vmul(const DwVfpRegister dst, |
| 2282 | const DwVfpRegister src1, |
| 2283 | const DwVfpRegister src2, |
| 2284 | const Condition cond) { |
| 2285 | // Dd = vmul(Dn, Dm) double precision floating point multiplication. |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 2286 | // Dd = D:Vd; Dm=M:Vm; Dn=N:Vm. |
| 2287 | // Instruction details available in ARM DDI 0406A, A8-784. |
| 2288 | // cond(31-28) | 11100(27-23)| D=?(22) | 10(21-20) | Vn(19-16) | |
| 2289 | // Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=0 | 0(6) | M=?(5) | 0(4) | Vm(3-0) |
| 2290 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
| 2291 | emit(cond | 0xE*B24 | 0x2*B20 | src1.code()*B16 | |
| 2292 | dst.code()*B12 | 0x5*B9 | B8 | src2.code()); |
| 2293 | } |
| 2294 | |
| 2295 | |
Leon Clarke | e46be81 | 2010-01-19 14:06:41 +0000 | [diff] [blame] | 2296 | void Assembler::vdiv(const DwVfpRegister dst, |
| 2297 | const DwVfpRegister src1, |
| 2298 | const DwVfpRegister src2, |
| 2299 | const Condition cond) { |
| 2300 | // Dd = vdiv(Dn, Dm) double precision floating point division. |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 2301 | // Dd = D:Vd; Dm=M:Vm; Dn=N:Vm. |
| 2302 | // Instruction details available in ARM DDI 0406A, A8-584. |
| 2303 | // cond(31-28) | 11101(27-23)| D=?(22) | 00(21-20) | Vn(19-16) | |
| 2304 | // Vd(15-12) | 101(11-9) | sz(8)=1 | N(7)=? | 0(6) | M=?(5) | 0(4) | Vm(3-0) |
| 2305 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
| 2306 | emit(cond | 0xE*B24 | B23 | src1.code()*B16 | |
| 2307 | dst.code()*B12 | 0x5*B9 | B8 | src2.code()); |
| 2308 | } |
| 2309 | |
| 2310 | |
Leon Clarke | e46be81 | 2010-01-19 14:06:41 +0000 | [diff] [blame] | 2311 | void Assembler::vcmp(const DwVfpRegister src1, |
| 2312 | const DwVfpRegister src2, |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 2313 | const SBit s, |
| 2314 | const Condition cond) { |
| 2315 | // vcmp(Dd, Dm) double precision floating point comparison. |
| 2316 | // Instruction details available in ARM DDI 0406A, A8-570. |
| 2317 | // cond(31-28) | 11101 (27-23)| D=?(22) | 11 (21-20) | 0100 (19-16) | |
| 2318 | // Vd(15-12) | 101(11-9) | sz(8)=1 | E(7)=? | 1(6) | M(5)=? | 0(4) | Vm(3-0) |
| 2319 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
| 2320 | emit(cond | 0xE*B24 |B23 | 0x3*B20 | B18 | |
| 2321 | src1.code()*B12 | 0x5*B9 | B8 | B6 | src2.code()); |
| 2322 | } |
| 2323 | |
| 2324 | |
Iain Merrick | 7568138 | 2010-08-19 15:07:18 +0100 | [diff] [blame] | 2325 | void Assembler::vcmp(const DwVfpRegister src1, |
| 2326 | const double src2, |
| 2327 | const SBit s, |
| 2328 | const Condition cond) { |
| 2329 | // vcmp(Dd, Dm) double precision floating point comparison. |
| 2330 | // Instruction details available in ARM DDI 0406A, A8-570. |
| 2331 | // cond(31-28) | 11101 (27-23)| D=?(22) | 11 (21-20) | 0101 (19-16) | |
| 2332 | // Vd(15-12) | 101(11-9) | sz(8)=1 | E(7)=? | 1(6) | M(5)=? | 0(4) | 0000(3-0) |
| 2333 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
| 2334 | ASSERT(src2 == 0.0); |
| 2335 | emit(cond | 0xE*B24 |B23 | 0x3*B20 | B18 | B16 | |
| 2336 | src1.code()*B12 | 0x5*B9 | B8 | B6); |
| 2337 | } |
| 2338 | |
| 2339 | |
Russell Brenner | 90bac25 | 2010-11-18 13:33:46 -0800 | [diff] [blame^] | 2340 | void Assembler::vmsr(Register dst, Condition cond) { |
| 2341 | // Instruction details available in ARM DDI 0406A, A8-652. |
| 2342 | // cond(31-28) | 1110 (27-24) | 1110(23-20)| 0001 (19-16) | |
| 2343 | // Rt(15-12) | 1010 (11-8) | 0(7) | 00 (6-5) | 1(4) | 0000(3-0) |
| 2344 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
| 2345 | emit(cond | 0xE*B24 | 0xE*B20 | B16 | |
| 2346 | dst.code()*B12 | 0xA*B8 | B4); |
| 2347 | } |
| 2348 | |
| 2349 | |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 2350 | void Assembler::vmrs(Register dst, Condition cond) { |
| 2351 | // Instruction details available in ARM DDI 0406A, A8-652. |
| 2352 | // cond(31-28) | 1110 (27-24) | 1111(23-20)| 0001 (19-16) | |
| 2353 | // Rt(15-12) | 1010 (11-8) | 0(7) | 00 (6-5) | 1(4) | 0000(3-0) |
| 2354 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
| 2355 | emit(cond | 0xE*B24 | 0xF*B20 | B16 | |
| 2356 | dst.code()*B12 | 0xA*B8 | B4); |
| 2357 | } |
| 2358 | |
| 2359 | |
Steve Block | 8defd9f | 2010-07-08 12:39:36 +0100 | [diff] [blame] | 2360 | void Assembler::vsqrt(const DwVfpRegister dst, |
| 2361 | const DwVfpRegister src, |
| 2362 | const Condition cond) { |
| 2363 | // cond(31-28) | 11101 (27-23)| D=?(22) | 11 (21-20) | 0001 (19-16) | |
| 2364 | // Vd(15-12) | 101(11-9) | sz(8)=1 | 11 (7-6) | M(5)=? | 0(4) | Vm(3-0) |
| 2365 | ASSERT(CpuFeatures::IsEnabled(VFP3)); |
| 2366 | emit(cond | 0xE*B24 | B23 | 0x3*B20 | B16 | |
| 2367 | dst.code()*B12 | 0x5*B9 | B8 | 3*B6 | src.code()); |
| 2368 | } |
| 2369 | |
| 2370 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2371 | // Pseudo instructions. |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 2372 | void Assembler::nop(int type) { |
| 2373 | // This is mov rx, rx. |
| 2374 | ASSERT(0 <= type && type <= 14); // mov pc, pc is not a nop. |
| 2375 | emit(al | 13*B21 | type*B12 | type); |
| 2376 | } |
| 2377 | |
| 2378 | |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 2379 | bool Assembler::ImmediateFitsAddrMode1Instruction(int32_t imm32) { |
| 2380 | uint32_t dummy1; |
| 2381 | uint32_t dummy2; |
| 2382 | return fits_shifter(imm32, &dummy1, &dummy2, NULL); |
| 2383 | } |
| 2384 | |
| 2385 | |
| 2386 | void Assembler::BlockConstPoolFor(int instructions) { |
| 2387 | BlockConstPoolBefore(pc_offset() + instructions * kInstrSize); |
| 2388 | } |
| 2389 | |
| 2390 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2391 | // Debugging. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 2392 | void Assembler::RecordJSReturn() { |
Teng-Hui Zhu | 3e5fa29 | 2010-11-09 16:16:48 -0800 | [diff] [blame] | 2393 | positions_recorder()->WriteRecordedPositions(); |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 2394 | CheckBuffer(); |
| 2395 | RecordRelocInfo(RelocInfo::JS_RETURN); |
| 2396 | } |
| 2397 | |
| 2398 | |
Ben Murdoch | 7f4d5bd | 2010-06-15 11:15:29 +0100 | [diff] [blame] | 2399 | void Assembler::RecordDebugBreakSlot() { |
Teng-Hui Zhu | 3e5fa29 | 2010-11-09 16:16:48 -0800 | [diff] [blame] | 2400 | positions_recorder()->WriteRecordedPositions(); |
Ben Murdoch | 7f4d5bd | 2010-06-15 11:15:29 +0100 | [diff] [blame] | 2401 | CheckBuffer(); |
| 2402 | RecordRelocInfo(RelocInfo::DEBUG_BREAK_SLOT); |
| 2403 | } |
| 2404 | |
| 2405 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 2406 | void Assembler::RecordComment(const char* msg) { |
| 2407 | if (FLAG_debug_code) { |
| 2408 | CheckBuffer(); |
| 2409 | RecordRelocInfo(RelocInfo::COMMENT, reinterpret_cast<intptr_t>(msg)); |
| 2410 | } |
| 2411 | } |
| 2412 | |
| 2413 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 2414 | void Assembler::GrowBuffer() { |
| 2415 | if (!own_buffer_) FATAL("external code buffer is too small"); |
| 2416 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2417 | // Compute new buffer size. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 2418 | CodeDesc desc; // the new buffer |
| 2419 | if (buffer_size_ < 4*KB) { |
| 2420 | desc.buffer_size = 4*KB; |
| 2421 | } else if (buffer_size_ < 1*MB) { |
| 2422 | desc.buffer_size = 2*buffer_size_; |
| 2423 | } else { |
| 2424 | desc.buffer_size = buffer_size_ + 1*MB; |
| 2425 | } |
| 2426 | CHECK_GT(desc.buffer_size, 0); // no overflow |
| 2427 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2428 | // Setup new buffer. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 2429 | desc.buffer = NewArray<byte>(desc.buffer_size); |
| 2430 | |
| 2431 | desc.instr_size = pc_offset(); |
| 2432 | desc.reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos(); |
| 2433 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2434 | // Copy the data. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 2435 | int pc_delta = desc.buffer - buffer_; |
| 2436 | int rc_delta = (desc.buffer + desc.buffer_size) - (buffer_ + buffer_size_); |
| 2437 | memmove(desc.buffer, buffer_, desc.instr_size); |
| 2438 | memmove(reloc_info_writer.pos() + rc_delta, |
| 2439 | reloc_info_writer.pos(), desc.reloc_size); |
| 2440 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2441 | // Switch buffers. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 2442 | DeleteArray(buffer_); |
| 2443 | buffer_ = desc.buffer; |
| 2444 | buffer_size_ = desc.buffer_size; |
| 2445 | pc_ += pc_delta; |
| 2446 | reloc_info_writer.Reposition(reloc_info_writer.pos() + rc_delta, |
| 2447 | reloc_info_writer.last_pc() + pc_delta); |
| 2448 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2449 | // None of our relocation types are pc relative pointing outside the code |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 2450 | // buffer nor pc absolute pointing inside the code buffer, so there is no need |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2451 | // to relocate any emitted relocation entries. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 2452 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2453 | // Relocate pending relocation entries. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 2454 | for (int i = 0; i < num_prinfo_; i++) { |
| 2455 | RelocInfo& rinfo = prinfo_[i]; |
| 2456 | ASSERT(rinfo.rmode() != RelocInfo::COMMENT && |
| 2457 | rinfo.rmode() != RelocInfo::POSITION); |
| 2458 | if (rinfo.rmode() != RelocInfo::JS_RETURN) { |
| 2459 | rinfo.set_pc(rinfo.pc() + pc_delta); |
| 2460 | } |
| 2461 | } |
| 2462 | } |
| 2463 | |
| 2464 | |
| 2465 | void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) { |
| 2466 | RelocInfo rinfo(pc_, rmode, data); // we do not try to reuse pool constants |
Ben Murdoch | 7f4d5bd | 2010-06-15 11:15:29 +0100 | [diff] [blame] | 2467 | if (rmode >= RelocInfo::JS_RETURN && rmode <= RelocInfo::DEBUG_BREAK_SLOT) { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2468 | // Adjust code for new modes. |
Ben Murdoch | 7f4d5bd | 2010-06-15 11:15:29 +0100 | [diff] [blame] | 2469 | ASSERT(RelocInfo::IsDebugBreakSlot(rmode) |
| 2470 | || RelocInfo::IsJSReturn(rmode) |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 2471 | || RelocInfo::IsComment(rmode) |
| 2472 | || RelocInfo::IsPosition(rmode)); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2473 | // These modes do not need an entry in the constant pool. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 2474 | } else { |
| 2475 | ASSERT(num_prinfo_ < kMaxNumPRInfo); |
| 2476 | prinfo_[num_prinfo_++] = rinfo; |
| 2477 | // Make sure the constant pool is not emitted in place of the next |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2478 | // instruction for which we just recorded relocation info. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 2479 | BlockConstPoolBefore(pc_offset() + kInstrSize); |
| 2480 | } |
| 2481 | if (rinfo.rmode() != RelocInfo::NONE) { |
| 2482 | // Don't record external references unless the heap will be serialized. |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 2483 | if (rmode == RelocInfo::EXTERNAL_REFERENCE) { |
| 2484 | #ifdef DEBUG |
| 2485 | if (!Serializer::enabled()) { |
| 2486 | Serializer::TooLateToEnableNow(); |
| 2487 | } |
| 2488 | #endif |
| 2489 | if (!Serializer::enabled() && !FLAG_debug_code) { |
| 2490 | return; |
| 2491 | } |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 2492 | } |
| 2493 | ASSERT(buffer_space() >= kMaxRelocSize); // too late to grow buffer here |
| 2494 | reloc_info_writer.Write(&rinfo); |
| 2495 | } |
| 2496 | } |
| 2497 | |
| 2498 | |
| 2499 | void Assembler::CheckConstPool(bool force_emit, bool require_jump) { |
| 2500 | // Calculate the offset of the next check. It will be overwritten |
| 2501 | // when a const pool is generated or when const pools are being |
| 2502 | // blocked for a specific range. |
| 2503 | next_buffer_check_ = pc_offset() + kCheckConstInterval; |
| 2504 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2505 | // There is nothing to do if there are no pending relocation info entries. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 2506 | if (num_prinfo_ == 0) return; |
| 2507 | |
| 2508 | // We emit a constant pool at regular intervals of about kDistBetweenPools |
| 2509 | // or when requested by parameter force_emit (e.g. after each function). |
| 2510 | // We prefer not to emit a jump unless the max distance is reached or if we |
| 2511 | // are running low on slots, which can happen if a lot of constants are being |
| 2512 | // emitted (e.g. --debug-code and many static references). |
| 2513 | int dist = pc_offset() - last_const_pool_end_; |
| 2514 | if (!force_emit && dist < kMaxDistBetweenPools && |
| 2515 | (require_jump || dist < kDistBetweenPools) && |
| 2516 | // TODO(1236125): Cleanup the "magic" number below. We know that |
| 2517 | // the code generation will test every kCheckConstIntervalInst. |
| 2518 | // Thus we are safe as long as we generate less than 7 constant |
| 2519 | // entries per instruction. |
| 2520 | (num_prinfo_ < (kMaxNumPRInfo - (7 * kCheckConstIntervalInst)))) { |
| 2521 | return; |
| 2522 | } |
| 2523 | |
| 2524 | // If we did not return by now, we need to emit the constant pool soon. |
| 2525 | |
| 2526 | // However, some small sequences of instructions must not be broken up by the |
| 2527 | // insertion of a constant pool; such sequences are protected by setting |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 2528 | // either const_pool_blocked_nesting_ or no_const_pool_before_, which are |
| 2529 | // both checked here. Also, recursive calls to CheckConstPool are blocked by |
| 2530 | // no_const_pool_before_. |
| 2531 | if (const_pool_blocked_nesting_ > 0 || pc_offset() < no_const_pool_before_) { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2532 | // Emission is currently blocked; make sure we try again as soon as |
| 2533 | // possible. |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 2534 | if (const_pool_blocked_nesting_ > 0) { |
| 2535 | next_buffer_check_ = pc_offset() + kInstrSize; |
| 2536 | } else { |
| 2537 | next_buffer_check_ = no_const_pool_before_; |
| 2538 | } |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 2539 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2540 | // Something is wrong if emission is forced and blocked at the same time. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 2541 | ASSERT(!force_emit); |
| 2542 | return; |
| 2543 | } |
| 2544 | |
| 2545 | int jump_instr = require_jump ? kInstrSize : 0; |
| 2546 | |
| 2547 | // Check that the code buffer is large enough before emitting the constant |
| 2548 | // pool and relocation information (include the jump over the pool and the |
| 2549 | // constant pool marker). |
| 2550 | int max_needed_space = |
| 2551 | jump_instr + kInstrSize + num_prinfo_*(kInstrSize + kMaxRelocSize); |
| 2552 | while (buffer_space() <= (max_needed_space + kGap)) GrowBuffer(); |
| 2553 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2554 | // Block recursive calls to CheckConstPool. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 2555 | BlockConstPoolBefore(pc_offset() + jump_instr + kInstrSize + |
| 2556 | num_prinfo_*kInstrSize); |
| 2557 | // Don't bother to check for the emit calls below. |
| 2558 | next_buffer_check_ = no_const_pool_before_; |
| 2559 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2560 | // Emit jump over constant pool if necessary. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 2561 | Label after_pool; |
| 2562 | if (require_jump) b(&after_pool); |
| 2563 | |
| 2564 | RecordComment("[ Constant Pool"); |
| 2565 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2566 | // Put down constant pool marker "Undefined instruction" as specified by |
| 2567 | // A3.1 Instruction set encoding. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 2568 | emit(0x03000000 | num_prinfo_); |
| 2569 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2570 | // Emit constant pool entries. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 2571 | for (int i = 0; i < num_prinfo_; i++) { |
| 2572 | RelocInfo& rinfo = prinfo_[i]; |
| 2573 | ASSERT(rinfo.rmode() != RelocInfo::COMMENT && |
| 2574 | rinfo.rmode() != RelocInfo::POSITION && |
| 2575 | rinfo.rmode() != RelocInfo::STATEMENT_POSITION); |
| 2576 | Instr instr = instr_at(rinfo.pc()); |
| 2577 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2578 | // Instruction to patch must be a ldr/str [pc, #offset]. |
| 2579 | // P and U set, B and W clear, Rn == pc, offset12 still 0. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 2580 | ASSERT((instr & (7*B25 | P | U | B | W | 15*B16 | Off12Mask)) == |
| 2581 | (2*B25 | P | U | pc.code()*B16)); |
| 2582 | int delta = pc_ - rinfo.pc() - 8; |
| 2583 | ASSERT(delta >= -4); // instr could be ldr pc, [pc, #-4] followed by targ32 |
| 2584 | if (delta < 0) { |
| 2585 | instr &= ~U; |
| 2586 | delta = -delta; |
| 2587 | } |
| 2588 | ASSERT(is_uint12(delta)); |
| 2589 | instr_at_put(rinfo.pc(), instr + delta); |
| 2590 | emit(rinfo.data()); |
| 2591 | } |
| 2592 | num_prinfo_ = 0; |
| 2593 | last_const_pool_end_ = pc_offset(); |
| 2594 | |
| 2595 | RecordComment("]"); |
| 2596 | |
| 2597 | if (after_pool.is_linked()) { |
| 2598 | bind(&after_pool); |
| 2599 | } |
| 2600 | |
| 2601 | // Since a constant pool was just emitted, move the check offset forward by |
| 2602 | // the standard interval. |
| 2603 | next_buffer_check_ = pc_offset() + kCheckConstInterval; |
| 2604 | } |
| 2605 | |
| 2606 | |
| 2607 | } } // namespace v8::internal |
Leon Clarke | f7060e2 | 2010-06-03 12:02:55 +0100 | [diff] [blame] | 2608 | |
| 2609 | #endif // V8_TARGET_ARCH_ARM |