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gerrit-public.fairphone.software / fp2-dev / platform / external / v8 / 3942d2ab9eee35cb86018242521effc970f4e902 / . / src / compiler / arm / instruction-codes-arm.h
blob: 401100be753d57d0ef932af1a98456f37b634826 [file] [log] [blame]
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]1// Copyright 2014 the V8 project authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5#ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
6#define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
7
8namespace v8 {
9namespace internal {
10namespace compiler {
11
12// ARM-specific opcodes that specify which assembly sequence to emit.
13// Most opcodes specify a single instruction.
14#define TARGET_ARCH_OPCODE_LIST(V) \
15 V(ArmAdd) \
16 V(ArmAnd) \
17 V(ArmBic) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]18 V(ArmClz) \
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]19 V(ArmCmp) \
20 V(ArmCmn) \
21 V(ArmTst) \
22 V(ArmTeq) \
23 V(ArmOrr) \
24 V(ArmEor) \
25 V(ArmSub) \
26 V(ArmRsb) \
27 V(ArmMul) \
28 V(ArmMla) \
29 V(ArmMls) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]30 V(ArmSmmul) \
31 V(ArmSmmla) \
32 V(ArmUmull) \
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]33 V(ArmSdiv) \
34 V(ArmUdiv) \
35 V(ArmMov) \
36 V(ArmMvn) \
37 V(ArmBfc) \
38 V(ArmUbfx) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]39 V(ArmSxtb) \
40 V(ArmSxth) \
41 V(ArmSxtab) \
42 V(ArmSxtah) \
43 V(ArmUxtb) \
44 V(ArmUxth) \
45 V(ArmUxtab) \
46 V(ArmUxtah) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]47 V(ArmVcmpF32) \
48 V(ArmVaddF32) \
49 V(ArmVsubF32) \
50 V(ArmVmulF32) \
51 V(ArmVmlaF32) \
52 V(ArmVmlsF32) \
53 V(ArmVdivF32) \
54 V(ArmVabsF32) \
55 V(ArmVnegF32) \
56 V(ArmVsqrtF32) \
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]57 V(ArmVcmpF64) \
58 V(ArmVaddF64) \
59 V(ArmVsubF64) \
60 V(ArmVmulF64) \
61 V(ArmVmlaF64) \
62 V(ArmVmlsF64) \
63 V(ArmVdivF64) \
64 V(ArmVmodF64) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]65 V(ArmVabsF64) \
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]66 V(ArmVnegF64) \
67 V(ArmVsqrtF64) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]68 V(ArmVrintmF32) \
69 V(ArmVrintmF64) \
70 V(ArmVrintpF32) \
71 V(ArmVrintpF64) \
72 V(ArmVrintzF32) \
73 V(ArmVrintzF64) \
74 V(ArmVrintaF64) \
75 V(ArmVrintnF32) \
76 V(ArmVrintnF64) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]77 V(ArmVcvtF32F64) \
78 V(ArmVcvtF64F32) \
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]79 V(ArmVcvtF64S32) \
80 V(ArmVcvtF64U32) \
81 V(ArmVcvtS32F64) \
82 V(ArmVcvtU32F64) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]83 V(ArmVmovLowU32F64) \
84 V(ArmVmovLowF64U32) \
85 V(ArmVmovHighU32F64) \
86 V(ArmVmovHighF64U32) \
87 V(ArmVmovF64U32U32) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]88 V(ArmVldrF32) \
89 V(ArmVstrF32) \
90 V(ArmVldrF64) \
91 V(ArmVstrF64) \
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]92 V(ArmLdrb) \
93 V(ArmLdrsb) \
94 V(ArmStrb) \
95 V(ArmLdrh) \
96 V(ArmLdrsh) \
97 V(ArmStrh) \
98 V(ArmLdr) \
99 V(ArmStr) \
100 V(ArmPush) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]101 V(ArmPoke)
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]102
103
104// Addressing modes represent the "shape" of inputs to an instruction.
105// Many instructions support multiple addressing modes. Addressing modes
106// are encoded into the InstructionCode of the instruction and tell the
107// code generator after register allocation which assembler method to call.
108#define TARGET_ADDRESSING_MODE_LIST(V) \
109 V(Offset_RI) /* [%r0 + K] */ \
110 V(Offset_RR) /* [%r0 + %r1] */ \
111 V(Operand2_I) /* K */ \
112 V(Operand2_R) /* %r0 */ \
113 V(Operand2_R_ASR_I) /* %r0 ASR K */ \
114 V(Operand2_R_LSL_I) /* %r0 LSL K */ \
115 V(Operand2_R_LSR_I) /* %r0 LSR K */ \
116 V(Operand2_R_ROR_I) /* %r0 ROR K */ \
117 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \
118 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \
119 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \
120 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */
121
122} // namespace compiler
123} // namespace internal
124} // namespace v8
125
126#endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_