| Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1 | // Copyright 2014 the V8 project authors. All rights reserved. |
| 2 | // Use of this source code is governed by a BSD-style license that can be |
| 3 | // found in the LICENSE file. |
| 4 | |
| 5 | #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ |
| 6 | #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ |
| 7 | |
| 8 | namespace v8 { |
| 9 | namespace internal { |
| 10 | namespace compiler { |
| 11 | |
| 12 | // ARM-specific opcodes that specify which assembly sequence to emit. |
| 13 | // Most opcodes specify a single instruction. |
| 14 | #define TARGET_ARCH_OPCODE_LIST(V) \ |
| 15 | V(ArmAdd) \ |
| 16 | V(ArmAnd) \ |
| 17 | V(ArmBic) \ |
| 18 | V(ArmCmp) \ |
| 19 | V(ArmCmn) \ |
| 20 | V(ArmTst) \ |
| 21 | V(ArmTeq) \ |
| 22 | V(ArmOrr) \ |
| 23 | V(ArmEor) \ |
| 24 | V(ArmSub) \ |
| 25 | V(ArmRsb) \ |
| 26 | V(ArmMul) \ |
| 27 | V(ArmMla) \ |
| 28 | V(ArmMls) \ |
| Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame^] | 29 | V(ArmSmmul) \ |
| 30 | V(ArmSmmla) \ |
| 31 | V(ArmUmull) \ |
| Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 32 | V(ArmSdiv) \ |
| 33 | V(ArmUdiv) \ |
| 34 | V(ArmMov) \ |
| 35 | V(ArmMvn) \ |
| 36 | V(ArmBfc) \ |
| 37 | V(ArmUbfx) \ |
| Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame^] | 38 | V(ArmSxtb) \ |
| 39 | V(ArmSxth) \ |
| 40 | V(ArmSxtab) \ |
| 41 | V(ArmSxtah) \ |
| 42 | V(ArmUxtb) \ |
| 43 | V(ArmUxth) \ |
| 44 | V(ArmUxtab) \ |
| 45 | V(ArmUxtah) \ |
| Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 46 | V(ArmVcmpF64) \ |
| 47 | V(ArmVaddF64) \ |
| 48 | V(ArmVsubF64) \ |
| 49 | V(ArmVmulF64) \ |
| 50 | V(ArmVmlaF64) \ |
| 51 | V(ArmVmlsF64) \ |
| 52 | V(ArmVdivF64) \ |
| 53 | V(ArmVmodF64) \ |
| 54 | V(ArmVnegF64) \ |
| 55 | V(ArmVsqrtF64) \ |
| Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame^] | 56 | V(ArmVfloorF64) \ |
| 57 | V(ArmVceilF64) \ |
| 58 | V(ArmVroundTruncateF64) \ |
| 59 | V(ArmVroundTiesAwayF64) \ |
| 60 | V(ArmVcvtF32F64) \ |
| 61 | V(ArmVcvtF64F32) \ |
| Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 62 | V(ArmVcvtF64S32) \ |
| 63 | V(ArmVcvtF64U32) \ |
| 64 | V(ArmVcvtS32F64) \ |
| 65 | V(ArmVcvtU32F64) \ |
| Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame^] | 66 | V(ArmVldrF32) \ |
| 67 | V(ArmVstrF32) \ |
| 68 | V(ArmVldrF64) \ |
| 69 | V(ArmVstrF64) \ |
| Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 70 | V(ArmLdrb) \ |
| 71 | V(ArmLdrsb) \ |
| 72 | V(ArmStrb) \ |
| 73 | V(ArmLdrh) \ |
| 74 | V(ArmLdrsh) \ |
| 75 | V(ArmStrh) \ |
| 76 | V(ArmLdr) \ |
| 77 | V(ArmStr) \ |
| 78 | V(ArmPush) \ |
| 79 | V(ArmStoreWriteBarrier) |
| 80 | |
| 81 | |
| 82 | // Addressing modes represent the "shape" of inputs to an instruction. |
| 83 | // Many instructions support multiple addressing modes. Addressing modes |
| 84 | // are encoded into the InstructionCode of the instruction and tell the |
| 85 | // code generator after register allocation which assembler method to call. |
| 86 | #define TARGET_ADDRESSING_MODE_LIST(V) \ |
| 87 | V(Offset_RI) /* [%r0 + K] */ \ |
| 88 | V(Offset_RR) /* [%r0 + %r1] */ \ |
| 89 | V(Operand2_I) /* K */ \ |
| 90 | V(Operand2_R) /* %r0 */ \ |
| 91 | V(Operand2_R_ASR_I) /* %r0 ASR K */ \ |
| 92 | V(Operand2_R_LSL_I) /* %r0 LSL K */ \ |
| 93 | V(Operand2_R_LSR_I) /* %r0 LSR K */ \ |
| 94 | V(Operand2_R_ROR_I) /* %r0 ROR K */ \ |
| 95 | V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \ |
| 96 | V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \ |
| 97 | V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \ |
| 98 | V(Operand2_R_ROR_R) /* %r0 ROR %r1 */ |
| 99 | |
| 100 | } // namespace compiler |
| 101 | } // namespace internal |
| 102 | } // namespace v8 |
| 103 | |
| 104 | #endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ |