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gerrit-public.fairphone.software / fp2-dev / platform / external / v8 / 4a90d5fbbb6802c59093b866f3478a814bf02b95 / . / src / compiler / mips / instruction-codes-mips.h
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Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]1// Copyright 2014 the V8 project authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5#ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
6#define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
7
8namespace v8 {
9namespace internal {
10namespace compiler {
11
12// MIPS-specific opcodes that specify which assembly sequence to emit.
13// Most opcodes specify a single instruction.
14#define TARGET_ARCH_OPCODE_LIST(V) \
15 V(MipsAdd) \
16 V(MipsAddOvf) \
17 V(MipsSub) \
18 V(MipsSubOvf) \
19 V(MipsMul) \
20 V(MipsMulHigh) \
21 V(MipsMulHighU) \
22 V(MipsDiv) \
23 V(MipsDivU) \
24 V(MipsMod) \
25 V(MipsModU) \
26 V(MipsAnd) \
27 V(MipsOr) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame^]28 V(MipsNor) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]29 V(MipsXor) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame^]30 V(MipsClz) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]31 V(MipsShl) \
32 V(MipsShr) \
33 V(MipsSar) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame^]34 V(MipsExt) \
35 V(MipsIns) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]36 V(MipsRor) \
37 V(MipsMov) \
38 V(MipsTst) \
39 V(MipsCmp) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame^]40 V(MipsCmpS) \
41 V(MipsAddS) \
42 V(MipsSubS) \
43 V(MipsMulS) \
44 V(MipsDivS) \
45 V(MipsModS) \
46 V(MipsAbsS) \
47 V(MipsSqrtS) \
48 V(MipsMaxS) \
49 V(MipsMinS) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]50 V(MipsCmpD) \
51 V(MipsAddD) \
52 V(MipsSubD) \
53 V(MipsMulD) \
54 V(MipsDivD) \
55 V(MipsModD) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame^]56 V(MipsAbsD) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]57 V(MipsSqrtD) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame^]58 V(MipsMaxD) \
59 V(MipsMinD) \
60 V(MipsFloat32RoundDown) \
61 V(MipsFloat32RoundTruncate) \
62 V(MipsFloat32RoundUp) \
63 V(MipsFloat32RoundTiesEven) \
64 V(MipsFloat64RoundDown) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]65 V(MipsFloat64RoundTruncate) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame^]66 V(MipsFloat64RoundUp) \
67 V(MipsFloat64RoundTiesEven) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]68 V(MipsCvtSD) \
69 V(MipsCvtDS) \
70 V(MipsTruncWD) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame^]71 V(MipsRoundWD) \
72 V(MipsFloorWD) \
73 V(MipsCeilWD) \
74 V(MipsTruncWS) \
75 V(MipsRoundWS) \
76 V(MipsFloorWS) \
77 V(MipsCeilWS) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]78 V(MipsTruncUwD) \
79 V(MipsCvtDW) \
80 V(MipsCvtDUw) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame^]81 V(MipsCvtSW) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]82 V(MipsLb) \
83 V(MipsLbu) \
84 V(MipsSb) \
85 V(MipsLh) \
86 V(MipsLhu) \
87 V(MipsSh) \
88 V(MipsLw) \
89 V(MipsSw) \
90 V(MipsLwc1) \
91 V(MipsSwc1) \
92 V(MipsLdc1) \
93 V(MipsSdc1) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame^]94 V(MipsFloat64ExtractLowWord32) \
95 V(MipsFloat64ExtractHighWord32) \
96 V(MipsFloat64InsertLowWord32) \
97 V(MipsFloat64InsertHighWord32) \
98 V(MipsFloat64Max) \
99 V(MipsFloat64Min) \
100 V(MipsFloat32Max) \
101 V(MipsFloat32Min) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]102 V(MipsPush) \
103 V(MipsStoreToStackSlot) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame^]104 V(MipsStackClaim)
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]105
106
107// Addressing modes represent the "shape" of inputs to an instruction.
108// Many instructions support multiple addressing modes. Addressing modes
109// are encoded into the InstructionCode of the instruction and tell the
110// code generator after register allocation which assembler method to call.
111//
112// We use the following local notation for addressing modes:
113//
114// R = register
115// O = register or stack slot
116// D = double register
117// I = immediate (handle, external, int32)
118// MRI = [register + immediate]
119// MRR = [register + register]
120// TODO(plind): Add the new r6 address modes.
121#define TARGET_ADDRESSING_MODE_LIST(V) \
122 V(MRI) /* [%r0 + K] */ \
123 V(MRR) /* [%r0 + %r1] */
124
125
126} // namespace compiler
127} // namespace internal
128} // namespace v8
129
130#endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_