Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame^] | 1 | // Copyright (c) 1994-2006 Sun Microsystems Inc. |
| 2 | // All Rights Reserved. |
| 3 | // |
| 4 | // Redistribution and use in source and binary forms, with or without |
| 5 | // modification, are permitted provided that the following conditions are |
| 6 | // met: |
| 7 | // |
| 8 | // - Redistributions of source code must retain the above copyright notice, |
| 9 | // this list of conditions and the following disclaimer. |
| 10 | // |
| 11 | // - Redistribution in binary form must reproduce the above copyright |
| 12 | // notice, this list of conditions and the following disclaimer in the |
| 13 | // documentation and/or other materials provided with the distribution. |
| 14 | // |
| 15 | // - Neither the name of Sun Microsystems or the names of contributors may |
| 16 | // be used to endorse or promote products derived from this software without |
| 17 | // specific prior written permission. |
| 18 | // |
| 19 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS |
| 20 | // IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
| 21 | // THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
| 22 | // PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 23 | // CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 24 | // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 25 | // PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
| 26 | // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
| 27 | // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
| 28 | // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 29 | // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 30 | |
| 31 | // The original source code covered by the above license above has been |
| 32 | // modified significantly by Google Inc. |
| 33 | // Copyright 2006-2009 the V8 project authors. All rights reserved. |
| 34 | |
| 35 | // A lightweight X64 Assembler. |
| 36 | |
| 37 | #ifndef V8_X64_ASSEMBLER_X64_H_ |
| 38 | #define V8_X64_ASSEMBLER_X64_H_ |
| 39 | |
| 40 | namespace v8 { |
| 41 | namespace internal { |
| 42 | |
| 43 | // Utility functions |
| 44 | |
| 45 | // Test whether a 64-bit value is in a specific range. |
| 46 | static inline bool is_uint32(int64_t x) { |
| 47 | static const int64_t kUInt32Mask = V8_INT64_C(0xffffffff); |
| 48 | return x == (x & kUInt32Mask); |
| 49 | } |
| 50 | |
| 51 | static inline bool is_int32(int64_t x) { |
| 52 | static const int64_t kMinIntValue = V8_INT64_C(-0x80000000); |
| 53 | return is_uint32(x - kMinIntValue); |
| 54 | } |
| 55 | |
| 56 | static inline bool uint_is_int32(uint64_t x) { |
| 57 | static const uint64_t kMaxIntValue = V8_UINT64_C(0x80000000); |
| 58 | return x < kMaxIntValue; |
| 59 | } |
| 60 | |
| 61 | static inline bool is_uint32(uint64_t x) { |
| 62 | static const uint64_t kMaxUIntValue = V8_UINT64_C(0x100000000); |
| 63 | return x < kMaxUIntValue; |
| 64 | } |
| 65 | |
| 66 | // CPU Registers. |
| 67 | // |
| 68 | // 1) We would prefer to use an enum, but enum values are assignment- |
| 69 | // compatible with int, which has caused code-generation bugs. |
| 70 | // |
| 71 | // 2) We would prefer to use a class instead of a struct but we don't like |
| 72 | // the register initialization to depend on the particular initialization |
| 73 | // order (which appears to be different on OS X, Linux, and Windows for the |
| 74 | // installed versions of C++ we tried). Using a struct permits C-style |
| 75 | // "initialization". Also, the Register objects cannot be const as this |
| 76 | // forces initialization stubs in MSVC, making us dependent on initialization |
| 77 | // order. |
| 78 | // |
| 79 | // 3) By not using an enum, we are possibly preventing the compiler from |
| 80 | // doing certain constant folds, which may significantly reduce the |
| 81 | // code generated for some assembly instructions (because they boil down |
| 82 | // to a few constants). If this is a problem, we could change the code |
| 83 | // such that we use an enum in optimized mode, and the struct in debug |
| 84 | // mode. This way we get the compile-time error checking in debug mode |
| 85 | // and best performance in optimized code. |
| 86 | // |
| 87 | |
| 88 | struct Register { |
| 89 | static Register toRegister(int code) { |
| 90 | Register r = { code }; |
| 91 | return r; |
| 92 | } |
| 93 | bool is_valid() const { return 0 <= code_ && code_ < 16; } |
| 94 | bool is(Register reg) const { return code_ == reg.code_; } |
| 95 | int code() const { |
| 96 | ASSERT(is_valid()); |
| 97 | return code_; |
| 98 | } |
| 99 | int bit() const { |
| 100 | return 1 << code_; |
| 101 | } |
| 102 | |
| 103 | // Return the high bit of the register code as a 0 or 1. Used often |
| 104 | // when constructing the REX prefix byte. |
| 105 | int high_bit() const { |
| 106 | return code_ >> 3; |
| 107 | } |
| 108 | // Return the 3 low bits of the register code. Used when encoding registers |
| 109 | // in modR/M, SIB, and opcode bytes. |
| 110 | int low_bits() const { |
| 111 | return code_ & 0x7; |
| 112 | } |
| 113 | |
| 114 | // (unfortunately we can't make this private in a struct when initializing |
| 115 | // by assignment.) |
| 116 | int code_; |
| 117 | }; |
| 118 | |
| 119 | extern Register rax; |
| 120 | extern Register rcx; |
| 121 | extern Register rdx; |
| 122 | extern Register rbx; |
| 123 | extern Register rsp; |
| 124 | extern Register rbp; |
| 125 | extern Register rsi; |
| 126 | extern Register rdi; |
| 127 | extern Register r8; |
| 128 | extern Register r9; |
| 129 | extern Register r10; |
| 130 | extern Register r11; |
| 131 | extern Register r12; |
| 132 | extern Register r13; |
| 133 | extern Register r14; |
| 134 | extern Register r15; |
| 135 | extern Register no_reg; |
| 136 | |
| 137 | |
| 138 | struct MMXRegister { |
| 139 | bool is_valid() const { return 0 <= code_ && code_ < 2; } |
| 140 | int code() const { |
| 141 | ASSERT(is_valid()); |
| 142 | return code_; |
| 143 | } |
| 144 | |
| 145 | int code_; |
| 146 | }; |
| 147 | |
| 148 | extern MMXRegister mm0; |
| 149 | extern MMXRegister mm1; |
| 150 | extern MMXRegister mm2; |
| 151 | extern MMXRegister mm3; |
| 152 | extern MMXRegister mm4; |
| 153 | extern MMXRegister mm5; |
| 154 | extern MMXRegister mm6; |
| 155 | extern MMXRegister mm7; |
| 156 | extern MMXRegister mm8; |
| 157 | extern MMXRegister mm9; |
| 158 | extern MMXRegister mm10; |
| 159 | extern MMXRegister mm11; |
| 160 | extern MMXRegister mm12; |
| 161 | extern MMXRegister mm13; |
| 162 | extern MMXRegister mm14; |
| 163 | extern MMXRegister mm15; |
| 164 | |
| 165 | |
| 166 | struct XMMRegister { |
| 167 | bool is_valid() const { return 0 <= code_ && code_ < 16; } |
| 168 | int code() const { |
| 169 | ASSERT(is_valid()); |
| 170 | return code_; |
| 171 | } |
| 172 | |
| 173 | // Return the high bit of the register code as a 0 or 1. Used often |
| 174 | // when constructing the REX prefix byte. |
| 175 | int high_bit() const { |
| 176 | return code_ >> 3; |
| 177 | } |
| 178 | // Return the 3 low bits of the register code. Used when encoding registers |
| 179 | // in modR/M, SIB, and opcode bytes. |
| 180 | int low_bits() const { |
| 181 | return code_ & 0x7; |
| 182 | } |
| 183 | |
| 184 | int code_; |
| 185 | }; |
| 186 | |
| 187 | extern XMMRegister xmm0; |
| 188 | extern XMMRegister xmm1; |
| 189 | extern XMMRegister xmm2; |
| 190 | extern XMMRegister xmm3; |
| 191 | extern XMMRegister xmm4; |
| 192 | extern XMMRegister xmm5; |
| 193 | extern XMMRegister xmm6; |
| 194 | extern XMMRegister xmm7; |
| 195 | extern XMMRegister xmm8; |
| 196 | extern XMMRegister xmm9; |
| 197 | extern XMMRegister xmm10; |
| 198 | extern XMMRegister xmm11; |
| 199 | extern XMMRegister xmm12; |
| 200 | extern XMMRegister xmm13; |
| 201 | extern XMMRegister xmm14; |
| 202 | extern XMMRegister xmm15; |
| 203 | |
| 204 | enum Condition { |
| 205 | // any value < 0 is considered no_condition |
| 206 | no_condition = -1, |
| 207 | |
| 208 | overflow = 0, |
| 209 | no_overflow = 1, |
| 210 | below = 2, |
| 211 | above_equal = 3, |
| 212 | equal = 4, |
| 213 | not_equal = 5, |
| 214 | below_equal = 6, |
| 215 | above = 7, |
| 216 | negative = 8, |
| 217 | positive = 9, |
| 218 | parity_even = 10, |
| 219 | parity_odd = 11, |
| 220 | less = 12, |
| 221 | greater_equal = 13, |
| 222 | less_equal = 14, |
| 223 | greater = 15, |
| 224 | |
| 225 | // aliases |
| 226 | carry = below, |
| 227 | not_carry = above_equal, |
| 228 | zero = equal, |
| 229 | not_zero = not_equal, |
| 230 | sign = negative, |
| 231 | not_sign = positive |
| 232 | }; |
| 233 | |
| 234 | |
| 235 | // Returns the equivalent of !cc. |
| 236 | // Negation of the default no_condition (-1) results in a non-default |
| 237 | // no_condition value (-2). As long as tests for no_condition check |
| 238 | // for condition < 0, this will work as expected. |
| 239 | inline Condition NegateCondition(Condition cc); |
| 240 | |
| 241 | // Corresponds to transposing the operands of a comparison. |
| 242 | inline Condition ReverseCondition(Condition cc) { |
| 243 | switch (cc) { |
| 244 | case below: |
| 245 | return above; |
| 246 | case above: |
| 247 | return below; |
| 248 | case above_equal: |
| 249 | return below_equal; |
| 250 | case below_equal: |
| 251 | return above_equal; |
| 252 | case less: |
| 253 | return greater; |
| 254 | case greater: |
| 255 | return less; |
| 256 | case greater_equal: |
| 257 | return less_equal; |
| 258 | case less_equal: |
| 259 | return greater_equal; |
| 260 | default: |
| 261 | return cc; |
| 262 | }; |
| 263 | } |
| 264 | |
| 265 | enum Hint { |
| 266 | no_hint = 0, |
| 267 | not_taken = 0x2e, |
| 268 | taken = 0x3e |
| 269 | }; |
| 270 | |
| 271 | // The result of negating a hint is as if the corresponding condition |
| 272 | // were negated by NegateCondition. That is, no_hint is mapped to |
| 273 | // itself and not_taken and taken are mapped to each other. |
| 274 | inline Hint NegateHint(Hint hint) { |
| 275 | return (hint == no_hint) |
| 276 | ? no_hint |
| 277 | : ((hint == not_taken) ? taken : not_taken); |
| 278 | } |
| 279 | |
| 280 | |
| 281 | // ----------------------------------------------------------------------------- |
| 282 | // Machine instruction Immediates |
| 283 | |
| 284 | class Immediate BASE_EMBEDDED { |
| 285 | public: |
| 286 | explicit Immediate(int32_t value) : value_(value) {} |
| 287 | inline explicit Immediate(Smi* value); |
| 288 | |
| 289 | private: |
| 290 | int32_t value_; |
| 291 | |
| 292 | friend class Assembler; |
| 293 | }; |
| 294 | |
| 295 | |
| 296 | // ----------------------------------------------------------------------------- |
| 297 | // Machine instruction Operands |
| 298 | |
| 299 | enum ScaleFactor { |
| 300 | times_1 = 0, |
| 301 | times_2 = 1, |
| 302 | times_4 = 2, |
| 303 | times_8 = 3, |
| 304 | times_int_size = times_4, |
| 305 | times_half_pointer_size = times_4, |
| 306 | times_pointer_size = times_8 |
| 307 | }; |
| 308 | |
| 309 | |
| 310 | class Operand BASE_EMBEDDED { |
| 311 | public: |
| 312 | // [base + disp/r] |
| 313 | Operand(Register base, int32_t disp); |
| 314 | |
| 315 | // [base + index*scale + disp/r] |
| 316 | Operand(Register base, |
| 317 | Register index, |
| 318 | ScaleFactor scale, |
| 319 | int32_t disp); |
| 320 | |
| 321 | // [index*scale + disp/r] |
| 322 | Operand(Register index, |
| 323 | ScaleFactor scale, |
| 324 | int32_t disp); |
| 325 | |
| 326 | private: |
| 327 | byte rex_; |
| 328 | byte buf_[10]; |
| 329 | // The number of bytes in buf_. |
| 330 | unsigned int len_; |
| 331 | RelocInfo::Mode rmode_; |
| 332 | |
| 333 | // Set the ModR/M byte without an encoded 'reg' register. The |
| 334 | // register is encoded later as part of the emit_operand operation. |
| 335 | // set_modrm can be called before or after set_sib and set_disp*. |
| 336 | inline void set_modrm(int mod, Register rm); |
| 337 | |
| 338 | // Set the SIB byte if one is needed. Sets the length to 2 rather than 1. |
| 339 | inline void set_sib(ScaleFactor scale, Register index, Register base); |
| 340 | |
| 341 | // Adds operand displacement fields (offsets added to the memory address). |
| 342 | // Needs to be called after set_sib, not before it. |
| 343 | inline void set_disp8(int disp); |
| 344 | inline void set_disp32(int disp); |
| 345 | |
| 346 | friend class Assembler; |
| 347 | }; |
| 348 | |
| 349 | |
| 350 | // CpuFeatures keeps track of which features are supported by the target CPU. |
| 351 | // Supported features must be enabled by a Scope before use. |
| 352 | // Example: |
| 353 | // if (CpuFeatures::IsSupported(SSE3)) { |
| 354 | // CpuFeatures::Scope fscope(SSE3); |
| 355 | // // Generate SSE3 floating point code. |
| 356 | // } else { |
| 357 | // // Generate standard x87 or SSE2 floating point code. |
| 358 | // } |
| 359 | class CpuFeatures : public AllStatic { |
| 360 | public: |
| 361 | // Feature flags bit positions. They are mostly based on the CPUID spec. |
| 362 | // (We assign CPUID itself to one of the currently reserved bits -- |
| 363 | // feel free to change this if needed.) |
| 364 | enum Feature { SSE3 = 32, |
| 365 | SSE2 = 26, |
| 366 | CMOV = 15, |
| 367 | RDTSC = 4, |
| 368 | CPUID = 10, |
| 369 | SAHF = 0}; |
| 370 | // Detect features of the target CPU. Set safe defaults if the serializer |
| 371 | // is enabled (snapshots must be portable). |
| 372 | static void Probe(); |
| 373 | // Check whether a feature is supported by the target CPU. |
| 374 | static bool IsSupported(Feature f) { |
| 375 | return (supported_ & (V8_UINT64_C(1) << f)) != 0; |
| 376 | } |
| 377 | // Check whether a feature is currently enabled. |
| 378 | static bool IsEnabled(Feature f) { |
| 379 | return (enabled_ & (V8_UINT64_C(1) << f)) != 0; |
| 380 | } |
| 381 | // Enable a specified feature within a scope. |
| 382 | class Scope BASE_EMBEDDED { |
| 383 | #ifdef DEBUG |
| 384 | public: |
| 385 | explicit Scope(Feature f) { |
| 386 | ASSERT(CpuFeatures::IsSupported(f)); |
| 387 | old_enabled_ = CpuFeatures::enabled_; |
| 388 | CpuFeatures::enabled_ |= (V8_UINT64_C(1) << f); |
| 389 | } |
| 390 | ~Scope() { CpuFeatures::enabled_ = old_enabled_; } |
| 391 | private: |
| 392 | uint64_t old_enabled_; |
| 393 | #else |
| 394 | public: |
| 395 | explicit Scope(Feature f) {} |
| 396 | #endif |
| 397 | }; |
| 398 | private: |
| 399 | // Safe defaults include SSE2 and CMOV for X64. It is always available, if |
| 400 | // anyone checks, but they shouldn't need to check. |
| 401 | static const uint64_t kDefaultCpuFeatures = |
| 402 | (1 << CpuFeatures::SSE2 | 1 << CpuFeatures::CMOV); |
| 403 | static uint64_t supported_; |
| 404 | static uint64_t enabled_; |
| 405 | }; |
| 406 | |
| 407 | |
| 408 | class Assembler : public Malloced { |
| 409 | private: |
| 410 | // We check before assembling an instruction that there is sufficient |
| 411 | // space to write an instruction and its relocation information. |
| 412 | // The relocation writer's position must be kGap bytes above the end of |
| 413 | // the generated instructions. This leaves enough space for the |
| 414 | // longest possible x64 instruction, 15 bytes, and the longest possible |
| 415 | // relocation information encoding, RelocInfoWriter::kMaxLength == 16. |
| 416 | // (There is a 15 byte limit on x64 instruction length that rules out some |
| 417 | // otherwise valid instructions.) |
| 418 | // This allows for a single, fast space check per instruction. |
| 419 | static const int kGap = 32; |
| 420 | |
| 421 | public: |
| 422 | // Create an assembler. Instructions and relocation information are emitted |
| 423 | // into a buffer, with the instructions starting from the beginning and the |
| 424 | // relocation information starting from the end of the buffer. See CodeDesc |
| 425 | // for a detailed comment on the layout (globals.h). |
| 426 | // |
| 427 | // If the provided buffer is NULL, the assembler allocates and grows its own |
| 428 | // buffer, and buffer_size determines the initial buffer size. The buffer is |
| 429 | // owned by the assembler and deallocated upon destruction of the assembler. |
| 430 | // |
| 431 | // If the provided buffer is not NULL, the assembler uses the provided buffer |
| 432 | // for code generation and assumes its size to be buffer_size. If the buffer |
| 433 | // is too small, a fatal error occurs. No deallocation of the buffer is done |
| 434 | // upon destruction of the assembler. |
| 435 | Assembler(void* buffer, int buffer_size); |
| 436 | ~Assembler(); |
| 437 | |
| 438 | // GetCode emits any pending (non-emitted) code and fills the descriptor |
| 439 | // desc. GetCode() is idempotent; it returns the same result if no other |
| 440 | // Assembler functions are invoked in between GetCode() calls. |
| 441 | void GetCode(CodeDesc* desc); |
| 442 | |
| 443 | // Read/Modify the code target in the branch/call instruction at pc. |
| 444 | // On the x64 architecture, the address is absolute, not relative. |
| 445 | static inline Address target_address_at(Address pc); |
| 446 | static inline void set_target_address_at(Address pc, Address target); |
| 447 | |
| 448 | // Distance between the address of the code target in the call instruction |
| 449 | // and the return address. Checked in the debug build. |
| 450 | static const int kCallTargetAddressOffset = 3 + kPointerSize; |
| 451 | // Distance between start of patched return sequence and the emitted address |
| 452 | // to jump to (movq = REX.W 0xB8+r.). |
| 453 | static const int kPatchReturnSequenceAddressOffset = 2; |
| 454 | |
| 455 | // --------------------------------------------------------------------------- |
| 456 | // Code generation |
| 457 | // |
| 458 | // Function names correspond one-to-one to x64 instruction mnemonics. |
| 459 | // Unless specified otherwise, instructions operate on 64-bit operands. |
| 460 | // |
| 461 | // If we need versions of an assembly instruction that operate on different |
| 462 | // width arguments, we add a single-letter suffix specifying the width. |
| 463 | // This is done for the following instructions: mov, cmp, inc, dec, |
| 464 | // add, sub, and test. |
| 465 | // There are no versions of these instructions without the suffix. |
| 466 | // - Instructions on 8-bit (byte) operands/registers have a trailing 'b'. |
| 467 | // - Instructions on 16-bit (word) operands/registers have a trailing 'w'. |
| 468 | // - Instructions on 32-bit (doubleword) operands/registers use 'l'. |
| 469 | // - Instructions on 64-bit (quadword) operands/registers use 'q'. |
| 470 | // |
| 471 | // Some mnemonics, such as "and", are the same as C++ keywords. |
| 472 | // Naming conflicts with C++ keywords are resolved by adding a trailing '_'. |
| 473 | |
| 474 | // Insert the smallest number of nop instructions |
| 475 | // possible to align the pc offset to a multiple |
| 476 | // of m. m must be a power of 2. |
| 477 | void Align(int m); |
| 478 | |
| 479 | // Stack |
| 480 | void pushfq(); |
| 481 | void popfq(); |
| 482 | |
| 483 | void push(Immediate value); |
| 484 | void push(Register src); |
| 485 | void push(const Operand& src); |
| 486 | void push(Label* label, RelocInfo::Mode relocation_mode); |
| 487 | |
| 488 | void pop(Register dst); |
| 489 | void pop(const Operand& dst); |
| 490 | |
| 491 | void enter(Immediate size); |
| 492 | void leave(); |
| 493 | |
| 494 | // Moves |
| 495 | void movb(Register dst, const Operand& src); |
| 496 | void movb(Register dst, Immediate imm); |
| 497 | void movb(const Operand& dst, Register src); |
| 498 | |
| 499 | void movl(Register dst, Register src); |
| 500 | void movl(Register dst, const Operand& src); |
| 501 | void movl(const Operand& dst, Register src); |
| 502 | void movl(const Operand& dst, Immediate imm); |
| 503 | // Load a 32-bit immediate value, zero-extended to 64 bits. |
| 504 | void movl(Register dst, Immediate imm32); |
| 505 | |
| 506 | // Move 64 bit register value to 64-bit memory location. |
| 507 | void movq(const Operand& dst, Register src); |
| 508 | // Move 64 bit memory location to 64-bit register value. |
| 509 | void movq(Register dst, const Operand& src); |
| 510 | void movq(Register dst, Register src); |
| 511 | // Sign extends immediate 32-bit value to 64 bits. |
| 512 | void movq(Register dst, Immediate x); |
| 513 | // Move the offset of the label location relative to the current |
| 514 | // position (after the move) to the destination. |
| 515 | void movl(const Operand& dst, Label* src); |
| 516 | |
| 517 | // Move sign extended immediate to memory location. |
| 518 | void movq(const Operand& dst, Immediate value); |
| 519 | // New x64 instructions to load a 64-bit immediate into a register. |
| 520 | // All 64-bit immediates must have a relocation mode. |
| 521 | void movq(Register dst, void* ptr, RelocInfo::Mode rmode); |
| 522 | void movq(Register dst, int64_t value, RelocInfo::Mode rmode); |
| 523 | void movq(Register dst, const char* s, RelocInfo::Mode rmode); |
| 524 | // Moves the address of the external reference into the register. |
| 525 | void movq(Register dst, ExternalReference ext); |
| 526 | void movq(Register dst, Handle<Object> handle, RelocInfo::Mode rmode); |
| 527 | |
| 528 | void movsxlq(Register dst, Register src); |
| 529 | void movsxlq(Register dst, const Operand& src); |
| 530 | void movzxbq(Register dst, const Operand& src); |
| 531 | void movzxbl(Register dst, const Operand& src); |
| 532 | void movzxwl(Register dst, const Operand& src); |
| 533 | |
| 534 | // New x64 instruction to load from an immediate 64-bit pointer into RAX. |
| 535 | void load_rax(void* ptr, RelocInfo::Mode rmode); |
| 536 | void load_rax(ExternalReference ext); |
| 537 | |
| 538 | // Conditional moves. |
| 539 | void cmovq(Condition cc, Register dst, Register src); |
| 540 | void cmovq(Condition cc, Register dst, const Operand& src); |
| 541 | void cmovl(Condition cc, Register dst, Register src); |
| 542 | void cmovl(Condition cc, Register dst, const Operand& src); |
| 543 | |
| 544 | // Exchange two registers |
| 545 | void xchg(Register dst, Register src); |
| 546 | |
| 547 | // Arithmetics |
| 548 | void addl(Register dst, Register src) { |
| 549 | if (dst.low_bits() == 4) { // Forces SIB byte. |
| 550 | arithmetic_op_32(0x01, src, dst); |
| 551 | } else { |
| 552 | arithmetic_op_32(0x03, dst, src); |
| 553 | } |
| 554 | } |
| 555 | |
| 556 | void addl(Register dst, Immediate src) { |
| 557 | immediate_arithmetic_op_32(0x0, dst, src); |
| 558 | } |
| 559 | |
| 560 | void addl(Register dst, const Operand& src) { |
| 561 | arithmetic_op_32(0x03, dst, src); |
| 562 | } |
| 563 | |
| 564 | void addl(const Operand& dst, Immediate src) { |
| 565 | immediate_arithmetic_op_32(0x0, dst, src); |
| 566 | } |
| 567 | |
| 568 | void addq(Register dst, Register src) { |
| 569 | arithmetic_op(0x03, dst, src); |
| 570 | } |
| 571 | |
| 572 | void addq(Register dst, const Operand& src) { |
| 573 | arithmetic_op(0x03, dst, src); |
| 574 | } |
| 575 | |
| 576 | void addq(const Operand& dst, Register src) { |
| 577 | arithmetic_op(0x01, src, dst); |
| 578 | } |
| 579 | |
| 580 | void addq(Register dst, Immediate src) { |
| 581 | immediate_arithmetic_op(0x0, dst, src); |
| 582 | } |
| 583 | |
| 584 | void addq(const Operand& dst, Immediate src) { |
| 585 | immediate_arithmetic_op(0x0, dst, src); |
| 586 | } |
| 587 | |
| 588 | void cmpb(Register dst, Immediate src) { |
| 589 | immediate_arithmetic_op_8(0x7, dst, src); |
| 590 | } |
| 591 | |
| 592 | void cmpb_al(Immediate src); |
| 593 | |
| 594 | void cmpb(Register dst, Register src) { |
| 595 | arithmetic_op(0x3A, dst, src); |
| 596 | } |
| 597 | |
| 598 | void cmpb(Register dst, const Operand& src) { |
| 599 | arithmetic_op(0x3A, dst, src); |
| 600 | } |
| 601 | |
| 602 | void cmpb(const Operand& dst, Register src) { |
| 603 | arithmetic_op(0x38, src, dst); |
| 604 | } |
| 605 | |
| 606 | void cmpb(const Operand& dst, Immediate src) { |
| 607 | immediate_arithmetic_op_8(0x7, dst, src); |
| 608 | } |
| 609 | |
| 610 | void cmpw(const Operand& dst, Immediate src) { |
| 611 | immediate_arithmetic_op_16(0x7, dst, src); |
| 612 | } |
| 613 | |
| 614 | void cmpw(Register dst, Immediate src) { |
| 615 | immediate_arithmetic_op_16(0x7, dst, src); |
| 616 | } |
| 617 | |
| 618 | void cmpw(Register dst, const Operand& src) { |
| 619 | arithmetic_op_16(0x3B, dst, src); |
| 620 | } |
| 621 | |
| 622 | void cmpw(Register dst, Register src) { |
| 623 | arithmetic_op_16(0x3B, dst, src); |
| 624 | } |
| 625 | |
| 626 | void cmpw(const Operand& dst, Register src) { |
| 627 | arithmetic_op_16(0x39, src, dst); |
| 628 | } |
| 629 | |
| 630 | void cmpl(Register dst, Register src) { |
| 631 | arithmetic_op_32(0x3B, dst, src); |
| 632 | } |
| 633 | |
| 634 | void cmpl(Register dst, const Operand& src) { |
| 635 | arithmetic_op_32(0x3B, dst, src); |
| 636 | } |
| 637 | |
| 638 | void cmpl(const Operand& dst, Register src) { |
| 639 | arithmetic_op_32(0x39, src, dst); |
| 640 | } |
| 641 | |
| 642 | void cmpl(Register dst, Immediate src) { |
| 643 | immediate_arithmetic_op_32(0x7, dst, src); |
| 644 | } |
| 645 | |
| 646 | void cmpl(const Operand& dst, Immediate src) { |
| 647 | immediate_arithmetic_op_32(0x7, dst, src); |
| 648 | } |
| 649 | |
| 650 | void cmpq(Register dst, Register src) { |
| 651 | arithmetic_op(0x3B, dst, src); |
| 652 | } |
| 653 | |
| 654 | void cmpq(Register dst, const Operand& src) { |
| 655 | arithmetic_op(0x3B, dst, src); |
| 656 | } |
| 657 | |
| 658 | void cmpq(const Operand& dst, Register src) { |
| 659 | arithmetic_op(0x39, src, dst); |
| 660 | } |
| 661 | |
| 662 | void cmpq(Register dst, Immediate src) { |
| 663 | immediate_arithmetic_op(0x7, dst, src); |
| 664 | } |
| 665 | |
| 666 | void cmpq(const Operand& dst, Immediate src) { |
| 667 | immediate_arithmetic_op(0x7, dst, src); |
| 668 | } |
| 669 | |
| 670 | void and_(Register dst, Register src) { |
| 671 | arithmetic_op(0x23, dst, src); |
| 672 | } |
| 673 | |
| 674 | void and_(Register dst, const Operand& src) { |
| 675 | arithmetic_op(0x23, dst, src); |
| 676 | } |
| 677 | |
| 678 | void and_(const Operand& dst, Register src) { |
| 679 | arithmetic_op(0x21, src, dst); |
| 680 | } |
| 681 | |
| 682 | void and_(Register dst, Immediate src) { |
| 683 | immediate_arithmetic_op(0x4, dst, src); |
| 684 | } |
| 685 | |
| 686 | void and_(const Operand& dst, Immediate src) { |
| 687 | immediate_arithmetic_op(0x4, dst, src); |
| 688 | } |
| 689 | |
| 690 | void andl(Register dst, Immediate src) { |
| 691 | immediate_arithmetic_op_32(0x4, dst, src); |
| 692 | } |
| 693 | |
| 694 | void decq(Register dst); |
| 695 | void decq(const Operand& dst); |
| 696 | void decl(Register dst); |
| 697 | void decl(const Operand& dst); |
| 698 | |
| 699 | // Sign-extends rax into rdx:rax. |
| 700 | void cqo(); |
| 701 | // Sign-extends eax into edx:eax. |
| 702 | void cdq(); |
| 703 | |
| 704 | // Divide rdx:rax by src. Quotient in rax, remainder in rdx. |
| 705 | void idivq(Register src); |
| 706 | // Divide edx:eax by lower 32 bits of src. Quotient in eax, rem. in edx. |
| 707 | void idivl(Register src); |
| 708 | |
| 709 | // Signed multiply instructions. |
| 710 | void imul(Register src); // rdx:rax = rax * src. |
| 711 | void imul(Register dst, Register src); // dst = dst * src. |
| 712 | void imul(Register dst, const Operand& src); // dst = dst * src. |
| 713 | void imul(Register dst, Register src, Immediate imm); // dst = src * imm. |
| 714 | // Multiply 32 bit registers |
| 715 | void imull(Register dst, Register src); // dst = dst * src. |
| 716 | |
| 717 | void incq(Register dst); |
| 718 | void incq(const Operand& dst); |
| 719 | void incl(const Operand& dst); |
| 720 | |
| 721 | void lea(Register dst, const Operand& src); |
| 722 | |
| 723 | // Multiply rax by src, put the result in rdx:rax. |
| 724 | void mul(Register src); |
| 725 | |
| 726 | void neg(Register dst); |
| 727 | void neg(const Operand& dst); |
| 728 | void negl(Register dst); |
| 729 | |
| 730 | void not_(Register dst); |
| 731 | void not_(const Operand& dst); |
| 732 | |
| 733 | void or_(Register dst, Register src) { |
| 734 | arithmetic_op(0x0B, dst, src); |
| 735 | } |
| 736 | |
| 737 | void orl(Register dst, Register src) { |
| 738 | arithmetic_op_32(0x0B, dst, src); |
| 739 | } |
| 740 | |
| 741 | void or_(Register dst, const Operand& src) { |
| 742 | arithmetic_op(0x0B, dst, src); |
| 743 | } |
| 744 | |
| 745 | void or_(const Operand& dst, Register src) { |
| 746 | arithmetic_op(0x09, src, dst); |
| 747 | } |
| 748 | |
| 749 | void or_(Register dst, Immediate src) { |
| 750 | immediate_arithmetic_op(0x1, dst, src); |
| 751 | } |
| 752 | |
| 753 | void or_(const Operand& dst, Immediate src) { |
| 754 | immediate_arithmetic_op(0x1, dst, src); |
| 755 | } |
| 756 | |
| 757 | |
| 758 | void rcl(Register dst, uint8_t imm8); |
| 759 | |
| 760 | // Shifts dst:src left by cl bits, affecting only dst. |
| 761 | void shld(Register dst, Register src); |
| 762 | |
| 763 | // Shifts src:dst right by cl bits, affecting only dst. |
| 764 | void shrd(Register dst, Register src); |
| 765 | |
| 766 | // Shifts dst right, duplicating sign bit, by shift_amount bits. |
| 767 | // Shifting by 1 is handled efficiently. |
| 768 | void sar(Register dst, Immediate shift_amount) { |
| 769 | shift(dst, shift_amount, 0x7); |
| 770 | } |
| 771 | |
| 772 | // Shifts dst right, duplicating sign bit, by shift_amount bits. |
| 773 | // Shifting by 1 is handled efficiently. |
| 774 | void sarl(Register dst, Immediate shift_amount) { |
| 775 | shift_32(dst, shift_amount, 0x7); |
| 776 | } |
| 777 | |
| 778 | // Shifts dst right, duplicating sign bit, by cl % 64 bits. |
| 779 | void sar(Register dst) { |
| 780 | shift(dst, 0x7); |
| 781 | } |
| 782 | |
| 783 | // Shifts dst right, duplicating sign bit, by cl % 64 bits. |
| 784 | void sarl(Register dst) { |
| 785 | shift_32(dst, 0x7); |
| 786 | } |
| 787 | |
| 788 | void shl(Register dst, Immediate shift_amount) { |
| 789 | shift(dst, shift_amount, 0x4); |
| 790 | } |
| 791 | |
| 792 | void shl(Register dst) { |
| 793 | shift(dst, 0x4); |
| 794 | } |
| 795 | |
| 796 | void shll(Register dst) { |
| 797 | shift_32(dst, 0x4); |
| 798 | } |
| 799 | |
| 800 | void shll(Register dst, Immediate shift_amount) { |
| 801 | shift_32(dst, shift_amount, 0x4); |
| 802 | } |
| 803 | |
| 804 | void shr(Register dst, Immediate shift_amount) { |
| 805 | shift(dst, shift_amount, 0x5); |
| 806 | } |
| 807 | |
| 808 | void shr(Register dst) { |
| 809 | shift(dst, 0x5); |
| 810 | } |
| 811 | |
| 812 | void shrl(Register dst) { |
| 813 | shift_32(dst, 0x5); |
| 814 | } |
| 815 | |
| 816 | void shrl(Register dst, Immediate shift_amount) { |
| 817 | shift_32(dst, shift_amount, 0x5); |
| 818 | } |
| 819 | |
| 820 | void store_rax(void* dst, RelocInfo::Mode mode); |
| 821 | void store_rax(ExternalReference ref); |
| 822 | |
| 823 | void subq(Register dst, Register src) { |
| 824 | arithmetic_op(0x2B, dst, src); |
| 825 | } |
| 826 | |
| 827 | void subq(Register dst, const Operand& src) { |
| 828 | arithmetic_op(0x2B, dst, src); |
| 829 | } |
| 830 | |
| 831 | void subq(const Operand& dst, Register src) { |
| 832 | arithmetic_op(0x29, src, dst); |
| 833 | } |
| 834 | |
| 835 | void subq(Register dst, Immediate src) { |
| 836 | immediate_arithmetic_op(0x5, dst, src); |
| 837 | } |
| 838 | |
| 839 | void subq(const Operand& dst, Immediate src) { |
| 840 | immediate_arithmetic_op(0x5, dst, src); |
| 841 | } |
| 842 | |
| 843 | void subl(Register dst, Register src) { |
| 844 | arithmetic_op_32(0x2B, dst, src); |
| 845 | } |
| 846 | |
| 847 | void subl(const Operand& dst, Immediate src) { |
| 848 | immediate_arithmetic_op_32(0x5, dst, src); |
| 849 | } |
| 850 | |
| 851 | void subl(Register dst, Immediate src) { |
| 852 | immediate_arithmetic_op_32(0x5, dst, src); |
| 853 | } |
| 854 | |
| 855 | void subb(Register dst, Immediate src) { |
| 856 | immediate_arithmetic_op_8(0x5, dst, src); |
| 857 | } |
| 858 | |
| 859 | void testb(Register reg, Immediate mask); |
| 860 | void testb(const Operand& op, Immediate mask); |
| 861 | void testl(Register dst, Register src); |
| 862 | void testl(Register reg, Immediate mask); |
| 863 | void testl(const Operand& op, Immediate mask); |
| 864 | void testq(const Operand& op, Register reg); |
| 865 | void testq(Register dst, Register src); |
| 866 | void testq(Register dst, Immediate mask); |
| 867 | |
| 868 | void xor_(Register dst, Register src) { |
| 869 | arithmetic_op(0x33, dst, src); |
| 870 | } |
| 871 | |
| 872 | void xorl(Register dst, Register src) { |
| 873 | arithmetic_op_32(0x33, dst, src); |
| 874 | } |
| 875 | |
| 876 | void xor_(Register dst, const Operand& src) { |
| 877 | arithmetic_op(0x33, dst, src); |
| 878 | } |
| 879 | |
| 880 | void xor_(const Operand& dst, Register src) { |
| 881 | arithmetic_op(0x31, src, dst); |
| 882 | } |
| 883 | |
| 884 | void xor_(Register dst, Immediate src) { |
| 885 | immediate_arithmetic_op(0x6, dst, src); |
| 886 | } |
| 887 | |
| 888 | void xor_(const Operand& dst, Immediate src) { |
| 889 | immediate_arithmetic_op(0x6, dst, src); |
| 890 | } |
| 891 | |
| 892 | // Bit operations. |
| 893 | void bt(const Operand& dst, Register src); |
| 894 | void bts(const Operand& dst, Register src); |
| 895 | |
| 896 | // Miscellaneous |
| 897 | void cpuid(); |
| 898 | void hlt(); |
| 899 | void int3(); |
| 900 | void nop(); |
| 901 | void nop(int n); |
| 902 | void rdtsc(); |
| 903 | void ret(int imm16); |
| 904 | void setcc(Condition cc, Register reg); |
| 905 | |
| 906 | // Label operations & relative jumps (PPUM Appendix D) |
| 907 | // |
| 908 | // Takes a branch opcode (cc) and a label (L) and generates |
| 909 | // either a backward branch or a forward branch and links it |
| 910 | // to the label fixup chain. Usage: |
| 911 | // |
| 912 | // Label L; // unbound label |
| 913 | // j(cc, &L); // forward branch to unbound label |
| 914 | // bind(&L); // bind label to the current pc |
| 915 | // j(cc, &L); // backward branch to bound label |
| 916 | // bind(&L); // illegal: a label may be bound only once |
| 917 | // |
| 918 | // Note: The same Label can be used for forward and backward branches |
| 919 | // but it may be bound only once. |
| 920 | |
| 921 | void bind(Label* L); // binds an unbound label L to the current code position |
| 922 | |
| 923 | // Calls |
| 924 | // Call near relative 32-bit displacement, relative to next instruction. |
| 925 | void call(Label* L); |
| 926 | |
| 927 | // Call near absolute indirect, address in register |
| 928 | void call(Register adr); |
| 929 | |
| 930 | // Call near indirect |
| 931 | void call(const Operand& operand); |
| 932 | |
| 933 | // Jumps |
| 934 | // Jump short or near relative. |
| 935 | void jmp(Label* L); // unconditional jump to L |
| 936 | |
| 937 | // Jump near absolute indirect (r64) |
| 938 | void jmp(Register adr); |
| 939 | |
| 940 | // Jump near absolute indirect (m64) |
| 941 | void jmp(const Operand& src); |
| 942 | |
| 943 | // Conditional jumps |
| 944 | void j(Condition cc, Label* L); |
| 945 | |
| 946 | // Floating-point operations |
| 947 | void fld(int i); |
| 948 | |
| 949 | void fld1(); |
| 950 | void fldz(); |
| 951 | |
| 952 | void fld_s(const Operand& adr); |
| 953 | void fld_d(const Operand& adr); |
| 954 | |
| 955 | void fstp_s(const Operand& adr); |
| 956 | void fstp_d(const Operand& adr); |
| 957 | |
| 958 | void fild_s(const Operand& adr); |
| 959 | void fild_d(const Operand& adr); |
| 960 | |
| 961 | void fist_s(const Operand& adr); |
| 962 | |
| 963 | void fistp_s(const Operand& adr); |
| 964 | void fistp_d(const Operand& adr); |
| 965 | |
| 966 | void fisttp_s(const Operand& adr); |
| 967 | |
| 968 | void fabs(); |
| 969 | void fchs(); |
| 970 | |
| 971 | void fadd(int i); |
| 972 | void fsub(int i); |
| 973 | void fmul(int i); |
| 974 | void fdiv(int i); |
| 975 | |
| 976 | void fisub_s(const Operand& adr); |
| 977 | |
| 978 | void faddp(int i = 1); |
| 979 | void fsubp(int i = 1); |
| 980 | void fsubrp(int i = 1); |
| 981 | void fmulp(int i = 1); |
| 982 | void fdivp(int i = 1); |
| 983 | void fprem(); |
| 984 | void fprem1(); |
| 985 | |
| 986 | void fxch(int i = 1); |
| 987 | void fincstp(); |
| 988 | void ffree(int i = 0); |
| 989 | |
| 990 | void ftst(); |
| 991 | void fucomp(int i); |
| 992 | void fucompp(); |
| 993 | void fcompp(); |
| 994 | void fnstsw_ax(); |
| 995 | void fwait(); |
| 996 | void fnclex(); |
| 997 | |
| 998 | void fsin(); |
| 999 | void fcos(); |
| 1000 | |
| 1001 | void frndint(); |
| 1002 | |
| 1003 | void sahf(); |
| 1004 | |
| 1005 | // SSE2 instructions |
| 1006 | void movsd(const Operand& dst, XMMRegister src); |
| 1007 | void movsd(Register src, XMMRegister dst); |
| 1008 | void movsd(XMMRegister dst, Register src); |
| 1009 | void movsd(XMMRegister src, const Operand& dst); |
| 1010 | |
| 1011 | void cvttss2si(Register dst, const Operand& src); |
| 1012 | void cvttsd2si(Register dst, const Operand& src); |
| 1013 | |
| 1014 | void cvtlsi2sd(XMMRegister dst, const Operand& src); |
| 1015 | void cvtlsi2sd(XMMRegister dst, Register src); |
| 1016 | void cvtqsi2sd(XMMRegister dst, const Operand& src); |
| 1017 | void cvtqsi2sd(XMMRegister dst, Register src); |
| 1018 | |
| 1019 | void addsd(XMMRegister dst, XMMRegister src); |
| 1020 | void subsd(XMMRegister dst, XMMRegister src); |
| 1021 | void mulsd(XMMRegister dst, XMMRegister src); |
| 1022 | void divsd(XMMRegister dst, XMMRegister src); |
| 1023 | |
| 1024 | |
| 1025 | void emit_sse_operand(XMMRegister dst, XMMRegister src); |
| 1026 | void emit_sse_operand(XMMRegister reg, const Operand& adr); |
| 1027 | void emit_sse_operand(XMMRegister dst, Register src); |
| 1028 | |
| 1029 | // Use either movsd or movlpd. |
| 1030 | // void movdbl(XMMRegister dst, const Operand& src); |
| 1031 | // void movdbl(const Operand& dst, XMMRegister src); |
| 1032 | |
| 1033 | // Debugging |
| 1034 | void Print(); |
| 1035 | |
| 1036 | // Check the code size generated from label to here. |
| 1037 | int SizeOfCodeGeneratedSince(Label* l) { return pc_offset() - l->pos(); } |
| 1038 | |
| 1039 | // Mark address of the ExitJSFrame code. |
| 1040 | void RecordJSReturn(); |
| 1041 | |
| 1042 | // Record a comment relocation entry that can be used by a disassembler. |
| 1043 | // Use --debug_code to enable. |
| 1044 | void RecordComment(const char* msg); |
| 1045 | |
| 1046 | void RecordPosition(int pos); |
| 1047 | void RecordStatementPosition(int pos); |
| 1048 | void WriteRecordedPositions(); |
| 1049 | |
| 1050 | // Writes a doubleword of data in the code stream. |
| 1051 | // Used for inline tables, e.g., jump-tables. |
| 1052 | // void dd(uint32_t data); |
| 1053 | |
| 1054 | // Writes a quadword of data in the code stream. |
| 1055 | // Used for inline tables, e.g., jump-tables. |
| 1056 | // void dd(uint64_t data, RelocInfo::Mode reloc_info); |
| 1057 | |
| 1058 | int pc_offset() const { return pc_ - buffer_; } |
| 1059 | int current_statement_position() const { return current_statement_position_; } |
| 1060 | int current_position() const { return current_position_; } |
| 1061 | |
| 1062 | // Check if there is less than kGap bytes available in the buffer. |
| 1063 | // If this is the case, we need to grow the buffer before emitting |
| 1064 | // an instruction or relocation information. |
| 1065 | inline bool buffer_overflow() const { |
| 1066 | return pc_ >= reloc_info_writer.pos() - kGap; |
| 1067 | } |
| 1068 | |
| 1069 | // Get the number of bytes available in the buffer. |
| 1070 | inline int available_space() const { return reloc_info_writer.pos() - pc_; } |
| 1071 | |
| 1072 | // Avoid overflows for displacements etc. |
| 1073 | static const int kMaximalBufferSize = 512*MB; |
| 1074 | static const int kMinimalBufferSize = 4*KB; |
| 1075 | |
| 1076 | protected: |
| 1077 | // void movsd(XMMRegister dst, const Operand& src); |
| 1078 | // void movsd(const Operand& dst, XMMRegister src); |
| 1079 | |
| 1080 | // void emit_sse_operand(XMMRegister reg, const Operand& adr); |
| 1081 | // void emit_sse_operand(XMMRegister dst, XMMRegister src); |
| 1082 | |
| 1083 | |
| 1084 | private: |
| 1085 | byte* addr_at(int pos) { return buffer_ + pos; } |
| 1086 | byte byte_at(int pos) { return buffer_[pos]; } |
| 1087 | uint32_t long_at(int pos) { |
| 1088 | return *reinterpret_cast<uint32_t*>(addr_at(pos)); |
| 1089 | } |
| 1090 | void long_at_put(int pos, uint32_t x) { |
| 1091 | *reinterpret_cast<uint32_t*>(addr_at(pos)) = x; |
| 1092 | } |
| 1093 | |
| 1094 | // code emission |
| 1095 | void GrowBuffer(); |
| 1096 | |
| 1097 | void emit(byte x) { *pc_++ = x; } |
| 1098 | inline void emitl(uint32_t x); |
| 1099 | inline void emit(Handle<Object> handle); |
| 1100 | inline void emitq(uint64_t x, RelocInfo::Mode rmode); |
| 1101 | inline void emitw(uint16_t x); |
| 1102 | void emit(Immediate x) { emitl(x.value_); } |
| 1103 | |
| 1104 | // Emits a REX prefix that encodes a 64-bit operand size and |
| 1105 | // the top bit of both register codes. |
| 1106 | // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B. |
| 1107 | // REX.W is set. |
| 1108 | inline void emit_rex_64(Register reg, Register rm_reg); |
| 1109 | inline void emit_rex_64(XMMRegister reg, Register rm_reg); |
| 1110 | |
| 1111 | // Emits a REX prefix that encodes a 64-bit operand size and |
| 1112 | // the top bit of the destination, index, and base register codes. |
| 1113 | // The high bit of reg is used for REX.R, the high bit of op's base |
| 1114 | // register is used for REX.B, and the high bit of op's index register |
| 1115 | // is used for REX.X. REX.W is set. |
| 1116 | inline void emit_rex_64(Register reg, const Operand& op); |
| 1117 | inline void emit_rex_64(XMMRegister reg, const Operand& op); |
| 1118 | |
| 1119 | // Emits a REX prefix that encodes a 64-bit operand size and |
| 1120 | // the top bit of the register code. |
| 1121 | // The high bit of register is used for REX.B. |
| 1122 | // REX.W is set and REX.R and REX.X are clear. |
| 1123 | inline void emit_rex_64(Register rm_reg); |
| 1124 | |
| 1125 | // Emits a REX prefix that encodes a 64-bit operand size and |
| 1126 | // the top bit of the index and base register codes. |
| 1127 | // The high bit of op's base register is used for REX.B, and the high |
| 1128 | // bit of op's index register is used for REX.X. |
| 1129 | // REX.W is set and REX.R clear. |
| 1130 | inline void emit_rex_64(const Operand& op); |
| 1131 | |
| 1132 | // Emit a REX prefix that only sets REX.W to choose a 64-bit operand size. |
| 1133 | void emit_rex_64() { emit(0x48); } |
| 1134 | |
| 1135 | // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B. |
| 1136 | // REX.W is clear. |
| 1137 | inline void emit_rex_32(Register reg, Register rm_reg); |
| 1138 | |
| 1139 | // The high bit of reg is used for REX.R, the high bit of op's base |
| 1140 | // register is used for REX.B, and the high bit of op's index register |
| 1141 | // is used for REX.X. REX.W is cleared. |
| 1142 | inline void emit_rex_32(Register reg, const Operand& op); |
| 1143 | |
| 1144 | // High bit of rm_reg goes to REX.B. |
| 1145 | // REX.W, REX.R and REX.X are clear. |
| 1146 | inline void emit_rex_32(Register rm_reg); |
| 1147 | |
| 1148 | // High bit of base goes to REX.B and high bit of index to REX.X. |
| 1149 | // REX.W and REX.R are clear. |
| 1150 | inline void emit_rex_32(const Operand& op); |
| 1151 | |
| 1152 | // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B. |
| 1153 | // REX.W is cleared. If no REX bits are set, no byte is emitted. |
| 1154 | inline void emit_optional_rex_32(Register reg, Register rm_reg); |
| 1155 | |
| 1156 | // The high bit of reg is used for REX.R, the high bit of op's base |
| 1157 | // register is used for REX.B, and the high bit of op's index register |
| 1158 | // is used for REX.X. REX.W is cleared. If no REX bits are set, nothing |
| 1159 | // is emitted. |
| 1160 | inline void emit_optional_rex_32(Register reg, const Operand& op); |
| 1161 | |
| 1162 | // As for emit_optional_rex_32(Register, Register), except that |
| 1163 | // the registers are XMM registers. |
| 1164 | inline void emit_optional_rex_32(XMMRegister reg, XMMRegister base); |
| 1165 | |
| 1166 | // As for emit_optional_rex_32(Register, Register), except that |
| 1167 | // the registers are XMM registers. |
| 1168 | inline void emit_optional_rex_32(XMMRegister reg, Register base); |
| 1169 | |
| 1170 | // As for emit_optional_rex_32(Register, const Operand&), except that |
| 1171 | // the register is an XMM register. |
| 1172 | inline void emit_optional_rex_32(XMMRegister reg, const Operand& op); |
| 1173 | |
| 1174 | // Optionally do as emit_rex_32(Register) if the register number has |
| 1175 | // the high bit set. |
| 1176 | inline void emit_optional_rex_32(Register rm_reg); |
| 1177 | |
| 1178 | // Optionally do as emit_rex_32(const Operand&) if the operand register |
| 1179 | // numbers have a high bit set. |
| 1180 | inline void emit_optional_rex_32(const Operand& op); |
| 1181 | |
| 1182 | |
| 1183 | // Emit the ModR/M byte, and optionally the SIB byte and |
| 1184 | // 1- or 4-byte offset for a memory operand. Also encodes |
| 1185 | // the second operand of the operation, a register or operation |
| 1186 | // subcode, into the reg field of the ModR/M byte. |
| 1187 | void emit_operand(Register reg, const Operand& adr) { |
| 1188 | emit_operand(reg.low_bits(), adr); |
| 1189 | } |
| 1190 | |
| 1191 | // Emit the ModR/M byte, and optionally the SIB byte and |
| 1192 | // 1- or 4-byte offset for a memory operand. Also used to encode |
| 1193 | // a three-bit opcode extension into the ModR/M byte. |
| 1194 | void emit_operand(int rm, const Operand& adr); |
| 1195 | |
| 1196 | // Emit a ModR/M byte with registers coded in the reg and rm_reg fields. |
| 1197 | void emit_modrm(Register reg, Register rm_reg) { |
| 1198 | emit(0xC0 | reg.low_bits() << 3 | rm_reg.low_bits()); |
| 1199 | } |
| 1200 | |
| 1201 | // Emit a ModR/M byte with an operation subcode in the reg field and |
| 1202 | // a register in the rm_reg field. |
| 1203 | void emit_modrm(int code, Register rm_reg) { |
| 1204 | ASSERT(is_uint3(code)); |
| 1205 | emit(0xC0 | code << 3 | rm_reg.low_bits()); |
| 1206 | } |
| 1207 | |
| 1208 | // Emit the code-object-relative offset of the label's position |
| 1209 | inline void emit_code_relative_offset(Label* label); |
| 1210 | |
| 1211 | // Emit machine code for one of the operations ADD, ADC, SUB, SBC, |
| 1212 | // AND, OR, XOR, or CMP. The encodings of these operations are all |
| 1213 | // similar, differing just in the opcode or in the reg field of the |
| 1214 | // ModR/M byte. |
| 1215 | void arithmetic_op_16(byte opcode, Register reg, Register rm_reg); |
| 1216 | void arithmetic_op_16(byte opcode, Register reg, const Operand& rm_reg); |
| 1217 | void arithmetic_op_32(byte opcode, Register reg, Register rm_reg); |
| 1218 | void arithmetic_op_32(byte opcode, Register reg, const Operand& rm_reg); |
| 1219 | void arithmetic_op(byte opcode, Register reg, Register rm_reg); |
| 1220 | void arithmetic_op(byte opcode, Register reg, const Operand& rm_reg); |
| 1221 | void immediate_arithmetic_op(byte subcode, Register dst, Immediate src); |
| 1222 | void immediate_arithmetic_op(byte subcode, const Operand& dst, Immediate src); |
| 1223 | // Operate on a byte in memory or register. |
| 1224 | void immediate_arithmetic_op_8(byte subcode, |
| 1225 | Register dst, |
| 1226 | Immediate src); |
| 1227 | void immediate_arithmetic_op_8(byte subcode, |
| 1228 | const Operand& dst, |
| 1229 | Immediate src); |
| 1230 | // Operate on a word in memory or register. |
| 1231 | void immediate_arithmetic_op_16(byte subcode, |
| 1232 | Register dst, |
| 1233 | Immediate src); |
| 1234 | void immediate_arithmetic_op_16(byte subcode, |
| 1235 | const Operand& dst, |
| 1236 | Immediate src); |
| 1237 | // Operate on a 32-bit word in memory or register. |
| 1238 | void immediate_arithmetic_op_32(byte subcode, |
| 1239 | Register dst, |
| 1240 | Immediate src); |
| 1241 | void immediate_arithmetic_op_32(byte subcode, |
| 1242 | const Operand& dst, |
| 1243 | Immediate src); |
| 1244 | |
| 1245 | // Emit machine code for a shift operation. |
| 1246 | void shift(Register dst, Immediate shift_amount, int subcode); |
| 1247 | void shift_32(Register dst, Immediate shift_amount, int subcode); |
| 1248 | // Shift dst by cl % 64 bits. |
| 1249 | void shift(Register dst, int subcode); |
| 1250 | void shift_32(Register dst, int subcode); |
| 1251 | |
| 1252 | void emit_farith(int b1, int b2, int i); |
| 1253 | |
| 1254 | // labels |
| 1255 | // void print(Label* L); |
| 1256 | void bind_to(Label* L, int pos); |
| 1257 | void link_to(Label* L, Label* appendix); |
| 1258 | |
| 1259 | // record reloc info for current pc_ |
| 1260 | void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0); |
| 1261 | |
| 1262 | friend class CodePatcher; |
| 1263 | friend class EnsureSpace; |
| 1264 | friend class RegExpMacroAssemblerX64; |
| 1265 | |
| 1266 | // Code buffer: |
| 1267 | // The buffer into which code and relocation info are generated. |
| 1268 | byte* buffer_; |
| 1269 | int buffer_size_; |
| 1270 | // True if the assembler owns the buffer, false if buffer is external. |
| 1271 | bool own_buffer_; |
| 1272 | // A previously allocated buffer of kMinimalBufferSize bytes, or NULL. |
| 1273 | static byte* spare_buffer_; |
| 1274 | |
| 1275 | // code generation |
| 1276 | byte* pc_; // the program counter; moves forward |
| 1277 | RelocInfoWriter reloc_info_writer; |
| 1278 | |
| 1279 | // push-pop elimination |
| 1280 | byte* last_pc_; |
| 1281 | |
| 1282 | // source position information |
| 1283 | int current_statement_position_; |
| 1284 | int current_position_; |
| 1285 | int written_statement_position_; |
| 1286 | int written_position_; |
| 1287 | }; |
| 1288 | |
| 1289 | |
| 1290 | // Helper class that ensures that there is enough space for generating |
| 1291 | // instructions and relocation information. The constructor makes |
| 1292 | // sure that there is enough space and (in debug mode) the destructor |
| 1293 | // checks that we did not generate too much. |
| 1294 | class EnsureSpace BASE_EMBEDDED { |
| 1295 | public: |
| 1296 | explicit EnsureSpace(Assembler* assembler) : assembler_(assembler) { |
| 1297 | if (assembler_->buffer_overflow()) assembler_->GrowBuffer(); |
| 1298 | #ifdef DEBUG |
| 1299 | space_before_ = assembler_->available_space(); |
| 1300 | #endif |
| 1301 | } |
| 1302 | |
| 1303 | #ifdef DEBUG |
| 1304 | ~EnsureSpace() { |
| 1305 | int bytes_generated = space_before_ - assembler_->available_space(); |
| 1306 | ASSERT(bytes_generated < assembler_->kGap); |
| 1307 | } |
| 1308 | #endif |
| 1309 | |
| 1310 | private: |
| 1311 | Assembler* assembler_; |
| 1312 | #ifdef DEBUG |
| 1313 | int space_before_; |
| 1314 | #endif |
| 1315 | }; |
| 1316 | |
| 1317 | } } // namespace v8::internal |
| 1318 | |
| 1319 | #endif // V8_X64_ASSEMBLER_X64_H_ |