Ben Murdoch | b0fe162 | 2011-05-05 13:52:32 +0100 | [diff] [blame^] | 1 | // Copyright 2010 the V8 project authors. All rights reserved. |
| 2 | // Redistribution and use in source and binary forms, with or without |
| 3 | // modification, are permitted provided that the following conditions are |
| 4 | // met: |
| 5 | // |
| 6 | // * Redistributions of source code must retain the above copyright |
| 7 | // notice, this list of conditions and the following disclaimer. |
| 8 | // * Redistributions in binary form must reproduce the above |
| 9 | // copyright notice, this list of conditions and the following |
| 10 | // disclaimer in the documentation and/or other materials provided |
| 11 | // with the distribution. |
| 12 | // * Neither the name of Google Inc. nor the names of its |
| 13 | // contributors may be used to endorse or promote products derived |
| 14 | // from this software without specific prior written permission. |
| 15 | // |
| 16 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 17 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 18 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 19 | // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 20 | // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 21 | // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 22 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 23 | // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 24 | // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 25 | // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 26 | // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | |
| 28 | // This module gets enough CPU information to optimize the |
| 29 | // atomicops module on x86. |
| 30 | |
| 31 | #include <string.h> |
| 32 | |
| 33 | #include "atomicops.h" |
| 34 | |
| 35 | // This file only makes sense with atomicops_internals_x86_gcc.h -- it |
| 36 | // depends on structs that are defined in that file. If atomicops.h |
| 37 | // doesn't sub-include that file, then we aren't needed, and shouldn't |
| 38 | // try to do anything. |
| 39 | #ifdef V8_ATOMICOPS_INTERNALS_X86_GCC_H_ |
| 40 | |
| 41 | // Inline cpuid instruction. In PIC compilations, %ebx contains the address |
| 42 | // of the global offset table. To avoid breaking such executables, this code |
| 43 | // must preserve that register's value across cpuid instructions. |
| 44 | #if defined(__i386__) |
| 45 | #define cpuid(a, b, c, d, inp) \ |
| 46 | asm("mov %%ebx, %%edi\n" \ |
| 47 | "cpuid\n" \ |
| 48 | "xchg %%edi, %%ebx\n" \ |
| 49 | : "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp)) |
| 50 | #elif defined(__x86_64__) |
| 51 | #define cpuid(a, b, c, d, inp) \ |
| 52 | asm("mov %%rbx, %%rdi\n" \ |
| 53 | "cpuid\n" \ |
| 54 | "xchg %%rdi, %%rbx\n" \ |
| 55 | : "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp)) |
| 56 | #endif |
| 57 | |
| 58 | #if defined(cpuid) // initialize the struct only on x86 |
| 59 | |
| 60 | // Set the flags so that code will run correctly and conservatively, so even |
| 61 | // if we haven't been initialized yet, we're probably single threaded, and our |
| 62 | // default values should hopefully be pretty safe. |
| 63 | struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures = { |
| 64 | false, // bug can't exist before process spawns multiple threads |
| 65 | false, // no SSE2 |
| 66 | }; |
| 67 | |
| 68 | // Initialize the AtomicOps_Internalx86CPUFeatures struct. |
| 69 | static void AtomicOps_Internalx86CPUFeaturesInit() { |
| 70 | uint32_t eax; |
| 71 | uint32_t ebx; |
| 72 | uint32_t ecx; |
| 73 | uint32_t edx; |
| 74 | |
| 75 | // Get vendor string (issue CPUID with eax = 0) |
| 76 | cpuid(eax, ebx, ecx, edx, 0); |
| 77 | char vendor[13]; |
| 78 | memcpy(vendor, &ebx, 4); |
| 79 | memcpy(vendor + 4, &edx, 4); |
| 80 | memcpy(vendor + 8, &ecx, 4); |
| 81 | vendor[12] = 0; |
| 82 | |
| 83 | // get feature flags in ecx/edx, and family/model in eax |
| 84 | cpuid(eax, ebx, ecx, edx, 1); |
| 85 | |
| 86 | int family = (eax >> 8) & 0xf; // family and model fields |
| 87 | int model = (eax >> 4) & 0xf; |
| 88 | if (family == 0xf) { // use extended family and model fields |
| 89 | family += (eax >> 20) & 0xff; |
| 90 | model += ((eax >> 16) & 0xf) << 4; |
| 91 | } |
| 92 | |
| 93 | // Opteron Rev E has a bug in which on very rare occasions a locked |
| 94 | // instruction doesn't act as a read-acquire barrier if followed by a |
| 95 | // non-locked read-modify-write instruction. Rev F has this bug in |
| 96 | // pre-release versions, but not in versions released to customers, |
| 97 | // so we test only for Rev E, which is family 15, model 32..63 inclusive. |
| 98 | if (strcmp(vendor, "AuthenticAMD") == 0 && // AMD |
| 99 | family == 15 && |
| 100 | 32 <= model && model <= 63) { |
| 101 | AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = true; |
| 102 | } else { |
| 103 | AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = false; |
| 104 | } |
| 105 | |
| 106 | // edx bit 26 is SSE2 which we use to tell use whether we can use mfence |
| 107 | AtomicOps_Internalx86CPUFeatures.has_sse2 = ((edx >> 26) & 1); |
| 108 | } |
| 109 | |
| 110 | namespace { |
| 111 | |
| 112 | class AtomicOpsx86Initializer { |
| 113 | public: |
| 114 | AtomicOpsx86Initializer() { |
| 115 | AtomicOps_Internalx86CPUFeaturesInit(); |
| 116 | } |
| 117 | }; |
| 118 | |
| 119 | // A global to get use initialized on startup via static initialization :/ |
| 120 | AtomicOpsx86Initializer g_initer; |
| 121 | |
| 122 | } // namespace |
| 123 | |
| 124 | #endif // if x86 |
| 125 | |
| 126 | #endif // ifdef V8_ATOMICOPS_INTERNALS_X86_GCC_H_ |