| Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame^] | 1 | // Copyright 2014 the V8 project authors. All rights reserved. |
| 2 | // Use of this source code is governed by a BSD-style license that can be |
| 3 | // found in the LICENSE file. |
| 4 | |
| 5 | #ifndef V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_ |
| 6 | #define V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_ |
| 7 | |
| 8 | namespace v8 { |
| 9 | namespace internal { |
| 10 | namespace compiler { |
| 11 | |
| 12 | // IA32-specific opcodes that specify which assembly sequence to emit. |
| 13 | // Most opcodes specify a single instruction. |
| 14 | #define TARGET_ARCH_OPCODE_LIST(V) \ |
| 15 | V(IA32Add) \ |
| 16 | V(IA32And) \ |
| 17 | V(IA32Cmp) \ |
| 18 | V(IA32Test) \ |
| 19 | V(IA32Or) \ |
| 20 | V(IA32Xor) \ |
| 21 | V(IA32Sub) \ |
| 22 | V(IA32Imul) \ |
| 23 | V(IA32Idiv) \ |
| 24 | V(IA32Udiv) \ |
| 25 | V(IA32Not) \ |
| 26 | V(IA32Neg) \ |
| 27 | V(IA32Shl) \ |
| 28 | V(IA32Shr) \ |
| 29 | V(IA32Sar) \ |
| 30 | V(IA32Ror) \ |
| 31 | V(SSEFloat64Cmp) \ |
| 32 | V(SSEFloat64Add) \ |
| 33 | V(SSEFloat64Sub) \ |
| 34 | V(SSEFloat64Mul) \ |
| 35 | V(SSEFloat64Div) \ |
| 36 | V(SSEFloat64Mod) \ |
| 37 | V(SSEFloat64Sqrt) \ |
| 38 | V(SSEFloat64ToInt32) \ |
| 39 | V(SSEFloat64ToUint32) \ |
| 40 | V(SSEInt32ToFloat64) \ |
| 41 | V(SSEUint32ToFloat64) \ |
| 42 | V(IA32Movsxbl) \ |
| 43 | V(IA32Movzxbl) \ |
| 44 | V(IA32Movb) \ |
| 45 | V(IA32Movsxwl) \ |
| 46 | V(IA32Movzxwl) \ |
| 47 | V(IA32Movw) \ |
| 48 | V(IA32Movl) \ |
| 49 | V(IA32Movss) \ |
| 50 | V(IA32Movsd) \ |
| 51 | V(IA32Push) \ |
| 52 | V(IA32StoreWriteBarrier) |
| 53 | |
| 54 | |
| 55 | // Addressing modes represent the "shape" of inputs to an instruction. |
| 56 | // Many instructions support multiple addressing modes. Addressing modes |
| 57 | // are encoded into the InstructionCode of the instruction and tell the |
| 58 | // code generator after register allocation which assembler method to call. |
| 59 | // |
| 60 | // We use the following local notation for addressing modes: |
| 61 | // |
| 62 | // R = register |
| 63 | // O = register or stack slot |
| 64 | // D = double register |
| 65 | // I = immediate (handle, external, int32) |
| 66 | // MR = [register] |
| 67 | // MI = [immediate] |
| 68 | // MRN = [register + register * N in {1, 2, 4, 8}] |
| 69 | // MRI = [register + immediate] |
| 70 | // MRNI = [register + register * N in {1, 2, 4, 8} + immediate] |
| 71 | #define TARGET_ADDRESSING_MODE_LIST(V) \ |
| 72 | V(MI) /* [K] */ \ |
| 73 | V(MR) /* [%r0] */ \ |
| 74 | V(MRI) /* [%r0 + K] */ \ |
| 75 | V(MR1I) /* [%r0 + %r1 * 1 + K] */ \ |
| 76 | V(MR2I) /* [%r0 + %r1 * 2 + K] */ \ |
| 77 | V(MR4I) /* [%r0 + %r1 * 4 + K] */ \ |
| 78 | V(MR8I) /* [%r0 + %r1 * 8 + K] */ |
| 79 | |
| 80 | } // namespace compiler |
| 81 | } // namespace internal |
| 82 | } // namespace v8 |
| 83 | |
| 84 | #endif // V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_ |