Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1 | // Copyright 2013 the V8 project authors. All rights reserved. |
| 2 | // Use of this source code is governed by a BSD-style license that can be |
| 3 | // found in the LICENSE file. |
| 4 | |
| 5 | #ifndef V8_ARM64_ASSEMBLER_ARM64_INL_H_ |
| 6 | #define V8_ARM64_ASSEMBLER_ARM64_INL_H_ |
| 7 | |
| 8 | #include "src/arm64/assembler-arm64.h" |
| 9 | #include "src/assembler.h" |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 10 | #include "src/debug/debug.h" |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 11 | |
| 12 | |
| 13 | namespace v8 { |
| 14 | namespace internal { |
| 15 | |
| 16 | |
| 17 | bool CpuFeatures::SupportsCrankshaft() { return true; } |
| 18 | |
| 19 | |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 20 | void RelocInfo::apply(intptr_t delta) { |
| 21 | // On arm64 only internal references need extra work. |
| 22 | DCHECK(RelocInfo::IsInternalReference(rmode_)); |
| 23 | |
| 24 | // Absolute code pointer inside code object moves with the code object. |
| 25 | intptr_t* p = reinterpret_cast<intptr_t*>(pc_); |
| 26 | *p += delta; // Relocate entry. |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 27 | } |
| 28 | |
| 29 | |
| 30 | void RelocInfo::set_target_address(Address target, |
| 31 | WriteBarrierMode write_barrier_mode, |
| 32 | ICacheFlushMode icache_flush_mode) { |
| 33 | DCHECK(IsCodeTarget(rmode_) || IsRuntimeEntry(rmode_)); |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 34 | Assembler::set_target_address_at(isolate_, pc_, host_, target, |
| 35 | icache_flush_mode); |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 36 | if (write_barrier_mode == UPDATE_WRITE_BARRIER && host() != NULL && |
| 37 | IsCodeTarget(rmode_)) { |
| 38 | Object* target_code = Code::GetCodeFromTargetAddress(target); |
| 39 | host()->GetHeap()->incremental_marking()->RecordWriteIntoCode( |
| 40 | host(), this, HeapObject::cast(target_code)); |
| 41 | } |
| 42 | } |
| 43 | |
Ben Murdoch | da12d29 | 2016-06-02 14:46:10 +0100 | [diff] [blame^] | 44 | void RelocInfo::update_wasm_memory_reference( |
| 45 | Address old_base, Address new_base, size_t old_size, size_t new_size, |
| 46 | ICacheFlushMode icache_flush_mode) { |
| 47 | DCHECK(IsWasmMemoryReference(rmode_)); |
| 48 | DCHECK(old_base <= wasm_memory_reference() && |
| 49 | wasm_memory_reference() < old_base + old_size); |
| 50 | Address updated_reference = new_base + (wasm_memory_reference() - old_base); |
| 51 | DCHECK(new_base <= updated_reference && |
| 52 | updated_reference < new_base + new_size); |
| 53 | Assembler::set_target_address_at(isolate_, pc_, host_, updated_reference, |
| 54 | icache_flush_mode); |
| 55 | } |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 56 | |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 57 | inline int CPURegister::code() const { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 58 | DCHECK(IsValid()); |
| 59 | return reg_code; |
| 60 | } |
| 61 | |
| 62 | |
| 63 | inline CPURegister::RegisterType CPURegister::type() const { |
| 64 | DCHECK(IsValidOrNone()); |
| 65 | return reg_type; |
| 66 | } |
| 67 | |
| 68 | |
| 69 | inline RegList CPURegister::Bit() const { |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 70 | DCHECK(static_cast<size_t>(reg_code) < (sizeof(RegList) * kBitsPerByte)); |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 71 | return IsValid() ? 1UL << reg_code : 0; |
| 72 | } |
| 73 | |
| 74 | |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 75 | inline int CPURegister::SizeInBits() const { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 76 | DCHECK(IsValid()); |
| 77 | return reg_size; |
| 78 | } |
| 79 | |
| 80 | |
| 81 | inline int CPURegister::SizeInBytes() const { |
| 82 | DCHECK(IsValid()); |
| 83 | DCHECK(SizeInBits() % 8 == 0); |
| 84 | return reg_size / 8; |
| 85 | } |
| 86 | |
| 87 | |
| 88 | inline bool CPURegister::Is32Bits() const { |
| 89 | DCHECK(IsValid()); |
| 90 | return reg_size == 32; |
| 91 | } |
| 92 | |
| 93 | |
| 94 | inline bool CPURegister::Is64Bits() const { |
| 95 | DCHECK(IsValid()); |
| 96 | return reg_size == 64; |
| 97 | } |
| 98 | |
| 99 | |
| 100 | inline bool CPURegister::IsValid() const { |
| 101 | if (IsValidRegister() || IsValidFPRegister()) { |
| 102 | DCHECK(!IsNone()); |
| 103 | return true; |
| 104 | } else { |
| 105 | DCHECK(IsNone()); |
| 106 | return false; |
| 107 | } |
| 108 | } |
| 109 | |
| 110 | |
| 111 | inline bool CPURegister::IsValidRegister() const { |
| 112 | return IsRegister() && |
| 113 | ((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits)) && |
| 114 | ((reg_code < kNumberOfRegisters) || (reg_code == kSPRegInternalCode)); |
| 115 | } |
| 116 | |
| 117 | |
| 118 | inline bool CPURegister::IsValidFPRegister() const { |
| 119 | return IsFPRegister() && |
| 120 | ((reg_size == kSRegSizeInBits) || (reg_size == kDRegSizeInBits)) && |
| 121 | (reg_code < kNumberOfFPRegisters); |
| 122 | } |
| 123 | |
| 124 | |
| 125 | inline bool CPURegister::IsNone() const { |
| 126 | // kNoRegister types should always have size 0 and code 0. |
| 127 | DCHECK((reg_type != kNoRegister) || (reg_code == 0)); |
| 128 | DCHECK((reg_type != kNoRegister) || (reg_size == 0)); |
| 129 | |
| 130 | return reg_type == kNoRegister; |
| 131 | } |
| 132 | |
| 133 | |
| 134 | inline bool CPURegister::Is(const CPURegister& other) const { |
| 135 | DCHECK(IsValidOrNone() && other.IsValidOrNone()); |
| 136 | return Aliases(other) && (reg_size == other.reg_size); |
| 137 | } |
| 138 | |
| 139 | |
| 140 | inline bool CPURegister::Aliases(const CPURegister& other) const { |
| 141 | DCHECK(IsValidOrNone() && other.IsValidOrNone()); |
| 142 | return (reg_code == other.reg_code) && (reg_type == other.reg_type); |
| 143 | } |
| 144 | |
| 145 | |
| 146 | inline bool CPURegister::IsRegister() const { |
| 147 | return reg_type == kRegister; |
| 148 | } |
| 149 | |
| 150 | |
| 151 | inline bool CPURegister::IsFPRegister() const { |
| 152 | return reg_type == kFPRegister; |
| 153 | } |
| 154 | |
| 155 | |
| 156 | inline bool CPURegister::IsSameSizeAndType(const CPURegister& other) const { |
| 157 | return (reg_size == other.reg_size) && (reg_type == other.reg_type); |
| 158 | } |
| 159 | |
| 160 | |
| 161 | inline bool CPURegister::IsValidOrNone() const { |
| 162 | return IsValid() || IsNone(); |
| 163 | } |
| 164 | |
| 165 | |
| 166 | inline bool CPURegister::IsZero() const { |
| 167 | DCHECK(IsValid()); |
| 168 | return IsRegister() && (reg_code == kZeroRegCode); |
| 169 | } |
| 170 | |
| 171 | |
| 172 | inline bool CPURegister::IsSP() const { |
| 173 | DCHECK(IsValid()); |
| 174 | return IsRegister() && (reg_code == kSPRegInternalCode); |
| 175 | } |
| 176 | |
| 177 | |
| 178 | inline void CPURegList::Combine(const CPURegList& other) { |
| 179 | DCHECK(IsValid()); |
| 180 | DCHECK(other.type() == type_); |
| 181 | DCHECK(other.RegisterSizeInBits() == size_); |
| 182 | list_ |= other.list(); |
| 183 | } |
| 184 | |
| 185 | |
| 186 | inline void CPURegList::Remove(const CPURegList& other) { |
| 187 | DCHECK(IsValid()); |
| 188 | if (other.type() == type_) { |
| 189 | list_ &= ~other.list(); |
| 190 | } |
| 191 | } |
| 192 | |
| 193 | |
| 194 | inline void CPURegList::Combine(const CPURegister& other) { |
| 195 | DCHECK(other.type() == type_); |
| 196 | DCHECK(other.SizeInBits() == size_); |
| 197 | Combine(other.code()); |
| 198 | } |
| 199 | |
| 200 | |
| 201 | inline void CPURegList::Remove(const CPURegister& other1, |
| 202 | const CPURegister& other2, |
| 203 | const CPURegister& other3, |
| 204 | const CPURegister& other4) { |
| 205 | if (!other1.IsNone() && (other1.type() == type_)) Remove(other1.code()); |
| 206 | if (!other2.IsNone() && (other2.type() == type_)) Remove(other2.code()); |
| 207 | if (!other3.IsNone() && (other3.type() == type_)) Remove(other3.code()); |
| 208 | if (!other4.IsNone() && (other4.type() == type_)) Remove(other4.code()); |
| 209 | } |
| 210 | |
| 211 | |
| 212 | inline void CPURegList::Combine(int code) { |
| 213 | DCHECK(IsValid()); |
| 214 | DCHECK(CPURegister::Create(code, size_, type_).IsValid()); |
| 215 | list_ |= (1UL << code); |
| 216 | } |
| 217 | |
| 218 | |
| 219 | inline void CPURegList::Remove(int code) { |
| 220 | DCHECK(IsValid()); |
| 221 | DCHECK(CPURegister::Create(code, size_, type_).IsValid()); |
| 222 | list_ &= ~(1UL << code); |
| 223 | } |
| 224 | |
| 225 | |
| 226 | inline Register Register::XRegFromCode(unsigned code) { |
| 227 | if (code == kSPRegInternalCode) { |
| 228 | return csp; |
| 229 | } else { |
| 230 | DCHECK(code < kNumberOfRegisters); |
| 231 | return Register::Create(code, kXRegSizeInBits); |
| 232 | } |
| 233 | } |
| 234 | |
| 235 | |
| 236 | inline Register Register::WRegFromCode(unsigned code) { |
| 237 | if (code == kSPRegInternalCode) { |
| 238 | return wcsp; |
| 239 | } else { |
| 240 | DCHECK(code < kNumberOfRegisters); |
| 241 | return Register::Create(code, kWRegSizeInBits); |
| 242 | } |
| 243 | } |
| 244 | |
| 245 | |
| 246 | inline FPRegister FPRegister::SRegFromCode(unsigned code) { |
| 247 | DCHECK(code < kNumberOfFPRegisters); |
| 248 | return FPRegister::Create(code, kSRegSizeInBits); |
| 249 | } |
| 250 | |
| 251 | |
| 252 | inline FPRegister FPRegister::DRegFromCode(unsigned code) { |
| 253 | DCHECK(code < kNumberOfFPRegisters); |
| 254 | return FPRegister::Create(code, kDRegSizeInBits); |
| 255 | } |
| 256 | |
| 257 | |
| 258 | inline Register CPURegister::W() const { |
| 259 | DCHECK(IsValidRegister()); |
| 260 | return Register::WRegFromCode(reg_code); |
| 261 | } |
| 262 | |
| 263 | |
| 264 | inline Register CPURegister::X() const { |
| 265 | DCHECK(IsValidRegister()); |
| 266 | return Register::XRegFromCode(reg_code); |
| 267 | } |
| 268 | |
| 269 | |
| 270 | inline FPRegister CPURegister::S() const { |
| 271 | DCHECK(IsValidFPRegister()); |
| 272 | return FPRegister::SRegFromCode(reg_code); |
| 273 | } |
| 274 | |
| 275 | |
| 276 | inline FPRegister CPURegister::D() const { |
| 277 | DCHECK(IsValidFPRegister()); |
| 278 | return FPRegister::DRegFromCode(reg_code); |
| 279 | } |
| 280 | |
| 281 | |
| 282 | // Immediate. |
| 283 | // Default initializer is for int types |
| 284 | template<typename T> |
| 285 | struct ImmediateInitializer { |
| 286 | static const bool kIsIntType = true; |
| 287 | static inline RelocInfo::Mode rmode_for(T) { |
| 288 | return sizeof(T) == 8 ? RelocInfo::NONE64 : RelocInfo::NONE32; |
| 289 | } |
| 290 | static inline int64_t immediate_for(T t) { |
| 291 | STATIC_ASSERT(sizeof(T) <= 8); |
| 292 | return t; |
| 293 | } |
| 294 | }; |
| 295 | |
| 296 | |
| 297 | template<> |
| 298 | struct ImmediateInitializer<Smi*> { |
| 299 | static const bool kIsIntType = false; |
| 300 | static inline RelocInfo::Mode rmode_for(Smi* t) { |
| 301 | return RelocInfo::NONE64; |
| 302 | } |
| 303 | static inline int64_t immediate_for(Smi* t) {; |
| 304 | return reinterpret_cast<int64_t>(t); |
| 305 | } |
| 306 | }; |
| 307 | |
| 308 | |
| 309 | template<> |
| 310 | struct ImmediateInitializer<ExternalReference> { |
| 311 | static const bool kIsIntType = false; |
| 312 | static inline RelocInfo::Mode rmode_for(ExternalReference t) { |
| 313 | return RelocInfo::EXTERNAL_REFERENCE; |
| 314 | } |
| 315 | static inline int64_t immediate_for(ExternalReference t) {; |
| 316 | return reinterpret_cast<int64_t>(t.address()); |
| 317 | } |
| 318 | }; |
| 319 | |
| 320 | |
| 321 | template<typename T> |
| 322 | Immediate::Immediate(Handle<T> value) { |
| 323 | InitializeHandle(value); |
| 324 | } |
| 325 | |
| 326 | |
| 327 | template<typename T> |
| 328 | Immediate::Immediate(T t) |
| 329 | : value_(ImmediateInitializer<T>::immediate_for(t)), |
| 330 | rmode_(ImmediateInitializer<T>::rmode_for(t)) {} |
| 331 | |
| 332 | |
| 333 | template<typename T> |
| 334 | Immediate::Immediate(T t, RelocInfo::Mode rmode) |
| 335 | : value_(ImmediateInitializer<T>::immediate_for(t)), |
| 336 | rmode_(rmode) { |
| 337 | STATIC_ASSERT(ImmediateInitializer<T>::kIsIntType); |
| 338 | } |
| 339 | |
| 340 | |
| 341 | // Operand. |
| 342 | template<typename T> |
| 343 | Operand::Operand(Handle<T> value) : immediate_(value), reg_(NoReg) {} |
| 344 | |
| 345 | |
| 346 | template<typename T> |
| 347 | Operand::Operand(T t) : immediate_(t), reg_(NoReg) {} |
| 348 | |
| 349 | |
| 350 | template<typename T> |
| 351 | Operand::Operand(T t, RelocInfo::Mode rmode) |
| 352 | : immediate_(t, rmode), |
| 353 | reg_(NoReg) {} |
| 354 | |
| 355 | |
| 356 | Operand::Operand(Register reg, Shift shift, unsigned shift_amount) |
| 357 | : immediate_(0), |
| 358 | reg_(reg), |
| 359 | shift_(shift), |
| 360 | extend_(NO_EXTEND), |
| 361 | shift_amount_(shift_amount) { |
| 362 | DCHECK(reg.Is64Bits() || (shift_amount < kWRegSizeInBits)); |
| 363 | DCHECK(reg.Is32Bits() || (shift_amount < kXRegSizeInBits)); |
| 364 | DCHECK(!reg.IsSP()); |
| 365 | } |
| 366 | |
| 367 | |
| 368 | Operand::Operand(Register reg, Extend extend, unsigned shift_amount) |
| 369 | : immediate_(0), |
| 370 | reg_(reg), |
| 371 | shift_(NO_SHIFT), |
| 372 | extend_(extend), |
| 373 | shift_amount_(shift_amount) { |
| 374 | DCHECK(reg.IsValid()); |
| 375 | DCHECK(shift_amount <= 4); |
| 376 | DCHECK(!reg.IsSP()); |
| 377 | |
| 378 | // Extend modes SXTX and UXTX require a 64-bit register. |
| 379 | DCHECK(reg.Is64Bits() || ((extend != SXTX) && (extend != UXTX))); |
| 380 | } |
| 381 | |
| 382 | |
| 383 | bool Operand::IsImmediate() const { |
| 384 | return reg_.Is(NoReg); |
| 385 | } |
| 386 | |
| 387 | |
| 388 | bool Operand::IsShiftedRegister() const { |
| 389 | return reg_.IsValid() && (shift_ != NO_SHIFT); |
| 390 | } |
| 391 | |
| 392 | |
| 393 | bool Operand::IsExtendedRegister() const { |
| 394 | return reg_.IsValid() && (extend_ != NO_EXTEND); |
| 395 | } |
| 396 | |
| 397 | |
| 398 | bool Operand::IsZero() const { |
| 399 | if (IsImmediate()) { |
| 400 | return ImmediateValue() == 0; |
| 401 | } else { |
| 402 | return reg().IsZero(); |
| 403 | } |
| 404 | } |
| 405 | |
| 406 | |
| 407 | Operand Operand::ToExtendedRegister() const { |
| 408 | DCHECK(IsShiftedRegister()); |
| 409 | DCHECK((shift_ == LSL) && (shift_amount_ <= 4)); |
| 410 | return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_); |
| 411 | } |
| 412 | |
| 413 | |
| 414 | Immediate Operand::immediate() const { |
| 415 | DCHECK(IsImmediate()); |
| 416 | return immediate_; |
| 417 | } |
| 418 | |
| 419 | |
| 420 | int64_t Operand::ImmediateValue() const { |
| 421 | DCHECK(IsImmediate()); |
| 422 | return immediate_.value(); |
| 423 | } |
| 424 | |
| 425 | |
| 426 | Register Operand::reg() const { |
| 427 | DCHECK(IsShiftedRegister() || IsExtendedRegister()); |
| 428 | return reg_; |
| 429 | } |
| 430 | |
| 431 | |
| 432 | Shift Operand::shift() const { |
| 433 | DCHECK(IsShiftedRegister()); |
| 434 | return shift_; |
| 435 | } |
| 436 | |
| 437 | |
| 438 | Extend Operand::extend() const { |
| 439 | DCHECK(IsExtendedRegister()); |
| 440 | return extend_; |
| 441 | } |
| 442 | |
| 443 | |
| 444 | unsigned Operand::shift_amount() const { |
| 445 | DCHECK(IsShiftedRegister() || IsExtendedRegister()); |
| 446 | return shift_amount_; |
| 447 | } |
| 448 | |
| 449 | |
| 450 | Operand Operand::UntagSmi(Register smi) { |
| 451 | STATIC_ASSERT(kXRegSizeInBits == static_cast<unsigned>(kSmiShift + |
| 452 | kSmiValueSize)); |
| 453 | DCHECK(smi.Is64Bits()); |
| 454 | return Operand(smi, ASR, kSmiShift); |
| 455 | } |
| 456 | |
| 457 | |
| 458 | Operand Operand::UntagSmiAndScale(Register smi, int scale) { |
| 459 | STATIC_ASSERT(kXRegSizeInBits == static_cast<unsigned>(kSmiShift + |
| 460 | kSmiValueSize)); |
| 461 | DCHECK(smi.Is64Bits()); |
| 462 | DCHECK((scale >= 0) && (scale <= (64 - kSmiValueSize))); |
| 463 | if (scale > kSmiShift) { |
| 464 | return Operand(smi, LSL, scale - kSmiShift); |
| 465 | } else if (scale < kSmiShift) { |
| 466 | return Operand(smi, ASR, kSmiShift - scale); |
| 467 | } |
| 468 | return Operand(smi); |
| 469 | } |
| 470 | |
| 471 | |
| 472 | MemOperand::MemOperand() |
| 473 | : base_(NoReg), regoffset_(NoReg), offset_(0), addrmode_(Offset), |
| 474 | shift_(NO_SHIFT), extend_(NO_EXTEND), shift_amount_(0) { |
| 475 | } |
| 476 | |
| 477 | |
| 478 | MemOperand::MemOperand(Register base, int64_t offset, AddrMode addrmode) |
| 479 | : base_(base), regoffset_(NoReg), offset_(offset), addrmode_(addrmode), |
| 480 | shift_(NO_SHIFT), extend_(NO_EXTEND), shift_amount_(0) { |
| 481 | DCHECK(base.Is64Bits() && !base.IsZero()); |
| 482 | } |
| 483 | |
| 484 | |
| 485 | MemOperand::MemOperand(Register base, |
| 486 | Register regoffset, |
| 487 | Extend extend, |
| 488 | unsigned shift_amount) |
| 489 | : base_(base), regoffset_(regoffset), offset_(0), addrmode_(Offset), |
| 490 | shift_(NO_SHIFT), extend_(extend), shift_amount_(shift_amount) { |
| 491 | DCHECK(base.Is64Bits() && !base.IsZero()); |
| 492 | DCHECK(!regoffset.IsSP()); |
| 493 | DCHECK((extend == UXTW) || (extend == SXTW) || (extend == SXTX)); |
| 494 | |
| 495 | // SXTX extend mode requires a 64-bit offset register. |
| 496 | DCHECK(regoffset.Is64Bits() || (extend != SXTX)); |
| 497 | } |
| 498 | |
| 499 | |
| 500 | MemOperand::MemOperand(Register base, |
| 501 | Register regoffset, |
| 502 | Shift shift, |
| 503 | unsigned shift_amount) |
| 504 | : base_(base), regoffset_(regoffset), offset_(0), addrmode_(Offset), |
| 505 | shift_(shift), extend_(NO_EXTEND), shift_amount_(shift_amount) { |
| 506 | DCHECK(base.Is64Bits() && !base.IsZero()); |
| 507 | DCHECK(regoffset.Is64Bits() && !regoffset.IsSP()); |
| 508 | DCHECK(shift == LSL); |
| 509 | } |
| 510 | |
| 511 | |
| 512 | MemOperand::MemOperand(Register base, const Operand& offset, AddrMode addrmode) |
| 513 | : base_(base), addrmode_(addrmode) { |
| 514 | DCHECK(base.Is64Bits() && !base.IsZero()); |
| 515 | |
| 516 | if (offset.IsImmediate()) { |
| 517 | offset_ = offset.ImmediateValue(); |
| 518 | |
| 519 | regoffset_ = NoReg; |
| 520 | } else if (offset.IsShiftedRegister()) { |
| 521 | DCHECK(addrmode == Offset); |
| 522 | |
| 523 | regoffset_ = offset.reg(); |
Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame] | 524 | shift_ = offset.shift(); |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 525 | shift_amount_ = offset.shift_amount(); |
| 526 | |
| 527 | extend_ = NO_EXTEND; |
| 528 | offset_ = 0; |
| 529 | |
| 530 | // These assertions match those in the shifted-register constructor. |
| 531 | DCHECK(regoffset_.Is64Bits() && !regoffset_.IsSP()); |
| 532 | DCHECK(shift_ == LSL); |
| 533 | } else { |
| 534 | DCHECK(offset.IsExtendedRegister()); |
| 535 | DCHECK(addrmode == Offset); |
| 536 | |
| 537 | regoffset_ = offset.reg(); |
| 538 | extend_ = offset.extend(); |
| 539 | shift_amount_ = offset.shift_amount(); |
| 540 | |
Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame] | 541 | shift_ = NO_SHIFT; |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 542 | offset_ = 0; |
| 543 | |
| 544 | // These assertions match those in the extended-register constructor. |
| 545 | DCHECK(!regoffset_.IsSP()); |
| 546 | DCHECK((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX)); |
| 547 | DCHECK((regoffset_.Is64Bits() || (extend_ != SXTX))); |
| 548 | } |
| 549 | } |
| 550 | |
| 551 | bool MemOperand::IsImmediateOffset() const { |
| 552 | return (addrmode_ == Offset) && regoffset_.Is(NoReg); |
| 553 | } |
| 554 | |
| 555 | |
| 556 | bool MemOperand::IsRegisterOffset() const { |
| 557 | return (addrmode_ == Offset) && !regoffset_.Is(NoReg); |
| 558 | } |
| 559 | |
| 560 | |
| 561 | bool MemOperand::IsPreIndex() const { |
| 562 | return addrmode_ == PreIndex; |
| 563 | } |
| 564 | |
| 565 | |
| 566 | bool MemOperand::IsPostIndex() const { |
| 567 | return addrmode_ == PostIndex; |
| 568 | } |
| 569 | |
| 570 | Operand MemOperand::OffsetAsOperand() const { |
| 571 | if (IsImmediateOffset()) { |
| 572 | return offset(); |
| 573 | } else { |
| 574 | DCHECK(IsRegisterOffset()); |
| 575 | if (extend() == NO_EXTEND) { |
| 576 | return Operand(regoffset(), shift(), shift_amount()); |
| 577 | } else { |
| 578 | return Operand(regoffset(), extend(), shift_amount()); |
| 579 | } |
| 580 | } |
| 581 | } |
| 582 | |
| 583 | |
| 584 | void Assembler::Unreachable() { |
| 585 | #ifdef USE_SIMULATOR |
| 586 | debug("UNREACHABLE", __LINE__, BREAK); |
| 587 | #else |
| 588 | // Crash by branching to 0. lr now points near the fault. |
| 589 | Emit(BLR | Rn(xzr)); |
| 590 | #endif |
| 591 | } |
| 592 | |
| 593 | |
| 594 | Address Assembler::target_pointer_address_at(Address pc) { |
| 595 | Instruction* instr = reinterpret_cast<Instruction*>(pc); |
| 596 | DCHECK(instr->IsLdrLiteralX()); |
| 597 | return reinterpret_cast<Address>(instr->ImmPCOffsetTarget()); |
| 598 | } |
| 599 | |
| 600 | |
| 601 | // Read/Modify the code target address in the branch/call instruction at pc. |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 602 | Address Assembler::target_address_at(Address pc, Address constant_pool) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 603 | return Memory::Address_at(target_pointer_address_at(pc)); |
| 604 | } |
| 605 | |
| 606 | |
| 607 | Address Assembler::target_address_at(Address pc, Code* code) { |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 608 | Address constant_pool = code ? code->constant_pool() : NULL; |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 609 | return target_address_at(pc, constant_pool); |
| 610 | } |
| 611 | |
| 612 | |
| 613 | Address Assembler::target_address_from_return_address(Address pc) { |
| 614 | // Returns the address of the call target from the return address that will |
| 615 | // be returned to after a call. |
| 616 | // Call sequence on ARM64 is: |
| 617 | // ldr ip0, #... @ load from literal pool |
| 618 | // blr ip0 |
| 619 | Address candidate = pc - 2 * kInstructionSize; |
| 620 | Instruction* instr = reinterpret_cast<Instruction*>(candidate); |
| 621 | USE(instr); |
| 622 | DCHECK(instr->IsLdrLiteralX()); |
| 623 | return candidate; |
| 624 | } |
| 625 | |
| 626 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 627 | Address Assembler::return_address_from_call_start(Address pc) { |
| 628 | // The call, generated by MacroAssembler::Call, is one of two possible |
| 629 | // sequences: |
| 630 | // |
| 631 | // Without relocation: |
| 632 | // movz temp, #(target & 0x000000000000ffff) |
| 633 | // movk temp, #(target & 0x00000000ffff0000) |
| 634 | // movk temp, #(target & 0x0000ffff00000000) |
| 635 | // blr temp |
| 636 | // |
| 637 | // With relocation: |
| 638 | // ldr temp, =target |
| 639 | // blr temp |
| 640 | // |
| 641 | // The return address is immediately after the blr instruction in both cases, |
| 642 | // so it can be found by adding the call size to the address at the start of |
| 643 | // the call sequence. |
| 644 | STATIC_ASSERT(Assembler::kCallSizeWithoutRelocation == 4 * kInstructionSize); |
| 645 | STATIC_ASSERT(Assembler::kCallSizeWithRelocation == 2 * kInstructionSize); |
| 646 | |
| 647 | Instruction* instr = reinterpret_cast<Instruction*>(pc); |
| 648 | if (instr->IsMovz()) { |
| 649 | // Verify the instruction sequence. |
| 650 | DCHECK(instr->following(1)->IsMovk()); |
| 651 | DCHECK(instr->following(2)->IsMovk()); |
| 652 | DCHECK(instr->following(3)->IsBranchAndLinkToRegister()); |
| 653 | return pc + Assembler::kCallSizeWithoutRelocation; |
| 654 | } else { |
| 655 | // Verify the instruction sequence. |
| 656 | DCHECK(instr->IsLdrLiteralX()); |
| 657 | DCHECK(instr->following(1)->IsBranchAndLinkToRegister()); |
| 658 | return pc + Assembler::kCallSizeWithRelocation; |
| 659 | } |
| 660 | } |
| 661 | |
| 662 | |
| 663 | void Assembler::deserialization_set_special_target_at( |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 664 | Isolate* isolate, Address constant_pool_entry, Code* code, Address target) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 665 | Memory::Address_at(constant_pool_entry) = target; |
| 666 | } |
| 667 | |
| 668 | |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 669 | void Assembler::deserialization_set_target_internal_reference_at( |
| 670 | Isolate* isolate, Address pc, Address target, RelocInfo::Mode mode) { |
| 671 | Memory::Address_at(pc) = target; |
| 672 | } |
| 673 | |
| 674 | |
| 675 | void Assembler::set_target_address_at(Isolate* isolate, Address pc, |
| 676 | Address constant_pool, Address target, |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 677 | ICacheFlushMode icache_flush_mode) { |
| 678 | Memory::Address_at(target_pointer_address_at(pc)) = target; |
| 679 | // Intuitively, we would think it is necessary to always flush the |
| 680 | // instruction cache after patching a target address in the code as follows: |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 681 | // Assembler::FlushICache(isolate(), pc, sizeof(target)); |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 682 | // However, on ARM, an instruction is actually patched in the case of |
| 683 | // embedded constants of the form: |
| 684 | // ldr ip, [pc, #...] |
| 685 | // since the instruction accessing this address in the constant pool remains |
| 686 | // unchanged, a flush is not required. |
| 687 | } |
| 688 | |
| 689 | |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 690 | void Assembler::set_target_address_at(Isolate* isolate, Address pc, Code* code, |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 691 | Address target, |
| 692 | ICacheFlushMode icache_flush_mode) { |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 693 | Address constant_pool = code ? code->constant_pool() : NULL; |
| 694 | set_target_address_at(isolate, pc, constant_pool, target, icache_flush_mode); |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 695 | } |
| 696 | |
| 697 | |
| 698 | int RelocInfo::target_address_size() { |
| 699 | return kPointerSize; |
| 700 | } |
| 701 | |
| 702 | |
| 703 | Address RelocInfo::target_address() { |
| 704 | DCHECK(IsCodeTarget(rmode_) || IsRuntimeEntry(rmode_)); |
| 705 | return Assembler::target_address_at(pc_, host_); |
| 706 | } |
| 707 | |
Ben Murdoch | da12d29 | 2016-06-02 14:46:10 +0100 | [diff] [blame^] | 708 | Address RelocInfo::wasm_memory_reference() { |
| 709 | DCHECK(IsWasmMemoryReference(rmode_)); |
| 710 | return Assembler::target_address_at(pc_, host_); |
| 711 | } |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 712 | |
| 713 | Address RelocInfo::target_address_address() { |
| 714 | DCHECK(IsCodeTarget(rmode_) || IsRuntimeEntry(rmode_) |
| 715 | || rmode_ == EMBEDDED_OBJECT |
| 716 | || rmode_ == EXTERNAL_REFERENCE); |
| 717 | return Assembler::target_pointer_address_at(pc_); |
| 718 | } |
| 719 | |
| 720 | |
| 721 | Address RelocInfo::constant_pool_entry_address() { |
| 722 | DCHECK(IsInConstantPool()); |
| 723 | return Assembler::target_pointer_address_at(pc_); |
| 724 | } |
| 725 | |
| 726 | |
| 727 | Object* RelocInfo::target_object() { |
| 728 | DCHECK(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT); |
| 729 | return reinterpret_cast<Object*>(Assembler::target_address_at(pc_, host_)); |
| 730 | } |
| 731 | |
| 732 | |
| 733 | Handle<Object> RelocInfo::target_object_handle(Assembler* origin) { |
| 734 | DCHECK(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT); |
| 735 | return Handle<Object>(reinterpret_cast<Object**>( |
| 736 | Assembler::target_address_at(pc_, host_))); |
| 737 | } |
| 738 | |
| 739 | |
| 740 | void RelocInfo::set_target_object(Object* target, |
| 741 | WriteBarrierMode write_barrier_mode, |
| 742 | ICacheFlushMode icache_flush_mode) { |
| 743 | DCHECK(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT); |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 744 | Assembler::set_target_address_at(isolate_, pc_, host_, |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 745 | reinterpret_cast<Address>(target), |
| 746 | icache_flush_mode); |
| 747 | if (write_barrier_mode == UPDATE_WRITE_BARRIER && |
| 748 | host() != NULL && |
| 749 | target->IsHeapObject()) { |
Ben Murdoch | 097c5b2 | 2016-05-18 11:27:45 +0100 | [diff] [blame] | 750 | host()->GetHeap()->incremental_marking()->RecordWriteIntoCode( |
| 751 | host(), this, HeapObject::cast(target)); |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 752 | } |
| 753 | } |
| 754 | |
| 755 | |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 756 | Address RelocInfo::target_external_reference() { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 757 | DCHECK(rmode_ == EXTERNAL_REFERENCE); |
| 758 | return Assembler::target_address_at(pc_, host_); |
| 759 | } |
| 760 | |
| 761 | |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 762 | Address RelocInfo::target_internal_reference() { |
| 763 | DCHECK(rmode_ == INTERNAL_REFERENCE); |
| 764 | return Memory::Address_at(pc_); |
| 765 | } |
| 766 | |
| 767 | |
| 768 | Address RelocInfo::target_internal_reference_address() { |
| 769 | DCHECK(rmode_ == INTERNAL_REFERENCE); |
| 770 | return reinterpret_cast<Address>(pc_); |
| 771 | } |
| 772 | |
| 773 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 774 | Address RelocInfo::target_runtime_entry(Assembler* origin) { |
| 775 | DCHECK(IsRuntimeEntry(rmode_)); |
| 776 | return target_address(); |
| 777 | } |
| 778 | |
| 779 | |
| 780 | void RelocInfo::set_target_runtime_entry(Address target, |
| 781 | WriteBarrierMode write_barrier_mode, |
| 782 | ICacheFlushMode icache_flush_mode) { |
| 783 | DCHECK(IsRuntimeEntry(rmode_)); |
| 784 | if (target_address() != target) { |
| 785 | set_target_address(target, write_barrier_mode, icache_flush_mode); |
| 786 | } |
| 787 | } |
| 788 | |
| 789 | |
| 790 | Handle<Cell> RelocInfo::target_cell_handle() { |
| 791 | UNIMPLEMENTED(); |
| 792 | Cell *null_cell = NULL; |
| 793 | return Handle<Cell>(null_cell); |
| 794 | } |
| 795 | |
| 796 | |
| 797 | Cell* RelocInfo::target_cell() { |
| 798 | DCHECK(rmode_ == RelocInfo::CELL); |
| 799 | return Cell::FromValueAddress(Memory::Address_at(pc_)); |
| 800 | } |
| 801 | |
| 802 | |
| 803 | void RelocInfo::set_target_cell(Cell* cell, |
| 804 | WriteBarrierMode write_barrier_mode, |
| 805 | ICacheFlushMode icache_flush_mode) { |
| 806 | UNIMPLEMENTED(); |
| 807 | } |
| 808 | |
| 809 | |
| 810 | static const int kNoCodeAgeSequenceLength = 5 * kInstructionSize; |
| 811 | static const int kCodeAgeStubEntryOffset = 3 * kInstructionSize; |
| 812 | |
| 813 | |
| 814 | Handle<Object> RelocInfo::code_age_stub_handle(Assembler* origin) { |
| 815 | UNREACHABLE(); // This should never be reached on ARM64. |
| 816 | return Handle<Object>(); |
| 817 | } |
| 818 | |
| 819 | |
| 820 | Code* RelocInfo::code_age_stub() { |
| 821 | DCHECK(rmode_ == RelocInfo::CODE_AGE_SEQUENCE); |
| 822 | // Read the stub entry point from the code age sequence. |
| 823 | Address stub_entry_address = pc_ + kCodeAgeStubEntryOffset; |
| 824 | return Code::GetCodeFromTargetAddress(Memory::Address_at(stub_entry_address)); |
| 825 | } |
| 826 | |
| 827 | |
| 828 | void RelocInfo::set_code_age_stub(Code* stub, |
| 829 | ICacheFlushMode icache_flush_mode) { |
| 830 | DCHECK(rmode_ == RelocInfo::CODE_AGE_SEQUENCE); |
| 831 | DCHECK(!Code::IsYoungSequence(stub->GetIsolate(), pc_)); |
| 832 | // Overwrite the stub entry point in the code age sequence. This is loaded as |
| 833 | // a literal so there is no need to call FlushICache here. |
| 834 | Address stub_entry_address = pc_ + kCodeAgeStubEntryOffset; |
| 835 | Memory::Address_at(stub_entry_address) = stub->instruction_start(); |
| 836 | } |
| 837 | |
| 838 | |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 839 | Address RelocInfo::debug_call_address() { |
| 840 | DCHECK(IsDebugBreakSlot(rmode()) && IsPatchedDebugBreakSlotSequence()); |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 841 | // For the above sequences the Relocinfo points to the load literal loading |
| 842 | // the call address. |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 843 | STATIC_ASSERT(Assembler::kPatchDebugBreakSlotAddressOffset == 0); |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 844 | return Assembler::target_address_at(pc_, host_); |
| 845 | } |
| 846 | |
| 847 | |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 848 | void RelocInfo::set_debug_call_address(Address target) { |
| 849 | DCHECK(IsDebugBreakSlot(rmode()) && IsPatchedDebugBreakSlotSequence()); |
| 850 | STATIC_ASSERT(Assembler::kPatchDebugBreakSlotAddressOffset == 0); |
| 851 | Assembler::set_target_address_at(isolate_, pc_, host_, target); |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 852 | if (host() != NULL) { |
| 853 | Object* target_code = Code::GetCodeFromTargetAddress(target); |
| 854 | host()->GetHeap()->incremental_marking()->RecordWriteIntoCode( |
| 855 | host(), this, HeapObject::cast(target_code)); |
| 856 | } |
| 857 | } |
| 858 | |
| 859 | |
| 860 | void RelocInfo::WipeOut() { |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 861 | DCHECK(IsEmbeddedObject(rmode_) || IsCodeTarget(rmode_) || |
| 862 | IsRuntimeEntry(rmode_) || IsExternalReference(rmode_) || |
| 863 | IsInternalReference(rmode_)); |
| 864 | if (IsInternalReference(rmode_)) { |
| 865 | Memory::Address_at(pc_) = NULL; |
| 866 | } else { |
| 867 | Assembler::set_target_address_at(isolate_, pc_, host_, NULL); |
| 868 | } |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 869 | } |
| 870 | |
| 871 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 872 | void RelocInfo::Visit(Isolate* isolate, ObjectVisitor* visitor) { |
| 873 | RelocInfo::Mode mode = rmode(); |
| 874 | if (mode == RelocInfo::EMBEDDED_OBJECT) { |
| 875 | visitor->VisitEmbeddedPointer(this); |
| 876 | } else if (RelocInfo::IsCodeTarget(mode)) { |
| 877 | visitor->VisitCodeTarget(this); |
| 878 | } else if (mode == RelocInfo::CELL) { |
| 879 | visitor->VisitCell(this); |
| 880 | } else if (mode == RelocInfo::EXTERNAL_REFERENCE) { |
| 881 | visitor->VisitExternalReference(this); |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 882 | } else if (mode == RelocInfo::INTERNAL_REFERENCE) { |
| 883 | visitor->VisitInternalReference(this); |
| 884 | } else if (RelocInfo::IsDebugBreakSlot(mode) && |
| 885 | IsPatchedDebugBreakSlotSequence()) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 886 | visitor->VisitDebugTarget(this); |
| 887 | } else if (RelocInfo::IsRuntimeEntry(mode)) { |
| 888 | visitor->VisitRuntimeEntry(this); |
| 889 | } |
| 890 | } |
| 891 | |
| 892 | |
| 893 | template<typename StaticVisitor> |
| 894 | void RelocInfo::Visit(Heap* heap) { |
| 895 | RelocInfo::Mode mode = rmode(); |
| 896 | if (mode == RelocInfo::EMBEDDED_OBJECT) { |
| 897 | StaticVisitor::VisitEmbeddedPointer(heap, this); |
| 898 | } else if (RelocInfo::IsCodeTarget(mode)) { |
| 899 | StaticVisitor::VisitCodeTarget(heap, this); |
| 900 | } else if (mode == RelocInfo::CELL) { |
| 901 | StaticVisitor::VisitCell(heap, this); |
| 902 | } else if (mode == RelocInfo::EXTERNAL_REFERENCE) { |
| 903 | StaticVisitor::VisitExternalReference(this); |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 904 | } else if (mode == RelocInfo::INTERNAL_REFERENCE) { |
| 905 | StaticVisitor::VisitInternalReference(this); |
| 906 | } else if (RelocInfo::IsDebugBreakSlot(mode) && |
| 907 | IsPatchedDebugBreakSlotSequence()) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 908 | StaticVisitor::VisitDebugTarget(heap, this); |
| 909 | } else if (RelocInfo::IsRuntimeEntry(mode)) { |
| 910 | StaticVisitor::VisitRuntimeEntry(this); |
| 911 | } |
| 912 | } |
| 913 | |
| 914 | |
| 915 | LoadStoreOp Assembler::LoadOpFor(const CPURegister& rt) { |
| 916 | DCHECK(rt.IsValid()); |
| 917 | if (rt.IsRegister()) { |
| 918 | return rt.Is64Bits() ? LDR_x : LDR_w; |
| 919 | } else { |
| 920 | DCHECK(rt.IsFPRegister()); |
| 921 | return rt.Is64Bits() ? LDR_d : LDR_s; |
| 922 | } |
| 923 | } |
| 924 | |
| 925 | |
| 926 | LoadStorePairOp Assembler::LoadPairOpFor(const CPURegister& rt, |
| 927 | const CPURegister& rt2) { |
| 928 | DCHECK(AreSameSizeAndType(rt, rt2)); |
| 929 | USE(rt2); |
| 930 | if (rt.IsRegister()) { |
| 931 | return rt.Is64Bits() ? LDP_x : LDP_w; |
| 932 | } else { |
| 933 | DCHECK(rt.IsFPRegister()); |
| 934 | return rt.Is64Bits() ? LDP_d : LDP_s; |
| 935 | } |
| 936 | } |
| 937 | |
| 938 | |
| 939 | LoadStoreOp Assembler::StoreOpFor(const CPURegister& rt) { |
| 940 | DCHECK(rt.IsValid()); |
| 941 | if (rt.IsRegister()) { |
| 942 | return rt.Is64Bits() ? STR_x : STR_w; |
| 943 | } else { |
| 944 | DCHECK(rt.IsFPRegister()); |
| 945 | return rt.Is64Bits() ? STR_d : STR_s; |
| 946 | } |
| 947 | } |
| 948 | |
| 949 | |
| 950 | LoadStorePairOp Assembler::StorePairOpFor(const CPURegister& rt, |
| 951 | const CPURegister& rt2) { |
| 952 | DCHECK(AreSameSizeAndType(rt, rt2)); |
| 953 | USE(rt2); |
| 954 | if (rt.IsRegister()) { |
| 955 | return rt.Is64Bits() ? STP_x : STP_w; |
| 956 | } else { |
| 957 | DCHECK(rt.IsFPRegister()); |
| 958 | return rt.Is64Bits() ? STP_d : STP_s; |
| 959 | } |
| 960 | } |
| 961 | |
| 962 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 963 | LoadLiteralOp Assembler::LoadLiteralOpFor(const CPURegister& rt) { |
| 964 | if (rt.IsRegister()) { |
| 965 | return rt.Is64Bits() ? LDR_x_lit : LDR_w_lit; |
| 966 | } else { |
| 967 | DCHECK(rt.IsFPRegister()); |
| 968 | return rt.Is64Bits() ? LDR_d_lit : LDR_s_lit; |
| 969 | } |
| 970 | } |
| 971 | |
| 972 | |
| 973 | int Assembler::LinkAndGetInstructionOffsetTo(Label* label) { |
| 974 | DCHECK(kStartOfLabelLinkChain == 0); |
| 975 | int offset = LinkAndGetByteOffsetTo(label); |
| 976 | DCHECK(IsAligned(offset, kInstructionSize)); |
| 977 | return offset >> kInstructionSizeLog2; |
| 978 | } |
| 979 | |
| 980 | |
| 981 | Instr Assembler::Flags(FlagsUpdate S) { |
| 982 | if (S == SetFlags) { |
| 983 | return 1 << FlagsUpdate_offset; |
| 984 | } else if (S == LeaveFlags) { |
| 985 | return 0 << FlagsUpdate_offset; |
| 986 | } |
| 987 | UNREACHABLE(); |
| 988 | return 0; |
| 989 | } |
| 990 | |
| 991 | |
| 992 | Instr Assembler::Cond(Condition cond) { |
| 993 | return cond << Condition_offset; |
| 994 | } |
| 995 | |
| 996 | |
| 997 | Instr Assembler::ImmPCRelAddress(int imm21) { |
| 998 | CHECK(is_int21(imm21)); |
| 999 | Instr imm = static_cast<Instr>(truncate_to_int21(imm21)); |
| 1000 | Instr immhi = (imm >> ImmPCRelLo_width) << ImmPCRelHi_offset; |
| 1001 | Instr immlo = imm << ImmPCRelLo_offset; |
| 1002 | return (immhi & ImmPCRelHi_mask) | (immlo & ImmPCRelLo_mask); |
| 1003 | } |
| 1004 | |
| 1005 | |
| 1006 | Instr Assembler::ImmUncondBranch(int imm26) { |
| 1007 | CHECK(is_int26(imm26)); |
| 1008 | return truncate_to_int26(imm26) << ImmUncondBranch_offset; |
| 1009 | } |
| 1010 | |
| 1011 | |
| 1012 | Instr Assembler::ImmCondBranch(int imm19) { |
| 1013 | CHECK(is_int19(imm19)); |
| 1014 | return truncate_to_int19(imm19) << ImmCondBranch_offset; |
| 1015 | } |
| 1016 | |
| 1017 | |
| 1018 | Instr Assembler::ImmCmpBranch(int imm19) { |
| 1019 | CHECK(is_int19(imm19)); |
| 1020 | return truncate_to_int19(imm19) << ImmCmpBranch_offset; |
| 1021 | } |
| 1022 | |
| 1023 | |
| 1024 | Instr Assembler::ImmTestBranch(int imm14) { |
| 1025 | CHECK(is_int14(imm14)); |
| 1026 | return truncate_to_int14(imm14) << ImmTestBranch_offset; |
| 1027 | } |
| 1028 | |
| 1029 | |
| 1030 | Instr Assembler::ImmTestBranchBit(unsigned bit_pos) { |
| 1031 | DCHECK(is_uint6(bit_pos)); |
| 1032 | // Subtract five from the shift offset, as we need bit 5 from bit_pos. |
| 1033 | unsigned b5 = bit_pos << (ImmTestBranchBit5_offset - 5); |
| 1034 | unsigned b40 = bit_pos << ImmTestBranchBit40_offset; |
| 1035 | b5 &= ImmTestBranchBit5_mask; |
| 1036 | b40 &= ImmTestBranchBit40_mask; |
| 1037 | return b5 | b40; |
| 1038 | } |
| 1039 | |
| 1040 | |
| 1041 | Instr Assembler::SF(Register rd) { |
| 1042 | return rd.Is64Bits() ? SixtyFourBits : ThirtyTwoBits; |
| 1043 | } |
| 1044 | |
| 1045 | |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 1046 | Instr Assembler::ImmAddSub(int imm) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1047 | DCHECK(IsImmAddSub(imm)); |
| 1048 | if (is_uint12(imm)) { // No shift required. |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 1049 | imm <<= ImmAddSub_offset; |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1050 | } else { |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 1051 | imm = ((imm >> 12) << ImmAddSub_offset) | (1 << ShiftAddSub_offset); |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1052 | } |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 1053 | return imm; |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1054 | } |
| 1055 | |
| 1056 | |
| 1057 | Instr Assembler::ImmS(unsigned imms, unsigned reg_size) { |
| 1058 | DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(imms)) || |
| 1059 | ((reg_size == kWRegSizeInBits) && is_uint5(imms))); |
| 1060 | USE(reg_size); |
| 1061 | return imms << ImmS_offset; |
| 1062 | } |
| 1063 | |
| 1064 | |
| 1065 | Instr Assembler::ImmR(unsigned immr, unsigned reg_size) { |
| 1066 | DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(immr)) || |
| 1067 | ((reg_size == kWRegSizeInBits) && is_uint5(immr))); |
| 1068 | USE(reg_size); |
| 1069 | DCHECK(is_uint6(immr)); |
| 1070 | return immr << ImmR_offset; |
| 1071 | } |
| 1072 | |
| 1073 | |
| 1074 | Instr Assembler::ImmSetBits(unsigned imms, unsigned reg_size) { |
| 1075 | DCHECK((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits)); |
| 1076 | DCHECK(is_uint6(imms)); |
| 1077 | DCHECK((reg_size == kXRegSizeInBits) || is_uint6(imms + 3)); |
| 1078 | USE(reg_size); |
| 1079 | return imms << ImmSetBits_offset; |
| 1080 | } |
| 1081 | |
| 1082 | |
| 1083 | Instr Assembler::ImmRotate(unsigned immr, unsigned reg_size) { |
| 1084 | DCHECK((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits)); |
| 1085 | DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(immr)) || |
| 1086 | ((reg_size == kWRegSizeInBits) && is_uint5(immr))); |
| 1087 | USE(reg_size); |
| 1088 | return immr << ImmRotate_offset; |
| 1089 | } |
| 1090 | |
| 1091 | |
| 1092 | Instr Assembler::ImmLLiteral(int imm19) { |
| 1093 | CHECK(is_int19(imm19)); |
| 1094 | return truncate_to_int19(imm19) << ImmLLiteral_offset; |
| 1095 | } |
| 1096 | |
| 1097 | |
| 1098 | Instr Assembler::BitN(unsigned bitn, unsigned reg_size) { |
| 1099 | DCHECK((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits)); |
| 1100 | DCHECK((reg_size == kXRegSizeInBits) || (bitn == 0)); |
| 1101 | USE(reg_size); |
| 1102 | return bitn << BitN_offset; |
| 1103 | } |
| 1104 | |
| 1105 | |
| 1106 | Instr Assembler::ShiftDP(Shift shift) { |
| 1107 | DCHECK(shift == LSL || shift == LSR || shift == ASR || shift == ROR); |
| 1108 | return shift << ShiftDP_offset; |
| 1109 | } |
| 1110 | |
| 1111 | |
| 1112 | Instr Assembler::ImmDPShift(unsigned amount) { |
| 1113 | DCHECK(is_uint6(amount)); |
| 1114 | return amount << ImmDPShift_offset; |
| 1115 | } |
| 1116 | |
| 1117 | |
| 1118 | Instr Assembler::ExtendMode(Extend extend) { |
| 1119 | return extend << ExtendMode_offset; |
| 1120 | } |
| 1121 | |
| 1122 | |
| 1123 | Instr Assembler::ImmExtendShift(unsigned left_shift) { |
| 1124 | DCHECK(left_shift <= 4); |
| 1125 | return left_shift << ImmExtendShift_offset; |
| 1126 | } |
| 1127 | |
| 1128 | |
| 1129 | Instr Assembler::ImmCondCmp(unsigned imm) { |
| 1130 | DCHECK(is_uint5(imm)); |
| 1131 | return imm << ImmCondCmp_offset; |
| 1132 | } |
| 1133 | |
| 1134 | |
| 1135 | Instr Assembler::Nzcv(StatusFlags nzcv) { |
| 1136 | return ((nzcv >> Flags_offset) & 0xf) << Nzcv_offset; |
| 1137 | } |
| 1138 | |
| 1139 | |
| 1140 | Instr Assembler::ImmLSUnsigned(int imm12) { |
| 1141 | DCHECK(is_uint12(imm12)); |
| 1142 | return imm12 << ImmLSUnsigned_offset; |
| 1143 | } |
| 1144 | |
| 1145 | |
| 1146 | Instr Assembler::ImmLS(int imm9) { |
| 1147 | DCHECK(is_int9(imm9)); |
| 1148 | return truncate_to_int9(imm9) << ImmLS_offset; |
| 1149 | } |
| 1150 | |
| 1151 | |
| 1152 | Instr Assembler::ImmLSPair(int imm7, LSDataSize size) { |
| 1153 | DCHECK(((imm7 >> size) << size) == imm7); |
| 1154 | int scaled_imm7 = imm7 >> size; |
| 1155 | DCHECK(is_int7(scaled_imm7)); |
| 1156 | return truncate_to_int7(scaled_imm7) << ImmLSPair_offset; |
| 1157 | } |
| 1158 | |
| 1159 | |
| 1160 | Instr Assembler::ImmShiftLS(unsigned shift_amount) { |
| 1161 | DCHECK(is_uint1(shift_amount)); |
| 1162 | return shift_amount << ImmShiftLS_offset; |
| 1163 | } |
| 1164 | |
| 1165 | |
| 1166 | Instr Assembler::ImmException(int imm16) { |
| 1167 | DCHECK(is_uint16(imm16)); |
| 1168 | return imm16 << ImmException_offset; |
| 1169 | } |
| 1170 | |
| 1171 | |
| 1172 | Instr Assembler::ImmSystemRegister(int imm15) { |
| 1173 | DCHECK(is_uint15(imm15)); |
| 1174 | return imm15 << ImmSystemRegister_offset; |
| 1175 | } |
| 1176 | |
| 1177 | |
| 1178 | Instr Assembler::ImmHint(int imm7) { |
| 1179 | DCHECK(is_uint7(imm7)); |
| 1180 | return imm7 << ImmHint_offset; |
| 1181 | } |
| 1182 | |
| 1183 | |
| 1184 | Instr Assembler::ImmBarrierDomain(int imm2) { |
| 1185 | DCHECK(is_uint2(imm2)); |
| 1186 | return imm2 << ImmBarrierDomain_offset; |
| 1187 | } |
| 1188 | |
| 1189 | |
| 1190 | Instr Assembler::ImmBarrierType(int imm2) { |
| 1191 | DCHECK(is_uint2(imm2)); |
| 1192 | return imm2 << ImmBarrierType_offset; |
| 1193 | } |
| 1194 | |
| 1195 | |
| 1196 | LSDataSize Assembler::CalcLSDataSize(LoadStoreOp op) { |
| 1197 | DCHECK((SizeLS_offset + SizeLS_width) == (kInstructionSize * 8)); |
| 1198 | return static_cast<LSDataSize>(op >> SizeLS_offset); |
| 1199 | } |
| 1200 | |
| 1201 | |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 1202 | Instr Assembler::ImmMoveWide(int imm) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1203 | DCHECK(is_uint16(imm)); |
| 1204 | return imm << ImmMoveWide_offset; |
| 1205 | } |
| 1206 | |
| 1207 | |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 1208 | Instr Assembler::ShiftMoveWide(int shift) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1209 | DCHECK(is_uint2(shift)); |
| 1210 | return shift << ShiftMoveWide_offset; |
| 1211 | } |
| 1212 | |
| 1213 | |
| 1214 | Instr Assembler::FPType(FPRegister fd) { |
| 1215 | return fd.Is64Bits() ? FP64 : FP32; |
| 1216 | } |
| 1217 | |
| 1218 | |
| 1219 | Instr Assembler::FPScale(unsigned scale) { |
| 1220 | DCHECK(is_uint6(scale)); |
| 1221 | return scale << FPScale_offset; |
| 1222 | } |
| 1223 | |
| 1224 | |
| 1225 | const Register& Assembler::AppropriateZeroRegFor(const CPURegister& reg) const { |
| 1226 | return reg.Is64Bits() ? xzr : wzr; |
| 1227 | } |
| 1228 | |
| 1229 | |
| 1230 | inline void Assembler::CheckBufferSpace() { |
| 1231 | DCHECK(pc_ < (buffer_ + buffer_size_)); |
| 1232 | if (buffer_space() < kGap) { |
| 1233 | GrowBuffer(); |
| 1234 | } |
| 1235 | } |
| 1236 | |
| 1237 | |
| 1238 | inline void Assembler::CheckBuffer() { |
| 1239 | CheckBufferSpace(); |
| 1240 | if (pc_offset() >= next_veneer_pool_check_) { |
| 1241 | CheckVeneerPool(false, true); |
| 1242 | } |
| 1243 | if (pc_offset() >= next_constant_pool_check_) { |
| 1244 | CheckConstPool(false, true); |
| 1245 | } |
| 1246 | } |
| 1247 | |
| 1248 | |
| 1249 | TypeFeedbackId Assembler::RecordedAstId() { |
| 1250 | DCHECK(!recorded_ast_id_.IsNone()); |
| 1251 | return recorded_ast_id_; |
| 1252 | } |
| 1253 | |
| 1254 | |
| 1255 | void Assembler::ClearRecordedAstId() { |
| 1256 | recorded_ast_id_ = TypeFeedbackId::None(); |
| 1257 | } |
| 1258 | |
| 1259 | |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 1260 | } // namespace internal |
| 1261 | } // namespace v8 |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1262 | |
| 1263 | #endif // V8_ARM64_ASSEMBLER_ARM64_INL_H_ |