Leon Clarke | d91b9f7 | 2010-01-27 17:25:45 +0000 | [diff] [blame] | 1 | // Copyright 2010 the V8 project authors. All rights reserved. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 2 | // Redistribution and use in source and binary forms, with or without |
| 3 | // modification, are permitted provided that the following conditions are |
| 4 | // met: |
| 5 | // |
| 6 | // * Redistributions of source code must retain the above copyright |
| 7 | // notice, this list of conditions and the following disclaimer. |
| 8 | // * Redistributions in binary form must reproduce the above |
| 9 | // copyright notice, this list of conditions and the following |
| 10 | // disclaimer in the documentation and/or other materials provided |
| 11 | // with the distribution. |
| 12 | // * Neither the name of Google Inc. nor the names of its |
| 13 | // contributors may be used to endorse or promote products derived |
| 14 | // from this software without specific prior written permission. |
| 15 | // |
| 16 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 17 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 18 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 19 | // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 20 | // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 21 | // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 22 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 23 | // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 24 | // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 25 | // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 26 | // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | |
| 28 | #ifndef V8_ARM_CONSTANTS_ARM_H_ |
| 29 | #define V8_ARM_CONSTANTS_ARM_H_ |
| 30 | |
| 31 | // The simulator emulates the EABI so we define the USE_ARM_EABI macro if we |
| 32 | // are not running on real ARM hardware. One reason for this is that the |
| 33 | // old ABI uses fp registers in the calling convention and the simulator does |
| 34 | // not simulate fp registers or coroutine instructions. |
| 35 | #if defined(__ARM_EABI__) || !defined(__arm__) |
| 36 | # define USE_ARM_EABI 1 |
| 37 | #endif |
| 38 | |
| 39 | // This means that interwork-compatible jump instructions are generated. We |
| 40 | // want to generate them on the simulator too so it makes snapshots that can |
| 41 | // be used on real hardware. |
| 42 | #if defined(__THUMB_INTERWORK__) || !defined(__arm__) |
| 43 | # define USE_THUMB_INTERWORK 1 |
| 44 | #endif |
| 45 | |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 46 | #if defined(__ARM_ARCH_7A__) || \ |
| 47 | defined(__ARM_ARCH_7R__) || \ |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 48 | defined(__ARM_ARCH_7__) |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 49 | # define CAN_USE_ARMV7_INSTRUCTIONS 1 |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 50 | #endif |
| 51 | |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 52 | #if defined(__ARM_ARCH_6__) || \ |
| 53 | defined(__ARM_ARCH_6J__) || \ |
| 54 | defined(__ARM_ARCH_6K__) || \ |
| 55 | defined(__ARM_ARCH_6Z__) || \ |
| 56 | defined(__ARM_ARCH_6ZK__) || \ |
| 57 | defined(__ARM_ARCH_6T2__) || \ |
| 58 | defined(CAN_USE_ARMV7_INSTRUCTIONS) |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 59 | # define CAN_USE_ARMV6_INSTRUCTIONS 1 |
| 60 | #endif |
| 61 | |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 62 | #if defined(__ARM_ARCH_5T__) || \ |
| 63 | defined(__ARM_ARCH_5TE__) || \ |
| 64 | defined(CAN_USE_ARMV6_INSTRUCTIONS) |
| 65 | # define CAN_USE_ARMV5_INSTRUCTIONS 1 |
| 66 | # define CAN_USE_THUMB_INSTRUCTIONS 1 |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 67 | #endif |
| 68 | |
Ben Murdoch | 7f4d5bd | 2010-06-15 11:15:29 +0100 | [diff] [blame] | 69 | // Simulator should support ARM5 instructions and unaligned access by default. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 70 | #if !defined(__arm__) |
| 71 | # define CAN_USE_ARMV5_INSTRUCTIONS 1 |
| 72 | # define CAN_USE_THUMB_INSTRUCTIONS 1 |
Ben Murdoch | 7f4d5bd | 2010-06-15 11:15:29 +0100 | [diff] [blame] | 73 | |
| 74 | # ifndef CAN_USE_UNALIGNED_ACCESSES |
| 75 | # define CAN_USE_UNALIGNED_ACCESSES 1 |
| 76 | # endif |
| 77 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 78 | #endif |
| 79 | |
Kristian Monsen | 25f6136 | 2010-05-21 11:50:48 +0100 | [diff] [blame] | 80 | #if CAN_USE_UNALIGNED_ACCESSES |
| 81 | #define V8_TARGET_CAN_READ_UNALIGNED 1 |
| 82 | #endif |
| 83 | |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 84 | // Using blx may yield better code, so use it when required or when available |
| 85 | #if defined(USE_THUMB_INTERWORK) || defined(CAN_USE_ARMV5_INSTRUCTIONS) |
| 86 | #define USE_BLX 1 |
| 87 | #endif |
| 88 | |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 89 | namespace v8 { |
| 90 | namespace internal { |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 91 | |
| 92 | // Number of registers in normal ARM mode. |
| 93 | static const int kNumRegisters = 16; |
| 94 | |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 95 | // VFP support. |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 96 | static const int kNumVFPSingleRegisters = 32; |
| 97 | static const int kNumVFPDoubleRegisters = 16; |
| 98 | static const int kNumVFPRegisters = |
| 99 | kNumVFPSingleRegisters + kNumVFPDoubleRegisters; |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 100 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 101 | // PC is register 15. |
| 102 | static const int kPCRegister = 15; |
| 103 | static const int kNoRegister = -1; |
| 104 | |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 105 | // ----------------------------------------------------------------------------- |
| 106 | // Conditions. |
| 107 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 108 | // Defines constants and accessor classes to assemble, disassemble and |
| 109 | // simulate ARM instructions. |
| 110 | // |
| 111 | // Section references in the code refer to the "ARM Architecture Reference |
| 112 | // Manual" from July 2005 (available at http://www.arm.com/miscPDFs/14128.pdf) |
| 113 | // |
| 114 | // Constants for specific fields are defined in their respective named enums. |
| 115 | // General constants are in an anonymous enum in class Instr. |
| 116 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 117 | // Values for the condition field as defined in section A3.2 |
| 118 | enum Condition { |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 119 | kNoCondition = -1, |
| 120 | |
| 121 | eq = 0 << 28, // Z set Equal. |
| 122 | ne = 1 << 28, // Z clear Not equal. |
| 123 | cs = 2 << 28, // C set Unsigned higher or same. |
| 124 | cc = 3 << 28, // C clear Unsigned lower. |
| 125 | mi = 4 << 28, // N set Negative. |
| 126 | pl = 5 << 28, // N clear Positive or zero. |
| 127 | vs = 6 << 28, // V set Overflow. |
| 128 | vc = 7 << 28, // V clear No overflow. |
| 129 | hi = 8 << 28, // C set, Z clear Unsigned higher. |
| 130 | ls = 9 << 28, // C clear or Z set Unsigned lower or same. |
| 131 | ge = 10 << 28, // N == V Greater or equal. |
| 132 | lt = 11 << 28, // N != V Less than. |
| 133 | gt = 12 << 28, // Z clear, N == V Greater than. |
| 134 | le = 13 << 28, // Z set or N != V Less then or equal |
| 135 | al = 14 << 28, // Always. |
| 136 | |
| 137 | kSpecialCondition = 15 << 28, // Special condition (refer to section A3.2.1). |
| 138 | kNumberOfConditions = 16, |
| 139 | |
| 140 | // Aliases. |
| 141 | hs = cs, // C set Unsigned higher or same. |
| 142 | lo = cc // C clear Unsigned lower. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 143 | }; |
| 144 | |
| 145 | |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 146 | inline Condition NegateCondition(Condition cond) { |
| 147 | ASSERT(cond != al); |
| 148 | return static_cast<Condition>(cond ^ ne); |
| 149 | } |
| 150 | |
| 151 | |
| 152 | // Corresponds to transposing the operands of a comparison. |
| 153 | inline Condition ReverseCondition(Condition cond) { |
| 154 | switch (cond) { |
| 155 | case lo: |
| 156 | return hi; |
| 157 | case hi: |
| 158 | return lo; |
| 159 | case hs: |
| 160 | return ls; |
| 161 | case ls: |
| 162 | return hs; |
| 163 | case lt: |
| 164 | return gt; |
| 165 | case gt: |
| 166 | return lt; |
| 167 | case ge: |
| 168 | return le; |
| 169 | case le: |
| 170 | return ge; |
| 171 | default: |
| 172 | return cond; |
| 173 | }; |
| 174 | } |
| 175 | |
| 176 | |
| 177 | // ----------------------------------------------------------------------------- |
| 178 | // Instructions encoding. |
| 179 | |
| 180 | // Instr is merely used by the Assembler to distinguish 32bit integers |
| 181 | // representing instructions from usual 32 bit values. |
| 182 | // Instruction objects are pointers to 32bit values, and provide methods to |
| 183 | // access the various ISA fields. |
| 184 | typedef int32_t Instr; |
| 185 | |
| 186 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 187 | // Opcodes for Data-processing instructions (instructions with a type 0 and 1) |
| 188 | // as defined in section A3.4 |
| 189 | enum Opcode { |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 190 | AND = 0 << 21, // Logical AND. |
| 191 | EOR = 1 << 21, // Logical Exclusive OR. |
| 192 | SUB = 2 << 21, // Subtract. |
| 193 | RSB = 3 << 21, // Reverse Subtract. |
| 194 | ADD = 4 << 21, // Add. |
| 195 | ADC = 5 << 21, // Add with Carry. |
| 196 | SBC = 6 << 21, // Subtract with Carry. |
| 197 | RSC = 7 << 21, // Reverse Subtract with Carry. |
| 198 | TST = 8 << 21, // Test. |
| 199 | TEQ = 9 << 21, // Test Equivalence. |
| 200 | CMP = 10 << 21, // Compare. |
| 201 | CMN = 11 << 21, // Compare Negated. |
| 202 | ORR = 12 << 21, // Logical (inclusive) OR. |
| 203 | MOV = 13 << 21, // Move. |
| 204 | BIC = 14 << 21, // Bit Clear. |
| 205 | MVN = 15 << 21 // Move Not. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 206 | }; |
| 207 | |
| 208 | |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 209 | // The bits for bit 7-4 for some type 0 miscellaneous instructions. |
| 210 | enum MiscInstructionsBits74 { |
| 211 | // With bits 22-21 01. |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 212 | BX = 1 << 4, |
| 213 | BXJ = 2 << 4, |
| 214 | BLX = 3 << 4, |
| 215 | BKPT = 7 << 4, |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 216 | |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 217 | // With bits 22-21 11. |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 218 | CLZ = 1 << 4 |
| 219 | }; |
| 220 | |
| 221 | |
| 222 | // Instruction encoding bits and masks. |
| 223 | enum { |
| 224 | H = 1 << 5, // Halfword (or byte). |
| 225 | S6 = 1 << 6, // Signed (or unsigned). |
| 226 | L = 1 << 20, // Load (or store). |
| 227 | S = 1 << 20, // Set condition code (or leave unchanged). |
| 228 | W = 1 << 21, // Writeback base register (or leave unchanged). |
| 229 | A = 1 << 21, // Accumulate in multiply instruction (or not). |
| 230 | B = 1 << 22, // Unsigned byte (or word). |
| 231 | N = 1 << 22, // Long (or short). |
| 232 | U = 1 << 23, // Positive (or negative) offset/index. |
| 233 | P = 1 << 24, // Offset/pre-indexed addressing (or post-indexed addressing). |
| 234 | I = 1 << 25, // Immediate shifter operand (or not). |
| 235 | |
| 236 | B4 = 1 << 4, |
| 237 | B5 = 1 << 5, |
| 238 | B6 = 1 << 6, |
| 239 | B7 = 1 << 7, |
| 240 | B8 = 1 << 8, |
| 241 | B9 = 1 << 9, |
| 242 | B12 = 1 << 12, |
| 243 | B16 = 1 << 16, |
| 244 | B18 = 1 << 18, |
| 245 | B19 = 1 << 19, |
| 246 | B20 = 1 << 20, |
| 247 | B21 = 1 << 21, |
| 248 | B22 = 1 << 22, |
| 249 | B23 = 1 << 23, |
| 250 | B24 = 1 << 24, |
| 251 | B25 = 1 << 25, |
| 252 | B26 = 1 << 26, |
| 253 | B27 = 1 << 27, |
| 254 | B28 = 1 << 28, |
| 255 | |
| 256 | // Instruction bit masks. |
| 257 | kCondMask = 15 << 28, |
| 258 | kALUMask = 0x6f << 21, |
| 259 | kRdMask = 15 << 12, // In str instruction. |
| 260 | kCoprocessorMask = 15 << 8, |
| 261 | kOpCodeMask = 15 << 21, // In data-processing instructions. |
| 262 | kImm24Mask = (1 << 24) - 1, |
| 263 | kOff12Mask = (1 << 12) - 1 |
| 264 | }; |
| 265 | |
| 266 | |
| 267 | // ----------------------------------------------------------------------------- |
| 268 | // Addressing modes and instruction variants. |
| 269 | |
| 270 | // Condition code updating mode. |
| 271 | enum SBit { |
| 272 | SetCC = 1 << 20, // Set condition code. |
| 273 | LeaveCC = 0 << 20 // Leave condition code unchanged. |
| 274 | }; |
| 275 | |
| 276 | |
| 277 | // Status register selection. |
| 278 | enum SRegister { |
| 279 | CPSR = 0 << 22, |
| 280 | SPSR = 1 << 22 |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 281 | }; |
| 282 | |
| 283 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 284 | // Shifter types for Data-processing operands as defined in section A5.1.2. |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 285 | enum ShiftOp { |
| 286 | LSL = 0 << 5, // Logical shift left. |
| 287 | LSR = 1 << 5, // Logical shift right. |
| 288 | ASR = 2 << 5, // Arithmetic shift right. |
| 289 | ROR = 3 << 5, // Rotate right. |
| 290 | |
| 291 | // RRX is encoded as ROR with shift_imm == 0. |
| 292 | // Use a special code to make the distinction. The RRX ShiftOp is only used |
| 293 | // as an argument, and will never actually be encoded. The Assembler will |
| 294 | // detect it and emit the correct ROR shift operand with shift_imm == 0. |
| 295 | RRX = -1, |
| 296 | kNumberOfShifts = 4 |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 297 | }; |
| 298 | |
| 299 | |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 300 | // Status register fields. |
| 301 | enum SRegisterField { |
| 302 | CPSR_c = CPSR | 1 << 16, |
| 303 | CPSR_x = CPSR | 1 << 17, |
| 304 | CPSR_s = CPSR | 1 << 18, |
| 305 | CPSR_f = CPSR | 1 << 19, |
| 306 | SPSR_c = SPSR | 1 << 16, |
| 307 | SPSR_x = SPSR | 1 << 17, |
| 308 | SPSR_s = SPSR | 1 << 18, |
| 309 | SPSR_f = SPSR | 1 << 19 |
| 310 | }; |
| 311 | |
| 312 | // Status register field mask (or'ed SRegisterField enum values). |
| 313 | typedef uint32_t SRegisterFieldMask; |
| 314 | |
| 315 | |
| 316 | // Memory operand addressing mode. |
| 317 | enum AddrMode { |
| 318 | // Bit encoding P U W. |
| 319 | Offset = (8|4|0) << 21, // Offset (without writeback to base). |
| 320 | PreIndex = (8|4|1) << 21, // Pre-indexed addressing with writeback. |
| 321 | PostIndex = (0|4|0) << 21, // Post-indexed addressing with writeback. |
| 322 | NegOffset = (8|0|0) << 21, // Negative offset (without writeback to base). |
| 323 | NegPreIndex = (8|0|1) << 21, // Negative pre-indexed with writeback. |
| 324 | NegPostIndex = (0|0|0) << 21 // Negative post-indexed with writeback. |
| 325 | }; |
| 326 | |
| 327 | |
| 328 | // Load/store multiple addressing mode. |
| 329 | enum BlockAddrMode { |
| 330 | // Bit encoding P U W . |
| 331 | da = (0|0|0) << 21, // Decrement after. |
| 332 | ia = (0|4|0) << 21, // Increment after. |
| 333 | db = (8|0|0) << 21, // Decrement before. |
| 334 | ib = (8|4|0) << 21, // Increment before. |
| 335 | da_w = (0|0|1) << 21, // Decrement after with writeback to base. |
| 336 | ia_w = (0|4|1) << 21, // Increment after with writeback to base. |
| 337 | db_w = (8|0|1) << 21, // Decrement before with writeback to base. |
| 338 | ib_w = (8|4|1) << 21, // Increment before with writeback to base. |
| 339 | |
| 340 | // Alias modes for comparison when writeback does not matter. |
| 341 | da_x = (0|0|0) << 21, // Decrement after. |
| 342 | ia_x = (0|4|0) << 21, // Increment after. |
| 343 | db_x = (8|0|0) << 21, // Decrement before. |
| 344 | ib_x = (8|4|0) << 21 // Increment before. |
| 345 | }; |
| 346 | |
| 347 | |
| 348 | // Coprocessor load/store operand size. |
| 349 | enum LFlag { |
| 350 | Long = 1 << 22, // Long load/store coprocessor. |
| 351 | Short = 0 << 22 // Short load/store coprocessor. |
| 352 | }; |
| 353 | |
| 354 | |
| 355 | // ----------------------------------------------------------------------------- |
| 356 | // Supervisor Call (svc) specific support. |
| 357 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 358 | // Special Software Interrupt codes when used in the presence of the ARM |
| 359 | // simulator. |
Teng-Hui Zhu | 3e5fa29 | 2010-11-09 16:16:48 -0800 | [diff] [blame] | 360 | // svc (formerly swi) provides a 24bit immediate value. Use bits 22:0 for |
| 361 | // standard SoftwareInterrupCode. Bit 23 is reserved for the stop feature. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 362 | enum SoftwareInterruptCodes { |
| 363 | // transition to C code |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 364 | kCallRtRedirected= 0x10, |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 365 | // break point |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 366 | kBreakpoint= 0x20, |
Teng-Hui Zhu | 3e5fa29 | 2010-11-09 16:16:48 -0800 | [diff] [blame] | 367 | // stop |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 368 | kStopCode = 1 << 23 |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 369 | }; |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 370 | static const uint32_t kStopCodeMask = kStopCode - 1; |
| 371 | static const uint32_t kMaxStopCode = kStopCode - 1; |
| 372 | static const int32_t kDefaultStopCode = -1; |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 373 | |
| 374 | |
Kristian Monsen | 80d68ea | 2010-09-08 11:05:35 +0100 | [diff] [blame] | 375 | // Type of VFP register. Determines register encoding. |
| 376 | enum VFPRegPrecision { |
| 377 | kSinglePrecision = 0, |
| 378 | kDoublePrecision = 1 |
| 379 | }; |
| 380 | |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 381 | |
| 382 | // VFP FPSCR constants. |
| 383 | enum VFPConversionMode { |
| 384 | kFPSCRRounding = 0, |
| 385 | kDefaultRoundToZero = 1 |
Russell Brenner | 90bac25 | 2010-11-18 13:33:46 -0800 | [diff] [blame] | 386 | }; |
Kristian Monsen | 80d68ea | 2010-09-08 11:05:35 +0100 | [diff] [blame] | 387 | |
Ben Murdoch | e0cee9b | 2011-05-25 10:26:03 +0100 | [diff] [blame^] | 388 | // This mask does not include the "inexact" or "input denormal" cumulative |
| 389 | // exceptions flags, because we usually don't want to check for it. |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 390 | static const uint32_t kVFPExceptionMask = 0xf; |
Ben Murdoch | e0cee9b | 2011-05-25 10:26:03 +0100 | [diff] [blame^] | 391 | static const uint32_t kVFPInexactExceptionBit = 1 << 4; |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 392 | static const uint32_t kVFPFlushToZeroMask = 1 << 24; |
| 393 | static const uint32_t kVFPInvalidExceptionBit = 1; |
| 394 | |
| 395 | static const uint32_t kVFPNConditionFlagBit = 1 << 31; |
| 396 | static const uint32_t kVFPZConditionFlagBit = 1 << 30; |
| 397 | static const uint32_t kVFPCConditionFlagBit = 1 << 29; |
| 398 | static const uint32_t kVFPVConditionFlagBit = 1 << 28; |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 399 | |
| 400 | |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 401 | // VFP rounding modes. See ARM DDI 0406B Page A2-29. |
| 402 | enum VFPRoundingMode { |
| 403 | RN = 0 << 22, // Round to Nearest. |
| 404 | RP = 1 << 22, // Round towards Plus Infinity. |
| 405 | RM = 2 << 22, // Round towards Minus Infinity. |
| 406 | RZ = 3 << 22, // Round towards zero. |
| 407 | |
| 408 | // Aliases. |
| 409 | kRoundToNearest = RN, |
| 410 | kRoundToPlusInf = RP, |
| 411 | kRoundToMinusInf = RM, |
| 412 | kRoundToZero = RZ |
| 413 | }; |
| 414 | |
| 415 | static const uint32_t kVFPRoundingModeMask = 3 << 22; |
| 416 | |
Ben Murdoch | e0cee9b | 2011-05-25 10:26:03 +0100 | [diff] [blame^] | 417 | enum CheckForInexactConversion { |
| 418 | kCheckForInexactConversion, |
| 419 | kDontCheckForInexactConversion |
| 420 | }; |
| 421 | |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 422 | // ----------------------------------------------------------------------------- |
| 423 | // Hints. |
| 424 | |
| 425 | // Branch hints are not used on the ARM. They are defined so that they can |
| 426 | // appear in shared function signatures, but will be ignored in ARM |
| 427 | // implementations. |
| 428 | enum Hint { no_hint }; |
| 429 | |
| 430 | // Hints are not used on the arm. Negating is trivial. |
| 431 | inline Hint NegateHint(Hint ignored) { return no_hint; } |
| 432 | |
| 433 | |
| 434 | // ----------------------------------------------------------------------------- |
| 435 | // Specific instructions, constants, and masks. |
| 436 | // These constants are declared in assembler-arm.cc, as they use named registers |
| 437 | // and other constants. |
| 438 | |
| 439 | |
| 440 | // add(sp, sp, 4) instruction (aka Pop()) |
| 441 | extern const Instr kPopInstruction; |
| 442 | |
| 443 | // str(r, MemOperand(sp, 4, NegPreIndex), al) instruction (aka push(r)) |
| 444 | // register r is not encoded. |
| 445 | extern const Instr kPushRegPattern; |
| 446 | |
| 447 | // ldr(r, MemOperand(sp, 4, PostIndex), al) instruction (aka pop(r)) |
| 448 | // register r is not encoded. |
| 449 | extern const Instr kPopRegPattern; |
| 450 | |
| 451 | // mov lr, pc |
| 452 | extern const Instr kMovLrPc; |
| 453 | // ldr rd, [pc, #offset] |
| 454 | extern const Instr kLdrPCMask; |
| 455 | extern const Instr kLdrPCPattern; |
| 456 | // blxcc rm |
| 457 | extern const Instr kBlxRegMask; |
| 458 | |
| 459 | extern const Instr kBlxRegPattern; |
| 460 | |
| 461 | extern const Instr kMovMvnMask; |
| 462 | extern const Instr kMovMvnPattern; |
| 463 | extern const Instr kMovMvnFlip; |
| 464 | extern const Instr kMovLeaveCCMask; |
| 465 | extern const Instr kMovLeaveCCPattern; |
| 466 | extern const Instr kMovwMask; |
| 467 | extern const Instr kMovwPattern; |
| 468 | extern const Instr kMovwLeaveCCFlip; |
| 469 | extern const Instr kCmpCmnMask; |
| 470 | extern const Instr kCmpCmnPattern; |
| 471 | extern const Instr kCmpCmnFlip; |
| 472 | extern const Instr kAddSubFlip; |
| 473 | extern const Instr kAndBicFlip; |
| 474 | |
| 475 | // A mask for the Rd register for push, pop, ldr, str instructions. |
| 476 | extern const Instr kLdrRegFpOffsetPattern; |
| 477 | |
| 478 | extern const Instr kStrRegFpOffsetPattern; |
| 479 | |
| 480 | extern const Instr kLdrRegFpNegOffsetPattern; |
| 481 | |
| 482 | extern const Instr kStrRegFpNegOffsetPattern; |
| 483 | |
| 484 | extern const Instr kLdrStrInstrTypeMask; |
| 485 | extern const Instr kLdrStrInstrArgumentMask; |
| 486 | extern const Instr kLdrStrOffsetMask; |
| 487 | |
| 488 | |
| 489 | // ----------------------------------------------------------------------------- |
| 490 | // Instruction abstraction. |
| 491 | |
| 492 | // The class Instruction enables access to individual fields defined in the ARM |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 493 | // architecture instruction set encoding as described in figure A3-1. |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 494 | // Note that the Assembler uses typedef int32_t Instr. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 495 | // |
| 496 | // Example: Test whether the instruction at ptr does set the condition code |
| 497 | // bits. |
| 498 | // |
| 499 | // bool InstructionSetsConditionCodes(byte* ptr) { |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 500 | // Instruction* instr = Instruction::At(ptr); |
| 501 | // int type = instr->TypeValue(); |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 502 | // return ((type == 0) || (type == 1)) && instr->HasS(); |
| 503 | // } |
| 504 | // |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 505 | class Instruction { |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 506 | public: |
| 507 | enum { |
| 508 | kInstrSize = 4, |
| 509 | kInstrSizeLog2 = 2, |
| 510 | kPCReadOffset = 8 |
| 511 | }; |
| 512 | |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 513 | // Helper macro to define static accessors. |
| 514 | // We use the cast to char* trick to bypass the strict anti-aliasing rules. |
| 515 | #define DECLARE_STATIC_TYPED_ACCESSOR(return_type, Name) \ |
| 516 | static inline return_type Name(Instr instr) { \ |
| 517 | char* temp = reinterpret_cast<char*>(&instr); \ |
| 518 | return reinterpret_cast<Instruction*>(temp)->Name(); \ |
| 519 | } |
| 520 | |
| 521 | #define DECLARE_STATIC_ACCESSOR(Name) DECLARE_STATIC_TYPED_ACCESSOR(int, Name) |
| 522 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 523 | // Get the raw instruction bits. |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 524 | inline Instr InstructionBits() const { |
| 525 | return *reinterpret_cast<const Instr*>(this); |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 526 | } |
| 527 | |
| 528 | // Set the raw instruction bits to value. |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 529 | inline void SetInstructionBits(Instr value) { |
| 530 | *reinterpret_cast<Instr*>(this) = value; |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 531 | } |
| 532 | |
| 533 | // Read one particular bit out of the instruction bits. |
| 534 | inline int Bit(int nr) const { |
| 535 | return (InstructionBits() >> nr) & 1; |
| 536 | } |
| 537 | |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 538 | // Read a bit field's value out of the instruction bits. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 539 | inline int Bits(int hi, int lo) const { |
| 540 | return (InstructionBits() >> lo) & ((2 << (hi - lo)) - 1); |
| 541 | } |
| 542 | |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 543 | // Read a bit field out of the instruction bits. |
| 544 | inline int BitField(int hi, int lo) const { |
| 545 | return InstructionBits() & (((2 << (hi - lo)) - 1) << lo); |
| 546 | } |
| 547 | |
| 548 | // Static support. |
| 549 | |
| 550 | // Read one particular bit out of the instruction bits. |
| 551 | static inline int Bit(Instr instr, int nr) { |
| 552 | return (instr >> nr) & 1; |
| 553 | } |
| 554 | |
| 555 | // Read the value of a bit field out of the instruction bits. |
| 556 | static inline int Bits(Instr instr, int hi, int lo) { |
| 557 | return (instr >> lo) & ((2 << (hi - lo)) - 1); |
| 558 | } |
| 559 | |
| 560 | |
| 561 | // Read a bit field out of the instruction bits. |
| 562 | static inline int BitField(Instr instr, int hi, int lo) { |
| 563 | return instr & (((2 << (hi - lo)) - 1) << lo); |
| 564 | } |
| 565 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 566 | |
| 567 | // Accessors for the different named fields used in the ARM encoding. |
| 568 | // The naming of these accessor corresponds to figure A3-1. |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 569 | // |
| 570 | // Two kind of accessors are declared: |
| 571 | // - <Name>Field() will return the raw field, ie the field's bits at their |
| 572 | // original place in the instruction encoding. |
| 573 | // eg. if instr is the 'addgt r0, r1, r2' instruction, encoded as 0xC0810002 |
| 574 | // ConditionField(instr) will return 0xC0000000. |
| 575 | // - <Name>Value() will return the field value, shifted back to bit 0. |
| 576 | // eg. if instr is the 'addgt r0, r1, r2' instruction, encoded as 0xC0810002 |
| 577 | // ConditionField(instr) will return 0xC. |
| 578 | |
| 579 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 580 | // Generally applicable fields |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 581 | inline Condition ConditionValue() const { |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 582 | return static_cast<Condition>(Bits(31, 28)); |
| 583 | } |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 584 | inline Condition ConditionField() const { |
| 585 | return static_cast<Condition>(BitField(31, 28)); |
| 586 | } |
| 587 | DECLARE_STATIC_TYPED_ACCESSOR(Condition, ConditionValue); |
| 588 | DECLARE_STATIC_TYPED_ACCESSOR(Condition, ConditionField); |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 589 | |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 590 | inline int TypeValue() const { return Bits(27, 25); } |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 591 | |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 592 | inline int RnValue() const { return Bits(19, 16); } |
| 593 | DECLARE_STATIC_ACCESSOR(RnValue); |
| 594 | inline int RdValue() const { return Bits(15, 12); } |
| 595 | DECLARE_STATIC_ACCESSOR(RdValue); |
| 596 | |
| 597 | inline int CoprocessorValue() const { return Bits(11, 8); } |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 598 | // Support for VFP. |
| 599 | // Vn(19-16) | Vd(15-12) | Vm(3-0) |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 600 | inline int VnValue() const { return Bits(19, 16); } |
| 601 | inline int VmValue() const { return Bits(3, 0); } |
| 602 | inline int VdValue() const { return Bits(15, 12); } |
| 603 | inline int NValue() const { return Bit(7); } |
| 604 | inline int MValue() const { return Bit(5); } |
| 605 | inline int DValue() const { return Bit(22); } |
| 606 | inline int RtValue() const { return Bits(15, 12); } |
| 607 | inline int PValue() const { return Bit(24); } |
| 608 | inline int UValue() const { return Bit(23); } |
| 609 | inline int Opc1Value() const { return (Bit(23) << 2) | Bits(21, 20); } |
| 610 | inline int Opc2Value() const { return Bits(19, 16); } |
| 611 | inline int Opc3Value() const { return Bits(7, 6); } |
| 612 | inline int SzValue() const { return Bit(8); } |
| 613 | inline int VLValue() const { return Bit(20); } |
| 614 | inline int VCValue() const { return Bit(8); } |
| 615 | inline int VAValue() const { return Bits(23, 21); } |
| 616 | inline int VBValue() const { return Bits(6, 5); } |
| 617 | inline int VFPNRegValue(VFPRegPrecision pre) { |
| 618 | return VFPGlueRegValue(pre, 16, 7); |
Kristian Monsen | 80d68ea | 2010-09-08 11:05:35 +0100 | [diff] [blame] | 619 | } |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 620 | inline int VFPMRegValue(VFPRegPrecision pre) { |
| 621 | return VFPGlueRegValue(pre, 0, 5); |
Kristian Monsen | 80d68ea | 2010-09-08 11:05:35 +0100 | [diff] [blame] | 622 | } |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 623 | inline int VFPDRegValue(VFPRegPrecision pre) { |
| 624 | return VFPGlueRegValue(pre, 12, 22); |
Kristian Monsen | 80d68ea | 2010-09-08 11:05:35 +0100 | [diff] [blame] | 625 | } |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 626 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 627 | // Fields used in Data processing instructions |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 628 | inline int OpcodeValue() const { |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 629 | return static_cast<Opcode>(Bits(24, 21)); |
| 630 | } |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 631 | inline Opcode OpcodeField() const { |
| 632 | return static_cast<Opcode>(BitField(24, 21)); |
| 633 | } |
| 634 | inline int SValue() const { return Bit(20); } |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 635 | // with register |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 636 | inline int RmValue() const { return Bits(3, 0); } |
| 637 | DECLARE_STATIC_ACCESSOR(RmValue); |
| 638 | inline int ShiftValue() const { return static_cast<ShiftOp>(Bits(6, 5)); } |
| 639 | inline ShiftOp ShiftField() const { |
| 640 | return static_cast<ShiftOp>(BitField(6, 5)); |
| 641 | } |
| 642 | inline int RegShiftValue() const { return Bit(4); } |
| 643 | inline int RsValue() const { return Bits(11, 8); } |
| 644 | inline int ShiftAmountValue() const { return Bits(11, 7); } |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 645 | // with immediate |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 646 | inline int RotateValue() const { return Bits(11, 8); } |
| 647 | inline int Immed8Value() const { return Bits(7, 0); } |
| 648 | inline int Immed4Value() const { return Bits(19, 16); } |
| 649 | inline int ImmedMovwMovtValue() const { |
| 650 | return Immed4Value() << 12 | Offset12Value(); } |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 651 | |
| 652 | // Fields used in Load/Store instructions |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 653 | inline int PUValue() const { return Bits(24, 23); } |
| 654 | inline int PUField() const { return BitField(24, 23); } |
| 655 | inline int BValue() const { return Bit(22); } |
| 656 | inline int WValue() const { return Bit(21); } |
| 657 | inline int LValue() const { return Bit(20); } |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 658 | // with register uses same fields as Data processing instructions above |
| 659 | // with immediate |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 660 | inline int Offset12Value() const { return Bits(11, 0); } |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 661 | // multiple |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 662 | inline int RlistValue() const { return Bits(15, 0); } |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 663 | // extra loads and stores |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 664 | inline int SignValue() const { return Bit(6); } |
| 665 | inline int HValue() const { return Bit(5); } |
| 666 | inline int ImmedHValue() const { return Bits(11, 8); } |
| 667 | inline int ImmedLValue() const { return Bits(3, 0); } |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 668 | |
| 669 | // Fields used in Branch instructions |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 670 | inline int LinkValue() const { return Bit(24); } |
| 671 | inline int SImmed24Value() const { return ((InstructionBits() << 8) >> 8); } |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 672 | |
| 673 | // Fields used in Software interrupt instructions |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 674 | inline SoftwareInterruptCodes SvcValue() const { |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 675 | return static_cast<SoftwareInterruptCodes>(Bits(23, 0)); |
| 676 | } |
| 677 | |
| 678 | // Test for special encodings of type 0 instructions (extra loads and stores, |
| 679 | // as well as multiplications). |
| 680 | inline bool IsSpecialType0() const { return (Bit(7) == 1) && (Bit(4) == 1); } |
| 681 | |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 682 | // Test for miscellaneous instructions encodings of type 0 instructions. |
| 683 | inline bool IsMiscType0() const { return (Bit(24) == 1) |
| 684 | && (Bit(23) == 0) |
| 685 | && (Bit(20) == 0) |
| 686 | && ((Bit(7) == 0)); } |
| 687 | |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 688 | // Test for a stop instruction. |
| 689 | inline bool IsStop() const { |
| 690 | return (TypeValue() == 7) && (Bit(24) == 1) && (SvcValue() >= kStopCode); |
| 691 | } |
| 692 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 693 | // Special accessors that test for existence of a value. |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 694 | inline bool HasS() const { return SValue() == 1; } |
| 695 | inline bool HasB() const { return BValue() == 1; } |
| 696 | inline bool HasW() const { return WValue() == 1; } |
| 697 | inline bool HasL() const { return LValue() == 1; } |
| 698 | inline bool HasU() const { return UValue() == 1; } |
| 699 | inline bool HasSign() const { return SignValue() == 1; } |
| 700 | inline bool HasH() const { return HValue() == 1; } |
| 701 | inline bool HasLink() const { return LinkValue() == 1; } |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 702 | |
Ben Murdoch | 3bec4d2 | 2010-07-22 14:51:16 +0100 | [diff] [blame] | 703 | // Decoding the double immediate in the vmov instruction. |
| 704 | double DoubleImmedVmov() const; |
| 705 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 706 | // Instructions are read of out a code stream. The only way to get a |
| 707 | // reference to an instruction is to convert a pointer. There is no way |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 708 | // to allocate or create instances of class Instruction. |
| 709 | // Use the At(pc) function to create references to Instruction. |
| 710 | static Instruction* At(byte* pc) { |
| 711 | return reinterpret_cast<Instruction*>(pc); |
| 712 | } |
| 713 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 714 | |
| 715 | private: |
Kristian Monsen | 80d68ea | 2010-09-08 11:05:35 +0100 | [diff] [blame] | 716 | // Join split register codes, depending on single or double precision. |
| 717 | // four_bit is the position of the least-significant bit of the four |
| 718 | // bit specifier. one_bit is the position of the additional single bit |
| 719 | // specifier. |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 720 | inline int VFPGlueRegValue(VFPRegPrecision pre, int four_bit, int one_bit) { |
Kristian Monsen | 80d68ea | 2010-09-08 11:05:35 +0100 | [diff] [blame] | 721 | if (pre == kSinglePrecision) { |
| 722 | return (Bits(four_bit + 3, four_bit) << 1) | Bit(one_bit); |
| 723 | } |
| 724 | return (Bit(one_bit) << 4) | Bits(four_bit + 3, four_bit); |
| 725 | } |
| 726 | |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 727 | // We need to prevent the creation of instances of class Instruction. |
| 728 | DISALLOW_IMPLICIT_CONSTRUCTORS(Instruction); |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 729 | }; |
| 730 | |
| 731 | |
| 732 | // Helper functions for converting between register numbers and names. |
| 733 | class Registers { |
| 734 | public: |
| 735 | // Return the name of the register. |
| 736 | static const char* Name(int reg); |
| 737 | |
| 738 | // Lookup the register number for the name provided. |
| 739 | static int Number(const char* name); |
| 740 | |
| 741 | struct RegisterAlias { |
| 742 | int reg; |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 743 | const char* name; |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 744 | }; |
| 745 | |
| 746 | private: |
| 747 | static const char* names_[kNumRegisters]; |
| 748 | static const RegisterAlias aliases_[]; |
| 749 | }; |
| 750 | |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 751 | // Helper functions for converting between VFP register numbers and names. |
| 752 | class VFPRegisters { |
| 753 | public: |
| 754 | // Return the name of the register. |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 755 | static const char* Name(int reg, bool is_double); |
| 756 | |
| 757 | // Lookup the register number for the name provided. |
| 758 | // Set flag pointed by is_double to true if register |
| 759 | // is double-precision. |
| 760 | static int Number(const char* name, bool* is_double); |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 761 | |
| 762 | private: |
| 763 | static const char* names_[kNumVFPRegisters]; |
| 764 | }; |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 765 | |
| 766 | |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 767 | } } // namespace v8::internal |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 768 | |
| 769 | #endif // V8_ARM_CONSTANTS_ARM_H_ |