Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 1 | // Copyright 2014 the V8 project authors. All rights reserved. |
| 2 | // Use of this source code is governed by a BSD-style license that can be |
| 3 | // found in the LICENSE file. |
| 4 | |
| 5 | #ifndef V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_ |
| 6 | #define V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_ |
| 7 | |
| 8 | namespace v8 { |
| 9 | namespace internal { |
| 10 | namespace compiler { |
| 11 | |
| 12 | // PPC-specific opcodes that specify which assembly sequence to emit. |
| 13 | // Most opcodes specify a single instruction. |
| 14 | #define TARGET_ARCH_OPCODE_LIST(V) \ |
| 15 | V(PPC_And) \ |
| 16 | V(PPC_AndComplement) \ |
| 17 | V(PPC_Or) \ |
| 18 | V(PPC_OrComplement) \ |
| 19 | V(PPC_Xor) \ |
| 20 | V(PPC_ShiftLeft32) \ |
| 21 | V(PPC_ShiftLeft64) \ |
Ben Murdoch | da12d29 | 2016-06-02 14:46:10 +0100 | [diff] [blame] | 22 | V(PPC_ShiftLeftPair) \ |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 23 | V(PPC_ShiftRight32) \ |
| 24 | V(PPC_ShiftRight64) \ |
Ben Murdoch | da12d29 | 2016-06-02 14:46:10 +0100 | [diff] [blame] | 25 | V(PPC_ShiftRightPair) \ |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 26 | V(PPC_ShiftRightAlg32) \ |
| 27 | V(PPC_ShiftRightAlg64) \ |
Ben Murdoch | da12d29 | 2016-06-02 14:46:10 +0100 | [diff] [blame] | 28 | V(PPC_ShiftRightAlgPair) \ |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 29 | V(PPC_RotRight32) \ |
| 30 | V(PPC_RotRight64) \ |
| 31 | V(PPC_Not) \ |
| 32 | V(PPC_RotLeftAndMask32) \ |
| 33 | V(PPC_RotLeftAndClear64) \ |
| 34 | V(PPC_RotLeftAndClearLeft64) \ |
| 35 | V(PPC_RotLeftAndClearRight64) \ |
| 36 | V(PPC_Add) \ |
| 37 | V(PPC_AddWithOverflow32) \ |
Ben Murdoch | da12d29 | 2016-06-02 14:46:10 +0100 | [diff] [blame] | 38 | V(PPC_AddPair) \ |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 39 | V(PPC_AddDouble) \ |
| 40 | V(PPC_Sub) \ |
| 41 | V(PPC_SubWithOverflow32) \ |
Ben Murdoch | da12d29 | 2016-06-02 14:46:10 +0100 | [diff] [blame] | 42 | V(PPC_SubPair) \ |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 43 | V(PPC_SubDouble) \ |
| 44 | V(PPC_Mul32) \ |
| 45 | V(PPC_Mul64) \ |
| 46 | V(PPC_MulHigh32) \ |
| 47 | V(PPC_MulHighU32) \ |
Ben Murdoch | da12d29 | 2016-06-02 14:46:10 +0100 | [diff] [blame] | 48 | V(PPC_MulPair) \ |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 49 | V(PPC_MulDouble) \ |
| 50 | V(PPC_Div32) \ |
| 51 | V(PPC_Div64) \ |
| 52 | V(PPC_DivU32) \ |
| 53 | V(PPC_DivU64) \ |
| 54 | V(PPC_DivDouble) \ |
| 55 | V(PPC_Mod32) \ |
| 56 | V(PPC_Mod64) \ |
| 57 | V(PPC_ModU32) \ |
| 58 | V(PPC_ModU64) \ |
| 59 | V(PPC_ModDouble) \ |
| 60 | V(PPC_Neg) \ |
| 61 | V(PPC_NegDouble) \ |
| 62 | V(PPC_SqrtDouble) \ |
| 63 | V(PPC_FloorDouble) \ |
| 64 | V(PPC_CeilDouble) \ |
| 65 | V(PPC_TruncateDouble) \ |
| 66 | V(PPC_RoundDouble) \ |
| 67 | V(PPC_MaxDouble) \ |
| 68 | V(PPC_MinDouble) \ |
| 69 | V(PPC_AbsDouble) \ |
| 70 | V(PPC_Cntlz32) \ |
| 71 | V(PPC_Cntlz64) \ |
| 72 | V(PPC_Popcnt32) \ |
| 73 | V(PPC_Popcnt64) \ |
| 74 | V(PPC_Cmp32) \ |
| 75 | V(PPC_Cmp64) \ |
| 76 | V(PPC_CmpDouble) \ |
| 77 | V(PPC_Tst32) \ |
| 78 | V(PPC_Tst64) \ |
| 79 | V(PPC_Push) \ |
| 80 | V(PPC_PushFrame) \ |
| 81 | V(PPC_StoreToStackSlot) \ |
| 82 | V(PPC_ExtendSignWord8) \ |
| 83 | V(PPC_ExtendSignWord16) \ |
| 84 | V(PPC_ExtendSignWord32) \ |
| 85 | V(PPC_Uint32ToUint64) \ |
| 86 | V(PPC_Int64ToInt32) \ |
| 87 | V(PPC_Int64ToFloat32) \ |
| 88 | V(PPC_Int64ToDouble) \ |
| 89 | V(PPC_Uint64ToFloat32) \ |
| 90 | V(PPC_Uint64ToDouble) \ |
Ben Murdoch | 097c5b2 | 2016-05-18 11:27:45 +0100 | [diff] [blame] | 91 | V(PPC_Int32ToFloat32) \ |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 92 | V(PPC_Int32ToDouble) \ |
Ben Murdoch | 097c5b2 | 2016-05-18 11:27:45 +0100 | [diff] [blame] | 93 | V(PPC_Uint32ToFloat32) \ |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 94 | V(PPC_Uint32ToDouble) \ |
| 95 | V(PPC_Float32ToDouble) \ |
Ben Murdoch | 61f157c | 2016-09-16 13:49:30 +0100 | [diff] [blame] | 96 | V(PPC_Float64SilenceNaN) \ |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 97 | V(PPC_DoubleToInt32) \ |
| 98 | V(PPC_DoubleToUint32) \ |
| 99 | V(PPC_DoubleToInt64) \ |
| 100 | V(PPC_DoubleToUint64) \ |
| 101 | V(PPC_DoubleToFloat32) \ |
| 102 | V(PPC_DoubleExtractLowWord32) \ |
| 103 | V(PPC_DoubleExtractHighWord32) \ |
| 104 | V(PPC_DoubleInsertLowWord32) \ |
| 105 | V(PPC_DoubleInsertHighWord32) \ |
| 106 | V(PPC_DoubleConstruct) \ |
| 107 | V(PPC_BitcastInt32ToFloat32) \ |
| 108 | V(PPC_BitcastFloat32ToInt32) \ |
| 109 | V(PPC_BitcastInt64ToDouble) \ |
| 110 | V(PPC_BitcastDoubleToInt64) \ |
| 111 | V(PPC_LoadWordS8) \ |
| 112 | V(PPC_LoadWordU8) \ |
| 113 | V(PPC_LoadWordS16) \ |
| 114 | V(PPC_LoadWordU16) \ |
| 115 | V(PPC_LoadWordS32) \ |
Ben Murdoch | c561043 | 2016-08-08 18:44:38 +0100 | [diff] [blame] | 116 | V(PPC_LoadWordU32) \ |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 117 | V(PPC_LoadWord64) \ |
| 118 | V(PPC_LoadFloat32) \ |
| 119 | V(PPC_LoadDouble) \ |
| 120 | V(PPC_StoreWord8) \ |
| 121 | V(PPC_StoreWord16) \ |
| 122 | V(PPC_StoreWord32) \ |
| 123 | V(PPC_StoreWord64) \ |
| 124 | V(PPC_StoreFloat32) \ |
| 125 | V(PPC_StoreDouble) |
| 126 | |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 127 | // Addressing modes represent the "shape" of inputs to an instruction. |
| 128 | // Many instructions support multiple addressing modes. Addressing modes |
| 129 | // are encoded into the InstructionCode of the instruction and tell the |
| 130 | // code generator after register allocation which assembler method to call. |
| 131 | // |
| 132 | // We use the following local notation for addressing modes: |
| 133 | // |
| 134 | // R = register |
| 135 | // O = register or stack slot |
| 136 | // D = double register |
| 137 | // I = immediate (handle, external, int32) |
| 138 | // MRI = [register + immediate] |
| 139 | // MRR = [register + register] |
| 140 | #define TARGET_ADDRESSING_MODE_LIST(V) \ |
| 141 | V(MRI) /* [%r0 + K] */ \ |
| 142 | V(MRR) /* [%r0 + %r1] */ |
| 143 | |
| 144 | } // namespace compiler |
| 145 | } // namespace internal |
| 146 | } // namespace v8 |
| 147 | |
| 148 | #endif // V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_ |