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gerrit-public.fairphone.software / fp2-dev / platform / external / v8 / refs/tags/fp2-sibon-18.03.1 / . / src / compiler / x87 / instruction-codes-x87.h
blob: 2b4be3e9e85f9c4868130d03217418a88969fa39 [file] [log] [blame]
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]1// Copyright 2014 the V8 project authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5#ifndef V8_COMPILER_X87_INSTRUCTION_CODES_X87_H_
6#define V8_COMPILER_X87_INSTRUCTION_CODES_X87_H_
7
8#include "src/compiler/instruction.h"
9#include "src/compiler/instruction-codes.h"
10namespace v8 {
11namespace internal {
12namespace compiler {
13
14// X87-specific opcodes that specify which assembly sequence to emit.
15// Most opcodes specify a single instruction.
16#define TARGET_ARCH_OPCODE_LIST(V) \
17 V(X87Add) \
18 V(X87And) \
19 V(X87Cmp) \
Ben Murdochda12d292016-06-02 14:46:10 +0100[diff] [blame]20 V(X87Cmp16) \
21 V(X87Cmp8) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]22 V(X87Test) \
Ben Murdochda12d292016-06-02 14:46:10 +0100[diff] [blame]23 V(X87Test16) \
24 V(X87Test8) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]25 V(X87Or) \
26 V(X87Xor) \
27 V(X87Sub) \
28 V(X87Imul) \
29 V(X87ImulHigh) \
30 V(X87UmulHigh) \
31 V(X87Idiv) \
32 V(X87Udiv) \
33 V(X87Not) \
34 V(X87Neg) \
35 V(X87Shl) \
36 V(X87Shr) \
37 V(X87Sar) \
Ben Murdochda12d292016-06-02 14:46:10 +0100[diff] [blame]38 V(X87AddPair) \
39 V(X87SubPair) \
40 V(X87MulPair) \
41 V(X87ShlPair) \
42 V(X87ShrPair) \
43 V(X87SarPair) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]44 V(X87Ror) \
45 V(X87Lzcnt) \
46 V(X87Popcnt) \
47 V(X87Float32Cmp) \
48 V(X87Float32Add) \
49 V(X87Float32Sub) \
50 V(X87Float32Mul) \
51 V(X87Float32Div) \
52 V(X87Float32Max) \
53 V(X87Float32Min) \
54 V(X87Float32Abs) \
55 V(X87Float32Sqrt) \
56 V(X87Float32Round) \
57 V(X87LoadFloat64Constant) \
58 V(X87Float64Add) \
59 V(X87Float64Sub) \
60 V(X87Float64Mul) \
61 V(X87Float64Div) \
62 V(X87Float64Mod) \
63 V(X87Float64Max) \
64 V(X87Float64Min) \
65 V(X87Float64Abs) \
Ben Murdoch097c5b22016-05-18 11:27:45 +0100[diff] [blame]66 V(X87Int32ToFloat32) \
67 V(X87Uint32ToFloat32) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]68 V(X87Int32ToFloat64) \
69 V(X87Float32ToFloat64) \
70 V(X87Uint32ToFloat64) \
71 V(X87Float64ToInt32) \
Ben Murdoch097c5b22016-05-18 11:27:45 +0100[diff] [blame]72 V(X87Float32ToInt32) \
73 V(X87Float32ToUint32) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]74 V(X87Float64ToFloat32) \
75 V(X87Float64ToUint32) \
76 V(X87Float64ExtractHighWord32) \
77 V(X87Float64ExtractLowWord32) \
78 V(X87Float64InsertHighWord32) \
79 V(X87Float64InsertLowWord32) \
80 V(X87Float64Sqrt) \
81 V(X87Float64Round) \
82 V(X87Float64Cmp) \
Ben Murdoch61f157c2016-09-16 13:49:30 +0100[diff] [blame]83 V(X87Float64SilenceNaN) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]84 V(X87Movsxbl) \
85 V(X87Movzxbl) \
86 V(X87Movb) \
87 V(X87Movsxwl) \
88 V(X87Movzxwl) \
89 V(X87Movw) \
90 V(X87Movl) \
91 V(X87Movss) \
92 V(X87Movsd) \
93 V(X87Lea) \
94 V(X87BitcastFI) \
95 V(X87BitcastIF) \
96 V(X87Push) \
97 V(X87PushFloat64) \
98 V(X87PushFloat32) \
99 V(X87Poke) \
Ben Murdochc5610432016-08-08 18:44:38 +0100[diff] [blame]100 V(X87StackCheck) \
101 V(X87Xchgb) \
102 V(X87Xchgw) \
103 V(X87Xchgl)
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]104
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]105// Addressing modes represent the "shape" of inputs to an instruction.
106// Many instructions support multiple addressing modes. Addressing modes
107// are encoded into the InstructionCode of the instruction and tell the
108// code generator after register allocation which assembler method to call.
109//
110// We use the following local notation for addressing modes:
111//
112// M = memory operand
113// R = base register
114// N = index register * N for N in {1, 2, 4, 8}
115// I = immediate displacement (int32_t)
116
117#define TARGET_ADDRESSING_MODE_LIST(V) \
118 V(MR) /* [%r1 ] */ \
119 V(MRI) /* [%r1 + K] */ \
120 V(MR1) /* [%r1 + %r2*1 ] */ \
121 V(MR2) /* [%r1 + %r2*2 ] */ \
122 V(MR4) /* [%r1 + %r2*4 ] */ \
123 V(MR8) /* [%r1 + %r2*8 ] */ \
124 V(MR1I) /* [%r1 + %r2*1 + K] */ \
125 V(MR2I) /* [%r1 + %r2*2 + K] */ \
126 V(MR4I) /* [%r1 + %r2*3 + K] */ \
127 V(MR8I) /* [%r1 + %r2*4 + K] */ \
128 V(M1) /* [ %r2*1 ] */ \
129 V(M2) /* [ %r2*2 ] */ \
130 V(M4) /* [ %r2*4 ] */ \
131 V(M8) /* [ %r2*8 ] */ \
132 V(M1I) /* [ %r2*1 + K] */ \
133 V(M2I) /* [ %r2*2 + K] */ \
134 V(M4I) /* [ %r2*4 + K] */ \
135 V(M8I) /* [ %r2*8 + K] */ \
136 V(MI) /* [ K] */
137
138} // namespace compiler
139} // namespace internal
140} // namespace v8
141
142#endif // V8_COMPILER_X87_INSTRUCTION_CODES_X87_H_