sewardj | 07133bf | 2002-06-13 10:25:56 +0000 | [diff] [blame] | 1 | |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 2 | /*--------------------------------------------------------------------*/ |
njn | 101e572 | 2005-04-21 02:37:54 +0000 | [diff] [blame] | 3 | /*--- Cachegrind: everything but the simulation itself. ---*/ |
njn25 | cac76cb | 2002-09-23 11:21:57 +0000 | [diff] [blame] | 4 | /*--- cg_main.c ---*/ |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 5 | /*--------------------------------------------------------------------*/ |
| 6 | |
| 7 | /* |
nethercote | 137bc55 | 2003-11-14 17:47:54 +0000 | [diff] [blame] | 8 | This file is part of Cachegrind, a Valgrind tool for cache |
njn | c953984 | 2002-10-02 13:26:35 +0000 | [diff] [blame] | 9 | profiling programs. |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 10 | |
njn | 9f20746 | 2009-03-10 22:02:09 +0000 | [diff] [blame] | 11 | Copyright (C) 2002-2009 Nicholas Nethercote |
njn | 2bc1012 | 2005-05-08 02:10:27 +0000 | [diff] [blame] | 12 | njn@valgrind.org |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 13 | |
| 14 | This program is free software; you can redistribute it and/or |
| 15 | modify it under the terms of the GNU General Public License as |
| 16 | published by the Free Software Foundation; either version 2 of the |
| 17 | License, or (at your option) any later version. |
| 18 | |
| 19 | This program is distributed in the hope that it will be useful, but |
| 20 | WITHOUT ANY WARRANTY; without even the implied warranty of |
| 21 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 22 | General Public License for more details. |
| 23 | |
| 24 | You should have received a copy of the GNU General Public License |
| 25 | along with this program; if not, write to the Free Software |
| 26 | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA |
| 27 | 02111-1307, USA. |
| 28 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 29 | The GNU General Public License is contained in the file COPYING. |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 30 | */ |
| 31 | |
njn | c7561b9 | 2005-06-19 01:24:32 +0000 | [diff] [blame] | 32 | #include "pub_tool_basics.h" |
sewardj | 4cfea4f | 2006-10-14 19:26:10 +0000 | [diff] [blame] | 33 | #include "pub_tool_vki.h" |
njn | ea27e46 | 2005-05-31 02:38:09 +0000 | [diff] [blame] | 34 | #include "pub_tool_debuginfo.h" |
njn | 97405b2 | 2005-06-02 03:39:33 +0000 | [diff] [blame] | 35 | #include "pub_tool_libcbase.h" |
njn | 132bfcc | 2005-06-04 19:16:06 +0000 | [diff] [blame] | 36 | #include "pub_tool_libcassert.h" |
njn | eb8896b | 2005-06-04 20:03:55 +0000 | [diff] [blame] | 37 | #include "pub_tool_libcfile.h" |
njn | 36a20fa | 2005-06-03 03:08:39 +0000 | [diff] [blame] | 38 | #include "pub_tool_libcprint.h" |
njn | f39e9a3 | 2005-06-12 02:43:17 +0000 | [diff] [blame] | 39 | #include "pub_tool_libcproc.h" |
njn | f536bbb | 2005-06-13 04:21:38 +0000 | [diff] [blame] | 40 | #include "pub_tool_machine.h" |
njn | 717cde5 | 2005-05-10 02:47:21 +0000 | [diff] [blame] | 41 | #include "pub_tool_mallocfree.h" |
njn | 2024234 | 2005-05-16 23:31:24 +0000 | [diff] [blame] | 42 | #include "pub_tool_options.h" |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 43 | #include "pub_tool_oset.h" |
njn | 43b9a8a | 2005-05-10 04:37:01 +0000 | [diff] [blame] | 44 | #include "pub_tool_tooliface.h" |
sewardj | 14c7cc5 | 2007-02-25 15:08:24 +0000 | [diff] [blame] | 45 | #include "pub_tool_xarray.h" |
sewardj | 45f4e7c | 2005-09-27 19:20:21 +0000 | [diff] [blame] | 46 | #include "pub_tool_clientstate.h" |
sewardj | 5bb8682 | 2005-12-23 12:47:42 +0000 | [diff] [blame] | 47 | #include "pub_tool_machine.h" // VG_(fnptr_to_fnentry) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 48 | |
nethercote | b35a8b9 | 2004-09-11 16:45:27 +0000 | [diff] [blame] | 49 | #include "cg_arch.h" |
nethercote | 27fc1da | 2004-01-04 16:56:57 +0000 | [diff] [blame] | 50 | #include "cg_sim.c" |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 51 | #include "cg_branchpred.c" |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 52 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 53 | /*------------------------------------------------------------*/ |
| 54 | /*--- Constants ---*/ |
| 55 | /*------------------------------------------------------------*/ |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 56 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 57 | /* Set to 1 for very verbose debugging */ |
| 58 | #define DEBUG_CG 0 |
| 59 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 60 | #define MIN_LINE_SIZE 16 |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 61 | #define FILE_LEN VKI_PATH_MAX |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 62 | #define FN_LEN 256 |
njn | 7cf0bd3 | 2002-06-08 13:36:03 +0000 | [diff] [blame] | 63 | |
| 64 | /*------------------------------------------------------------*/ |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 65 | /*--- Options ---*/ |
| 66 | /*------------------------------------------------------------*/ |
| 67 | |
njn | 374a36d | 2007-11-23 01:41:32 +0000 | [diff] [blame] | 68 | static Bool clo_cache_sim = True; /* do cache simulation? */ |
| 69 | static Bool clo_branch_sim = False; /* do branch simulation? */ |
| 70 | static Char* clo_cachegrind_out_file = "cachegrind.out.%p"; |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 71 | |
| 72 | /*------------------------------------------------------------*/ |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 73 | /*--- Types and Data Structures ---*/ |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 74 | /*------------------------------------------------------------*/ |
| 75 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 76 | typedef |
| 77 | struct { |
| 78 | ULong a; /* total # memory accesses of this kind */ |
| 79 | ULong m1; /* misses in the first level cache */ |
| 80 | ULong m2; /* misses in the second level cache */ |
| 81 | } |
| 82 | CacheCC; |
| 83 | |
| 84 | typedef |
| 85 | struct { |
| 86 | ULong b; /* total # branches of this kind */ |
| 87 | ULong mp; /* number of branches mispredicted */ |
| 88 | } |
| 89 | BranchCC; |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 90 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 91 | //------------------------------------------------------------ |
| 92 | // Primary data structure #1: CC table |
| 93 | // - Holds the per-source-line hit/miss stats, grouped by file/function/line. |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 94 | // - an ordered set of CCs. CC indexing done by file/function/line (as |
| 95 | // determined from the instrAddr). |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 96 | // - Traversed for dumping stats at end in file/func/line hierarchy. |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 97 | |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 98 | typedef struct { |
| 99 | Char* file; |
| 100 | Char* fn; |
| 101 | Int line; |
| 102 | } |
| 103 | CodeLoc; |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 104 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 105 | typedef struct { |
| 106 | CodeLoc loc; /* Source location that these counts pertain to */ |
| 107 | CacheCC Ir; /* Insn read counts */ |
| 108 | CacheCC Dr; /* Data read counts */ |
| 109 | CacheCC Dw; /* Data write/modify counts */ |
| 110 | BranchCC Bc; /* Conditional branch counts */ |
| 111 | BranchCC Bi; /* Indirect branch counts */ |
| 112 | } LineCC; |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 113 | |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 114 | // First compare file, then fn, then line. |
tom | 5a835d5 | 2007-12-30 12:28:26 +0000 | [diff] [blame] | 115 | static Word cmp_CodeLoc_LineCC(const void *vloc, const void *vcc) |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 116 | { |
njn | afa1226 | 2005-12-24 03:10:56 +0000 | [diff] [blame] | 117 | Word res; |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 118 | CodeLoc* a = (CodeLoc*)vloc; |
| 119 | CodeLoc* b = &(((LineCC*)vcc)->loc); |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 120 | |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 121 | res = VG_(strcmp)(a->file, b->file); |
| 122 | if (0 != res) |
| 123 | return res; |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 124 | |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 125 | res = VG_(strcmp)(a->fn, b->fn); |
| 126 | if (0 != res) |
| 127 | return res; |
| 128 | |
| 129 | return a->line - b->line; |
| 130 | } |
| 131 | |
| 132 | static OSet* CC_table; |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 133 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 134 | //------------------------------------------------------------ |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 135 | // Primary data structure #2: InstrInfo table |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 136 | // - Holds the cached info about each instr that is used for simulation. |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 137 | // - table(SB_start_addr, list(InstrInfo)) |
| 138 | // - For each SB, each InstrInfo in the list holds info about the |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 139 | // instruction (instrLen, instrAddr, etc), plus a pointer to its line |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 140 | // CC. This node is what's passed to the simulation function. |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 141 | // - When SBs are discarded the relevant list(instr_details) is freed. |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 142 | |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 143 | typedef struct _InstrInfo InstrInfo; |
| 144 | struct _InstrInfo { |
nethercote | ca1f2dc | 2004-07-21 08:49:02 +0000 | [diff] [blame] | 145 | Addr instr_addr; |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 146 | UChar instr_len; |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 147 | LineCC* parent; // parent line-CC |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 148 | }; |
| 149 | |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 150 | typedef struct _SB_info SB_info; |
| 151 | struct _SB_info { |
| 152 | Addr SB_addr; // key; MUST BE FIRST |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 153 | Int n_instrs; |
| 154 | InstrInfo instrs[0]; |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 155 | }; |
| 156 | |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 157 | static OSet* instrInfoTable; |
| 158 | |
| 159 | //------------------------------------------------------------ |
| 160 | // Secondary data structure: string table |
| 161 | // - holds strings, avoiding dups |
| 162 | // - used for filenames and function names, each of which will be |
| 163 | // pointed to by one or more CCs. |
| 164 | // - it also allows equality checks just by pointer comparison, which |
| 165 | // is good when printing the output file at the end. |
| 166 | |
| 167 | static OSet* stringTable; |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 168 | |
| 169 | //------------------------------------------------------------ |
| 170 | // Stats |
sewardj | 4f29ddf | 2002-05-03 22:29:04 +0000 | [diff] [blame] | 171 | static Int distinct_files = 0; |
| 172 | static Int distinct_fns = 0; |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 173 | static Int distinct_lines = 0; |
sewardj | 4f29ddf | 2002-05-03 22:29:04 +0000 | [diff] [blame] | 174 | static Int distinct_instrs = 0; |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 175 | |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 176 | static Int full_debugs = 0; |
| 177 | static Int file_line_debugs = 0; |
| 178 | static Int fn_debugs = 0; |
| 179 | static Int no_debugs = 0; |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 180 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 181 | /*------------------------------------------------------------*/ |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 182 | /*--- String table operations ---*/ |
| 183 | /*------------------------------------------------------------*/ |
| 184 | |
tom | 5a835d5 | 2007-12-30 12:28:26 +0000 | [diff] [blame] | 185 | static Word stringCmp( const void* key, const void* elem ) |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 186 | { |
| 187 | return VG_(strcmp)(*(Char**)key, *(Char**)elem); |
| 188 | } |
| 189 | |
| 190 | // Get a permanent string; either pull it out of the string table if it's |
| 191 | // been encountered before, or dup it and put it into the string table. |
| 192 | static Char* get_perm_string(Char* s) |
| 193 | { |
njn | e2a9ad3 | 2007-09-17 05:30:48 +0000 | [diff] [blame] | 194 | Char** s_ptr = VG_(OSetGen_Lookup)(stringTable, &s); |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 195 | if (s_ptr) { |
| 196 | return *s_ptr; |
| 197 | } else { |
njn | e2a9ad3 | 2007-09-17 05:30:48 +0000 | [diff] [blame] | 198 | Char** s_node = VG_(OSetGen_AllocNode)(stringTable, sizeof(Char*)); |
sewardj | 9c606bd | 2008-09-18 18:12:50 +0000 | [diff] [blame] | 199 | *s_node = VG_(strdup)("cg.main.gps.1", s); |
njn | e2a9ad3 | 2007-09-17 05:30:48 +0000 | [diff] [blame] | 200 | VG_(OSetGen_Insert)(stringTable, s_node); |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 201 | return *s_node; |
| 202 | } |
| 203 | } |
| 204 | |
| 205 | /*------------------------------------------------------------*/ |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 206 | /*--- CC table operations ---*/ |
| 207 | /*------------------------------------------------------------*/ |
njn | 4294fd4 | 2002-06-05 14:41:10 +0000 | [diff] [blame] | 208 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 209 | static void get_debug_info(Addr instr_addr, Char file[FILE_LEN], |
| 210 | Char fn[FN_LEN], Int* line) |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 211 | { |
njn | f3b61d6 | 2007-09-17 00:41:07 +0000 | [diff] [blame] | 212 | Char dir[FILE_LEN]; |
| 213 | Bool found_dirname; |
sewardj | 7cee6f9 | 2005-06-13 17:39:06 +0000 | [diff] [blame] | 214 | Bool found_file_line = VG_(get_filename_linenum)( |
| 215 | instr_addr, |
| 216 | file, FILE_LEN, |
njn | f3b61d6 | 2007-09-17 00:41:07 +0000 | [diff] [blame] | 217 | dir, FILE_LEN, &found_dirname, |
sewardj | 7cee6f9 | 2005-06-13 17:39:06 +0000 | [diff] [blame] | 218 | line |
| 219 | ); |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 220 | Bool found_fn = VG_(get_fnname)(instr_addr, fn, FN_LEN); |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 221 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 222 | if (!found_file_line) { |
| 223 | VG_(strcpy)(file, "???"); |
| 224 | *line = 0; |
| 225 | } |
| 226 | if (!found_fn) { |
| 227 | VG_(strcpy)(fn, "???"); |
| 228 | } |
njn | f3b61d6 | 2007-09-17 00:41:07 +0000 | [diff] [blame] | 229 | |
| 230 | if (found_dirname) { |
| 231 | // +1 for the '/'. |
| 232 | tl_assert(VG_(strlen)(dir) + VG_(strlen)(file) + 1 < FILE_LEN); |
| 233 | VG_(strcat)(dir, "/"); // Append '/' |
| 234 | VG_(strcat)(dir, file); // Append file to dir |
| 235 | VG_(strcpy)(file, dir); // Move dir+file to file |
| 236 | } |
| 237 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 238 | if (found_file_line) { |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 239 | if (found_fn) full_debugs++; |
| 240 | else file_line_debugs++; |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 241 | } else { |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 242 | if (found_fn) fn_debugs++; |
| 243 | else no_debugs++; |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 244 | } |
| 245 | } |
| 246 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 247 | // Do a three step traversal: by file, then fn, then line. |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 248 | // Returns a pointer to the line CC, creates a new one if necessary. |
| 249 | static LineCC* get_lineCC(Addr origAddr) |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 250 | { |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 251 | Char file[FILE_LEN], fn[FN_LEN]; |
| 252 | Int line; |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 253 | CodeLoc loc; |
| 254 | LineCC* lineCC; |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 255 | |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 256 | get_debug_info(origAddr, file, fn, &line); |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 257 | |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 258 | loc.file = file; |
| 259 | loc.fn = fn; |
| 260 | loc.line = line; |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 261 | |
njn | e2a9ad3 | 2007-09-17 05:30:48 +0000 | [diff] [blame] | 262 | lineCC = VG_(OSetGen_Lookup)(CC_table, &loc); |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 263 | if (!lineCC) { |
| 264 | // Allocate and zero a new node. |
njn | e2a9ad3 | 2007-09-17 05:30:48 +0000 | [diff] [blame] | 265 | lineCC = VG_(OSetGen_AllocNode)(CC_table, sizeof(LineCC)); |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 266 | lineCC->loc.file = get_perm_string(loc.file); |
| 267 | lineCC->loc.fn = get_perm_string(loc.fn); |
| 268 | lineCC->loc.line = loc.line; |
njn | 0a8db5c | 2007-04-02 03:11:41 +0000 | [diff] [blame] | 269 | lineCC->Ir.a = 0; |
| 270 | lineCC->Ir.m1 = 0; |
| 271 | lineCC->Ir.m2 = 0; |
| 272 | lineCC->Dr.a = 0; |
| 273 | lineCC->Dr.m1 = 0; |
| 274 | lineCC->Dr.m2 = 0; |
| 275 | lineCC->Dw.a = 0; |
| 276 | lineCC->Dw.m1 = 0; |
| 277 | lineCC->Dw.m2 = 0; |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 278 | lineCC->Bc.b = 0; |
| 279 | lineCC->Bc.mp = 0; |
| 280 | lineCC->Bi.b = 0; |
| 281 | lineCC->Bi.mp = 0; |
njn | e2a9ad3 | 2007-09-17 05:30:48 +0000 | [diff] [blame] | 282 | VG_(OSetGen_Insert)(CC_table, lineCC); |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 283 | } |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 284 | |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 285 | return lineCC; |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 286 | } |
| 287 | |
| 288 | /*------------------------------------------------------------*/ |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 289 | /*--- Cache simulation functions ---*/ |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 290 | /*------------------------------------------------------------*/ |
| 291 | |
njn | af839f5 | 2005-06-23 03:27:57 +0000 | [diff] [blame] | 292 | static VG_REGPARM(1) |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 293 | void log_1I_0D_cache_access(InstrInfo* n) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 294 | { |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 295 | //VG_(printf)("1I_0D : CCaddr=0x%010lx, iaddr=0x%010lx, isize=%lu\n", |
| 296 | // n, n->instr_addr, n->instr_len); |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 297 | cachesim_I1_doref(n->instr_addr, n->instr_len, |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 298 | &n->parent->Ir.m1, &n->parent->Ir.m2); |
| 299 | n->parent->Ir.a++; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 300 | } |
| 301 | |
njn | af839f5 | 2005-06-23 03:27:57 +0000 | [diff] [blame] | 302 | static VG_REGPARM(2) |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 303 | void log_2I_0D_cache_access(InstrInfo* n, InstrInfo* n2) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 304 | { |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 305 | //VG_(printf)("2I_0D : CC1addr=0x%010lx, i1addr=0x%010lx, i1size=%lu\n" |
| 306 | // " CC2addr=0x%010lx, i2addr=0x%010lx, i2size=%lu\n", |
| 307 | // n, n->instr_addr, n->instr_len, |
| 308 | // n2, n2->instr_addr, n2->instr_len); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 309 | cachesim_I1_doref(n->instr_addr, n->instr_len, |
| 310 | &n->parent->Ir.m1, &n->parent->Ir.m2); |
| 311 | n->parent->Ir.a++; |
| 312 | cachesim_I1_doref(n2->instr_addr, n2->instr_len, |
| 313 | &n2->parent->Ir.m1, &n2->parent->Ir.m2); |
| 314 | n2->parent->Ir.a++; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 315 | } |
| 316 | |
| 317 | static VG_REGPARM(3) |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 318 | void log_3I_0D_cache_access(InstrInfo* n, InstrInfo* n2, InstrInfo* n3) |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 319 | { |
| 320 | //VG_(printf)("3I_0D : CC1addr=0x%010lx, i1addr=0x%010lx, i1size=%lu\n" |
| 321 | // " CC2addr=0x%010lx, i2addr=0x%010lx, i2size=%lu\n" |
| 322 | // " CC3addr=0x%010lx, i3addr=0x%010lx, i3size=%lu\n", |
| 323 | // n, n->instr_addr, n->instr_len, |
| 324 | // n2, n2->instr_addr, n2->instr_len, |
| 325 | // n3, n3->instr_addr, n3->instr_len); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 326 | cachesim_I1_doref(n->instr_addr, n->instr_len, |
| 327 | &n->parent->Ir.m1, &n->parent->Ir.m2); |
| 328 | n->parent->Ir.a++; |
| 329 | cachesim_I1_doref(n2->instr_addr, n2->instr_len, |
| 330 | &n2->parent->Ir.m1, &n2->parent->Ir.m2); |
| 331 | n2->parent->Ir.a++; |
| 332 | cachesim_I1_doref(n3->instr_addr, n3->instr_len, |
| 333 | &n3->parent->Ir.m1, &n3->parent->Ir.m2); |
| 334 | n3->parent->Ir.a++; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 335 | } |
| 336 | |
| 337 | static VG_REGPARM(3) |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 338 | void log_1I_1Dr_cache_access(InstrInfo* n, Addr data_addr, Word data_size) |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 339 | { |
| 340 | //VG_(printf)("1I_1Dr: CCaddr=0x%010lx, iaddr=0x%010lx, isize=%lu\n" |
| 341 | // " daddr=0x%010lx, dsize=%lu\n", |
| 342 | // n, n->instr_addr, n->instr_len, data_addr, data_size); |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 343 | cachesim_I1_doref(n->instr_addr, n->instr_len, |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 344 | &n->parent->Ir.m1, &n->parent->Ir.m2); |
| 345 | n->parent->Ir.a++; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 346 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 347 | cachesim_D1_doref(data_addr, data_size, |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 348 | &n->parent->Dr.m1, &n->parent->Dr.m2); |
| 349 | n->parent->Dr.a++; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 350 | } |
| 351 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 352 | static VG_REGPARM(3) |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 353 | void log_1I_1Dw_cache_access(InstrInfo* n, Addr data_addr, Word data_size) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 354 | { |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 355 | //VG_(printf)("1I_1Dw: CCaddr=0x%010lx, iaddr=0x%010lx, isize=%lu\n" |
| 356 | // " daddr=0x%010lx, dsize=%lu\n", |
| 357 | // n, n->instr_addr, n->instr_len, data_addr, data_size); |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 358 | cachesim_I1_doref(n->instr_addr, n->instr_len, |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 359 | &n->parent->Ir.m1, &n->parent->Ir.m2); |
| 360 | n->parent->Ir.a++; |
| 361 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 362 | cachesim_D1_doref(data_addr, data_size, |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 363 | &n->parent->Dw.m1, &n->parent->Dw.m2); |
| 364 | n->parent->Dw.a++; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 365 | } |
| 366 | |
njn | af839f5 | 2005-06-23 03:27:57 +0000 | [diff] [blame] | 367 | static VG_REGPARM(3) |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 368 | void log_0I_1Dr_cache_access(InstrInfo* n, Addr data_addr, Word data_size) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 369 | { |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 370 | //VG_(printf)("0I_1Dr: CCaddr=0x%010lx, daddr=0x%010lx, dsize=%lu\n", |
| 371 | // n, data_addr, data_size); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 372 | cachesim_D1_doref(data_addr, data_size, |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 373 | &n->parent->Dr.m1, &n->parent->Dr.m2); |
| 374 | n->parent->Dr.a++; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 375 | } |
| 376 | |
| 377 | static VG_REGPARM(3) |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 378 | void log_0I_1Dw_cache_access(InstrInfo* n, Addr data_addr, Word data_size) |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 379 | { |
| 380 | //VG_(printf)("0I_1Dw: CCaddr=0x%010lx, daddr=0x%010lx, dsize=%lu\n", |
| 381 | // n, data_addr, data_size); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 382 | cachesim_D1_doref(data_addr, data_size, |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 383 | &n->parent->Dw.m1, &n->parent->Dw.m2); |
| 384 | n->parent->Dw.a++; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 385 | } |
| 386 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 387 | /* For branches, we consult two different predictors, one which |
| 388 | predicts taken/untaken for conditional branches, and the other |
| 389 | which predicts the branch target address for indirect branches |
| 390 | (jump-to-register style ones). */ |
| 391 | |
| 392 | static VG_REGPARM(2) |
| 393 | void log_cond_branch(InstrInfo* n, Word taken) |
| 394 | { |
| 395 | //VG_(printf)("cbrnch: CCaddr=0x%010lx, taken=0x%010lx\n", |
| 396 | // n, taken); |
| 397 | n->parent->Bc.b++; |
| 398 | n->parent->Bc.mp |
| 399 | += (1 & do_cond_branch_predict(n->instr_addr, taken)); |
| 400 | } |
| 401 | |
| 402 | static VG_REGPARM(2) |
| 403 | void log_ind_branch(InstrInfo* n, UWord actual_dst) |
| 404 | { |
| 405 | //VG_(printf)("ibrnch: CCaddr=0x%010lx, dst=0x%010lx\n", |
| 406 | // n, actual_dst); |
| 407 | n->parent->Bi.b++; |
| 408 | n->parent->Bi.mp |
| 409 | += (1 & do_ind_branch_predict(n->instr_addr, actual_dst)); |
| 410 | } |
| 411 | |
| 412 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 413 | /*------------------------------------------------------------*/ |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 414 | /*--- Instrumentation types and structures ---*/ |
| 415 | /*------------------------------------------------------------*/ |
| 416 | |
| 417 | /* Maintain an ordered list of memory events which are outstanding, in |
| 418 | the sense that no IR has yet been generated to do the relevant |
| 419 | helper calls. The BB is scanned top to bottom and memory events |
| 420 | are added to the end of the list, merging with the most recent |
| 421 | notified event where possible (Dw immediately following Dr and |
| 422 | having the same size and EA can be merged). |
| 423 | |
| 424 | This merging is done so that for architectures which have |
| 425 | load-op-store instructions (x86, amd64), the insn is treated as if |
| 426 | it makes just one memory reference (a modify), rather than two (a |
| 427 | read followed by a write at the same address). |
| 428 | |
| 429 | At various points the list will need to be flushed, that is, IR |
| 430 | generated from it. That must happen before any possible exit from |
| 431 | the block (the end, or an IRStmt_Exit). Flushing also takes place |
| 432 | when there is no space to add a new event. |
| 433 | |
| 434 | If we require the simulation statistics to be up to date with |
| 435 | respect to possible memory exceptions, then the list would have to |
| 436 | be flushed before each memory reference. That would however lose |
| 437 | performance by inhibiting event-merging during flushing. |
| 438 | |
| 439 | Flushing the list consists of walking it start to end and emitting |
| 440 | instrumentation IR for each event, in the order in which they |
| 441 | appear. It may be possible to emit a single call for two adjacent |
| 442 | events in order to reduce the number of helper function calls made. |
| 443 | For example, it could well be profitable to handle two adjacent Ir |
| 444 | events with a single helper call. */ |
| 445 | |
| 446 | typedef |
| 447 | IRExpr |
| 448 | IRAtom; |
| 449 | |
| 450 | typedef |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 451 | enum { |
| 452 | Ev_Ir, // Instruction read |
| 453 | Ev_Dr, // Data read |
| 454 | Ev_Dw, // Data write |
| 455 | Ev_Dm, // Data modify (read then write) |
| 456 | Ev_Bc, // branch conditional |
| 457 | Ev_Bi // branch indirect (to unknown destination) |
| 458 | } |
| 459 | EventTag; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 460 | |
| 461 | typedef |
| 462 | struct { |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 463 | EventTag tag; |
| 464 | InstrInfo* inode; |
| 465 | union { |
| 466 | struct { |
| 467 | } Ir; |
| 468 | struct { |
| 469 | IRAtom* ea; |
| 470 | Int szB; |
| 471 | } Dr; |
| 472 | struct { |
| 473 | IRAtom* ea; |
| 474 | Int szB; |
| 475 | } Dw; |
| 476 | struct { |
| 477 | IRAtom* ea; |
| 478 | Int szB; |
| 479 | } Dm; |
| 480 | struct { |
| 481 | IRAtom* taken; /* :: Ity_I1 */ |
| 482 | } Bc; |
| 483 | struct { |
| 484 | IRAtom* dst; |
| 485 | } Bi; |
| 486 | } Ev; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 487 | } |
| 488 | Event; |
| 489 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 490 | static void init_Event ( Event* ev ) { |
| 491 | VG_(memset)(ev, 0, sizeof(Event)); |
| 492 | } |
| 493 | |
| 494 | static IRAtom* get_Event_dea ( Event* ev ) { |
| 495 | switch (ev->tag) { |
| 496 | case Ev_Dr: return ev->Ev.Dr.ea; |
| 497 | case Ev_Dw: return ev->Ev.Dw.ea; |
| 498 | case Ev_Dm: return ev->Ev.Dm.ea; |
| 499 | default: tl_assert(0); |
| 500 | } |
| 501 | } |
| 502 | |
| 503 | static Int get_Event_dszB ( Event* ev ) { |
| 504 | switch (ev->tag) { |
| 505 | case Ev_Dr: return ev->Ev.Dr.szB; |
| 506 | case Ev_Dw: return ev->Ev.Dw.szB; |
| 507 | case Ev_Dm: return ev->Ev.Dm.szB; |
| 508 | default: tl_assert(0); |
| 509 | } |
| 510 | } |
| 511 | |
| 512 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 513 | /* Up to this many unnotified events are allowed. Number is |
| 514 | arbitrary. Larger numbers allow more event merging to occur, but |
| 515 | potentially induce more spilling due to extending live ranges of |
| 516 | address temporaries. */ |
| 517 | #define N_EVENTS 16 |
| 518 | |
| 519 | |
| 520 | /* A struct which holds all the running state during instrumentation. |
| 521 | Mostly to avoid passing loads of parameters everywhere. */ |
| 522 | typedef |
| 523 | struct { |
| 524 | /* The current outstanding-memory-event list. */ |
| 525 | Event events[N_EVENTS]; |
| 526 | Int events_used; |
| 527 | |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 528 | /* The array of InstrInfo bins for the BB. */ |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 529 | SB_info* sbInfo; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 530 | |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 531 | /* Number InstrInfo bins 'used' so far. */ |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 532 | Int sbInfo_i; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 533 | |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 534 | /* The output SB being constructed. */ |
| 535 | IRSB* sbOut; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 536 | } |
| 537 | CgState; |
| 538 | |
| 539 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 540 | /*------------------------------------------------------------*/ |
| 541 | /*--- Instrumentation main ---*/ |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 542 | /*------------------------------------------------------------*/ |
| 543 | |
sewardj | 4ba057c | 2005-10-18 12:04:18 +0000 | [diff] [blame] | 544 | // Note that origAddr is the real origAddr, not the address of the first |
| 545 | // instruction in the block (they can be different due to redirection). |
nethercote | 564b2b0 | 2004-08-07 15:54:53 +0000 | [diff] [blame] | 546 | static |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 547 | SB_info* get_SB_info(IRSB* sbIn, Addr origAddr) |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 548 | { |
njn | 4bd67b5 | 2005-08-11 00:47:10 +0000 | [diff] [blame] | 549 | Int i, n_instrs; |
| 550 | IRStmt* st; |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 551 | SB_info* sbInfo; |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 552 | |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 553 | // Count number of original instrs in SB |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 554 | n_instrs = 0; |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 555 | for (i = 0; i < sbIn->stmts_used; i++) { |
| 556 | st = sbIn->stmts[i]; |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 557 | if (Ist_IMark == st->tag) n_instrs++; |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 558 | } |
| 559 | |
njn | f7d2609 | 2005-10-12 16:45:17 +0000 | [diff] [blame] | 560 | // Check that we don't have an entry for this BB in the instr-info table. |
| 561 | // If this assertion fails, there has been some screwup: some |
| 562 | // translations must have been discarded but Cachegrind hasn't discarded |
| 563 | // the corresponding entries in the instr-info table. |
njn | e2a9ad3 | 2007-09-17 05:30:48 +0000 | [diff] [blame] | 564 | sbInfo = VG_(OSetGen_Lookup)(instrInfoTable, &origAddr); |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 565 | tl_assert(NULL == sbInfo); |
sewardj | a3a29a5 | 2005-10-12 16:16:03 +0000 | [diff] [blame] | 566 | |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 567 | // BB never translated before (at this address, at least; could have |
| 568 | // been unloaded and then reloaded elsewhere in memory) |
njn | e2a9ad3 | 2007-09-17 05:30:48 +0000 | [diff] [blame] | 569 | sbInfo = VG_(OSetGen_AllocNode)(instrInfoTable, |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 570 | sizeof(SB_info) + n_instrs*sizeof(InstrInfo)); |
| 571 | sbInfo->SB_addr = origAddr; |
| 572 | sbInfo->n_instrs = n_instrs; |
njn | e2a9ad3 | 2007-09-17 05:30:48 +0000 | [diff] [blame] | 573 | VG_(OSetGen_Insert)( instrInfoTable, sbInfo ); |
sewardj | a3a29a5 | 2005-10-12 16:16:03 +0000 | [diff] [blame] | 574 | distinct_instrs++; |
| 575 | |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 576 | return sbInfo; |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 577 | } |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 578 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 579 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 580 | static void showEvent ( Event* ev ) |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 581 | { |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 582 | switch (ev->tag) { |
| 583 | case Ev_Ir: |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 584 | VG_(printf)("Ir %p\n", ev->inode); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 585 | break; |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 586 | case Ev_Dr: |
| 587 | VG_(printf)("Dr %p %d EA=", ev->inode, ev->Ev.Dr.szB); |
| 588 | ppIRExpr(ev->Ev.Dr.ea); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 589 | VG_(printf)("\n"); |
| 590 | break; |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 591 | case Ev_Dw: |
| 592 | VG_(printf)("Dw %p %d EA=", ev->inode, ev->Ev.Dw.szB); |
| 593 | ppIRExpr(ev->Ev.Dw.ea); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 594 | VG_(printf)("\n"); |
| 595 | break; |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 596 | case Ev_Dm: |
| 597 | VG_(printf)("Dm %p %d EA=", ev->inode, ev->Ev.Dm.szB); |
| 598 | ppIRExpr(ev->Ev.Dm.ea); |
| 599 | VG_(printf)("\n"); |
| 600 | break; |
| 601 | case Ev_Bc: |
| 602 | VG_(printf)("Bc %p GA=", ev->inode); |
| 603 | ppIRExpr(ev->Ev.Bc.taken); |
| 604 | VG_(printf)("\n"); |
| 605 | break; |
| 606 | case Ev_Bi: |
| 607 | VG_(printf)("Bi %p DST=", ev->inode); |
| 608 | ppIRExpr(ev->Ev.Bi.dst); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 609 | VG_(printf)("\n"); |
| 610 | break; |
| 611 | default: |
| 612 | tl_assert(0); |
| 613 | break; |
| 614 | } |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 615 | } |
| 616 | |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 617 | // Reserve and initialise an InstrInfo for the first mention of a new insn. |
| 618 | static |
| 619 | InstrInfo* setup_InstrInfo ( CgState* cgs, Addr instr_addr, UInt instr_len ) |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 620 | { |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 621 | InstrInfo* i_node; |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 622 | tl_assert(cgs->sbInfo_i >= 0); |
| 623 | tl_assert(cgs->sbInfo_i < cgs->sbInfo->n_instrs); |
| 624 | i_node = &cgs->sbInfo->instrs[ cgs->sbInfo_i ]; |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 625 | i_node->instr_addr = instr_addr; |
| 626 | i_node->instr_len = instr_len; |
| 627 | i_node->parent = get_lineCC(instr_addr); |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 628 | cgs->sbInfo_i++; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 629 | return i_node; |
| 630 | } |
sewardj | 17a56bf | 2005-03-21 01:35:02 +0000 | [diff] [blame] | 631 | |
sewardj | 17a56bf | 2005-03-21 01:35:02 +0000 | [diff] [blame] | 632 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 633 | /* Generate code for all outstanding memory events, and mark the queue |
| 634 | empty. Code is generated into cgs->bbOut, and this activity |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 635 | 'consumes' slots in cgs->sbInfo. */ |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 636 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 637 | static void flushEvents ( CgState* cgs ) |
| 638 | { |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 639 | Int i, regparms; |
| 640 | Char* helperName; |
| 641 | void* helperAddr; |
| 642 | IRExpr** argv; |
| 643 | IRExpr* i_node_expr; |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 644 | IRDirty* di; |
njn | c285dca | 2005-10-15 22:07:28 +0000 | [diff] [blame] | 645 | Event* ev; |
| 646 | Event* ev2; |
| 647 | Event* ev3; |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 648 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 649 | i = 0; |
| 650 | while (i < cgs->events_used) { |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 651 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 652 | helperName = NULL; |
| 653 | helperAddr = NULL; |
| 654 | argv = NULL; |
| 655 | regparms = 0; |
| 656 | |
| 657 | /* generate IR to notify event i and possibly the ones |
| 658 | immediately following it. */ |
| 659 | tl_assert(i >= 0 && i < cgs->events_used); |
njn | c285dca | 2005-10-15 22:07:28 +0000 | [diff] [blame] | 660 | |
| 661 | ev = &cgs->events[i]; |
| 662 | ev2 = ( i < cgs->events_used-1 ? &cgs->events[i+1] : NULL ); |
| 663 | ev3 = ( i < cgs->events_used-2 ? &cgs->events[i+2] : NULL ); |
| 664 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 665 | if (DEBUG_CG) { |
| 666 | VG_(printf)(" flush "); |
njn | c285dca | 2005-10-15 22:07:28 +0000 | [diff] [blame] | 667 | showEvent( ev ); |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 668 | } |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 669 | |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 670 | i_node_expr = mkIRExpr_HWord( (HWord)ev->inode ); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 671 | |
| 672 | /* Decide on helper fn to call and args to pass it, and advance |
| 673 | i appropriately. */ |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 674 | switch (ev->tag) { |
| 675 | case Ev_Ir: |
| 676 | /* Merge an Ir with a following Dr/Dm. */ |
| 677 | if (ev2 && (ev2->tag == Ev_Dr || ev2->tag == Ev_Dm)) { |
| 678 | /* Why is this true? It's because we're merging an Ir |
| 679 | with a following Dr or Dm. The Ir derives from the |
| 680 | instruction's IMark and the Dr/Dm from data |
| 681 | references which follow it. In short it holds |
| 682 | because each insn starts with an IMark, hence an |
| 683 | Ev_Ir, and so these Dr/Dm must pertain to the |
| 684 | immediately preceding Ir. Same applies to analogous |
| 685 | assertions in the subsequent cases. */ |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 686 | tl_assert(ev2->inode == ev->inode); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 687 | helperName = "log_1I_1Dr_cache_access"; |
| 688 | helperAddr = &log_1I_1Dr_cache_access; |
| 689 | argv = mkIRExprVec_3( i_node_expr, |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 690 | get_Event_dea(ev2), |
| 691 | mkIRExpr_HWord( get_Event_dszB(ev2) ) ); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 692 | regparms = 3; |
| 693 | i += 2; |
| 694 | } |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 695 | /* Merge an Ir with a following Dw. */ |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 696 | else |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 697 | if (ev2 && ev2->tag == Ev_Dw) { |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 698 | tl_assert(ev2->inode == ev->inode); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 699 | helperName = "log_1I_1Dw_cache_access"; |
| 700 | helperAddr = &log_1I_1Dw_cache_access; |
| 701 | argv = mkIRExprVec_3( i_node_expr, |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 702 | get_Event_dea(ev2), |
| 703 | mkIRExpr_HWord( get_Event_dszB(ev2) ) ); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 704 | regparms = 3; |
| 705 | i += 2; |
| 706 | } |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 707 | /* Merge an Ir with two following Irs. */ |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 708 | else |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 709 | if (ev2 && ev3 && ev2->tag == Ev_Ir && ev3->tag == Ev_Ir) |
njn | c285dca | 2005-10-15 22:07:28 +0000 | [diff] [blame] | 710 | { |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 711 | helperName = "log_3I_0D_cache_access"; |
| 712 | helperAddr = &log_3I_0D_cache_access; |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 713 | argv = mkIRExprVec_3( i_node_expr, |
| 714 | mkIRExpr_HWord( (HWord)ev2->inode ), |
| 715 | mkIRExpr_HWord( (HWord)ev3->inode ) ); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 716 | regparms = 3; |
| 717 | i += 3; |
| 718 | } |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 719 | /* Merge an Ir with one following Ir. */ |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 720 | else |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 721 | if (ev2 && ev2->tag == Ev_Ir) { |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 722 | helperName = "log_2I_0D_cache_access"; |
| 723 | helperAddr = &log_2I_0D_cache_access; |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 724 | argv = mkIRExprVec_2( i_node_expr, |
| 725 | mkIRExpr_HWord( (HWord)ev2->inode ) ); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 726 | regparms = 2; |
| 727 | i += 2; |
| 728 | } |
| 729 | /* No merging possible; emit as-is. */ |
| 730 | else { |
| 731 | helperName = "log_1I_0D_cache_access"; |
| 732 | helperAddr = &log_1I_0D_cache_access; |
| 733 | argv = mkIRExprVec_1( i_node_expr ); |
| 734 | regparms = 1; |
| 735 | i++; |
| 736 | } |
| 737 | break; |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 738 | case Ev_Dr: |
| 739 | case Ev_Dm: |
| 740 | /* Data read or modify */ |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 741 | helperName = "log_0I_1Dr_cache_access"; |
| 742 | helperAddr = &log_0I_1Dr_cache_access; |
| 743 | argv = mkIRExprVec_3( i_node_expr, |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 744 | get_Event_dea(ev), |
| 745 | mkIRExpr_HWord( get_Event_dszB(ev) ) ); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 746 | regparms = 3; |
| 747 | i++; |
| 748 | break; |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 749 | case Ev_Dw: |
| 750 | /* Data write */ |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 751 | helperName = "log_0I_1Dw_cache_access"; |
| 752 | helperAddr = &log_0I_1Dw_cache_access; |
| 753 | argv = mkIRExprVec_3( i_node_expr, |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 754 | get_Event_dea(ev), |
| 755 | mkIRExpr_HWord( get_Event_dszB(ev) ) ); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 756 | regparms = 3; |
| 757 | i++; |
| 758 | break; |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 759 | case Ev_Bc: |
| 760 | /* Conditional branch */ |
| 761 | helperName = "log_cond_branch"; |
| 762 | helperAddr = &log_cond_branch; |
| 763 | argv = mkIRExprVec_2( i_node_expr, ev->Ev.Bc.taken ); |
| 764 | regparms = 2; |
| 765 | i++; |
| 766 | break; |
| 767 | case Ev_Bi: |
| 768 | /* Branch to an unknown destination */ |
| 769 | helperName = "log_ind_branch"; |
| 770 | helperAddr = &log_ind_branch; |
| 771 | argv = mkIRExprVec_2( i_node_expr, ev->Ev.Bi.dst ); |
| 772 | regparms = 2; |
| 773 | i++; |
| 774 | break; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 775 | default: |
| 776 | tl_assert(0); |
| 777 | } |
| 778 | |
| 779 | /* Add the helper. */ |
| 780 | tl_assert(helperName); |
| 781 | tl_assert(helperAddr); |
| 782 | tl_assert(argv); |
sewardj | 5bb8682 | 2005-12-23 12:47:42 +0000 | [diff] [blame] | 783 | di = unsafeIRDirty_0_N( regparms, |
| 784 | helperName, VG_(fnptr_to_fnentry)( helperAddr ), |
| 785 | argv ); |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 786 | addStmtToIRSB( cgs->sbOut, IRStmt_Dirty(di) ); |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 787 | } |
| 788 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 789 | cgs->events_used = 0; |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 790 | } |
njn | 14d01ce | 2004-11-26 11:30:14 +0000 | [diff] [blame] | 791 | |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 792 | static void addEvent_Ir ( CgState* cgs, InstrInfo* inode ) |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 793 | { |
| 794 | Event* evt; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 795 | if (cgs->events_used == N_EVENTS) |
| 796 | flushEvents(cgs); |
| 797 | tl_assert(cgs->events_used >= 0 && cgs->events_used < N_EVENTS); |
| 798 | evt = &cgs->events[cgs->events_used]; |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 799 | init_Event(evt); |
| 800 | evt->tag = Ev_Ir; |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 801 | evt->inode = inode; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 802 | cgs->events_used++; |
| 803 | } |
| 804 | |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 805 | static |
| 806 | void addEvent_Dr ( CgState* cgs, InstrInfo* inode, Int datasize, IRAtom* ea ) |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 807 | { |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 808 | Event* evt; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 809 | tl_assert(isIRAtom(ea)); |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 810 | tl_assert(datasize >= 1 && datasize <= MIN_LINE_SIZE); |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 811 | if (!clo_cache_sim) |
| 812 | return; |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 813 | if (cgs->events_used == N_EVENTS) |
| 814 | flushEvents(cgs); |
| 815 | tl_assert(cgs->events_used >= 0 && cgs->events_used < N_EVENTS); |
| 816 | evt = &cgs->events[cgs->events_used]; |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 817 | init_Event(evt); |
| 818 | evt->tag = Ev_Dr; |
| 819 | evt->inode = inode; |
| 820 | evt->Ev.Dr.szB = datasize; |
| 821 | evt->Ev.Dr.ea = ea; |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 822 | cgs->events_used++; |
| 823 | } |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 824 | |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 825 | static |
| 826 | void addEvent_Dw ( CgState* cgs, InstrInfo* inode, Int datasize, IRAtom* ea ) |
| 827 | { |
| 828 | Event* lastEvt; |
| 829 | Event* evt; |
| 830 | |
| 831 | tl_assert(isIRAtom(ea)); |
| 832 | tl_assert(datasize >= 1 && datasize <= MIN_LINE_SIZE); |
| 833 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 834 | if (!clo_cache_sim) |
| 835 | return; |
| 836 | |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 837 | /* Is it possible to merge this write with the preceding read? */ |
| 838 | lastEvt = &cgs->events[cgs->events_used-1]; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 839 | if (cgs->events_used > 0 |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 840 | && lastEvt->tag == Ev_Dr |
| 841 | && lastEvt->Ev.Dr.szB == datasize |
| 842 | && lastEvt->inode == inode |
| 843 | && eqIRAtom(lastEvt->Ev.Dr.ea, ea)) |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 844 | { |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 845 | lastEvt->tag = Ev_Dm; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 846 | return; |
| 847 | } |
| 848 | |
| 849 | /* No. Add as normal. */ |
| 850 | if (cgs->events_used == N_EVENTS) |
| 851 | flushEvents(cgs); |
| 852 | tl_assert(cgs->events_used >= 0 && cgs->events_used < N_EVENTS); |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 853 | evt = &cgs->events[cgs->events_used]; |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 854 | init_Event(evt); |
| 855 | evt->tag = Ev_Dw; |
| 856 | evt->inode = inode; |
| 857 | evt->Ev.Dw.szB = datasize; |
| 858 | evt->Ev.Dw.ea = ea; |
| 859 | cgs->events_used++; |
| 860 | } |
| 861 | |
| 862 | static |
| 863 | void addEvent_Bc ( CgState* cgs, InstrInfo* inode, IRAtom* guard ) |
| 864 | { |
| 865 | Event* evt; |
| 866 | tl_assert(isIRAtom(guard)); |
| 867 | tl_assert(typeOfIRExpr(cgs->sbOut->tyenv, guard) |
| 868 | == (sizeof(HWord)==4 ? Ity_I32 : Ity_I64)); |
| 869 | if (!clo_branch_sim) |
| 870 | return; |
| 871 | if (cgs->events_used == N_EVENTS) |
| 872 | flushEvents(cgs); |
| 873 | tl_assert(cgs->events_used >= 0 && cgs->events_used < N_EVENTS); |
| 874 | evt = &cgs->events[cgs->events_used]; |
| 875 | init_Event(evt); |
| 876 | evt->tag = Ev_Bc; |
| 877 | evt->inode = inode; |
| 878 | evt->Ev.Bc.taken = guard; |
| 879 | cgs->events_used++; |
| 880 | } |
| 881 | |
| 882 | static |
| 883 | void addEvent_Bi ( CgState* cgs, InstrInfo* inode, IRAtom* whereTo ) |
| 884 | { |
| 885 | Event* evt; |
| 886 | tl_assert(isIRAtom(whereTo)); |
| 887 | tl_assert(typeOfIRExpr(cgs->sbOut->tyenv, whereTo) |
| 888 | == (sizeof(HWord)==4 ? Ity_I32 : Ity_I64)); |
| 889 | if (!clo_branch_sim) |
| 890 | return; |
| 891 | if (cgs->events_used == N_EVENTS) |
| 892 | flushEvents(cgs); |
| 893 | tl_assert(cgs->events_used >= 0 && cgs->events_used < N_EVENTS); |
| 894 | evt = &cgs->events[cgs->events_used]; |
| 895 | init_Event(evt); |
| 896 | evt->tag = Ev_Bi; |
| 897 | evt->inode = inode; |
| 898 | evt->Ev.Bi.dst = whereTo; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 899 | cgs->events_used++; |
| 900 | } |
| 901 | |
| 902 | //////////////////////////////////////////////////////////// |
| 903 | |
| 904 | |
sewardj | 4ba057c | 2005-10-18 12:04:18 +0000 | [diff] [blame] | 905 | static |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 906 | IRSB* cg_instrument ( VgCallbackClosure* closure, |
| 907 | IRSB* sbIn, |
sewardj | 461df9c | 2006-01-17 02:06:39 +0000 | [diff] [blame] | 908 | VexGuestLayout* layout, |
| 909 | VexGuestExtents* vge, |
sewardj | 4ba057c | 2005-10-18 12:04:18 +0000 | [diff] [blame] | 910 | IRType gWordTy, IRType hWordTy ) |
njn | 14d01ce | 2004-11-26 11:30:14 +0000 | [diff] [blame] | 911 | { |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 912 | Int i, isize; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 913 | IRStmt* st; |
| 914 | Addr64 cia; /* address of current insn */ |
| 915 | CgState cgs; |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 916 | IRTypeEnv* tyenv = sbIn->tyenv; |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 917 | InstrInfo* curr_inode = NULL; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 918 | |
sewardj | d54babf | 2005-03-21 00:55:49 +0000 | [diff] [blame] | 919 | if (gWordTy != hWordTy) { |
| 920 | /* We don't currently support this case. */ |
| 921 | VG_(tool_panic)("host/guest word size mismatch"); |
| 922 | } |
| 923 | |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 924 | // Set up new SB |
| 925 | cgs.sbOut = deepCopyIRSBExceptStmts(sbIn); |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 926 | |
sewardj | a9f538c | 2005-10-23 12:06:55 +0000 | [diff] [blame] | 927 | // Copy verbatim any IR preamble preceding the first IMark |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 928 | i = 0; |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 929 | while (i < sbIn->stmts_used && sbIn->stmts[i]->tag != Ist_IMark) { |
| 930 | addStmtToIRSB( cgs.sbOut, sbIn->stmts[i] ); |
sewardj | a9f538c | 2005-10-23 12:06:55 +0000 | [diff] [blame] | 931 | i++; |
| 932 | } |
| 933 | |
| 934 | // Get the first statement, and initial cia from it |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 935 | tl_assert(sbIn->stmts_used > 0); |
| 936 | tl_assert(i < sbIn->stmts_used); |
| 937 | st = sbIn->stmts[i]; |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 938 | tl_assert(Ist_IMark == st->tag); |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 939 | |
| 940 | cia = st->Ist.IMark.addr; |
| 941 | isize = st->Ist.IMark.len; |
| 942 | // If Vex fails to decode an instruction, the size will be zero. |
| 943 | // Pretend otherwise. |
| 944 | if (isize == 0) isize = VG_MIN_INSTR_SZB; |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 945 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 946 | // Set up running state and get block info |
sewardj | 3a384b3 | 2006-01-22 01:12:51 +0000 | [diff] [blame] | 947 | tl_assert(closure->readdr == vge->base[0]); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 948 | cgs.events_used = 0; |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 949 | cgs.sbInfo = get_SB_info(sbIn, (Addr)closure->readdr); |
| 950 | cgs.sbInfo_i = 0; |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 951 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 952 | if (DEBUG_CG) |
| 953 | VG_(printf)("\n\n---------- cg_instrument ----------\n"); |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 954 | |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 955 | // Traverse the block, initialising inodes, adding events and flushing as |
| 956 | // necessary. |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 957 | for (/*use current i*/; i < sbIn->stmts_used; i++) { |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 958 | |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 959 | st = sbIn->stmts[i]; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 960 | tl_assert(isFlatIRStmt(st)); |
njn | b3507ea | 2005-08-02 23:07:02 +0000 | [diff] [blame] | 961 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 962 | switch (st->tag) { |
| 963 | case Ist_NoOp: |
| 964 | case Ist_AbiHint: |
| 965 | case Ist_Put: |
| 966 | case Ist_PutI: |
sewardj | 72d7513 | 2007-11-09 23:06:35 +0000 | [diff] [blame] | 967 | case Ist_MBE: |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 968 | break; |
njn | 20677cc | 2005-08-12 23:47:51 +0000 | [diff] [blame] | 969 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 970 | case Ist_IMark: |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 971 | cia = st->Ist.IMark.addr; |
| 972 | isize = st->Ist.IMark.len; |
| 973 | |
| 974 | // If Vex fails to decode an instruction, the size will be zero. |
| 975 | // Pretend otherwise. |
| 976 | if (isize == 0) isize = VG_MIN_INSTR_SZB; |
| 977 | |
njn | a5ad9ba | 2005-11-10 15:20:37 +0000 | [diff] [blame] | 978 | // Sanity-check size. |
| 979 | tl_assert( (VG_MIN_INSTR_SZB <= isize && isize <= VG_MAX_INSTR_SZB) |
| 980 | || VG_CLREQ_SZB == isize ); |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 981 | |
| 982 | // Get space for and init the inode, record it as the current one. |
| 983 | // Subsequent Dr/Dw/Dm events from the same instruction will |
| 984 | // also use it. |
| 985 | curr_inode = setup_InstrInfo(&cgs, cia, isize); |
| 986 | |
| 987 | addEvent_Ir( &cgs, curr_inode ); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 988 | break; |
| 989 | |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 990 | case Ist_WrTmp: { |
| 991 | IRExpr* data = st->Ist.WrTmp.data; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 992 | if (data->tag == Iex_Load) { |
| 993 | IRExpr* aexpr = data->Iex.Load.addr; |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 994 | // Note also, endianness info is ignored. I guess |
| 995 | // that's not interesting. |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 996 | addEvent_Dr( &cgs, curr_inode, sizeofIRType(data->Iex.Load.ty), |
| 997 | aexpr ); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 998 | } |
| 999 | break; |
njn | b3507ea | 2005-08-02 23:07:02 +0000 | [diff] [blame] | 1000 | } |
| 1001 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1002 | case Ist_Store: { |
| 1003 | IRExpr* data = st->Ist.Store.data; |
| 1004 | IRExpr* aexpr = st->Ist.Store.addr; |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 1005 | addEvent_Dw( &cgs, curr_inode, |
| 1006 | sizeofIRType(typeOfIRExpr(tyenv, data)), aexpr ); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1007 | break; |
| 1008 | } |
njn | b3507ea | 2005-08-02 23:07:02 +0000 | [diff] [blame] | 1009 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1010 | case Ist_Dirty: { |
| 1011 | Int dataSize; |
| 1012 | IRDirty* d = st->Ist.Dirty.details; |
| 1013 | if (d->mFx != Ifx_None) { |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 1014 | /* This dirty helper accesses memory. Collect the details. */ |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1015 | tl_assert(d->mAddr != NULL); |
| 1016 | tl_assert(d->mSize != 0); |
| 1017 | dataSize = d->mSize; |
| 1018 | // Large (eg. 28B, 108B, 512B on x86) data-sized |
| 1019 | // instructions will be done inaccurately, but they're |
| 1020 | // very rare and this avoids errors from hitting more |
| 1021 | // than two cache lines in the simulation. |
| 1022 | if (dataSize > MIN_LINE_SIZE) |
| 1023 | dataSize = MIN_LINE_SIZE; |
| 1024 | if (d->mFx == Ifx_Read || d->mFx == Ifx_Modify) |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 1025 | addEvent_Dr( &cgs, curr_inode, dataSize, d->mAddr ); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1026 | if (d->mFx == Ifx_Write || d->mFx == Ifx_Modify) |
njn | fd9f622 | 2005-10-16 00:17:37 +0000 | [diff] [blame] | 1027 | addEvent_Dw( &cgs, curr_inode, dataSize, d->mAddr ); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1028 | } else { |
| 1029 | tl_assert(d->mAddr == NULL); |
| 1030 | tl_assert(d->mSize == 0); |
| 1031 | } |
| 1032 | break; |
| 1033 | } |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 1034 | |
sewardj | 1c0ce7a | 2009-07-01 08:10:49 +0000 | [diff] [blame^] | 1035 | case Ist_CAS: { |
| 1036 | /* We treat it as a read and a write of the location. I |
| 1037 | think that is the same behaviour as it was before IRCAS |
| 1038 | was introduced, since prior to that point, the Vex |
| 1039 | front ends would translate a lock-prefixed instruction |
| 1040 | into a (normal) read followed by a (normal) write. */ |
| 1041 | Int dataSize; |
| 1042 | IRCAS* cas = st->Ist.CAS.details; |
| 1043 | tl_assert(cas->addr != NULL); |
| 1044 | tl_assert(cas->dataLo != NULL); |
| 1045 | dataSize = sizeofIRType(typeOfIRExpr(tyenv, cas->dataLo)); |
| 1046 | if (cas->dataHi != NULL) |
| 1047 | dataSize *= 2; /* since it's a doubleword-CAS */ |
| 1048 | /* I don't think this can ever happen, but play safe. */ |
| 1049 | if (dataSize > MIN_LINE_SIZE) |
| 1050 | dataSize = MIN_LINE_SIZE; |
| 1051 | addEvent_Dr( &cgs, curr_inode, dataSize, cas->addr ); |
| 1052 | addEvent_Dw( &cgs, curr_inode, dataSize, cas->addr ); |
| 1053 | break; |
| 1054 | } |
| 1055 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1056 | case Ist_Exit: { |
| 1057 | /* Stuff to widen the guard expression to a host word, so |
| 1058 | we can pass it to the branch predictor simulation |
| 1059 | functions easily. */ |
| 1060 | Bool inverted; |
| 1061 | Addr64 nia, sea; |
| 1062 | IRConst* dst; |
| 1063 | IROp tyW = hWordTy; |
| 1064 | IROp widen = tyW==Ity_I32 ? Iop_1Uto32 : Iop_1Uto64; |
| 1065 | IROp opXOR = tyW==Ity_I32 ? Iop_Xor32 : Iop_Xor64; |
| 1066 | IRTemp guard1 = newIRTemp(cgs.sbOut->tyenv, Ity_I1); |
| 1067 | IRTemp guardW = newIRTemp(cgs.sbOut->tyenv, tyW); |
| 1068 | IRTemp guard = newIRTemp(cgs.sbOut->tyenv, tyW); |
| 1069 | IRExpr* one = tyW==Ity_I32 ? IRExpr_Const(IRConst_U32(1)) |
| 1070 | : IRExpr_Const(IRConst_U64(1)); |
| 1071 | |
| 1072 | /* First we need to figure out whether the side exit got |
| 1073 | inverted by the ir optimiser. To do that, figure out |
| 1074 | the next (fallthrough) instruction's address and the |
| 1075 | side exit address and see if they are the same. */ |
| 1076 | nia = cia + (Addr64)isize; |
| 1077 | if (tyW == Ity_I32) |
| 1078 | nia &= 0xFFFFFFFFULL; |
| 1079 | |
| 1080 | /* Side exit address */ |
| 1081 | dst = st->Ist.Exit.dst; |
| 1082 | if (tyW == Ity_I32) { |
| 1083 | tl_assert(dst->tag == Ico_U32); |
| 1084 | sea = (Addr64)(UInt)dst->Ico.U32; |
| 1085 | } else { |
| 1086 | tl_assert(tyW == Ity_I64); |
| 1087 | tl_assert(dst->tag == Ico_U64); |
| 1088 | sea = dst->Ico.U64; |
| 1089 | } |
| 1090 | |
| 1091 | inverted = nia == sea; |
| 1092 | |
| 1093 | /* Widen the guard expression. */ |
| 1094 | addStmtToIRSB( cgs.sbOut, |
| 1095 | IRStmt_WrTmp( guard1, st->Ist.Exit.guard )); |
| 1096 | addStmtToIRSB( cgs.sbOut, |
| 1097 | IRStmt_WrTmp( guardW, |
| 1098 | IRExpr_Unop(widen, |
| 1099 | IRExpr_RdTmp(guard1))) ); |
| 1100 | /* If the exit is inverted, invert the sense of the guard. */ |
| 1101 | addStmtToIRSB( |
| 1102 | cgs.sbOut, |
| 1103 | IRStmt_WrTmp( |
| 1104 | guard, |
| 1105 | inverted ? IRExpr_Binop(opXOR, IRExpr_RdTmp(guardW), one) |
| 1106 | : IRExpr_RdTmp(guardW) |
| 1107 | )); |
| 1108 | /* And post the event. */ |
| 1109 | addEvent_Bc( &cgs, curr_inode, IRExpr_RdTmp(guard) ); |
| 1110 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1111 | /* We may never reach the next statement, so need to flush |
| 1112 | all outstanding transactions now. */ |
| 1113 | flushEvents( &cgs ); |
| 1114 | break; |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1115 | } |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1116 | |
| 1117 | default: |
| 1118 | tl_assert(0); |
| 1119 | break; |
njn | b3507ea | 2005-08-02 23:07:02 +0000 | [diff] [blame] | 1120 | } |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 1121 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1122 | /* Copy the original statement */ |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 1123 | addStmtToIRSB( cgs.sbOut, st ); |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 1124 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1125 | if (DEBUG_CG) { |
| 1126 | ppIRStmt(st); |
| 1127 | VG_(printf)("\n"); |
| 1128 | } |
| 1129 | } |
| 1130 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1131 | /* Deal with branches to unknown destinations. Except ignore ones |
| 1132 | which are function returns as we assume the return stack |
| 1133 | predictor never mispredicts. */ |
| 1134 | if (sbIn->jumpkind == Ijk_Boring) { |
| 1135 | if (0) { ppIRExpr( sbIn->next ); VG_(printf)("\n"); } |
| 1136 | switch (sbIn->next->tag) { |
| 1137 | case Iex_Const: |
| 1138 | break; /* boring - branch to known address */ |
| 1139 | case Iex_RdTmp: |
| 1140 | /* looks like an indirect branch (branch to unknown) */ |
| 1141 | addEvent_Bi( &cgs, curr_inode, sbIn->next ); |
| 1142 | break; |
| 1143 | default: |
| 1144 | /* shouldn't happen - if the incoming IR is properly |
| 1145 | flattened, should only have tmp and const cases to |
| 1146 | consider. */ |
| 1147 | tl_assert(0); |
| 1148 | } |
| 1149 | } |
| 1150 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1151 | /* At the end of the bb. Flush outstandings. */ |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1152 | flushEvents( &cgs ); |
| 1153 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1154 | /* done. stay sane ... */ |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 1155 | tl_assert(cgs.sbInfo_i == cgs.sbInfo->n_instrs); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1156 | |
| 1157 | if (DEBUG_CG) { |
| 1158 | VG_(printf)( "goto {"); |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 1159 | ppIRJumpKind(sbIn->jumpkind); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1160 | VG_(printf)( "} "); |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 1161 | ppIRExpr( sbIn->next ); |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1162 | VG_(printf)( "}\n"); |
| 1163 | } |
| 1164 | |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 1165 | return cgs.sbOut; |
njn | 14d01ce | 2004-11-26 11:30:14 +0000 | [diff] [blame] | 1166 | } |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1167 | |
| 1168 | /*------------------------------------------------------------*/ |
nethercote | b35a8b9 | 2004-09-11 16:45:27 +0000 | [diff] [blame] | 1169 | /*--- Cache configuration ---*/ |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1170 | /*------------------------------------------------------------*/ |
| 1171 | |
sewardj | b5f6f51 | 2005-03-10 23:59:00 +0000 | [diff] [blame] | 1172 | #define UNDEFINED_CACHE { -1, -1, -1 } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1173 | |
| 1174 | static cache_t clo_I1_cache = UNDEFINED_CACHE; |
| 1175 | static cache_t clo_D1_cache = UNDEFINED_CACHE; |
| 1176 | static cache_t clo_L2_cache = UNDEFINED_CACHE; |
| 1177 | |
njn | 7cf0bd3 | 2002-06-08 13:36:03 +0000 | [diff] [blame] | 1178 | /* Checks cache config is ok; makes it so if not. */ |
sewardj | 07133bf | 2002-06-13 10:25:56 +0000 | [diff] [blame] | 1179 | static |
njn | a1d1a64 | 2004-11-26 18:36:02 +0000 | [diff] [blame] | 1180 | void check_cache(cache_t* cache, Char *name) |
njn | 7cf0bd3 | 2002-06-08 13:36:03 +0000 | [diff] [blame] | 1181 | { |
weidendo | 144b76c | 2009-01-26 22:56:14 +0000 | [diff] [blame] | 1182 | /* Simulator requires line size and set count to be powers of two */ |
| 1183 | if (( cache->size % (cache->line_size * cache->assoc) != 0) || |
| 1184 | (-1 == VG_(log2)(cache->size/cache->line_size/cache->assoc))) { |
njn | 6f74a7e | 2009-03-12 00:06:45 +0000 | [diff] [blame] | 1185 | VG_UMSG("error: %s set count not a power of two; aborting.", name); |
njn | a1d1a64 | 2004-11-26 18:36:02 +0000 | [diff] [blame] | 1186 | VG_(exit)(1); |
njn | 7cf0bd3 | 2002-06-08 13:36:03 +0000 | [diff] [blame] | 1187 | } |
| 1188 | |
sewardj | 07133bf | 2002-06-13 10:25:56 +0000 | [diff] [blame] | 1189 | if (-1 == VG_(log2)(cache->line_size)) { |
njn | 6f74a7e | 2009-03-12 00:06:45 +0000 | [diff] [blame] | 1190 | VG_UMSG("error: %s line size of %dB not a power of two; aborting.", |
| 1191 | name, cache->line_size); |
njn | a1d1a64 | 2004-11-26 18:36:02 +0000 | [diff] [blame] | 1192 | VG_(exit)(1); |
njn | 7cf0bd3 | 2002-06-08 13:36:03 +0000 | [diff] [blame] | 1193 | } |
| 1194 | |
njn | 6a3009b | 2005-03-20 00:20:06 +0000 | [diff] [blame] | 1195 | // Then check line size >= 16 -- any smaller and a single instruction could |
| 1196 | // straddle three cache lines, which breaks a simulation assertion and is |
| 1197 | // stupid anyway. |
njn | 7cf0bd3 | 2002-06-08 13:36:03 +0000 | [diff] [blame] | 1198 | if (cache->line_size < MIN_LINE_SIZE) { |
njn | 6f74a7e | 2009-03-12 00:06:45 +0000 | [diff] [blame] | 1199 | VG_UMSG("error: %s line size of %dB too small; aborting.", |
| 1200 | name, cache->line_size); |
njn | a1d1a64 | 2004-11-26 18:36:02 +0000 | [diff] [blame] | 1201 | VG_(exit)(1); |
njn | 7cf0bd3 | 2002-06-08 13:36:03 +0000 | [diff] [blame] | 1202 | } |
| 1203 | |
| 1204 | /* Then check cache size > line size (causes seg faults if not). */ |
| 1205 | if (cache->size <= cache->line_size) { |
njn | 6f74a7e | 2009-03-12 00:06:45 +0000 | [diff] [blame] | 1206 | VG_UMSG("error: %s cache size of %dB <= line size of %dB; aborting.", |
| 1207 | name, cache->size, cache->line_size); |
njn | a1d1a64 | 2004-11-26 18:36:02 +0000 | [diff] [blame] | 1208 | VG_(exit)(1); |
njn | 7cf0bd3 | 2002-06-08 13:36:03 +0000 | [diff] [blame] | 1209 | } |
| 1210 | |
| 1211 | /* Then check assoc <= (size / line size) (seg faults otherwise). */ |
| 1212 | if (cache->assoc > (cache->size / cache->line_size)) { |
njn | 6f74a7e | 2009-03-12 00:06:45 +0000 | [diff] [blame] | 1213 | VG_UMSG("warning: %s associativity > (size / line size); aborting.", |
| 1214 | name); |
njn | a1d1a64 | 2004-11-26 18:36:02 +0000 | [diff] [blame] | 1215 | VG_(exit)(1); |
njn | 7cf0bd3 | 2002-06-08 13:36:03 +0000 | [diff] [blame] | 1216 | } |
| 1217 | } |
| 1218 | |
sewardj | 07133bf | 2002-06-13 10:25:56 +0000 | [diff] [blame] | 1219 | static |
nethercote | b35a8b9 | 2004-09-11 16:45:27 +0000 | [diff] [blame] | 1220 | void configure_caches(cache_t* I1c, cache_t* D1c, cache_t* L2c) |
njn | 7cf0bd3 | 2002-06-08 13:36:03 +0000 | [diff] [blame] | 1221 | { |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 1222 | #define DEFINED(L) (-1 != L.size || -1 != L.assoc || -1 != L.line_size) |
| 1223 | |
nethercote | b35a8b9 | 2004-09-11 16:45:27 +0000 | [diff] [blame] | 1224 | Int n_clos = 0; |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 1225 | |
nethercote | b35a8b9 | 2004-09-11 16:45:27 +0000 | [diff] [blame] | 1226 | // Count how many were defined on the command line. |
| 1227 | if (DEFINED(clo_I1_cache)) { n_clos++; } |
| 1228 | if (DEFINED(clo_D1_cache)) { n_clos++; } |
| 1229 | if (DEFINED(clo_L2_cache)) { n_clos++; } |
njn | 7cf0bd3 | 2002-06-08 13:36:03 +0000 | [diff] [blame] | 1230 | |
njn | a1d1a64 | 2004-11-26 18:36:02 +0000 | [diff] [blame] | 1231 | // Set the cache config (using auto-detection, if supported by the |
| 1232 | // architecture) |
njn | af839f5 | 2005-06-23 03:27:57 +0000 | [diff] [blame] | 1233 | VG_(configure_caches)( I1c, D1c, L2c, (3 == n_clos) ); |
sewardj | b1a77a4 | 2002-07-13 13:31:20 +0000 | [diff] [blame] | 1234 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 1235 | // Then replace with any defined on the command line. |
nethercote | b35a8b9 | 2004-09-11 16:45:27 +0000 | [diff] [blame] | 1236 | if (DEFINED(clo_I1_cache)) { *I1c = clo_I1_cache; } |
| 1237 | if (DEFINED(clo_D1_cache)) { *D1c = clo_D1_cache; } |
| 1238 | if (DEFINED(clo_L2_cache)) { *L2c = clo_L2_cache; } |
njn | 7cf0bd3 | 2002-06-08 13:36:03 +0000 | [diff] [blame] | 1239 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 1240 | // Then check values and fix if not acceptable. |
njn | a1d1a64 | 2004-11-26 18:36:02 +0000 | [diff] [blame] | 1241 | check_cache(I1c, "I1"); |
| 1242 | check_cache(D1c, "D1"); |
| 1243 | check_cache(L2c, "L2"); |
njn | 7cf0bd3 | 2002-06-08 13:36:03 +0000 | [diff] [blame] | 1244 | |
njn | 6f74a7e | 2009-03-12 00:06:45 +0000 | [diff] [blame] | 1245 | if (VG_(clo_verbosity) >= 2) { |
| 1246 | VG_UMSG("Cache configuration used:"); |
| 1247 | VG_UMSG(" I1: %dB, %d-way, %dB lines", |
| 1248 | I1c->size, I1c->assoc, I1c->line_size); |
| 1249 | VG_UMSG(" D1: %dB, %d-way, %dB lines", |
| 1250 | D1c->size, D1c->assoc, D1c->line_size); |
| 1251 | VG_UMSG(" L2: %dB, %d-way, %dB lines", |
| 1252 | L2c->size, L2c->assoc, L2c->line_size); |
njn | 7cf0bd3 | 2002-06-08 13:36:03 +0000 | [diff] [blame] | 1253 | } |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 1254 | #undef CMD_LINE_DEFINED |
njn | 7cf0bd3 | 2002-06-08 13:36:03 +0000 | [diff] [blame] | 1255 | } |
| 1256 | |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1257 | /*------------------------------------------------------------*/ |
njn | 51d827b | 2005-05-09 01:02:08 +0000 | [diff] [blame] | 1258 | /*--- cg_fini() and related function ---*/ |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1259 | /*------------------------------------------------------------*/ |
| 1260 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 1261 | // Total reads/writes/misses. Calculated during CC traversal at the end. |
| 1262 | // All auto-zeroed. |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1263 | static CacheCC Ir_total; |
| 1264 | static CacheCC Dr_total; |
| 1265 | static CacheCC Dw_total; |
| 1266 | static BranchCC Bc_total; |
| 1267 | static BranchCC Bi_total; |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 1268 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 1269 | static void fprint_CC_table_and_calc_totals(void) |
| 1270 | { |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 1271 | Int i, fd; |
sewardj | 9264559 | 2005-07-23 09:18:34 +0000 | [diff] [blame] | 1272 | SysRes sres; |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 1273 | Char buf[512], *currFile = NULL, *currFn = NULL; |
| 1274 | LineCC* lineCC; |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1275 | |
njn | 7064fb2 | 2008-05-29 23:09:52 +0000 | [diff] [blame] | 1276 | // Setup output filename. Nb: it's important to do this now, ie. as late |
| 1277 | // as possible. If we do it at start-up and the program forks and the |
| 1278 | // output file format string contains a %p (pid) specifier, both the |
| 1279 | // parent and child will incorrectly write to the same file; this |
| 1280 | // happened in 3.3.0. |
| 1281 | Char* cachegrind_out_file = |
| 1282 | VG_(expand_file_name)("--cachegrind-out-file", clo_cachegrind_out_file); |
| 1283 | |
sewardj | 9264559 | 2005-07-23 09:18:34 +0000 | [diff] [blame] | 1284 | sres = VG_(open)(cachegrind_out_file, VKI_O_CREAT|VKI_O_TRUNC|VKI_O_WRONLY, |
| 1285 | VKI_S_IRUSR|VKI_S_IWUSR); |
njn | cda2f0f | 2009-05-18 02:12:08 +0000 | [diff] [blame] | 1286 | if (sr_isError(sres)) { |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 1287 | // If the file can't be opened for whatever reason (conflict |
| 1288 | // between multiple cachegrinded processes?), give up now. |
njn | 6f74a7e | 2009-03-12 00:06:45 +0000 | [diff] [blame] | 1289 | VG_UMSG("error: can't open cache simulation output file '%s'", |
| 1290 | cachegrind_out_file ); |
| 1291 | VG_UMSG(" ... so simulation results will be missing."); |
njn | 7064fb2 | 2008-05-29 23:09:52 +0000 | [diff] [blame] | 1292 | VG_(free)(cachegrind_out_file); |
sewardj | 0744b6c | 2002-12-11 00:45:42 +0000 | [diff] [blame] | 1293 | return; |
sewardj | 9264559 | 2005-07-23 09:18:34 +0000 | [diff] [blame] | 1294 | } else { |
njn | cda2f0f | 2009-05-18 02:12:08 +0000 | [diff] [blame] | 1295 | fd = sr_Res(sres); |
njn | 7064fb2 | 2008-05-29 23:09:52 +0000 | [diff] [blame] | 1296 | VG_(free)(cachegrind_out_file); |
sewardj | 0744b6c | 2002-12-11 00:45:42 +0000 | [diff] [blame] | 1297 | } |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1298 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 1299 | // "desc:" lines (giving I1/D1/L2 cache configuration). The spaces after |
| 1300 | // the 2nd colon makes cg_annotate's output look nicer. |
| 1301 | VG_(sprintf)(buf, "desc: I1 cache: %s\n" |
| 1302 | "desc: D1 cache: %s\n" |
| 1303 | "desc: L2 cache: %s\n", |
| 1304 | I1.desc_line, D1.desc_line, L2.desc_line); |
njn | 7cf0bd3 | 2002-06-08 13:36:03 +0000 | [diff] [blame] | 1305 | VG_(write)(fd, (void*)buf, VG_(strlen)(buf)); |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1306 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 1307 | // "cmd:" line |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1308 | VG_(strcpy)(buf, "cmd:"); |
| 1309 | VG_(write)(fd, (void*)buf, VG_(strlen)(buf)); |
sewardj | 45f4e7c | 2005-09-27 19:20:21 +0000 | [diff] [blame] | 1310 | if (VG_(args_the_exename)) { |
| 1311 | VG_(write)(fd, " ", 1); |
| 1312 | VG_(write)(fd, VG_(args_the_exename), |
| 1313 | VG_(strlen)( VG_(args_the_exename) )); |
| 1314 | } |
sewardj | 14c7cc5 | 2007-02-25 15:08:24 +0000 | [diff] [blame] | 1315 | for (i = 0; i < VG_(sizeXA)( VG_(args_for_client) ); i++) { |
| 1316 | HChar* arg = * (HChar**) VG_(indexXA)( VG_(args_for_client), i ); |
| 1317 | if (arg) { |
sewardj | 45f4e7c | 2005-09-27 19:20:21 +0000 | [diff] [blame] | 1318 | VG_(write)(fd, " ", 1); |
sewardj | 14c7cc5 | 2007-02-25 15:08:24 +0000 | [diff] [blame] | 1319 | VG_(write)(fd, arg, VG_(strlen)( arg )); |
sewardj | 45f4e7c | 2005-09-27 19:20:21 +0000 | [diff] [blame] | 1320 | } |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1321 | } |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 1322 | // "events:" line |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1323 | if (clo_cache_sim && clo_branch_sim) { |
| 1324 | VG_(sprintf)(buf, "\nevents: Ir I1mr I2mr Dr D1mr D2mr Dw D1mw D2mw " |
| 1325 | "Bc Bcm Bi Bim\n"); |
| 1326 | } |
| 1327 | else if (clo_cache_sim && !clo_branch_sim) { |
| 1328 | VG_(sprintf)(buf, "\nevents: Ir I1mr I2mr Dr D1mr D2mr Dw D1mw D2mw " |
| 1329 | "\n"); |
| 1330 | } |
| 1331 | else if (!clo_cache_sim && clo_branch_sim) { |
| 1332 | VG_(sprintf)(buf, "\nevents: Ir " |
| 1333 | "Bc Bcm Bi Bim\n"); |
| 1334 | } |
| 1335 | else |
| 1336 | tl_assert(0); /* can't happen */ |
| 1337 | |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1338 | VG_(write)(fd, (void*)buf, VG_(strlen)(buf)); |
| 1339 | |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 1340 | // Traverse every lineCC |
njn | e2a9ad3 | 2007-09-17 05:30:48 +0000 | [diff] [blame] | 1341 | VG_(OSetGen_ResetIter)(CC_table); |
| 1342 | while ( (lineCC = VG_(OSetGen_Next)(CC_table)) ) { |
njn | 4311fe6 | 2005-12-08 23:18:50 +0000 | [diff] [blame] | 1343 | Bool just_hit_a_new_file = False; |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 1344 | // If we've hit a new file, print a "fl=" line. Note that because |
| 1345 | // each string is stored exactly once in the string table, we can use |
| 1346 | // pointer comparison rather than strcmp() to test for equality, which |
| 1347 | // is good because most of the time the comparisons are equal and so |
njn | 4311fe6 | 2005-12-08 23:18:50 +0000 | [diff] [blame] | 1348 | // the whole strings would have to be checked. |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 1349 | if ( lineCC->loc.file != currFile ) { |
| 1350 | currFile = lineCC->loc.file; |
| 1351 | VG_(sprintf)(buf, "fl=%s\n", currFile); |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1352 | VG_(write)(fd, (void*)buf, VG_(strlen)(buf)); |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 1353 | distinct_files++; |
njn | 4311fe6 | 2005-12-08 23:18:50 +0000 | [diff] [blame] | 1354 | just_hit_a_new_file = True; |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1355 | } |
njn | 4311fe6 | 2005-12-08 23:18:50 +0000 | [diff] [blame] | 1356 | // If we've hit a new function, print a "fn=" line. We know to do |
| 1357 | // this when the function name changes, and also every time we hit a |
| 1358 | // new file (in which case the new function name might be the same as |
| 1359 | // in the old file, hence the just_hit_a_new_file test). |
| 1360 | if ( just_hit_a_new_file || lineCC->loc.fn != currFn ) { |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 1361 | currFn = lineCC->loc.fn; |
| 1362 | VG_(sprintf)(buf, "fn=%s\n", currFn); |
| 1363 | VG_(write)(fd, (void*)buf, VG_(strlen)(buf)); |
| 1364 | distinct_fns++; |
| 1365 | } |
| 1366 | |
| 1367 | // Print the LineCC |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1368 | if (clo_cache_sim && clo_branch_sim) { |
| 1369 | VG_(sprintf)(buf, "%u %llu %llu %llu" |
| 1370 | " %llu %llu %llu" |
| 1371 | " %llu %llu %llu" |
| 1372 | " %llu %llu %llu %llu\n", |
| 1373 | lineCC->loc.line, |
| 1374 | lineCC->Ir.a, lineCC->Ir.m1, lineCC->Ir.m2, |
| 1375 | lineCC->Dr.a, lineCC->Dr.m1, lineCC->Dr.m2, |
| 1376 | lineCC->Dw.a, lineCC->Dw.m1, lineCC->Dw.m2, |
| 1377 | lineCC->Bc.b, lineCC->Bc.mp, |
| 1378 | lineCC->Bi.b, lineCC->Bi.mp); |
| 1379 | } |
| 1380 | else if (clo_cache_sim && !clo_branch_sim) { |
| 1381 | VG_(sprintf)(buf, "%u %llu %llu %llu" |
| 1382 | " %llu %llu %llu" |
| 1383 | " %llu %llu %llu\n", |
| 1384 | lineCC->loc.line, |
| 1385 | lineCC->Ir.a, lineCC->Ir.m1, lineCC->Ir.m2, |
| 1386 | lineCC->Dr.a, lineCC->Dr.m1, lineCC->Dr.m2, |
| 1387 | lineCC->Dw.a, lineCC->Dw.m1, lineCC->Dw.m2); |
| 1388 | } |
| 1389 | else if (!clo_cache_sim && clo_branch_sim) { |
| 1390 | VG_(sprintf)(buf, "%u %llu" |
| 1391 | " %llu %llu %llu %llu\n", |
| 1392 | lineCC->loc.line, |
| 1393 | lineCC->Ir.a, |
| 1394 | lineCC->Bc.b, lineCC->Bc.mp, |
| 1395 | lineCC->Bi.b, lineCC->Bi.mp); |
| 1396 | } |
| 1397 | else |
| 1398 | tl_assert(0); |
| 1399 | |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 1400 | VG_(write)(fd, (void*)buf, VG_(strlen)(buf)); |
| 1401 | |
| 1402 | // Update summary stats |
| 1403 | Ir_total.a += lineCC->Ir.a; |
| 1404 | Ir_total.m1 += lineCC->Ir.m1; |
| 1405 | Ir_total.m2 += lineCC->Ir.m2; |
| 1406 | Dr_total.a += lineCC->Dr.a; |
| 1407 | Dr_total.m1 += lineCC->Dr.m1; |
| 1408 | Dr_total.m2 += lineCC->Dr.m2; |
| 1409 | Dw_total.a += lineCC->Dw.a; |
| 1410 | Dw_total.m1 += lineCC->Dw.m1; |
| 1411 | Dw_total.m2 += lineCC->Dw.m2; |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1412 | Bc_total.b += lineCC->Bc.b; |
| 1413 | Bc_total.mp += lineCC->Bc.mp; |
| 1414 | Bi_total.b += lineCC->Bi.b; |
| 1415 | Bi_total.mp += lineCC->Bi.mp; |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 1416 | |
| 1417 | distinct_lines++; |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1418 | } |
| 1419 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 1420 | // Summary stats must come after rest of table, since we calculate them |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1421 | // during traversal. */ |
| 1422 | if (clo_cache_sim && clo_branch_sim) { |
| 1423 | VG_(sprintf)(buf, "summary:" |
| 1424 | " %llu %llu %llu" |
| 1425 | " %llu %llu %llu" |
| 1426 | " %llu %llu %llu" |
| 1427 | " %llu %llu %llu %llu\n", |
| 1428 | Ir_total.a, Ir_total.m1, Ir_total.m2, |
| 1429 | Dr_total.a, Dr_total.m1, Dr_total.m2, |
| 1430 | Dw_total.a, Dw_total.m1, Dw_total.m2, |
| 1431 | Bc_total.b, Bc_total.mp, |
| 1432 | Bi_total.b, Bi_total.mp); |
| 1433 | } |
| 1434 | else if (clo_cache_sim && !clo_branch_sim) { |
| 1435 | VG_(sprintf)(buf, "summary:" |
| 1436 | " %llu %llu %llu" |
| 1437 | " %llu %llu %llu" |
| 1438 | " %llu %llu %llu\n", |
| 1439 | Ir_total.a, Ir_total.m1, Ir_total.m2, |
| 1440 | Dr_total.a, Dr_total.m1, Dr_total.m2, |
| 1441 | Dw_total.a, Dw_total.m1, Dw_total.m2); |
| 1442 | } |
| 1443 | else if (!clo_cache_sim && clo_branch_sim) { |
| 1444 | VG_(sprintf)(buf, "summary:" |
| 1445 | " %llu" |
| 1446 | " %llu %llu %llu %llu\n", |
| 1447 | Ir_total.a, |
| 1448 | Bc_total.b, Bc_total.mp, |
| 1449 | Bi_total.b, Bi_total.mp); |
| 1450 | } |
| 1451 | else |
| 1452 | tl_assert(0); |
| 1453 | |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1454 | VG_(write)(fd, (void*)buf, VG_(strlen)(buf)); |
| 1455 | VG_(close)(fd); |
| 1456 | } |
| 1457 | |
njn | 607adfc | 2003-09-30 14:15:44 +0000 | [diff] [blame] | 1458 | static UInt ULong_width(ULong n) |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1459 | { |
njn | 607adfc | 2003-09-30 14:15:44 +0000 | [diff] [blame] | 1460 | UInt w = 0; |
| 1461 | while (n > 0) { |
| 1462 | n = n / 10; |
| 1463 | w++; |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1464 | } |
sewardj | 46c59b1 | 2005-11-01 02:20:19 +0000 | [diff] [blame] | 1465 | if (w == 0) w = 1; |
njn | 607adfc | 2003-09-30 14:15:44 +0000 | [diff] [blame] | 1466 | return w + (w-1)/3; // add space for commas |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1467 | } |
| 1468 | |
njn | 51d827b | 2005-05-09 01:02:08 +0000 | [diff] [blame] | 1469 | static void cg_fini(Int exitcode) |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1470 | { |
njn | 1baf7db | 2006-04-18 22:34:48 +0000 | [diff] [blame] | 1471 | static Char buf1[128], buf2[128], buf3[128], buf4[123], fmt[128]; |
njn | 607adfc | 2003-09-30 14:15:44 +0000 | [diff] [blame] | 1472 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1473 | CacheCC D_total; |
| 1474 | BranchCC B_total; |
njn | 1d021fa | 2002-05-02 13:56:34 +0000 | [diff] [blame] | 1475 | ULong L2_total_m, L2_total_mr, L2_total_mw, |
| 1476 | L2_total, L2_total_r, L2_total_w; |
njn | 4c245e5 | 2009-03-15 23:25:38 +0000 | [diff] [blame] | 1477 | Int l1, l2, l3; |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1478 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1479 | /* Running with both cache and branch simulation disabled is not |
| 1480 | allowed (checked during command line option processing). */ |
| 1481 | tl_assert(clo_cache_sim || clo_branch_sim); |
| 1482 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 1483 | fprint_CC_table_and_calc_totals(); |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1484 | |
njn | 7cf0bd3 | 2002-06-08 13:36:03 +0000 | [diff] [blame] | 1485 | if (VG_(clo_verbosity) == 0) |
| 1486 | return; |
| 1487 | |
njn | f76d27a | 2009-05-28 01:53:07 +0000 | [diff] [blame] | 1488 | // Nb: this isn't called "MAX" because that overshadows a global on Darwin. |
| 1489 | #define CG_MAX(a, b) ((a) >= (b) ? (a) : (b)) |
njn | 4c245e5 | 2009-03-15 23:25:38 +0000 | [diff] [blame] | 1490 | |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1491 | /* I cache results. Use the I_refs value to determine the first column |
| 1492 | * width. */ |
njn | 607adfc | 2003-09-30 14:15:44 +0000 | [diff] [blame] | 1493 | l1 = ULong_width(Ir_total.a); |
njn | f76d27a | 2009-05-28 01:53:07 +0000 | [diff] [blame] | 1494 | l2 = ULong_width(CG_MAX(Dr_total.a, Bc_total.b)); |
| 1495 | l3 = ULong_width(CG_MAX(Dw_total.a, Bi_total.b)); |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1496 | |
njn | 607adfc | 2003-09-30 14:15:44 +0000 | [diff] [blame] | 1497 | /* Make format string, getting width right for numbers */ |
njn | 99cb9e3 | 2005-09-25 17:59:16 +0000 | [diff] [blame] | 1498 | VG_(sprintf)(fmt, "%%s %%,%dllu", l1); |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 1499 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1500 | /* Always print this */ |
njn | 6f74a7e | 2009-03-12 00:06:45 +0000 | [diff] [blame] | 1501 | VG_UMSG(fmt, "I refs: ", Ir_total.a); |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1502 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1503 | /* If cache profiling is enabled, show D access numbers and all |
| 1504 | miss numbers */ |
| 1505 | if (clo_cache_sim) { |
njn | 6f74a7e | 2009-03-12 00:06:45 +0000 | [diff] [blame] | 1506 | VG_UMSG(fmt, "I1 misses: ", Ir_total.m1); |
| 1507 | VG_UMSG(fmt, "L2i misses: ", Ir_total.m2); |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1508 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1509 | if (0 == Ir_total.a) Ir_total.a = 1; |
| 1510 | VG_(percentify)(Ir_total.m1, Ir_total.a, 2, l1+1, buf1); |
njn | 6f74a7e | 2009-03-12 00:06:45 +0000 | [diff] [blame] | 1511 | VG_UMSG("I1 miss rate: %s", buf1); |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1512 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1513 | VG_(percentify)(Ir_total.m2, Ir_total.a, 2, l1+1, buf1); |
njn | 6f74a7e | 2009-03-12 00:06:45 +0000 | [diff] [blame] | 1514 | VG_UMSG("L2i miss rate: %s", buf1); |
| 1515 | VG_UMSG(""); |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 1516 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1517 | /* D cache results. Use the D_refs.rd and D_refs.wr values to |
| 1518 | * determine the width of columns 2 & 3. */ |
| 1519 | D_total.a = Dr_total.a + Dw_total.a; |
| 1520 | D_total.m1 = Dr_total.m1 + Dw_total.m1; |
| 1521 | D_total.m2 = Dr_total.m2 + Dw_total.m2; |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1522 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1523 | /* Make format string, getting width right for numbers */ |
| 1524 | VG_(sprintf)(fmt, "%%s %%,%dllu (%%,%dllu rd + %%,%dllu wr)", l1, l2, l3); |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1525 | |
njn | 6f74a7e | 2009-03-12 00:06:45 +0000 | [diff] [blame] | 1526 | VG_UMSG(fmt, "D refs: ", |
| 1527 | D_total.a, Dr_total.a, Dw_total.a); |
| 1528 | VG_UMSG(fmt, "D1 misses: ", |
| 1529 | D_total.m1, Dr_total.m1, Dw_total.m1); |
| 1530 | VG_UMSG(fmt, "L2d misses: ", |
| 1531 | D_total.m2, Dr_total.m2, Dw_total.m2); |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 1532 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1533 | if (0 == D_total.a) D_total.a = 1; |
| 1534 | if (0 == Dr_total.a) Dr_total.a = 1; |
| 1535 | if (0 == Dw_total.a) Dw_total.a = 1; |
| 1536 | VG_(percentify)( D_total.m1, D_total.a, 1, l1+1, buf1); |
| 1537 | VG_(percentify)(Dr_total.m1, Dr_total.a, 1, l2+1, buf2); |
| 1538 | VG_(percentify)(Dw_total.m1, Dw_total.a, 1, l3+1, buf3); |
njn | 6f74a7e | 2009-03-12 00:06:45 +0000 | [diff] [blame] | 1539 | VG_UMSG("D1 miss rate: %s (%s + %s )", buf1, buf2,buf3); |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1540 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1541 | VG_(percentify)( D_total.m2, D_total.a, 1, l1+1, buf1); |
| 1542 | VG_(percentify)(Dr_total.m2, Dr_total.a, 1, l2+1, buf2); |
| 1543 | VG_(percentify)(Dw_total.m2, Dw_total.a, 1, l3+1, buf3); |
njn | 6f74a7e | 2009-03-12 00:06:45 +0000 | [diff] [blame] | 1544 | VG_UMSG("L2d miss rate: %s (%s + %s )", buf1, buf2,buf3); |
| 1545 | VG_UMSG(""); |
njn | 1d021fa | 2002-05-02 13:56:34 +0000 | [diff] [blame] | 1546 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1547 | /* L2 overall results */ |
njn | 1d021fa | 2002-05-02 13:56:34 +0000 | [diff] [blame] | 1548 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1549 | L2_total = Dr_total.m1 + Dw_total.m1 + Ir_total.m1; |
| 1550 | L2_total_r = Dr_total.m1 + Ir_total.m1; |
| 1551 | L2_total_w = Dw_total.m1; |
njn | 6f74a7e | 2009-03-12 00:06:45 +0000 | [diff] [blame] | 1552 | VG_UMSG(fmt, "L2 refs: ", |
| 1553 | L2_total, L2_total_r, L2_total_w); |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1554 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1555 | L2_total_m = Dr_total.m2 + Dw_total.m2 + Ir_total.m2; |
| 1556 | L2_total_mr = Dr_total.m2 + Ir_total.m2; |
| 1557 | L2_total_mw = Dw_total.m2; |
njn | 6f74a7e | 2009-03-12 00:06:45 +0000 | [diff] [blame] | 1558 | VG_UMSG(fmt, "L2 misses: ", |
| 1559 | L2_total_m, L2_total_mr, L2_total_mw); |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 1560 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1561 | VG_(percentify)(L2_total_m, (Ir_total.a + D_total.a), 1, l1+1, buf1); |
| 1562 | VG_(percentify)(L2_total_mr, (Ir_total.a + Dr_total.a), 1, l2+1, buf2); |
| 1563 | VG_(percentify)(L2_total_mw, Dw_total.a, 1, l3+1, buf3); |
njn | 6f74a7e | 2009-03-12 00:06:45 +0000 | [diff] [blame] | 1564 | VG_UMSG("L2 miss rate: %s (%s + %s )", buf1, buf2,buf3); |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1565 | } |
| 1566 | |
| 1567 | /* If branch profiling is enabled, show branch overall results. */ |
| 1568 | if (clo_branch_sim) { |
| 1569 | /* Make format string, getting width right for numbers */ |
| 1570 | VG_(sprintf)(fmt, "%%s %%,%dllu (%%,%dllu cond + %%,%dllu ind)", l1, l2, l3); |
| 1571 | |
| 1572 | if (0 == Bc_total.b) Bc_total.b = 1; |
| 1573 | if (0 == Bi_total.b) Bi_total.b = 1; |
| 1574 | B_total.b = Bc_total.b + Bi_total.b; |
| 1575 | B_total.mp = Bc_total.mp + Bi_total.mp; |
| 1576 | |
njn | 6f74a7e | 2009-03-12 00:06:45 +0000 | [diff] [blame] | 1577 | VG_UMSG(""); |
| 1578 | VG_UMSG(fmt, "Branches: ", |
| 1579 | B_total.b, Bc_total.b, Bi_total.b); |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1580 | |
njn | 6f74a7e | 2009-03-12 00:06:45 +0000 | [diff] [blame] | 1581 | VG_UMSG(fmt, "Mispredicts: ", |
| 1582 | B_total.mp, Bc_total.mp, Bi_total.mp); |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1583 | |
| 1584 | VG_(percentify)(B_total.mp, B_total.b, 1, l1+1, buf1); |
| 1585 | VG_(percentify)(Bc_total.mp, Bc_total.b, 1, l2+1, buf2); |
| 1586 | VG_(percentify)(Bi_total.mp, Bi_total.b, 1, l3+1, buf3); |
| 1587 | |
njn | 6f74a7e | 2009-03-12 00:06:45 +0000 | [diff] [blame] | 1588 | VG_UMSG("Mispred rate: %s (%s + %s )", buf1, buf2,buf3); |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1589 | } |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1590 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 1591 | // Various stats |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1592 | if (VG_(clo_verbosity) > 1) { |
njn | 1baf7db | 2006-04-18 22:34:48 +0000 | [diff] [blame] | 1593 | Int debug_lookups = full_debugs + fn_debugs + |
| 1594 | file_line_debugs + no_debugs; |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 1595 | |
njn | 6f74a7e | 2009-03-12 00:06:45 +0000 | [diff] [blame] | 1596 | VG_DMSG(""); |
| 1597 | VG_DMSG("cachegrind: distinct files: %d", distinct_files); |
| 1598 | VG_DMSG("cachegrind: distinct fns: %d", distinct_fns); |
| 1599 | VG_DMSG("cachegrind: distinct lines: %d", distinct_lines); |
| 1600 | VG_DMSG("cachegrind: distinct instrs:%d", distinct_instrs); |
| 1601 | VG_DMSG("cachegrind: debug lookups : %d", debug_lookups); |
njn | 1baf7db | 2006-04-18 22:34:48 +0000 | [diff] [blame] | 1602 | |
| 1603 | VG_(percentify)(full_debugs, debug_lookups, 1, 6, buf1); |
| 1604 | VG_(percentify)(file_line_debugs, debug_lookups, 1, 6, buf2); |
| 1605 | VG_(percentify)(fn_debugs, debug_lookups, 1, 6, buf3); |
| 1606 | VG_(percentify)(no_debugs, debug_lookups, 1, 6, buf4); |
njn | 6f74a7e | 2009-03-12 00:06:45 +0000 | [diff] [blame] | 1607 | VG_DMSG("cachegrind: with full info:%s (%d)", |
| 1608 | buf1, full_debugs); |
| 1609 | VG_DMSG("cachegrind: with file/line info:%s (%d)", |
| 1610 | buf2, file_line_debugs); |
| 1611 | VG_DMSG("cachegrind: with fn name info:%s (%d)", |
| 1612 | buf3, fn_debugs); |
| 1613 | VG_DMSG("cachegrind: with zero info:%s (%d)", |
| 1614 | buf4, no_debugs); |
njn | 1baf7db | 2006-04-18 22:34:48 +0000 | [diff] [blame] | 1615 | |
njn | 6f74a7e | 2009-03-12 00:06:45 +0000 | [diff] [blame] | 1616 | VG_DMSG("cachegrind: string table size: %lu", |
| 1617 | VG_(OSetGen_Size)(stringTable)); |
| 1618 | VG_DMSG("cachegrind: CC table size: %lu", |
| 1619 | VG_(OSetGen_Size)(CC_table)); |
| 1620 | VG_DMSG("cachegrind: InstrInfo table size: %lu", |
| 1621 | VG_(OSetGen_Size)(instrInfoTable)); |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1622 | } |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 1623 | } |
| 1624 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 1625 | /*--------------------------------------------------------------------*/ |
| 1626 | /*--- Discarding BB info ---*/ |
| 1627 | /*--------------------------------------------------------------------*/ |
sewardj | 18d7513 | 2002-05-16 11:06:21 +0000 | [diff] [blame] | 1628 | |
sewardj | a3a29a5 | 2005-10-12 16:16:03 +0000 | [diff] [blame] | 1629 | // Called when a translation is removed from the translation cache for |
| 1630 | // any reason at all: to free up space, because the guest code was |
| 1631 | // unmapped or modified, or for any arbitrary reason. |
sewardj | 4ba057c | 2005-10-18 12:04:18 +0000 | [diff] [blame] | 1632 | static |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 1633 | void cg_discard_superblock_info ( Addr64 orig_addr64, VexGuestExtents vge ) |
sewardj | 18d7513 | 2002-05-16 11:06:21 +0000 | [diff] [blame] | 1634 | { |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 1635 | SB_info* sbInfo; |
sewardj | 3a384b3 | 2006-01-22 01:12:51 +0000 | [diff] [blame] | 1636 | Addr orig_addr = (Addr)vge.base[0]; |
njn | 4294fd4 | 2002-06-05 14:41:10 +0000 | [diff] [blame] | 1637 | |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1638 | tl_assert(vge.n_used > 0); |
| 1639 | |
| 1640 | if (DEBUG_CG) |
sewardj | 4ba057c | 2005-10-18 12:04:18 +0000 | [diff] [blame] | 1641 | VG_(printf)( "discard_basic_block_info: %p, %p, %llu\n", |
| 1642 | (void*)(Addr)orig_addr, |
sewardj | 5155dec | 2005-10-12 10:09:23 +0000 | [diff] [blame] | 1643 | (void*)(Addr)vge.base[0], (ULong)vge.len[0]); |
njn | 4294fd4 | 2002-06-05 14:41:10 +0000 | [diff] [blame] | 1644 | |
sewardj | 4ba057c | 2005-10-18 12:04:18 +0000 | [diff] [blame] | 1645 | // Get BB info, remove from table, free BB info. Simple! Note that we |
| 1646 | // use orig_addr, not the first instruction address in vge. |
njn | e2a9ad3 | 2007-09-17 05:30:48 +0000 | [diff] [blame] | 1647 | sbInfo = VG_(OSetGen_Remove)(instrInfoTable, &orig_addr); |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 1648 | tl_assert(NULL != sbInfo); |
njn | e2a9ad3 | 2007-09-17 05:30:48 +0000 | [diff] [blame] | 1649 | VG_(OSetGen_FreeNode)(instrInfoTable, sbInfo); |
sewardj | 18d7513 | 2002-05-16 11:06:21 +0000 | [diff] [blame] | 1650 | } |
| 1651 | |
| 1652 | /*--------------------------------------------------------------------*/ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1653 | /*--- Command line processing ---*/ |
| 1654 | /*--------------------------------------------------------------------*/ |
| 1655 | |
njn | 0103de5 | 2005-10-10 16:49:01 +0000 | [diff] [blame] | 1656 | static void parse_cache_opt ( cache_t* cache, Char* opt ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1657 | { |
njn | 83df0b6 | 2009-02-25 01:01:05 +0000 | [diff] [blame] | 1658 | Long i1, i2, i3; |
| 1659 | Char* endptr; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1660 | |
njn | 83df0b6 | 2009-02-25 01:01:05 +0000 | [diff] [blame] | 1661 | // Option argument looks like "65536,2,64". Extract them. |
| 1662 | i1 = VG_(strtoll10)(opt, &endptr); if (*endptr != ',') goto bad; |
| 1663 | i2 = VG_(strtoll10)(endptr+1, &endptr); if (*endptr != ',') goto bad; |
| 1664 | i3 = VG_(strtoll10)(endptr+1, &endptr); if (*endptr != '\0') goto bad; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1665 | |
njn | 83df0b6 | 2009-02-25 01:01:05 +0000 | [diff] [blame] | 1666 | // Check for overflow. |
| 1667 | cache->size = (Int)i1; |
| 1668 | cache->assoc = (Int)i2; |
| 1669 | cache->line_size = (Int)i3; |
| 1670 | if (cache->size != i1) goto overflow; |
| 1671 | if (cache->assoc != i2) goto overflow; |
| 1672 | if (cache->line_size != i3) goto overflow; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1673 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1674 | return; |
| 1675 | |
njn | 83df0b6 | 2009-02-25 01:01:05 +0000 | [diff] [blame] | 1676 | overflow: |
njn | 6f74a7e | 2009-03-12 00:06:45 +0000 | [diff] [blame] | 1677 | VG_UMSG("one of the cache parameters was too large and overflowed\n"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1678 | bad: |
njn | 83df0b6 | 2009-02-25 01:01:05 +0000 | [diff] [blame] | 1679 | // XXX: this omits the "--I1/D1/L2=" part from the message, but that's |
| 1680 | // not a big deal. |
sewardj | 6893d65 | 2006-10-15 01:25:13 +0000 | [diff] [blame] | 1681 | VG_(err_bad_option)(opt); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1682 | } |
| 1683 | |
njn | 51d827b | 2005-05-09 01:02:08 +0000 | [diff] [blame] | 1684 | static Bool cg_process_cmd_line_option(Char* arg) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1685 | { |
njn | 83df0b6 | 2009-02-25 01:01:05 +0000 | [diff] [blame] | 1686 | Char* tmp_str; |
| 1687 | |
nethercote | 9313ac4 | 2004-07-06 21:54:20 +0000 | [diff] [blame] | 1688 | // 5 is length of "--I1=" |
njn | 83df0b6 | 2009-02-25 01:01:05 +0000 | [diff] [blame] | 1689 | if VG_STR_CLO(arg, "--I1", tmp_str) |
| 1690 | parse_cache_opt(&clo_I1_cache, tmp_str); |
| 1691 | else if VG_STR_CLO(arg, "--D1", tmp_str) |
| 1692 | parse_cache_opt(&clo_D1_cache, tmp_str); |
| 1693 | else if VG_STR_CLO(arg, "--L2", tmp_str) |
| 1694 | parse_cache_opt(&clo_L2_cache, tmp_str); |
| 1695 | |
| 1696 | else if VG_STR_CLO( arg, "--cachegrind-out-file", clo_cachegrind_out_file) {} |
| 1697 | else if VG_BOOL_CLO(arg, "--cache-sim", clo_cache_sim) {} |
| 1698 | else if VG_BOOL_CLO(arg, "--branch-sim", clo_branch_sim) {} |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1699 | else |
| 1700 | return False; |
| 1701 | |
| 1702 | return True; |
| 1703 | } |
| 1704 | |
njn | 51d827b | 2005-05-09 01:02:08 +0000 | [diff] [blame] | 1705 | static void cg_print_usage(void) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1706 | { |
njn | 3e88418 | 2003-04-15 13:03:23 +0000 | [diff] [blame] | 1707 | VG_(printf)( |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1708 | " --I1=<size>,<assoc>,<line_size> set I1 cache manually\n" |
| 1709 | " --D1=<size>,<assoc>,<line_size> set D1 cache manually\n" |
njn | 3e88418 | 2003-04-15 13:03:23 +0000 | [diff] [blame] | 1710 | " --L2=<size>,<assoc>,<line_size> set L2 cache manually\n" |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1711 | " --cache-sim=yes|no [yes] collect cache stats?\n" |
| 1712 | " --branch-sim=yes|no [no] collect branch prediction stats?\n" |
njn | 374a36d | 2007-11-23 01:41:32 +0000 | [diff] [blame] | 1713 | " --cachegrind-out-file=<file> output file name [cachegrind.out.%%p]\n" |
njn | 3e88418 | 2003-04-15 13:03:23 +0000 | [diff] [blame] | 1714 | ); |
| 1715 | } |
| 1716 | |
njn | 51d827b | 2005-05-09 01:02:08 +0000 | [diff] [blame] | 1717 | static void cg_print_debug_usage(void) |
njn | 3e88418 | 2003-04-15 13:03:23 +0000 | [diff] [blame] | 1718 | { |
| 1719 | VG_(printf)( |
| 1720 | " (none)\n" |
| 1721 | ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1722 | } |
| 1723 | |
| 1724 | /*--------------------------------------------------------------------*/ |
| 1725 | /*--- Setup ---*/ |
| 1726 | /*--------------------------------------------------------------------*/ |
| 1727 | |
sewardj | e1216cb | 2007-02-07 19:55:30 +0000 | [diff] [blame] | 1728 | static void cg_post_clo_init(void); /* just below */ |
| 1729 | |
njn | 51d827b | 2005-05-09 01:02:08 +0000 | [diff] [blame] | 1730 | static void cg_pre_clo_init(void) |
| 1731 | { |
njn | 51d827b | 2005-05-09 01:02:08 +0000 | [diff] [blame] | 1732 | VG_(details_name) ("Cachegrind"); |
| 1733 | VG_(details_version) (NULL); |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1734 | VG_(details_description) ("a cache and branch-prediction profiler"); |
njn | 51d827b | 2005-05-09 01:02:08 +0000 | [diff] [blame] | 1735 | VG_(details_copyright_author)( |
njn | 9f20746 | 2009-03-10 22:02:09 +0000 | [diff] [blame] | 1736 | "Copyright (C) 2002-2009, and GNU GPL'd, by Nicholas Nethercote et al."); |
njn | 51d827b | 2005-05-09 01:02:08 +0000 | [diff] [blame] | 1737 | VG_(details_bug_reports_to) (VG_BUGS_TO); |
sewardj | e808930 | 2006-10-17 02:15:17 +0000 | [diff] [blame] | 1738 | VG_(details_avg_translation_sizeB) ( 500 ); |
njn | 51d827b | 2005-05-09 01:02:08 +0000 | [diff] [blame] | 1739 | |
| 1740 | VG_(basic_tool_funcs) (cg_post_clo_init, |
| 1741 | cg_instrument, |
| 1742 | cg_fini); |
| 1743 | |
sewardj | 0b9d74a | 2006-12-24 02:24:11 +0000 | [diff] [blame] | 1744 | VG_(needs_superblock_discards)(cg_discard_superblock_info); |
njn | 51d827b | 2005-05-09 01:02:08 +0000 | [diff] [blame] | 1745 | VG_(needs_command_line_options)(cg_process_cmd_line_option, |
| 1746 | cg_print_usage, |
| 1747 | cg_print_debug_usage); |
sewardj | e1216cb | 2007-02-07 19:55:30 +0000 | [diff] [blame] | 1748 | } |
| 1749 | |
| 1750 | static void cg_post_clo_init(void) |
| 1751 | { |
sewardj | e1216cb | 2007-02-07 19:55:30 +0000 | [diff] [blame] | 1752 | cache_t I1c, D1c, L2c; |
njn | 51d827b | 2005-05-09 01:02:08 +0000 | [diff] [blame] | 1753 | |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1754 | /* Can't disable both cache and branch profiling */ |
| 1755 | if ((!clo_cache_sim) && (!clo_branch_sim)) { |
njn | 6f74a7e | 2009-03-12 00:06:45 +0000 | [diff] [blame] | 1756 | VG_UMSG("ERROR: --cache-sim=no --branch-sim=no is not allowed."); |
| 1757 | VG_UMSG("You must select cache profiling, or branch profiling, or both."); |
sewardj | 8badbaa | 2007-05-08 09:20:25 +0000 | [diff] [blame] | 1758 | VG_(exit)(2); |
| 1759 | } |
| 1760 | |
njn | e2a9ad3 | 2007-09-17 05:30:48 +0000 | [diff] [blame] | 1761 | CC_table = |
| 1762 | VG_(OSetGen_Create)(offsetof(LineCC, loc), |
| 1763 | cmp_CodeLoc_LineCC, |
sewardj | 9c606bd | 2008-09-18 18:12:50 +0000 | [diff] [blame] | 1764 | VG_(malloc), "cg.main.cpci.1", |
| 1765 | VG_(free)); |
njn | e2a9ad3 | 2007-09-17 05:30:48 +0000 | [diff] [blame] | 1766 | instrInfoTable = |
| 1767 | VG_(OSetGen_Create)(/*keyOff*/0, |
| 1768 | NULL, |
sewardj | 9c606bd | 2008-09-18 18:12:50 +0000 | [diff] [blame] | 1769 | VG_(malloc), "cg.main.cpci.2", |
| 1770 | VG_(free)); |
njn | e2a9ad3 | 2007-09-17 05:30:48 +0000 | [diff] [blame] | 1771 | stringTable = |
| 1772 | VG_(OSetGen_Create)(/*keyOff*/0, |
| 1773 | stringCmp, |
sewardj | 9c606bd | 2008-09-18 18:12:50 +0000 | [diff] [blame] | 1774 | VG_(malloc), "cg.main.cpci.3", |
| 1775 | VG_(free)); |
sewardj | e1216cb | 2007-02-07 19:55:30 +0000 | [diff] [blame] | 1776 | |
| 1777 | configure_caches(&I1c, &D1c, &L2c); |
| 1778 | |
| 1779 | cachesim_I1_initcache(I1c); |
| 1780 | cachesim_D1_initcache(D1c); |
| 1781 | cachesim_L2_initcache(L2c); |
njn | 51d827b | 2005-05-09 01:02:08 +0000 | [diff] [blame] | 1782 | } |
| 1783 | |
sewardj | 45f4e7c | 2005-09-27 19:20:21 +0000 | [diff] [blame] | 1784 | VG_DETERMINE_INTERFACE_VERSION(cg_pre_clo_init) |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 1785 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1786 | /*--------------------------------------------------------------------*/ |
njn | f69f945 | 2005-07-03 17:53:11 +0000 | [diff] [blame] | 1787 | /*--- end ---*/ |
sewardj | 18d7513 | 2002-05-16 11:06:21 +0000 | [diff] [blame] | 1788 | /*--------------------------------------------------------------------*/ |
njn | d3bef4f | 2005-10-15 17:46:18 +0000 | [diff] [blame] | 1789 | |