blob: 2a3f0f121a2469b31fbf8760e88cce922677a3e3 [file] [log] [blame]
sewardjde4a1d02002-03-22 01:27:54 +00001
2/*--------------------------------------------------------------------*/
njn2e8f4ef2005-05-14 21:44:20 +00003/*--- Asm-only TransTab stuff. pub_core_transtab_asm.h ---*/
sewardjde4a1d02002-03-22 01:27:54 +00004/*--------------------------------------------------------------------*/
5
6/*
njnb9c427c2004-12-01 14:14:42 +00007 This file is part of Valgrind, a dynamic binary instrumentation
8 framework.
sewardjde4a1d02002-03-22 01:27:54 +00009
sewardj0f157dd2013-10-18 14:27:36 +000010 Copyright (C) 2000-2013 Julian Seward
sewardjde4a1d02002-03-22 01:27:54 +000011 jseward@acm.org
sewardjde4a1d02002-03-22 01:27:54 +000012
13 This program is free software; you can redistribute it and/or
14 modify it under the terms of the GNU General Public License as
15 published by the Free Software Foundation; either version 2 of the
16 License, or (at your option) any later version.
17
18 This program is distributed in the hope that it will be useful, but
19 WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21 General Public License for more details.
22
23 You should have received a copy of the GNU General Public License
24 along with this program; if not, write to the Free Software
25 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
26 02111-1307, USA.
27
njn25e49d8e72002-09-23 09:36:25 +000028 The GNU General Public License is contained in the file COPYING.
sewardjde4a1d02002-03-22 01:27:54 +000029*/
30
njn2e8f4ef2005-05-14 21:44:20 +000031#ifndef __PUB_CORE_TRANSTAB_ASM_H
32#define __PUB_CORE_TRANSTAB_ASM_H
sewardj91f62782004-11-29 19:47:54 +000033
sewardj3387dda2005-12-26 17:58:58 +000034/* Constants for the fast translation lookup cache. It is a direct
35 mapped cache, with 2^VG_TT_FAST_BITS entries.
36
37 On x86/amd64, the cache index is computed as
38 'address[VG_TT_FAST_BITS-1 : 0]'.
39
sewardjf0c12502014-01-12 12:54:00 +000040 On ppc32/ppc64/mips32/mips64/arm64, the bottom two bits of
41 instruction addresses are zero, which means that function causes
42 only 1/4 of the entries to ever be used. So instead the function
43 is '(address >>u 2)[VG_TT_FAST_BITS-1 : 0]' on those targets.
sewardj59570ff2010-01-01 11:59:33 +000044
sewardj291849f2012-04-20 23:58:55 +000045 On ARM we shift by 1, since Thumb insns can be of size 2, hence to
46 minimise collisions and maximise cache utilisation we need to take
47 into account all but the least significant bit.
sewardjb5b87402011-03-07 16:05:35 +000048
49 On s390x the rightmost bit of an instruction address is zero.
50 For best table utilization shift the address to the right by 1 bit. */
sewardj3387dda2005-12-26 17:58:58 +000051
sewardjce29f372005-10-19 11:23:07 +000052#define VG_TT_FAST_BITS 15
sewardjde4a1d02002-03-22 01:27:54 +000053#define VG_TT_FAST_SIZE (1 << VG_TT_FAST_BITS)
54#define VG_TT_FAST_MASK ((VG_TT_FAST_SIZE) - 1)
55
sewardj3387dda2005-12-26 17:58:58 +000056/* This macro isn't usable in asm land; nevertheless this seems
57 like a good place to put it. */
sewardj4778c662011-04-28 14:58:15 +000058
sewardj3387dda2005-12-26 17:58:58 +000059#if defined(VGA_x86) || defined(VGA_amd64)
60# define VG_TT_FAST_HASH(_addr) ((((UWord)(_addr)) ) & VG_TT_FAST_MASK)
sewardj4778c662011-04-28 14:58:15 +000061
62#elif defined(VGA_s390x) || defined(VGA_arm)
sewardjb5b87402011-03-07 16:05:35 +000063# define VG_TT_FAST_HASH(_addr) ((((UWord)(_addr)) >> 1) & VG_TT_FAST_MASK)
sewardj4778c662011-04-28 14:58:15 +000064
petarj4df0bfc2013-02-27 23:17:33 +000065#elif defined(VGA_ppc32) || defined(VGA_ppc64) || defined(VGA_mips32) \
sewardjf0c12502014-01-12 12:54:00 +000066 || defined(VGA_mips64) || defined(VGA_arm64)
sewardj4778c662011-04-28 14:58:15 +000067# define VG_TT_FAST_HASH(_addr) ((((UWord)(_addr)) >> 2) & VG_TT_FAST_MASK)
68
sewardj3387dda2005-12-26 17:58:58 +000069#else
70# error "VG_TT_FAST_HASH: unknown platform"
71#endif
72
njn2e8f4ef2005-05-14 21:44:20 +000073#endif // __PUB_CORE_TRANSTAB_ASM_H
sewardjde4a1d02002-03-22 01:27:54 +000074
75/*--------------------------------------------------------------------*/
nethercote5a2664c2004-09-02 15:37:39 +000076/*--- end ---*/
sewardjde4a1d02002-03-22 01:27:54 +000077/*--------------------------------------------------------------------*/