sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1 | |
| 2 | /*--------------------------------------------------------------------*/ |
| 3 | /*--- The JITter: translate ucode back to x86 code. ---*/ |
| 4 | /*--- vg_from_ucode.c ---*/ |
| 5 | /*--------------------------------------------------------------------*/ |
njn | c953984 | 2002-10-02 13:26:35 +0000 | [diff] [blame] | 6 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 7 | /* |
njn | c953984 | 2002-10-02 13:26:35 +0000 | [diff] [blame] | 8 | This file is part of Valgrind, an extensible x86 protected-mode |
| 9 | emulator for monitoring program execution on x86-Unixes. |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 10 | |
| 11 | Copyright (C) 2000-2002 Julian Seward |
| 12 | jseward@acm.org |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 13 | |
| 14 | This program is free software; you can redistribute it and/or |
| 15 | modify it under the terms of the GNU General Public License as |
| 16 | published by the Free Software Foundation; either version 2 of the |
| 17 | License, or (at your option) any later version. |
| 18 | |
| 19 | This program is distributed in the hope that it will be useful, but |
| 20 | WITHOUT ANY WARRANTY; without even the implied warranty of |
| 21 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 22 | General Public License for more details. |
| 23 | |
| 24 | You should have received a copy of the GNU General Public License |
| 25 | along with this program; if not, write to the Free Software |
| 26 | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA |
| 27 | 02111-1307, USA. |
| 28 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 29 | The GNU General Public License is contained in the file COPYING. |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 30 | */ |
| 31 | |
| 32 | #include "vg_include.h" |
| 33 | |
| 34 | |
| 35 | /*------------------------------------------------------------*/ |
| 36 | /*--- Renamings of frequently-used global functions. ---*/ |
| 37 | /*------------------------------------------------------------*/ |
| 38 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 39 | #define dis VG_(print_codegen) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 40 | |
| 41 | /*------------------------------------------------------------*/ |
| 42 | /*--- Instruction emission -- turning final uinstrs back ---*/ |
| 43 | /*--- into x86 code. ---*/ |
| 44 | /*------------------------------------------------------------*/ |
| 45 | |
| 46 | /* [2001-07-08 This comment is now somewhat out of date.] |
| 47 | |
| 48 | This is straightforward but for one thing: to facilitate generating |
| 49 | code in a single pass, we generate position-independent code. To |
| 50 | do this, calls and jmps to fixed addresses must specify the address |
| 51 | by first loading it into a register, and jump to/call that |
| 52 | register. Fortunately, the only jump to a literal is the jump back |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 53 | to vg_dispatch, and only %eax is live then, conveniently. UCode |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 54 | call insns may only have a register as target anyway, so there's no |
| 55 | need to do anything fancy for them. |
| 56 | |
| 57 | The emit_* routines constitute the lowest level of instruction |
| 58 | emission. They simply emit the sequence of bytes corresponding to |
| 59 | the relevant instruction, with no further ado. In particular there |
| 60 | is no checking about whether uses of byte registers makes sense, |
| 61 | nor whether shift insns have their first operand in %cl, etc. |
| 62 | |
| 63 | These issues are taken care of by the level above, the synth_* |
| 64 | routines. These detect impossible operand combinations and turn |
| 65 | them into sequences of legal instructions. Finally, emitUInstr is |
| 66 | phrased in terms of the synth_* abstraction layer. */ |
| 67 | |
| 68 | static UChar* emitted_code; |
| 69 | static Int emitted_code_used; |
| 70 | static Int emitted_code_size; |
| 71 | |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 72 | /* offset (in bytes into the basic block) */ |
| 73 | static UShort jumps[VG_MAX_JUMPS]; |
| 74 | static Int jumpidx; |
| 75 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 76 | /* Statistics about C functions called from generated code. */ |
| 77 | static UInt ccalls = 0; |
| 78 | static UInt ccall_reg_saves = 0; |
| 79 | static UInt ccall_args = 0; |
| 80 | static UInt ccall_arg_setup_instrs = 0; |
| 81 | static UInt ccall_stack_clears = 0; |
| 82 | static UInt ccall_retvals = 0; |
| 83 | static UInt ccall_retval_movs = 0; |
| 84 | |
| 85 | /* Statistics about frequency of each UInstr */ |
| 86 | typedef |
| 87 | struct { |
| 88 | UInt counts; |
| 89 | UInt size; |
| 90 | } Histogram; |
| 91 | |
| 92 | /* Automatically zeroed because it's static. */ |
| 93 | static Histogram histogram[100]; |
| 94 | |
| 95 | void VG_(print_ccall_stats)(void) |
| 96 | { |
| 97 | VG_(message)(Vg_DebugMsg, |
| 98 | " ccalls: %u C calls, %u%% saves+restores avoided" |
| 99 | " (%d bytes)", |
| 100 | ccalls, |
| 101 | 100-(UInt)(ccall_reg_saves/(double)(ccalls*3)*100), |
| 102 | ((ccalls*3) - ccall_reg_saves)*2); |
| 103 | VG_(message)(Vg_DebugMsg, |
| 104 | " %u args, avg 0.%d setup instrs each (%d bytes)", |
| 105 | ccall_args, |
| 106 | (UInt)(ccall_arg_setup_instrs/(double)ccall_args*100), |
| 107 | (ccall_args - ccall_arg_setup_instrs)*2); |
| 108 | VG_(message)(Vg_DebugMsg, |
| 109 | " %d%% clear the stack (%d bytes)", |
| 110 | (UInt)(ccall_stack_clears/(double)ccalls*100), |
| 111 | (ccalls - ccall_stack_clears)*3); |
| 112 | VG_(message)(Vg_DebugMsg, |
| 113 | " %u retvals, %u%% of reg-reg movs avoided (%d bytes)", |
| 114 | ccall_retvals, |
| 115 | ( ccall_retvals == 0 |
| 116 | ? 100 |
| 117 | : 100-(UInt)(ccall_retval_movs / |
| 118 | (double)ccall_retvals*100)), |
| 119 | (ccall_retvals-ccall_retval_movs)*2); |
| 120 | } |
| 121 | |
| 122 | void VG_(print_UInstr_histogram)(void) |
| 123 | { |
| 124 | Int i, j; |
| 125 | UInt total_counts = 0; |
| 126 | UInt total_size = 0; |
sewardj | 6c3769f | 2002-11-29 01:02:45 +0000 | [diff] [blame] | 127 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 128 | for (i = 0; i < 100; i++) { |
| 129 | total_counts += histogram[i].counts; |
| 130 | total_size += histogram[i].size; |
| 131 | } |
| 132 | |
| 133 | VG_(printf)("-- UInstr frequencies -----------\n"); |
| 134 | for (i = 0; i < 100; i++) { |
| 135 | if (0 != histogram[i].counts) { |
| 136 | |
| 137 | UInt count_pc = |
| 138 | (UInt)(histogram[i].counts/(double)total_counts*100 + 0.5); |
| 139 | UInt size_pc = |
| 140 | (UInt)(histogram[i].size /(double)total_size *100 + 0.5); |
| 141 | UInt avg_size = |
| 142 | (UInt)(histogram[i].size / (double)histogram[i].counts + 0.5); |
| 143 | |
| 144 | VG_(printf)("%-7s:%8u (%2u%%), avg %2dB (%2u%%) |", |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 145 | VG_(name_UOpcode)(True, i), |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 146 | histogram[i].counts, count_pc, |
| 147 | avg_size, size_pc); |
| 148 | |
| 149 | for (j = 0; j < size_pc; j++) VG_(printf)("O"); |
| 150 | VG_(printf)("\n"); |
| 151 | |
| 152 | } else { |
| 153 | vg_assert(0 == histogram[i].size); |
| 154 | } |
| 155 | } |
| 156 | |
| 157 | VG_(printf)("total UInstrs %u, total size %u\n", total_counts, total_size); |
| 158 | } |
| 159 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 160 | static void expandEmittedCode ( void ) |
| 161 | { |
| 162 | Int i; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 163 | UChar *tmp = VG_(arena_malloc)(VG_AR_JITTER, 2 * emitted_code_size); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 164 | /* VG_(printf)("expand to %d\n", 2 * emitted_code_size); */ |
| 165 | for (i = 0; i < emitted_code_size; i++) |
| 166 | tmp[i] = emitted_code[i]; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 167 | VG_(arena_free)(VG_AR_JITTER, emitted_code); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 168 | emitted_code = tmp; |
| 169 | emitted_code_size *= 2; |
| 170 | } |
| 171 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 172 | /* Local calls will be inlined, cross-module ones not */ |
| 173 | __inline__ void VG_(emitB) ( UInt b ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 174 | { |
| 175 | if (dis) { |
| 176 | if (b < 16) VG_(printf)("0%x ", b); else VG_(printf)("%2x ", b); |
| 177 | } |
| 178 | if (emitted_code_used == emitted_code_size) |
| 179 | expandEmittedCode(); |
| 180 | |
| 181 | emitted_code[emitted_code_used] = (UChar)b; |
| 182 | emitted_code_used++; |
| 183 | } |
| 184 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 185 | __inline__ void VG_(emitW) ( UInt l ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 186 | { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 187 | VG_(emitB) ( (l) & 0x000000FF ); |
| 188 | VG_(emitB) ( (l >> 8) & 0x000000FF ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 189 | } |
| 190 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 191 | __inline__ void VG_(emitL) ( UInt l ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 192 | { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 193 | VG_(emitB) ( (l) & 0x000000FF ); |
| 194 | VG_(emitB) ( (l >> 8) & 0x000000FF ); |
| 195 | VG_(emitB) ( (l >> 16) & 0x000000FF ); |
| 196 | VG_(emitB) ( (l >> 24) & 0x000000FF ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 197 | } |
| 198 | |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 199 | __inline__ void VG_(new_emit) ( void ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 200 | { |
| 201 | if (dis) |
| 202 | VG_(printf)("\t %4d: ", emitted_code_used ); |
| 203 | } |
| 204 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 205 | |
| 206 | /*----------------------------------------------------*/ |
| 207 | /*--- Addressing modes ---*/ |
| 208 | /*----------------------------------------------------*/ |
| 209 | |
| 210 | static __inline__ UChar mkModRegRM ( UChar mod, UChar reg, UChar regmem ) |
| 211 | { |
| 212 | return ((mod & 3) << 6) | ((reg & 7) << 3) | (regmem & 7); |
| 213 | } |
| 214 | |
| 215 | static __inline__ UChar mkSIB ( Int scale, Int regindex, Int regbase ) |
| 216 | { |
| 217 | Int shift; |
| 218 | switch (scale) { |
| 219 | case 1: shift = 0; break; |
| 220 | case 2: shift = 1; break; |
| 221 | case 4: shift = 2; break; |
| 222 | case 8: shift = 3; break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 223 | default: VG_(core_panic)( "mkSIB" ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 224 | } |
| 225 | return ((shift & 3) << 6) | ((regindex & 7) << 3) | (regbase & 7); |
| 226 | } |
| 227 | |
| 228 | static __inline__ void emit_amode_litmem_reg ( Addr addr, Int reg ) |
| 229 | { |
| 230 | /* ($ADDR), reg */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 231 | VG_(emitB) ( mkModRegRM(0, reg, 5) ); |
| 232 | VG_(emitL) ( addr ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 233 | } |
| 234 | |
| 235 | static __inline__ void emit_amode_regmem_reg ( Int regmem, Int reg ) |
| 236 | { |
| 237 | /* (regmem), reg */ |
| 238 | if (regmem == R_ESP) |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 239 | VG_(core_panic)("emit_amode_regmem_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 240 | if (regmem == R_EBP) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 241 | VG_(emitB) ( mkModRegRM(1, reg, 5) ); |
| 242 | VG_(emitB) ( 0x00 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 243 | } else { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 244 | VG_(emitB)( mkModRegRM(0, reg, regmem) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 245 | } |
| 246 | } |
| 247 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 248 | void VG_(emit_amode_offregmem_reg) ( Int off, Int regmem, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 249 | { |
| 250 | if (regmem == R_ESP) |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 251 | VG_(core_panic)("emit_amode_offregmem_reg(ESP)"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 252 | if (off < -128 || off > 127) { |
| 253 | /* Use a large offset */ |
| 254 | /* d32(regmem), reg */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 255 | VG_(emitB) ( mkModRegRM(2, reg, regmem) ); |
| 256 | VG_(emitL) ( off ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 257 | } else { |
| 258 | /* d8(regmem), reg */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 259 | VG_(emitB) ( mkModRegRM(1, reg, regmem) ); |
| 260 | VG_(emitB) ( off & 0xFF ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 261 | } |
| 262 | } |
| 263 | |
| 264 | static __inline__ void emit_amode_sib_reg ( Int off, Int scale, Int regbase, |
| 265 | Int regindex, Int reg ) |
| 266 | { |
| 267 | if (regindex == R_ESP) |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 268 | VG_(core_panic)("emit_amode_sib_reg(ESP)"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 269 | if (off < -128 || off > 127) { |
| 270 | /* Use a 32-bit offset */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 271 | VG_(emitB) ( mkModRegRM(2, reg, 4) ); /* SIB with 32-bit displacement */ |
| 272 | VG_(emitB) ( mkSIB( scale, regindex, regbase ) ); |
| 273 | VG_(emitL) ( off ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 274 | } else { |
| 275 | /* Use an 8-bit offset */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 276 | VG_(emitB) ( mkModRegRM(1, reg, 4) ); /* SIB with 8-bit displacement */ |
| 277 | VG_(emitB) ( mkSIB( scale, regindex, regbase ) ); |
| 278 | VG_(emitB) ( off & 0xFF ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 279 | } |
| 280 | } |
| 281 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 282 | void VG_(emit_amode_ereg_greg) ( Int e_reg, Int g_reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 283 | { |
| 284 | /* other_reg, reg */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 285 | VG_(emitB) ( mkModRegRM(3, g_reg, e_reg) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 286 | } |
| 287 | |
| 288 | static __inline__ void emit_amode_greg_ereg ( Int g_reg, Int e_reg ) |
| 289 | { |
| 290 | /* other_reg, reg */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 291 | VG_(emitB) ( mkModRegRM(3, g_reg, e_reg) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 292 | } |
| 293 | |
| 294 | |
| 295 | /*----------------------------------------------------*/ |
| 296 | /*--- Opcode translation ---*/ |
| 297 | /*----------------------------------------------------*/ |
| 298 | |
| 299 | static __inline__ Int mkGrp1opcode ( Opcode opc ) |
| 300 | { |
| 301 | switch (opc) { |
| 302 | case ADD: return 0; |
| 303 | case OR: return 1; |
| 304 | case ADC: return 2; |
| 305 | case SBB: return 3; |
| 306 | case AND: return 4; |
| 307 | case SUB: return 5; |
| 308 | case XOR: return 6; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 309 | default: VG_(core_panic)("mkGrp1opcode"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 310 | } |
| 311 | } |
| 312 | |
| 313 | static __inline__ Int mkGrp2opcode ( Opcode opc ) |
| 314 | { |
| 315 | switch (opc) { |
| 316 | case ROL: return 0; |
| 317 | case ROR: return 1; |
| 318 | case RCL: return 2; |
| 319 | case RCR: return 3; |
| 320 | case SHL: return 4; |
| 321 | case SHR: return 5; |
| 322 | case SAR: return 7; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 323 | default: VG_(core_panic)("mkGrp2opcode"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 324 | } |
| 325 | } |
| 326 | |
| 327 | static __inline__ Int mkGrp3opcode ( Opcode opc ) |
| 328 | { |
| 329 | switch (opc) { |
| 330 | case NOT: return 2; |
| 331 | case NEG: return 3; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 332 | default: VG_(core_panic)("mkGrp3opcode"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 333 | } |
| 334 | } |
| 335 | |
| 336 | static __inline__ Int mkGrp4opcode ( Opcode opc ) |
| 337 | { |
| 338 | switch (opc) { |
| 339 | case INC: return 0; |
| 340 | case DEC: return 1; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 341 | default: VG_(core_panic)("mkGrp4opcode"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 342 | } |
| 343 | } |
| 344 | |
| 345 | static __inline__ Int mkGrp5opcode ( Opcode opc ) |
| 346 | { |
| 347 | switch (opc) { |
| 348 | case CALLM: return 2; |
| 349 | case JMP: return 4; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 350 | default: VG_(core_panic)("mkGrp5opcode"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 351 | } |
| 352 | } |
| 353 | |
| 354 | static __inline__ UChar mkPrimaryOpcode ( Opcode opc ) |
| 355 | { |
| 356 | switch (opc) { |
| 357 | case ADD: return 0x00; |
| 358 | case ADC: return 0x10; |
| 359 | case AND: return 0x20; |
| 360 | case XOR: return 0x30; |
| 361 | case OR: return 0x08; |
| 362 | case SBB: return 0x18; |
| 363 | case SUB: return 0x28; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 364 | default: VG_(core_panic)("mkPrimaryOpcode"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 365 | } |
| 366 | } |
| 367 | |
| 368 | /*----------------------------------------------------*/ |
| 369 | /*--- v-size (4, or 2 with OSO) insn emitters ---*/ |
| 370 | /*----------------------------------------------------*/ |
| 371 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 372 | void VG_(emit_movv_offregmem_reg) ( Int sz, Int off, Int areg, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 373 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 374 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 375 | if (sz == 2) VG_(emitB) ( 0x66 ); |
| 376 | VG_(emitB) ( 0x8B ); /* MOV Ev, Gv */ |
| 377 | VG_(emit_amode_offregmem_reg) ( off, areg, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 378 | if (dis) |
| 379 | VG_(printf)( "\n\t\tmov%c\t0x%x(%s), %s\n", |
| 380 | nameISize(sz), off, nameIReg(4,areg), nameIReg(sz,reg)); |
| 381 | } |
| 382 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 383 | void VG_(emit_movv_reg_offregmem) ( Int sz, Int reg, Int off, Int areg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 384 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 385 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 386 | if (sz == 2) VG_(emitB) ( 0x66 ); |
| 387 | VG_(emitB) ( 0x89 ); /* MOV Gv, Ev */ |
| 388 | VG_(emit_amode_offregmem_reg) ( off, areg, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 389 | if (dis) |
| 390 | VG_(printf)( "\n\t\tmov%c\t%s, 0x%x(%s)\n", |
| 391 | nameISize(sz), nameIReg(sz,reg), off, nameIReg(4,areg)); |
| 392 | } |
| 393 | |
| 394 | static void emit_movv_regmem_reg ( Int sz, Int reg1, Int reg2 ) |
| 395 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 396 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 397 | if (sz == 2) VG_(emitB) ( 0x66 ); |
| 398 | VG_(emitB) ( 0x8B ); /* MOV Ev, Gv */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 399 | emit_amode_regmem_reg ( reg1, reg2 ); |
| 400 | if (dis) |
| 401 | VG_(printf)( "\n\t\tmov%c\t(%s), %s\n", |
| 402 | nameISize(sz), nameIReg(4,reg1), nameIReg(sz,reg2)); |
| 403 | } |
| 404 | |
| 405 | static void emit_movv_reg_regmem ( Int sz, Int reg1, Int reg2 ) |
| 406 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 407 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 408 | if (sz == 2) VG_(emitB) ( 0x66 ); |
| 409 | VG_(emitB) ( 0x89 ); /* MOV Gv, Ev */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 410 | emit_amode_regmem_reg ( reg2, reg1 ); |
| 411 | if (dis) |
| 412 | VG_(printf)( "\n\t\tmov%c\t%s, (%s)\n", |
| 413 | nameISize(sz), nameIReg(sz,reg1), nameIReg(4,reg2)); |
| 414 | } |
| 415 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 416 | void VG_(emit_movv_reg_reg) ( Int sz, Int reg1, Int reg2 ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 417 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 418 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 419 | if (sz == 2) VG_(emitB) ( 0x66 ); |
| 420 | VG_(emitB) ( 0x89 ); /* MOV Gv, Ev */ |
| 421 | VG_(emit_amode_ereg_greg) ( reg2, reg1 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 422 | if (dis) |
| 423 | VG_(printf)( "\n\t\tmov%c\t%s, %s\n", |
| 424 | nameISize(sz), nameIReg(sz,reg1), nameIReg(sz,reg2)); |
| 425 | } |
| 426 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 427 | void VG_(emit_nonshiftopv_lit_reg) ( Int sz, Opcode opc, UInt lit, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 428 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 429 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 430 | if (sz == 2) VG_(emitB) ( 0x66 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 431 | if (lit == VG_(extend_s_8to32)(lit & 0x000000FF)) { |
| 432 | /* short form OK */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 433 | VG_(emitB) ( 0x83 ); /* Grp1 Ib,Ev */ |
| 434 | VG_(emit_amode_ereg_greg) ( reg, mkGrp1opcode(opc) ); |
| 435 | VG_(emitB) ( lit & 0x000000FF ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 436 | } else { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 437 | VG_(emitB) ( 0x81 ); /* Grp1 Iv,Ev */ |
| 438 | VG_(emit_amode_ereg_greg) ( reg, mkGrp1opcode(opc) ); |
| 439 | if (sz == 2) VG_(emitW) ( lit ); else VG_(emitL) ( lit ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 440 | } |
| 441 | if (dis) |
| 442 | VG_(printf)( "\n\t\t%s%c\t$0x%x, %s\n", |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 443 | VG_(name_UOpcode)(False,opc), nameISize(sz), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 444 | lit, nameIReg(sz,reg)); |
| 445 | } |
| 446 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 447 | void VG_(emit_shiftopv_lit_reg) ( Int sz, Opcode opc, UInt lit, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 448 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 449 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 450 | if (sz == 2) VG_(emitB) ( 0x66 ); |
| 451 | VG_(emitB) ( 0xC1 ); /* Grp2 Ib,Ev */ |
| 452 | VG_(emit_amode_ereg_greg) ( reg, mkGrp2opcode(opc) ); |
| 453 | VG_(emitB) ( lit ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 454 | if (dis) |
| 455 | VG_(printf)( "\n\t\t%s%c\t$%d, %s\n", |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 456 | VG_(name_UOpcode)(False,opc), nameISize(sz), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 457 | lit, nameIReg(sz,reg)); |
| 458 | } |
| 459 | |
| 460 | static void emit_shiftopv_cl_stack0 ( Int sz, Opcode opc ) |
| 461 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 462 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 463 | if (sz == 2) VG_(emitB) ( 0x66 ); |
| 464 | VG_(emitB) ( 0xD3 ); /* Grp2 CL,Ev */ |
| 465 | VG_(emitB) ( mkModRegRM ( 1, mkGrp2opcode(opc), 4 ) ); |
| 466 | VG_(emitB) ( 0x24 ); /* a SIB, I think `d8(%esp)' */ |
| 467 | VG_(emitB) ( 0x00 ); /* the d8 displacement */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 468 | if (dis) |
| 469 | VG_(printf)("\n\t\t%s%c %%cl, 0(%%esp)\n", |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 470 | VG_(name_UOpcode)(False,opc), nameISize(sz) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 471 | } |
| 472 | |
| 473 | static void emit_shiftopb_cl_stack0 ( Opcode opc ) |
| 474 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 475 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 476 | VG_(emitB) ( 0xD2 ); /* Grp2 CL,Eb */ |
| 477 | VG_(emitB) ( mkModRegRM ( 1, mkGrp2opcode(opc), 4 ) ); |
| 478 | VG_(emitB) ( 0x24 ); /* a SIB, I think `d8(%esp)' */ |
| 479 | VG_(emitB) ( 0x00 ); /* the d8 displacement */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 480 | if (dis) |
| 481 | VG_(printf)("\n\t\t%s%c %%cl, 0(%%esp)\n", |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 482 | VG_(name_UOpcode)(False,opc), nameISize(1) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 483 | } |
| 484 | |
| 485 | static void emit_nonshiftopv_offregmem_reg ( Int sz, Opcode opc, |
| 486 | Int off, Int areg, Int reg ) |
| 487 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 488 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 489 | if (sz == 2) VG_(emitB) ( 0x66 ); |
| 490 | VG_(emitB) ( 3 + mkPrimaryOpcode(opc) ); /* op Ev, Gv */ |
| 491 | VG_(emit_amode_offregmem_reg) ( off, areg, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 492 | if (dis) |
| 493 | VG_(printf)( "\n\t\t%s%c\t0x%x(%s), %s\n", |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 494 | VG_(name_UOpcode)(False,opc), nameISize(sz), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 495 | off, nameIReg(4,areg), nameIReg(sz,reg)); |
| 496 | } |
| 497 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 498 | void VG_(emit_nonshiftopv_reg_reg) ( Int sz, Opcode opc, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 499 | Int reg1, Int reg2 ) |
| 500 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 501 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 502 | if (sz == 2) VG_(emitB) ( 0x66 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 503 | # if 0 |
| 504 | /* Perfectly correct, but the GNU assembler uses the other form. |
| 505 | Therefore we too use the other form, to aid verification. */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 506 | VG_(emitB) ( 3 + mkPrimaryOpcode(opc) ); /* op Ev, Gv */ |
| 507 | VG_(emit_amode_ereg_greg) ( reg1, reg2 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 508 | # else |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 509 | VG_(emitB) ( 1 + mkPrimaryOpcode(opc) ); /* op Gv, Ev */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 510 | emit_amode_greg_ereg ( reg1, reg2 ); |
| 511 | # endif |
| 512 | if (dis) |
| 513 | VG_(printf)( "\n\t\t%s%c\t%s, %s\n", |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 514 | VG_(name_UOpcode)(False,opc), nameISize(sz), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 515 | nameIReg(sz,reg1), nameIReg(sz,reg2)); |
| 516 | } |
| 517 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 518 | void VG_(emit_movv_lit_reg) ( Int sz, UInt lit, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 519 | { |
| 520 | if (lit == 0) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 521 | VG_(emit_nonshiftopv_reg_reg) ( sz, XOR, reg, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 522 | return; |
| 523 | } |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 524 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 525 | if (sz == 2) VG_(emitB) ( 0x66 ); |
| 526 | VG_(emitB) ( 0xB8+reg ); /* MOV imm, Gv */ |
| 527 | if (sz == 2) VG_(emitW) ( lit ); else VG_(emitL) ( lit ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 528 | if (dis) |
| 529 | VG_(printf)( "\n\t\tmov%c\t$0x%x, %s\n", |
| 530 | nameISize(sz), lit, nameIReg(sz,reg)); |
| 531 | } |
| 532 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 533 | void VG_(emit_unaryopv_reg) ( Int sz, Opcode opc, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 534 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 535 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 536 | if (sz == 2) VG_(emitB) ( 0x66 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 537 | switch (opc) { |
| 538 | case NEG: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 539 | VG_(emitB) ( 0xF7 ); |
| 540 | VG_(emit_amode_ereg_greg) ( reg, mkGrp3opcode(NEG) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 541 | if (dis) |
| 542 | VG_(printf)( "\n\t\tneg%c\t%s\n", |
| 543 | nameISize(sz), nameIReg(sz,reg)); |
| 544 | break; |
| 545 | case NOT: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 546 | VG_(emitB) ( 0xF7 ); |
| 547 | VG_(emit_amode_ereg_greg) ( reg, mkGrp3opcode(NOT) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 548 | if (dis) |
| 549 | VG_(printf)( "\n\t\tnot%c\t%s\n", |
| 550 | nameISize(sz), nameIReg(sz,reg)); |
| 551 | break; |
| 552 | case DEC: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 553 | VG_(emitB) ( 0x48 + reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 554 | if (dis) |
| 555 | VG_(printf)( "\n\t\tdec%c\t%s\n", |
| 556 | nameISize(sz), nameIReg(sz,reg)); |
| 557 | break; |
| 558 | case INC: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 559 | VG_(emitB) ( 0x40 + reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 560 | if (dis) |
| 561 | VG_(printf)( "\n\t\tinc%c\t%s\n", |
| 562 | nameISize(sz), nameIReg(sz,reg)); |
| 563 | break; |
| 564 | default: |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 565 | VG_(core_panic)("VG_(emit_unaryopv_reg)"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 566 | } |
| 567 | } |
| 568 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 569 | void VG_(emit_pushv_reg) ( Int sz, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 570 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 571 | VG_(new_emit)(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 572 | if (sz == 2) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 573 | VG_(emitB) ( 0x66 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 574 | } else { |
| 575 | vg_assert(sz == 4); |
| 576 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 577 | VG_(emitB) ( 0x50 + reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 578 | if (dis) |
| 579 | VG_(printf)("\n\t\tpush%c %s\n", nameISize(sz), nameIReg(sz,reg)); |
| 580 | } |
| 581 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 582 | void VG_(emit_popv_reg) ( Int sz, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 583 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 584 | VG_(new_emit)(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 585 | if (sz == 2) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 586 | VG_(emitB) ( 0x66 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 587 | } else { |
| 588 | vg_assert(sz == 4); |
| 589 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 590 | VG_(emitB) ( 0x58 + reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 591 | if (dis) |
| 592 | VG_(printf)("\n\t\tpop%c %s\n", nameISize(sz), nameIReg(sz,reg)); |
| 593 | } |
| 594 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 595 | void VG_(emit_pushl_lit32) ( UInt int32 ) |
| 596 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 597 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 598 | VG_(emitB) ( 0x68 ); |
| 599 | VG_(emitL) ( int32 ); |
| 600 | if (dis) |
| 601 | VG_(printf)("\n\t\tpushl $0x%x\n", int32 ); |
| 602 | } |
| 603 | |
| 604 | void VG_(emit_pushl_lit8) ( Int lit8 ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 605 | { |
| 606 | vg_assert(lit8 >= -128 && lit8 < 128); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 607 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 608 | VG_(emitB) ( 0x6A ); |
| 609 | VG_(emitB) ( (UChar)((UInt)lit8) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 610 | if (dis) |
| 611 | VG_(printf)("\n\t\tpushl $%d\n", lit8 ); |
| 612 | } |
| 613 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 614 | void VG_(emit_cmpl_zero_reg) ( Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 615 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 616 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 617 | VG_(emitB) ( 0x83 ); |
| 618 | VG_(emit_amode_ereg_greg) ( reg, 7 /* Grp 3 opcode for CMP */ ); |
| 619 | VG_(emitB) ( 0x00 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 620 | if (dis) |
| 621 | VG_(printf)("\n\t\tcmpl $0, %s\n", nameIReg(4,reg)); |
| 622 | } |
| 623 | |
| 624 | static void emit_swapl_reg_ECX ( Int reg ) |
| 625 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 626 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 627 | VG_(emitB) ( 0x87 ); /* XCHG Gv,Ev */ |
| 628 | VG_(emit_amode_ereg_greg) ( reg, R_ECX ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 629 | if (dis) |
| 630 | VG_(printf)("\n\t\txchgl %%ecx, %s\n", nameIReg(4,reg)); |
| 631 | } |
| 632 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 633 | void VG_(emit_swapl_reg_EAX) ( Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 634 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 635 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 636 | VG_(emitB) ( 0x90 + reg ); /* XCHG Gv,eAX */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 637 | if (dis) |
| 638 | VG_(printf)("\n\t\txchgl %%eax, %s\n", nameIReg(4,reg)); |
| 639 | } |
| 640 | |
| 641 | static void emit_swapl_reg_reg ( Int reg1, Int reg2 ) |
| 642 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 643 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 644 | VG_(emitB) ( 0x87 ); /* XCHG Gv,Ev */ |
| 645 | VG_(emit_amode_ereg_greg) ( reg1, reg2 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 646 | if (dis) |
| 647 | VG_(printf)("\n\t\txchgl %s, %s\n", nameIReg(4,reg1), |
| 648 | nameIReg(4,reg2)); |
| 649 | } |
| 650 | |
| 651 | static void emit_bswapl_reg ( Int reg ) |
| 652 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 653 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 654 | VG_(emitB) ( 0x0F ); |
| 655 | VG_(emitB) ( 0xC8 + reg ); /* BSWAP r32 */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 656 | if (dis) |
| 657 | VG_(printf)("\n\t\tbswapl %s\n", nameIReg(4,reg)); |
| 658 | } |
| 659 | |
| 660 | static void emit_movl_reg_reg ( Int regs, Int regd ) |
| 661 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 662 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 663 | VG_(emitB) ( 0x89 ); /* MOV Gv,Ev */ |
| 664 | VG_(emit_amode_ereg_greg) ( regd, regs ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 665 | if (dis) |
| 666 | VG_(printf)("\n\t\tmovl %s, %s\n", nameIReg(4,regs), nameIReg(4,regd)); |
| 667 | } |
| 668 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 669 | void VG_(emit_movv_lit_offregmem) ( Int sz, UInt lit, Int off, Int memreg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 670 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 671 | VG_(new_emit)(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 672 | if (sz == 2) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 673 | VG_(emitB) ( 0x66 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 674 | } else { |
| 675 | vg_assert(sz == 4); |
| 676 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 677 | VG_(emitB) ( 0xC7 ); /* Grp11 Ev */ |
| 678 | VG_(emit_amode_offregmem_reg) ( off, memreg, 0 /* Grp11 subopcode for MOV */ ); |
| 679 | if (sz == 2) VG_(emitW) ( lit ); else VG_(emitL) ( lit ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 680 | if (dis) |
| 681 | VG_(printf)( "\n\t\tmov%c\t$0x%x, 0x%x(%s)\n", |
| 682 | nameISize(sz), lit, off, nameIReg(4,memreg) ); |
| 683 | } |
| 684 | |
| 685 | |
| 686 | /*----------------------------------------------------*/ |
| 687 | /*--- b-size (1 byte) instruction emitters ---*/ |
| 688 | /*----------------------------------------------------*/ |
| 689 | |
| 690 | /* There is some doubt as to whether C6 (Grp 11) is in the |
| 691 | 486 insn set. ToDo: investigate. */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 692 | void VG_(emit_movb_lit_offregmem) ( UInt lit, Int off, Int memreg ) |
| 693 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 694 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 695 | VG_(emitB) ( 0xC6 ); /* Grp11 Eb */ |
| 696 | VG_(emit_amode_offregmem_reg) ( off, memreg, 0 /* Grp11 subopcode for MOV */ ); |
| 697 | VG_(emitB) ( lit ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 698 | if (dis) |
| 699 | VG_(printf)( "\n\t\tmovb\t$0x%x, 0x%x(%s)\n", |
| 700 | lit, off, nameIReg(4,memreg) ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 701 | } |
| 702 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 703 | static void emit_nonshiftopb_offregmem_reg ( Opcode opc, |
| 704 | Int off, Int areg, Int reg ) |
| 705 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 706 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 707 | VG_(emitB) ( 2 + mkPrimaryOpcode(opc) ); /* op Eb, Gb */ |
| 708 | VG_(emit_amode_offregmem_reg) ( off, areg, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 709 | if (dis) |
| 710 | VG_(printf)( "\n\t\t%sb\t0x%x(%s), %s\n", |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 711 | VG_(name_UOpcode)(False,opc), off, nameIReg(4,areg), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 712 | nameIReg(1,reg)); |
| 713 | } |
| 714 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 715 | void VG_(emit_movb_reg_offregmem) ( Int reg, Int off, Int areg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 716 | { |
| 717 | /* Could do better when reg == %al. */ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 718 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 719 | VG_(emitB) ( 0x88 ); /* MOV G1, E1 */ |
| 720 | VG_(emit_amode_offregmem_reg) ( off, areg, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 721 | if (dis) |
| 722 | VG_(printf)( "\n\t\tmovb\t%s, 0x%x(%s)\n", |
| 723 | nameIReg(1,reg), off, nameIReg(4,areg)); |
| 724 | } |
| 725 | |
| 726 | static void emit_nonshiftopb_reg_reg ( Opcode opc, Int reg1, Int reg2 ) |
| 727 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 728 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 729 | VG_(emitB) ( 2 + mkPrimaryOpcode(opc) ); /* op Eb, Gb */ |
| 730 | VG_(emit_amode_ereg_greg) ( reg1, reg2 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 731 | if (dis) |
| 732 | VG_(printf)( "\n\t\t%sb\t%s, %s\n", |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 733 | VG_(name_UOpcode)(False,opc), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 734 | nameIReg(1,reg1), nameIReg(1,reg2)); |
| 735 | } |
| 736 | |
| 737 | static void emit_movb_reg_regmem ( Int reg1, Int reg2 ) |
| 738 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 739 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 740 | VG_(emitB) ( 0x88 ); /* MOV G1, E1 */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 741 | emit_amode_regmem_reg ( reg2, reg1 ); |
| 742 | if (dis) |
| 743 | VG_(printf)( "\n\t\tmovb\t%s, (%s)\n", nameIReg(1,reg1), |
| 744 | nameIReg(4,reg2)); |
| 745 | } |
| 746 | |
| 747 | static void emit_nonshiftopb_lit_reg ( Opcode opc, UInt lit, Int reg ) |
| 748 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 749 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 750 | VG_(emitB) ( 0x80 ); /* Grp1 Ib,Eb */ |
| 751 | VG_(emit_amode_ereg_greg) ( reg, mkGrp1opcode(opc) ); |
| 752 | VG_(emitB) ( lit & 0x000000FF ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 753 | if (dis) |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 754 | VG_(printf)( "\n\t\t%sb\t$0x%x, %s\n", VG_(name_UOpcode)(False,opc), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 755 | lit, nameIReg(1,reg)); |
| 756 | } |
| 757 | |
| 758 | static void emit_shiftopb_lit_reg ( Opcode opc, UInt lit, Int reg ) |
| 759 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 760 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 761 | VG_(emitB) ( 0xC0 ); /* Grp2 Ib,Eb */ |
| 762 | VG_(emit_amode_ereg_greg) ( reg, mkGrp2opcode(opc) ); |
| 763 | VG_(emitB) ( lit ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 764 | if (dis) |
| 765 | VG_(printf)( "\n\t\t%sb\t$%d, %s\n", |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 766 | VG_(name_UOpcode)(False,opc), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 767 | lit, nameIReg(1,reg)); |
| 768 | } |
| 769 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 770 | void VG_(emit_unaryopb_reg) ( Opcode opc, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 771 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 772 | VG_(new_emit)(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 773 | switch (opc) { |
| 774 | case INC: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 775 | VG_(emitB) ( 0xFE ); |
| 776 | VG_(emit_amode_ereg_greg) ( reg, mkGrp4opcode(INC) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 777 | if (dis) |
| 778 | VG_(printf)( "\n\t\tincb\t%s\n", nameIReg(1,reg)); |
| 779 | break; |
| 780 | case DEC: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 781 | VG_(emitB) ( 0xFE ); |
| 782 | VG_(emit_amode_ereg_greg) ( reg, mkGrp4opcode(DEC) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 783 | if (dis) |
| 784 | VG_(printf)( "\n\t\tdecb\t%s\n", nameIReg(1,reg)); |
| 785 | break; |
| 786 | case NOT: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 787 | VG_(emitB) ( 0xF6 ); |
| 788 | VG_(emit_amode_ereg_greg) ( reg, mkGrp3opcode(NOT) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 789 | if (dis) |
| 790 | VG_(printf)( "\n\t\tnotb\t%s\n", nameIReg(1,reg)); |
| 791 | break; |
| 792 | case NEG: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 793 | VG_(emitB) ( 0xF6 ); |
| 794 | VG_(emit_amode_ereg_greg) ( reg, mkGrp3opcode(NEG) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 795 | if (dis) |
| 796 | VG_(printf)( "\n\t\tnegb\t%s\n", nameIReg(1,reg)); |
| 797 | break; |
| 798 | default: |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 799 | VG_(core_panic)("VG_(emit_unaryopb_reg)"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 800 | } |
| 801 | } |
| 802 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 803 | void VG_(emit_testb_lit_reg) ( UInt lit, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 804 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 805 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 806 | VG_(emitB) ( 0xF6 ); /* Grp3 Eb */ |
| 807 | VG_(emit_amode_ereg_greg) ( reg, 0 /* Grp3 subopcode for TEST */ ); |
| 808 | VG_(emitB) ( lit ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 809 | if (dis) |
| 810 | VG_(printf)("\n\t\ttestb $0x%x, %s\n", lit, nameIReg(1,reg)); |
| 811 | } |
| 812 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 813 | /*----------------------------------------------------*/ |
| 814 | /*--- zero-extended load emitters ---*/ |
| 815 | /*----------------------------------------------------*/ |
| 816 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 817 | void VG_(emit_movzbl_offregmem_reg) ( Int off, Int regmem, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 818 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 819 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 820 | VG_(emitB) ( 0x0F ); VG_(emitB) ( 0xB6 ); /* MOVZBL */ |
| 821 | VG_(emit_amode_offregmem_reg) ( off, regmem, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 822 | if (dis) |
| 823 | VG_(printf)( "\n\t\tmovzbl\t0x%x(%s), %s\n", |
| 824 | off, nameIReg(4,regmem), nameIReg(4,reg)); |
| 825 | } |
| 826 | |
| 827 | static void emit_movzbl_regmem_reg ( Int reg1, Int reg2 ) |
| 828 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 829 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 830 | VG_(emitB) ( 0x0F ); VG_(emitB) ( 0xB6 ); /* MOVZBL */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 831 | emit_amode_regmem_reg ( reg1, reg2 ); |
| 832 | if (dis) |
| 833 | VG_(printf)( "\n\t\tmovzbl\t(%s), %s\n", nameIReg(4,reg1), |
| 834 | nameIReg(4,reg2)); |
| 835 | } |
| 836 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 837 | void VG_(emit_movzwl_offregmem_reg) ( Int off, Int areg, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 838 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 839 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 840 | VG_(emitB) ( 0x0F ); VG_(emitB) ( 0xB7 ); /* MOVZWL */ |
| 841 | VG_(emit_amode_offregmem_reg) ( off, areg, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 842 | if (dis) |
| 843 | VG_(printf)( "\n\t\tmovzwl\t0x%x(%s), %s\n", |
| 844 | off, nameIReg(4,areg), nameIReg(4,reg)); |
| 845 | } |
| 846 | |
| 847 | static void emit_movzwl_regmem_reg ( Int reg1, Int reg2 ) |
| 848 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 849 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 850 | VG_(emitB) ( 0x0F ); VG_(emitB) ( 0xB7 ); /* MOVZWL */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 851 | emit_amode_regmem_reg ( reg1, reg2 ); |
| 852 | if (dis) |
| 853 | VG_(printf)( "\n\t\tmovzwl\t(%s), %s\n", nameIReg(4,reg1), |
| 854 | nameIReg(4,reg2)); |
| 855 | } |
| 856 | |
| 857 | /*----------------------------------------------------*/ |
| 858 | /*--- FPU instruction emitters ---*/ |
| 859 | /*----------------------------------------------------*/ |
| 860 | |
| 861 | static void emit_get_fpu_state ( void ) |
| 862 | { |
| 863 | Int off = 4 * VGOFF_(m_fpustate); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 864 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 865 | VG_(emitB) ( 0xDD ); VG_(emitB) ( 0xA5 ); /* frstor d32(%ebp) */ |
| 866 | VG_(emitL) ( off ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 867 | if (dis) |
| 868 | VG_(printf)("\n\t\tfrstor\t%d(%%ebp)\n", off ); |
| 869 | } |
| 870 | |
| 871 | static void emit_put_fpu_state ( void ) |
| 872 | { |
| 873 | Int off = 4 * VGOFF_(m_fpustate); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 874 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 875 | VG_(emitB) ( 0xDD ); VG_(emitB) ( 0xB5 ); /* fnsave d32(%ebp) */ |
| 876 | VG_(emitL) ( off ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 877 | if (dis) |
| 878 | VG_(printf)("\n\t\tfnsave\t%d(%%ebp)\n", off ); |
| 879 | } |
| 880 | |
| 881 | static void emit_fpu_no_mem ( UChar first_byte, |
| 882 | UChar second_byte ) |
| 883 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 884 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 885 | VG_(emitB) ( first_byte ); |
| 886 | VG_(emitB) ( second_byte ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 887 | if (dis) |
| 888 | VG_(printf)("\n\t\tfpu-0x%x:0x%x\n", |
| 889 | (UInt)first_byte, (UInt)second_byte ); |
| 890 | } |
| 891 | |
| 892 | static void emit_fpu_regmem ( UChar first_byte, |
| 893 | UChar second_byte_masked, |
| 894 | Int reg ) |
| 895 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 896 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 897 | VG_(emitB) ( first_byte ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 898 | emit_amode_regmem_reg ( reg, second_byte_masked >> 3 ); |
| 899 | if (dis) |
| 900 | VG_(printf)("\n\t\tfpu-0x%x:0x%x-(%s)\n", |
| 901 | (UInt)first_byte, (UInt)second_byte_masked, |
| 902 | nameIReg(4,reg) ); |
| 903 | } |
| 904 | |
| 905 | |
| 906 | /*----------------------------------------------------*/ |
| 907 | /*--- misc instruction emitters ---*/ |
| 908 | /*----------------------------------------------------*/ |
| 909 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 910 | void VG_(emit_call_reg) ( Int reg ) |
| 911 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 912 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 913 | VG_(emitB) ( 0xFF ); /* Grp5 */ |
| 914 | VG_(emit_amode_ereg_greg) ( reg, mkGrp5opcode(CALLM) ); |
| 915 | if (dis) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 916 | VG_(printf)( "\n\t\tcall\t*%s\n", nameIReg(4,reg) ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 917 | } |
| 918 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 919 | static void emit_call_star_EBP_off ( Int byte_off ) |
| 920 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 921 | VG_(new_emit)(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 922 | if (byte_off < -128 || byte_off > 127) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 923 | VG_(emitB) ( 0xFF ); |
| 924 | VG_(emitB) ( 0x95 ); |
| 925 | VG_(emitL) ( byte_off ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 926 | } else { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 927 | VG_(emitB) ( 0xFF ); |
| 928 | VG_(emitB) ( 0x55 ); |
| 929 | VG_(emitB) ( byte_off ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 930 | } |
| 931 | if (dis) |
| 932 | VG_(printf)( "\n\t\tcall * %d(%%ebp)\n", byte_off ); |
| 933 | } |
| 934 | |
| 935 | |
| 936 | static void emit_addlit8_offregmem ( Int lit8, Int regmem, Int off ) |
| 937 | { |
| 938 | vg_assert(lit8 >= -128 && lit8 < 128); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 939 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 940 | VG_(emitB) ( 0x83 ); /* Grp1 Ib,Ev */ |
| 941 | VG_(emit_amode_offregmem_reg) ( off, regmem, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 942 | 0 /* Grp1 subopcode for ADD */ ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 943 | VG_(emitB) ( lit8 & 0xFF ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 944 | if (dis) |
| 945 | VG_(printf)( "\n\t\taddl $%d, %d(%s)\n", lit8, off, |
| 946 | nameIReg(4,regmem)); |
| 947 | } |
| 948 | |
| 949 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 950 | void VG_(emit_add_lit_to_esp) ( Int lit ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 951 | { |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 952 | if (lit < -128 || lit > 127) VG_(core_panic)("VG_(emit_add_lit_to_esp)"); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 953 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 954 | VG_(emitB) ( 0x83 ); |
| 955 | VG_(emitB) ( 0xC4 ); |
| 956 | VG_(emitB) ( lit & 0xFF ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 957 | if (dis) |
| 958 | VG_(printf)( "\n\t\taddl $%d, %%esp\n", lit ); |
| 959 | } |
| 960 | |
| 961 | |
| 962 | static void emit_movb_AL_zeroESPmem ( void ) |
| 963 | { |
| 964 | /* movb %al, 0(%esp) */ |
| 965 | /* 88442400 movb %al, 0(%esp) */ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 966 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 967 | VG_(emitB) ( 0x88 ); |
| 968 | VG_(emitB) ( 0x44 ); |
| 969 | VG_(emitB) ( 0x24 ); |
| 970 | VG_(emitB) ( 0x00 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 971 | if (dis) |
| 972 | VG_(printf)( "\n\t\tmovb %%al, 0(%%esp)\n" ); |
| 973 | } |
| 974 | |
| 975 | static void emit_movb_zeroESPmem_AL ( void ) |
| 976 | { |
| 977 | /* movb 0(%esp), %al */ |
| 978 | /* 8A442400 movb 0(%esp), %al */ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 979 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 980 | VG_(emitB) ( 0x8A ); |
| 981 | VG_(emitB) ( 0x44 ); |
| 982 | VG_(emitB) ( 0x24 ); |
| 983 | VG_(emitB) ( 0x00 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 984 | if (dis) |
| 985 | VG_(printf)( "\n\t\tmovb 0(%%esp), %%al\n" ); |
| 986 | } |
| 987 | |
| 988 | |
| 989 | /* Emit a jump short with an 8-bit signed offset. Note that the |
| 990 | offset is that which should be added to %eip once %eip has been |
| 991 | advanced over this insn. */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 992 | void VG_(emit_jcondshort_delta) ( Condcode cond, Int delta ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 993 | { |
| 994 | vg_assert(delta >= -128 && delta <= 127); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 995 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 996 | VG_(emitB) ( 0x70 + (UInt)cond ); |
| 997 | VG_(emitB) ( (UChar)delta ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 998 | if (dis) |
| 999 | VG_(printf)( "\n\t\tj%s-8\t%%eip+%d\n", |
| 1000 | VG_(nameCondcode)(cond), delta ); |
| 1001 | } |
| 1002 | |
| 1003 | static void emit_get_eflags ( void ) |
| 1004 | { |
| 1005 | Int off = 4 * VGOFF_(m_eflags); |
| 1006 | vg_assert(off >= 0 && off < 128); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1007 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1008 | VG_(emitB) ( 0xFF ); /* PUSHL off(%ebp) */ |
| 1009 | VG_(emitB) ( 0x75 ); |
| 1010 | VG_(emitB) ( off ); |
| 1011 | VG_(emitB) ( 0x9D ); /* POPFL */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1012 | if (dis) |
| 1013 | VG_(printf)( "\n\t\tpushl %d(%%ebp) ; popfl\n", off ); |
| 1014 | } |
| 1015 | |
| 1016 | static void emit_put_eflags ( void ) |
| 1017 | { |
| 1018 | Int off = 4 * VGOFF_(m_eflags); |
| 1019 | vg_assert(off >= 0 && off < 128); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1020 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1021 | VG_(emitB) ( 0x9C ); /* PUSHFL */ |
| 1022 | VG_(emitB) ( 0x8F ); /* POPL vg_m_state.m_eflags */ |
| 1023 | VG_(emitB) ( 0x45 ); |
| 1024 | VG_(emitB) ( off ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1025 | if (dis) |
| 1026 | VG_(printf)( "\n\t\tpushfl ; popl %d(%%ebp)\n", off ); |
| 1027 | } |
| 1028 | |
| 1029 | static void emit_setb_reg ( Int reg, Condcode cond ) |
| 1030 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1031 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1032 | VG_(emitB) ( 0x0F ); VG_(emitB) ( 0x90 + (UChar)cond ); |
| 1033 | VG_(emit_amode_ereg_greg) ( reg, 0 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1034 | if (dis) |
| 1035 | VG_(printf)("\n\t\tset%s %s\n", |
| 1036 | VG_(nameCondcode)(cond), nameIReg(1,reg)); |
| 1037 | } |
| 1038 | |
| 1039 | static void emit_ret ( void ) |
| 1040 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1041 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1042 | VG_(emitB) ( 0xC3 ); /* RET */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1043 | if (dis) |
| 1044 | VG_(printf)("\n\t\tret\n"); |
| 1045 | } |
| 1046 | |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 1047 | /* Predicate used in sanity checks elsewhere - returns true if any |
| 1048 | jump-site is an actual chained jump */ |
| 1049 | Bool VG_(is_chained_jumpsite)(Addr a) |
| 1050 | { |
| 1051 | UChar *cp = (UChar *)a; |
| 1052 | |
| 1053 | return (*cp == 0xE9); /* 0xE9 -- jmp */ |
| 1054 | } |
| 1055 | |
sewardj | 83f1186 | 2002-12-01 02:07:08 +0000 | [diff] [blame^] | 1056 | static |
| 1057 | Bool is_fresh_jumpsite(UChar *cp) |
| 1058 | { |
| 1059 | return |
| 1060 | cp[0] == 0x0F && /* UD2 */ |
| 1061 | cp[1] == 0x0B && |
| 1062 | cp[2] == 0x0F && /* UD2 */ |
| 1063 | cp[3] == 0x0B && |
| 1064 | cp[4] == 0x90; /* NOP */ |
| 1065 | } |
| 1066 | |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 1067 | /* Predicate used in sanity checks elsewhere - returns true if all |
| 1068 | jump-sites are calls to VG_(patch_me) */ |
| 1069 | Bool VG_(is_unchained_jumpsite)(Addr a) |
| 1070 | { |
| 1071 | UChar *cp = (UChar *)a; |
| 1072 | Int delta = ((Addr)&VG_(patch_me)) - (a + VG_PATCHME_CALLSZ); |
| 1073 | Int idelta; |
| 1074 | |
| 1075 | if (*cp++ != 0xE8) /* 0xE8 == call */ |
| 1076 | return False; |
| 1077 | |
| 1078 | idelta = (*cp++) << 0; |
| 1079 | idelta |= (*cp++) << 8; |
| 1080 | idelta |= (*cp++) << 16; |
| 1081 | idelta |= (*cp++) << 24; |
| 1082 | |
| 1083 | return idelta == delta; |
| 1084 | } |
| 1085 | |
| 1086 | /* Return target address for a direct jmp */ |
| 1087 | Addr VG_(get_jmp_dest)(Addr a) |
| 1088 | { |
| 1089 | Int delta; |
| 1090 | UChar *cp = (UChar *)a; |
| 1091 | |
| 1092 | if (*cp++ != 0xE9) /* 0xE9 == jmp */ |
| 1093 | return 0; |
| 1094 | |
| 1095 | delta = (*cp++) << 0; |
| 1096 | delta |= (*cp++) << 8; |
| 1097 | delta |= (*cp++) << 16; |
| 1098 | delta |= (*cp++) << 24; |
| 1099 | |
| 1100 | return a + VG_PATCHME_JMPSZ + delta; |
| 1101 | } |
| 1102 | |
| 1103 | /* unchain a BB by generating a call to VG_(patch_me) */ |
| 1104 | void VG_(unchain_jumpsite)(Addr a) |
| 1105 | { |
| 1106 | Int delta = ((Addr)&VG_(patch_me)) - (a + VG_PATCHME_CALLSZ); |
| 1107 | UChar *cp = (UChar *)a; |
| 1108 | |
| 1109 | if (VG_(is_unchained_jumpsite)(a)) |
| 1110 | return; /* don't write unnecessarily */ |
| 1111 | |
sewardj | 83f1186 | 2002-12-01 02:07:08 +0000 | [diff] [blame^] | 1112 | if (!is_fresh_jumpsite(cp)) |
| 1113 | VG_(bb_dechain_count)++; /* update stats */ |
| 1114 | |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 1115 | *cp++ = 0xE8; /* call */ |
| 1116 | *cp++ = (delta >> 0) & 0xff; |
| 1117 | *cp++ = (delta >> 8) & 0xff; |
| 1118 | *cp++ = (delta >> 16) & 0xff; |
| 1119 | *cp++ = (delta >> 24) & 0xff; |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 1120 | } |
| 1121 | |
| 1122 | /* This doesn't actually generate a call to VG_(patch_me), but |
| 1123 | reserves enough space in the instruction stream for it to happen |
| 1124 | and records the offset into the jump table. This is because call |
| 1125 | is a relative jump, and so will be affected when this code gets |
| 1126 | moved about. The translation table will "unchain" this basic block |
| 1127 | on insertion (with VG_(unchain_BB)()), and thereby generate a |
| 1128 | proper call instruction. */ |
| 1129 | static void emit_call_patchme( void ) |
| 1130 | { |
| 1131 | vg_assert(VG_PATCHME_CALLSZ == 5); |
| 1132 | |
| 1133 | VG_(new_emit)(); |
| 1134 | |
| 1135 | if (jumpidx >= VG_MAX_JUMPS) { |
| 1136 | /* If there too many jumps in this basic block, fall back to |
| 1137 | dispatch loop. We still need to keep it the same size as the |
| 1138 | call sequence. */ |
| 1139 | VG_(emitB) ( 0xC3 ); /* ret */ |
| 1140 | VG_(emitB) ( 0x90 ); /* nop */ |
| 1141 | VG_(emitB) ( 0x90 ); /* nop */ |
| 1142 | VG_(emitB) ( 0x90 ); /* nop */ |
| 1143 | VG_(emitB) ( 0x90 ); /* nop */ |
| 1144 | |
| 1145 | if (dis) |
| 1146 | VG_(printf)("\n\t\tret; nop; nop; nop; nop\n"); |
| 1147 | |
| 1148 | if (0 && VG_(clo_verbosity)) |
| 1149 | VG_(message)(Vg_DebugMsg, "too many chained jumps in basic-block"); |
| 1150 | } else { |
| 1151 | jumps[jumpidx++] = emitted_code_used; |
| 1152 | |
| 1153 | VG_(emitB) ( 0x0F ); /* UD2 - undefined instruction */ |
| 1154 | VG_(emitB) ( 0x0B ); |
| 1155 | VG_(emitB) ( 0x0F ); /* UD2 - undefined instruction */ |
| 1156 | VG_(emitB) ( 0x0B ); |
| 1157 | VG_(emitB) ( 0x90 ); /* NOP */ |
| 1158 | |
| 1159 | if (dis) |
| 1160 | VG_(printf)("\n\t\tud2; ud2; nop\n"); |
| 1161 | } |
| 1162 | } |
| 1163 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1164 | void VG_(emit_pushal) ( void ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1165 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1166 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1167 | VG_(emitB) ( 0x60 ); /* PUSHAL */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1168 | if (dis) |
| 1169 | VG_(printf)("\n\t\tpushal\n"); |
| 1170 | } |
| 1171 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1172 | void VG_(emit_popal) ( void ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1173 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1174 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1175 | VG_(emitB) ( 0x61 ); /* POPAL */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1176 | if (dis) |
| 1177 | VG_(printf)("\n\t\tpopal\n"); |
| 1178 | } |
| 1179 | |
| 1180 | static void emit_lea_litreg_reg ( UInt lit, Int regmem, Int reg ) |
| 1181 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1182 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1183 | VG_(emitB) ( 0x8D ); /* LEA M,Gv */ |
| 1184 | VG_(emit_amode_offregmem_reg) ( (Int)lit, regmem, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1185 | if (dis) |
| 1186 | VG_(printf)("\n\t\tleal 0x%x(%s), %s\n", |
| 1187 | lit, nameIReg(4,regmem), nameIReg(4,reg) ); |
| 1188 | } |
| 1189 | |
| 1190 | static void emit_lea_sib_reg ( UInt lit, Int scale, |
| 1191 | Int regbase, Int regindex, Int reg ) |
| 1192 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1193 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1194 | VG_(emitB) ( 0x8D ); /* LEA M,Gv */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1195 | emit_amode_sib_reg ( (Int)lit, scale, regbase, regindex, reg ); |
| 1196 | if (dis) |
| 1197 | VG_(printf)("\n\t\tleal 0x%x(%s,%s,%d), %s\n", |
| 1198 | lit, nameIReg(4,regbase), |
| 1199 | nameIReg(4,regindex), scale, |
| 1200 | nameIReg(4,reg) ); |
| 1201 | } |
| 1202 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1203 | void VG_(emit_AMD_prefetch_reg) ( Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1204 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1205 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1206 | VG_(emitB) ( 0x0F ); |
| 1207 | VG_(emitB) ( 0x0D ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1208 | emit_amode_regmem_reg ( reg, 1 /* 0 is prefetch; 1 is prefetchw */ ); |
| 1209 | if (dis) |
| 1210 | VG_(printf)("\n\t\tamd-prefetch (%s)\n", nameIReg(4,reg) ); |
| 1211 | } |
| 1212 | |
| 1213 | /*----------------------------------------------------*/ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1214 | /*--- Helper offset -> addr translation ---*/ |
| 1215 | /*----------------------------------------------------*/ |
| 1216 | |
| 1217 | /* Finds the baseBlock offset of a skin-specified helper. |
| 1218 | * Searches through compacts first, then non-compacts. */ |
| 1219 | Int VG_(helper_offset)(Addr a) |
| 1220 | { |
| 1221 | Int i; |
| 1222 | |
| 1223 | for (i = 0; i < VG_(n_compact_helpers); i++) |
| 1224 | if (VG_(compact_helper_addrs)[i] == a) |
| 1225 | return VG_(compact_helper_offsets)[i]; |
| 1226 | for (i = 0; i < VG_(n_noncompact_helpers); i++) |
| 1227 | if (VG_(noncompact_helper_addrs)[i] == a) |
| 1228 | return VG_(noncompact_helper_offsets)[i]; |
| 1229 | |
| 1230 | /* Shouldn't get here */ |
| 1231 | VG_(printf)( |
| 1232 | "\nCouldn't find offset of helper from its address (%p).\n" |
| 1233 | "A helper function probably used hasn't been registered?\n\n", a); |
| 1234 | |
| 1235 | VG_(printf)(" compact helpers: "); |
| 1236 | for (i = 0; i < VG_(n_compact_helpers); i++) |
| 1237 | VG_(printf)("%p ", VG_(compact_helper_addrs)[i]); |
| 1238 | |
| 1239 | VG_(printf)("\n non-compact helpers: "); |
| 1240 | for (i = 0; i < VG_(n_noncompact_helpers); i++) |
| 1241 | VG_(printf)("%p ", VG_(noncompact_helper_addrs)[i]); |
| 1242 | |
| 1243 | VG_(printf)("\n"); |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1244 | VG_(skin_panic)("Unfound helper"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1245 | } |
| 1246 | |
| 1247 | /*----------------------------------------------------*/ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1248 | /*--- Instruction synthesisers ---*/ |
| 1249 | /*----------------------------------------------------*/ |
| 1250 | |
| 1251 | static Condcode invertCondition ( Condcode cond ) |
| 1252 | { |
| 1253 | return (Condcode)(1 ^ (UInt)cond); |
| 1254 | } |
| 1255 | |
| 1256 | |
| 1257 | /* Synthesise a call to *baseBlock[offset], ie, |
| 1258 | call * (4 x offset)(%ebp). |
| 1259 | */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1260 | void VG_(synth_call) ( Bool ensure_shortform, Int word_offset ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1261 | { |
| 1262 | vg_assert(word_offset >= 0); |
| 1263 | vg_assert(word_offset < VG_BASEBLOCK_WORDS); |
| 1264 | if (ensure_shortform) |
| 1265 | vg_assert(word_offset < 32); |
| 1266 | emit_call_star_EBP_off ( 4 * word_offset ); |
| 1267 | } |
| 1268 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1269 | static void maybe_emit_movl_reg_reg ( UInt src, UInt dst ) |
njn | 6431be7 | 2002-07-28 09:53:34 +0000 | [diff] [blame] | 1270 | { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1271 | if (src != dst) { |
| 1272 | VG_(emit_movv_reg_reg) ( 4, src, dst ); |
| 1273 | ccall_arg_setup_instrs++; |
| 1274 | } |
njn | 6431be7 | 2002-07-28 09:53:34 +0000 | [diff] [blame] | 1275 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1276 | |
| 1277 | /* 'maybe' because it is sometimes skipped eg. for "movl %eax,%eax" */ |
| 1278 | static void maybe_emit_movl_litOrReg_reg ( UInt litOrReg, Tag tag, UInt reg ) |
| 1279 | { |
| 1280 | if (RealReg == tag) { |
| 1281 | maybe_emit_movl_reg_reg ( litOrReg, reg ); |
| 1282 | } else if (Literal == tag) { |
| 1283 | VG_(emit_movv_lit_reg) ( 4, litOrReg, reg ); |
| 1284 | ccall_arg_setup_instrs++; |
| 1285 | } |
| 1286 | else |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1287 | VG_(core_panic)("emit_movl_litOrReg_reg: unexpected tag"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1288 | } |
| 1289 | |
| 1290 | static |
| 1291 | void emit_swapl_arg_regs ( UInt reg1, UInt reg2 ) |
| 1292 | { |
| 1293 | if (R_EAX == reg1) { |
| 1294 | VG_(emit_swapl_reg_EAX) ( reg2 ); |
| 1295 | } else if (R_EAX == reg2) { |
| 1296 | VG_(emit_swapl_reg_EAX) ( reg1 ); |
| 1297 | } else { |
| 1298 | emit_swapl_reg_reg ( reg1, reg2 ); |
| 1299 | } |
| 1300 | ccall_arg_setup_instrs++; |
| 1301 | } |
| 1302 | |
| 1303 | static |
| 1304 | void emit_two_regs_args_setup ( UInt src1, UInt src2, UInt dst1, UInt dst2) |
| 1305 | { |
| 1306 | if (dst1 != src2) { |
| 1307 | maybe_emit_movl_reg_reg ( src1, dst1 ); |
| 1308 | maybe_emit_movl_reg_reg ( src2, dst2 ); |
| 1309 | |
| 1310 | } else if (dst2 != src1) { |
| 1311 | maybe_emit_movl_reg_reg ( src2, dst2 ); |
| 1312 | maybe_emit_movl_reg_reg ( src1, dst1 ); |
| 1313 | |
| 1314 | } else { |
| 1315 | /* swap to break cycle */ |
| 1316 | emit_swapl_arg_regs ( dst1, dst2 ); |
| 1317 | } |
| 1318 | } |
| 1319 | |
| 1320 | static |
| 1321 | void emit_three_regs_args_setup ( UInt src1, UInt src2, UInt src3, |
| 1322 | UInt dst1, UInt dst2, UInt dst3) |
| 1323 | { |
| 1324 | if (dst1 != src2 && dst1 != src3) { |
| 1325 | maybe_emit_movl_reg_reg ( src1, dst1 ); |
| 1326 | emit_two_regs_args_setup ( src2, src3, dst2, dst3 ); |
| 1327 | |
| 1328 | } else if (dst2 != src1 && dst2 != src3) { |
| 1329 | maybe_emit_movl_reg_reg ( src2, dst2 ); |
| 1330 | emit_two_regs_args_setup ( src1, src3, dst1, dst3 ); |
| 1331 | |
| 1332 | } else if (dst3 != src1 && dst3 != src2) { |
| 1333 | maybe_emit_movl_reg_reg ( src3, dst3 ); |
| 1334 | emit_two_regs_args_setup ( src1, src2, dst1, dst2 ); |
| 1335 | |
| 1336 | } else { |
| 1337 | /* break cycle */ |
| 1338 | if (dst1 == src2 && dst2 == src3 && dst3 == src1) { |
| 1339 | emit_swapl_arg_regs ( dst1, dst2 ); |
| 1340 | emit_swapl_arg_regs ( dst1, dst3 ); |
| 1341 | |
| 1342 | } else if (dst1 == src3 && dst2 == src1 && dst3 == src2) { |
| 1343 | emit_swapl_arg_regs ( dst1, dst3 ); |
| 1344 | emit_swapl_arg_regs ( dst1, dst2 ); |
| 1345 | |
| 1346 | } else { |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1347 | VG_(core_panic)("impossible 3-cycle"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1348 | } |
| 1349 | } |
| 1350 | } |
| 1351 | |
| 1352 | static |
| 1353 | void emit_two_regs_or_lits_args_setup ( UInt argv[], Tag tagv[], |
| 1354 | UInt src1, UInt src2, |
| 1355 | UInt dst1, UInt dst2) |
| 1356 | { |
| 1357 | /* If either are lits, order doesn't matter */ |
| 1358 | if (Literal == tagv[src1] || Literal == tagv[src2]) { |
| 1359 | maybe_emit_movl_litOrReg_reg ( argv[src1], tagv[src1], dst1 ); |
| 1360 | maybe_emit_movl_litOrReg_reg ( argv[src2], tagv[src2], dst2 ); |
| 1361 | |
| 1362 | } else { |
| 1363 | emit_two_regs_args_setup ( argv[src1], argv[src2], dst1, dst2 ); |
| 1364 | } |
| 1365 | } |
| 1366 | |
| 1367 | static |
| 1368 | void emit_three_regs_or_lits_args_setup ( UInt argv[], Tag tagv[], |
| 1369 | UInt src1, UInt src2, UInt src3, |
| 1370 | UInt dst1, UInt dst2, UInt dst3) |
| 1371 | { |
| 1372 | // SSS: fix this eventually -- make STOREV use two RealRegs? |
| 1373 | /* Not supporting literals for 3-arg C functions -- they're only used |
| 1374 | by STOREV which has 2 args */ |
| 1375 | vg_assert(RealReg == tagv[src1] && |
| 1376 | RealReg == tagv[src2] && |
| 1377 | RealReg == tagv[src3]); |
| 1378 | emit_three_regs_args_setup ( argv[src1], argv[src2], argv[src3], |
| 1379 | dst1, dst2, dst3 ); |
| 1380 | } |
| 1381 | |
| 1382 | /* Synthesise a call to a C function `fn' (which must be registered in |
| 1383 | baseBlock) doing all the reg saving and arg handling work. |
| 1384 | |
| 1385 | WARNING: a UInstr should *not* be translated with synth_ccall followed |
| 1386 | by some other x86 assembly code; vg_liveness_analysis() doesn't expect |
| 1387 | such behaviour and everything will fall over. |
| 1388 | */ |
| 1389 | void VG_(synth_ccall) ( Addr fn, Int argc, Int regparms_n, UInt argv[], |
| 1390 | Tag tagv[], Int ret_reg, |
| 1391 | RRegSet regs_live_before, RRegSet regs_live_after ) |
| 1392 | { |
| 1393 | Int i; |
| 1394 | Int stack_used = 0; |
| 1395 | Bool preserve_eax, preserve_ecx, preserve_edx; |
| 1396 | |
| 1397 | vg_assert(0 <= regparms_n && regparms_n <= 3); |
| 1398 | |
| 1399 | ccalls++; |
| 1400 | |
| 1401 | /* If %e[acd]x is live before and after the C call, save/restore it. |
| 1402 | Unless the return values clobbers the reg; in this case we must not |
| 1403 | save/restore the reg, because the restore would clobber the return |
| 1404 | value. (Before and after the UInstr really constitute separate live |
| 1405 | ranges, but you miss this if you don't consider what happens during |
| 1406 | the UInstr.) */ |
| 1407 | # define PRESERVE_REG(realReg) \ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1408 | (IS_RREG_LIVE(VG_(realreg_to_rank)(realReg), regs_live_before) && \ |
| 1409 | IS_RREG_LIVE(VG_(realreg_to_rank)(realReg), regs_live_after) && \ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1410 | ret_reg != realReg) |
| 1411 | |
| 1412 | preserve_eax = PRESERVE_REG(R_EAX); |
| 1413 | preserve_ecx = PRESERVE_REG(R_ECX); |
| 1414 | preserve_edx = PRESERVE_REG(R_EDX); |
| 1415 | |
| 1416 | # undef PRESERVE_REG |
| 1417 | |
| 1418 | /* Save caller-save regs as required */ |
| 1419 | if (preserve_eax) { VG_(emit_pushv_reg) ( 4, R_EAX ); ccall_reg_saves++; } |
| 1420 | if (preserve_ecx) { VG_(emit_pushv_reg) ( 4, R_ECX ); ccall_reg_saves++; } |
| 1421 | if (preserve_edx) { VG_(emit_pushv_reg) ( 4, R_EDX ); ccall_reg_saves++; } |
| 1422 | |
| 1423 | /* Args are passed in two groups: (a) via stack (b) via regs. regparms_n |
| 1424 | is the number of args passed in regs (maximum 3 for GCC on x86). */ |
| 1425 | |
| 1426 | ccall_args += argc; |
njn | 6431be7 | 2002-07-28 09:53:34 +0000 | [diff] [blame] | 1427 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1428 | /* First push stack args (RealRegs or Literals) in reverse order. */ |
| 1429 | for (i = argc-1; i >= regparms_n; i--) { |
| 1430 | switch (tagv[i]) { |
| 1431 | case RealReg: |
| 1432 | VG_(emit_pushv_reg) ( 4, argv[i] ); |
| 1433 | break; |
| 1434 | case Literal: |
| 1435 | /* Use short form of pushl if possible. */ |
| 1436 | if (argv[i] == VG_(extend_s_8to32) ( argv[i] )) |
| 1437 | VG_(emit_pushl_lit8) ( VG_(extend_s_8to32)(argv[i]) ); |
| 1438 | else |
| 1439 | VG_(emit_pushl_lit32)( argv[i] ); |
| 1440 | break; |
| 1441 | default: |
| 1442 | VG_(printf)("tag=%d\n", tagv[i]); |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1443 | VG_(core_panic)("VG_(synth_ccall): bad tag"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1444 | } |
| 1445 | stack_used += 4; |
| 1446 | ccall_arg_setup_instrs++; |
| 1447 | } |
njn | 6431be7 | 2002-07-28 09:53:34 +0000 | [diff] [blame] | 1448 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1449 | /* Then setup args in registers (arg[123] --> %e[adc]x; note order!). |
| 1450 | If moving values between registers, be careful not to clobber any on |
| 1451 | the way. Happily we can use xchgl to swap registers. |
| 1452 | */ |
| 1453 | switch (regparms_n) { |
njn | 6431be7 | 2002-07-28 09:53:34 +0000 | [diff] [blame] | 1454 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1455 | /* Trickiest. Args passed in %eax, %edx, and %ecx. */ |
| 1456 | case 3: |
| 1457 | emit_three_regs_or_lits_args_setup ( argv, tagv, 0, 1, 2, |
| 1458 | R_EAX, R_EDX, R_ECX ); |
| 1459 | break; |
njn | 6431be7 | 2002-07-28 09:53:34 +0000 | [diff] [blame] | 1460 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1461 | /* Less-tricky. Args passed in %eax and %edx. */ |
| 1462 | case 2: |
| 1463 | emit_two_regs_or_lits_args_setup ( argv, tagv, 0, 1, R_EAX, R_EDX ); |
| 1464 | break; |
| 1465 | |
| 1466 | /* Easy. Just move arg1 into %eax (if not already in there). */ |
| 1467 | case 1: |
| 1468 | maybe_emit_movl_litOrReg_reg ( argv[0], tagv[0], R_EAX ); |
| 1469 | break; |
| 1470 | |
| 1471 | case 0: |
| 1472 | break; |
| 1473 | |
| 1474 | default: |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1475 | VG_(core_panic)("VG_(synth_call): regparms_n value not in range 0..3"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1476 | } |
| 1477 | |
| 1478 | /* Call the function */ |
| 1479 | VG_(synth_call) ( False, VG_(helper_offset) ( fn ) ); |
| 1480 | |
| 1481 | /* Clear any args from stack */ |
| 1482 | if (0 != stack_used) { |
| 1483 | VG_(emit_add_lit_to_esp) ( stack_used ); |
| 1484 | ccall_stack_clears++; |
| 1485 | } |
| 1486 | |
| 1487 | /* Move return value into ret_reg if necessary and not already there */ |
| 1488 | if (INVALID_REALREG != ret_reg) { |
| 1489 | ccall_retvals++; |
| 1490 | if (R_EAX != ret_reg) { |
| 1491 | VG_(emit_movv_reg_reg) ( 4, R_EAX, ret_reg ); |
| 1492 | ccall_retval_movs++; |
| 1493 | } |
| 1494 | } |
| 1495 | |
| 1496 | /* Restore live caller-save regs as required */ |
| 1497 | if (preserve_edx) VG_(emit_popv_reg) ( 4, R_EDX ); |
| 1498 | if (preserve_ecx) VG_(emit_popv_reg) ( 4, R_ECX ); |
| 1499 | if (preserve_eax) VG_(emit_popv_reg) ( 4, R_EAX ); |
njn | 6431be7 | 2002-07-28 09:53:34 +0000 | [diff] [blame] | 1500 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1501 | |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 1502 | static void load_ebp_from_JmpKind ( JmpKind jmpkind ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1503 | { |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 1504 | switch (jmpkind) { |
| 1505 | case JmpBoring: |
| 1506 | break; |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 1507 | case JmpRet: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1508 | break; |
| 1509 | case JmpCall: |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 1510 | break; |
| 1511 | case JmpSyscall: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1512 | VG_(emit_movv_lit_reg) ( 4, VG_TRC_EBP_JMP_SYSCALL, R_EBP ); |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 1513 | break; |
| 1514 | case JmpClientReq: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1515 | VG_(emit_movv_lit_reg) ( 4, VG_TRC_EBP_JMP_CLIENTREQ, R_EBP ); |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 1516 | break; |
| 1517 | default: |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1518 | VG_(core_panic)("load_ebp_from_JmpKind"); |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 1519 | } |
| 1520 | } |
| 1521 | |
| 1522 | /* Jump to the next translation, by loading its original addr into |
| 1523 | %eax and returning to the scheduler. Signal special requirements |
| 1524 | by loading a special value into %ebp first. |
| 1525 | */ |
| 1526 | static void synth_jmp_reg ( Int reg, JmpKind jmpkind ) |
| 1527 | { |
| 1528 | load_ebp_from_JmpKind ( jmpkind ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1529 | if (reg != R_EAX) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1530 | VG_(emit_movv_reg_reg) ( 4, reg, R_EAX ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1531 | emit_ret(); |
| 1532 | } |
| 1533 | |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 1534 | static void synth_mov_reg_offregmem ( Int size, Int reg, Int off, Int areg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1535 | |
| 1536 | /* Same deal as synth_jmp_reg. */ |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 1537 | static void synth_jmp_lit ( Addr addr, JmpKind jmpkind ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1538 | { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1539 | VG_(emit_movv_lit_reg) ( 4, addr, R_EAX ); |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 1540 | |
| 1541 | if (VG_(clo_chain_bb) && (jmpkind == JmpBoring || jmpkind == JmpCall)) { |
| 1542 | synth_mov_reg_offregmem(4, R_EAX, 4*VGOFF_(m_eip), R_EBP); /* update EIP */ |
| 1543 | emit_call_patchme(); |
| 1544 | } else { |
| 1545 | load_ebp_from_JmpKind ( jmpkind ); |
| 1546 | emit_ret(); |
| 1547 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1548 | } |
| 1549 | |
| 1550 | |
sewardj | 2370f3b | 2002-11-30 15:01:01 +0000 | [diff] [blame] | 1551 | static void synth_mov_offregmem_reg ( Int size, Int off, Int areg, Int reg ); |
| 1552 | static void synth_nonshiftop_lit_reg ( Bool upd_cc, |
| 1553 | Opcode opcode, Int size, |
| 1554 | UInt lit, Int reg ); |
| 1555 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1556 | static void synth_jcond_lit ( Condcode cond, Addr addr ) |
| 1557 | { |
sewardj | 2370f3b | 2002-11-30 15:01:01 +0000 | [diff] [blame] | 1558 | UInt mask; |
| 1559 | Int delta; |
| 1560 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1561 | /* Do the following: |
| 1562 | get eflags |
| 1563 | jmp short if not cond to xyxyxy |
| 1564 | addr -> eax |
| 1565 | ret |
| 1566 | xyxyxy |
| 1567 | |
| 1568 | 2 0000 750C jnz xyxyxy |
| 1569 | 3 0002 B877665544 movl $0x44556677, %eax |
| 1570 | 4 0007 C3 ret |
| 1571 | 5 0008 FFE3 jmp *%ebx |
| 1572 | 6 xyxyxy: |
| 1573 | */ |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 1574 | if (VG_(clo_chain_bb)) { |
| 1575 | /* When using BB chaining, the jump sequence is: |
| 1576 | jmp short if not cond to xyxyxy |
| 1577 | addr -> eax |
| 1578 | call VG_(patch_me)/jmp target |
| 1579 | xyxyxy |
| 1580 | |
| 1581 | je 1f |
| 1582 | mov $0x4000d190,%eax // 5 |
| 1583 | mov %eax, VGOFF_(m_eip)(%ebp) // 3 |
| 1584 | call 0x40050f9a <vgPlain_patch_me> // 5 |
| 1585 | 1: mov $0x4000d042,%eax |
| 1586 | call 0x40050f9a <vgPlain_patch_me> |
| 1587 | */ |
sewardj | 83f1186 | 2002-12-01 02:07:08 +0000 | [diff] [blame^] | 1588 | delta = 5+3+5; |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 1589 | } else |
sewardj | 2370f3b | 2002-11-30 15:01:01 +0000 | [diff] [blame] | 1590 | delta = 5+1; |
| 1591 | |
| 1592 | if (!VG_(clo_fast_jcc)) { |
| 1593 | /* We're forced to do it the slow way. */ |
| 1594 | emit_get_eflags(); |
| 1595 | cond = invertCondition(cond); |
| 1596 | } else { |
| 1597 | switch (cond & ~1) { |
| 1598 | case CondB: mask = EFlagC; goto common; /* C=1 */ |
| 1599 | case CondZ: mask = EFlagZ; goto common; /* Z=1 */ |
| 1600 | case CondBE: mask = EFlagC | EFlagZ; goto common; /* C=1 || Z=1 */ |
| 1601 | case CondS: mask = EFlagS; goto common; /* S=1 */ |
| 1602 | case CondP: mask = EFlagP; goto common; /* P=1 */ |
| 1603 | default: |
| 1604 | /* Too complex .. we have to do it the slow way. */ |
| 1605 | emit_get_eflags(); |
| 1606 | cond = invertCondition(cond); |
| 1607 | break; |
| 1608 | |
| 1609 | common: |
| 1610 | VG_(new_emit)(); |
| 1611 | if ((mask & 0xff) == mask) { |
| 1612 | VG_(emitB) ( 0xF6 ); /* Grp3 */ |
| 1613 | VG_(emit_amode_offregmem_reg)( |
| 1614 | VGOFF_(m_eflags) * 4, R_EBP, 0 /* subcode for TEST */); |
| 1615 | VG_(emitB) (mask); |
| 1616 | if (dis) |
| 1617 | VG_(printf)("\n\t\ttestb $%x, %d(%%ebp)\n", |
| 1618 | mask, VGOFF_(m_eflags) * 4); |
| 1619 | } else { |
| 1620 | VG_(emitB) ( 0xF7 ); |
| 1621 | VG_(emit_amode_offregmem_reg)( |
| 1622 | VGOFF_(m_eflags) * 4, R_EBP, 0 /* subcode for TEST */); |
| 1623 | VG_(emitB) (mask); |
| 1624 | if (dis) |
| 1625 | VG_(printf)("\n\t\ttestx $%x, %d(%%ebp)\n", |
| 1626 | mask, VGOFF_(m_eflags) * 4); |
| 1627 | } |
| 1628 | |
| 1629 | if (cond & 1) |
| 1630 | cond = CondNZ; |
| 1631 | else |
| 1632 | cond = CondZ; |
| 1633 | break; |
| 1634 | } |
| 1635 | } |
| 1636 | |
| 1637 | VG_(emit_jcondshort_delta) ( cond, delta ); |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 1638 | synth_jmp_lit ( addr, JmpBoring ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1639 | } |
| 1640 | |
| 1641 | |
sewardj | 2370f3b | 2002-11-30 15:01:01 +0000 | [diff] [blame] | 1642 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1643 | static void synth_jmp_ifzero_reg_lit ( Int reg, Addr addr ) |
| 1644 | { |
| 1645 | /* 0000 83FF00 cmpl $0, %edi |
| 1646 | 0003 750A jnz next |
| 1647 | 0005 B844332211 movl $0x11223344, %eax |
| 1648 | 000a C3 ret |
| 1649 | next: |
| 1650 | */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1651 | VG_(emit_cmpl_zero_reg) ( reg ); |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 1652 | if (VG_(clo_chain_bb)) |
| 1653 | VG_(emit_jcondshort_delta) ( CondNZ, 5+3+5 ); |
| 1654 | else |
| 1655 | VG_(emit_jcondshort_delta) ( CondNZ, 5+1 ); |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 1656 | synth_jmp_lit ( addr, JmpBoring ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1657 | } |
| 1658 | |
| 1659 | |
| 1660 | static void synth_mov_lit_reg ( Int size, UInt lit, Int reg ) |
| 1661 | { |
| 1662 | /* Load the zero-extended literal into reg, at size l, |
| 1663 | regardless of the request size. */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1664 | VG_(emit_movv_lit_reg) ( 4, lit, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1665 | } |
| 1666 | |
| 1667 | |
| 1668 | static void synth_mov_regmem_reg ( Int size, Int reg1, Int reg2 ) |
| 1669 | { |
| 1670 | switch (size) { |
| 1671 | case 4: emit_movv_regmem_reg ( 4, reg1, reg2 ); break; |
| 1672 | case 2: emit_movzwl_regmem_reg ( reg1, reg2 ); break; |
| 1673 | case 1: emit_movzbl_regmem_reg ( reg1, reg2 ); break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1674 | default: VG_(core_panic)("synth_mov_regmem_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1675 | } |
| 1676 | } |
| 1677 | |
| 1678 | |
| 1679 | static void synth_mov_offregmem_reg ( Int size, Int off, Int areg, Int reg ) |
| 1680 | { |
| 1681 | switch (size) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1682 | case 4: VG_(emit_movv_offregmem_reg) ( 4, off, areg, reg ); break; |
| 1683 | case 2: VG_(emit_movzwl_offregmem_reg) ( off, areg, reg ); break; |
| 1684 | case 1: VG_(emit_movzbl_offregmem_reg) ( off, areg, reg ); break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1685 | default: VG_(core_panic)("synth_mov_offregmem_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1686 | } |
| 1687 | } |
| 1688 | |
| 1689 | |
| 1690 | static void synth_mov_reg_offregmem ( Int size, Int reg, |
| 1691 | Int off, Int areg ) |
| 1692 | { |
| 1693 | switch (size) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1694 | case 4: VG_(emit_movv_reg_offregmem) ( 4, reg, off, areg ); break; |
| 1695 | case 2: VG_(emit_movv_reg_offregmem) ( 2, reg, off, areg ); break; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1696 | case 1: if (reg < 4) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1697 | VG_(emit_movb_reg_offregmem) ( reg, off, areg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1698 | } |
| 1699 | else { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1700 | VG_(emit_swapl_reg_EAX) ( reg ); |
| 1701 | VG_(emit_movb_reg_offregmem) ( R_AL, off, areg ); |
| 1702 | VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1703 | } |
| 1704 | break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1705 | default: VG_(core_panic)("synth_mov_reg_offregmem"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1706 | } |
| 1707 | } |
| 1708 | |
| 1709 | |
| 1710 | static void synth_mov_reg_memreg ( Int size, Int reg1, Int reg2 ) |
| 1711 | { |
| 1712 | Int s1; |
| 1713 | switch (size) { |
| 1714 | case 4: emit_movv_reg_regmem ( 4, reg1, reg2 ); break; |
| 1715 | case 2: emit_movv_reg_regmem ( 2, reg1, reg2 ); break; |
| 1716 | case 1: if (reg1 < 4) { |
| 1717 | emit_movb_reg_regmem ( reg1, reg2 ); |
| 1718 | } |
| 1719 | else { |
| 1720 | /* Choose a swap reg which is < 4 and not reg1 or reg2. */ |
| 1721 | for (s1 = 0; s1 == reg1 || s1 == reg2; s1++) ; |
| 1722 | emit_swapl_reg_reg ( s1, reg1 ); |
| 1723 | emit_movb_reg_regmem ( s1, reg2 ); |
| 1724 | emit_swapl_reg_reg ( s1, reg1 ); |
| 1725 | } |
| 1726 | break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1727 | default: VG_(core_panic)("synth_mov_reg_litmem"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1728 | } |
| 1729 | } |
| 1730 | |
| 1731 | |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1732 | static void synth_unaryop_reg ( Bool upd_cc, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1733 | Opcode opcode, Int size, |
| 1734 | Int reg ) |
| 1735 | { |
| 1736 | /* NB! opcode is a uinstr opcode, not an x86 one! */ |
| 1737 | switch (size) { |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1738 | case 4: if (upd_cc) emit_get_eflags(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1739 | VG_(emit_unaryopv_reg) ( 4, opcode, reg ); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1740 | if (upd_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1741 | break; |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1742 | case 2: if (upd_cc) emit_get_eflags(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1743 | VG_(emit_unaryopv_reg) ( 2, opcode, reg ); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1744 | if (upd_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1745 | break; |
| 1746 | case 1: if (reg < 4) { |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1747 | if (upd_cc) emit_get_eflags(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1748 | VG_(emit_unaryopb_reg) ( opcode, reg ); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1749 | if (upd_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1750 | } else { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1751 | VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1752 | if (upd_cc) emit_get_eflags(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1753 | VG_(emit_unaryopb_reg) ( opcode, R_AL ); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1754 | if (upd_cc) emit_put_eflags(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1755 | VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1756 | } |
| 1757 | break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1758 | default: VG_(core_panic)("synth_unaryop_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1759 | } |
| 1760 | } |
| 1761 | |
| 1762 | |
| 1763 | |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1764 | static void synth_nonshiftop_reg_reg ( Bool upd_cc, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1765 | Opcode opcode, Int size, |
| 1766 | Int reg1, Int reg2 ) |
| 1767 | { |
| 1768 | /* NB! opcode is a uinstr opcode, not an x86 one! */ |
| 1769 | switch (size) { |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1770 | case 4: if (upd_cc) emit_get_eflags(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1771 | VG_(emit_nonshiftopv_reg_reg) ( 4, opcode, reg1, reg2 ); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1772 | if (upd_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1773 | break; |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1774 | case 2: if (upd_cc) emit_get_eflags(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1775 | VG_(emit_nonshiftopv_reg_reg) ( 2, opcode, reg1, reg2 ); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1776 | if (upd_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1777 | break; |
| 1778 | case 1: { /* Horrible ... */ |
| 1779 | Int s1, s2; |
| 1780 | /* Choose s1 and s2 to be x86 regs which we can talk about the |
| 1781 | lowest 8 bits, ie either %eax, %ebx, %ecx or %edx. Make |
| 1782 | sure s1 != s2 and that neither of them equal either reg1 or |
| 1783 | reg2. Then use them as temporaries to make things work. */ |
| 1784 | if (reg1 < 4 && reg2 < 4) { |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1785 | if (upd_cc) emit_get_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1786 | emit_nonshiftopb_reg_reg(opcode, reg1, reg2); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1787 | if (upd_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1788 | break; |
| 1789 | } |
| 1790 | for (s1 = 0; s1 == reg1 || s1 == reg2; s1++) ; |
| 1791 | if (reg1 >= 4 && reg2 < 4) { |
| 1792 | emit_swapl_reg_reg ( reg1, s1 ); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1793 | if (upd_cc) emit_get_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1794 | emit_nonshiftopb_reg_reg(opcode, s1, reg2); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1795 | if (upd_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1796 | emit_swapl_reg_reg ( reg1, s1 ); |
| 1797 | break; |
| 1798 | } |
| 1799 | for (s2 = 0; s2 == reg1 || s2 == reg2 || s2 == s1; s2++) ; |
| 1800 | if (reg1 < 4 && reg2 >= 4) { |
| 1801 | emit_swapl_reg_reg ( reg2, s2 ); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1802 | if (upd_cc) emit_get_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1803 | emit_nonshiftopb_reg_reg(opcode, reg1, s2); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1804 | if (upd_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1805 | emit_swapl_reg_reg ( reg2, s2 ); |
| 1806 | break; |
| 1807 | } |
| 1808 | if (reg1 >= 4 && reg2 >= 4 && reg1 != reg2) { |
| 1809 | emit_swapl_reg_reg ( reg1, s1 ); |
| 1810 | emit_swapl_reg_reg ( reg2, s2 ); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1811 | if (upd_cc) emit_get_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1812 | emit_nonshiftopb_reg_reg(opcode, s1, s2); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1813 | if (upd_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1814 | emit_swapl_reg_reg ( reg1, s1 ); |
| 1815 | emit_swapl_reg_reg ( reg2, s2 ); |
| 1816 | break; |
| 1817 | } |
| 1818 | if (reg1 >= 4 && reg2 >= 4 && reg1 == reg2) { |
| 1819 | emit_swapl_reg_reg ( reg1, s1 ); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1820 | if (upd_cc) emit_get_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1821 | emit_nonshiftopb_reg_reg(opcode, s1, s1); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1822 | if (upd_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1823 | emit_swapl_reg_reg ( reg1, s1 ); |
| 1824 | break; |
| 1825 | } |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1826 | VG_(core_panic)("synth_nonshiftopb_reg_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1827 | } |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1828 | default: VG_(core_panic)("synth_nonshiftop_reg_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1829 | } |
| 1830 | } |
| 1831 | |
| 1832 | |
| 1833 | static void synth_nonshiftop_offregmem_reg ( |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1834 | Bool upd_cc, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1835 | Opcode opcode, Int size, |
| 1836 | Int off, Int areg, Int reg ) |
| 1837 | { |
| 1838 | switch (size) { |
| 1839 | case 4: |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1840 | if (upd_cc) emit_get_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1841 | emit_nonshiftopv_offregmem_reg ( 4, opcode, off, areg, reg ); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1842 | if (upd_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1843 | break; |
| 1844 | case 2: |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1845 | if (upd_cc) emit_get_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1846 | emit_nonshiftopv_offregmem_reg ( 2, opcode, off, areg, reg ); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1847 | if (upd_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1848 | break; |
| 1849 | case 1: |
| 1850 | if (reg < 4) { |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1851 | if (upd_cc) emit_get_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1852 | emit_nonshiftopb_offregmem_reg ( opcode, off, areg, reg ); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1853 | if (upd_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1854 | } else { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1855 | VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1856 | if (upd_cc) emit_get_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1857 | emit_nonshiftopb_offregmem_reg ( opcode, off, areg, R_AL ); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1858 | if (upd_cc) emit_put_eflags(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1859 | VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1860 | } |
| 1861 | break; |
| 1862 | default: |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1863 | VG_(core_panic)("synth_nonshiftop_offregmem_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1864 | } |
| 1865 | } |
| 1866 | |
| 1867 | |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1868 | static void synth_nonshiftop_lit_reg ( Bool upd_cc, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1869 | Opcode opcode, Int size, |
| 1870 | UInt lit, Int reg ) |
| 1871 | { |
| 1872 | switch (size) { |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1873 | case 4: if (upd_cc) emit_get_eflags(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1874 | VG_(emit_nonshiftopv_lit_reg) ( 4, opcode, lit, reg ); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1875 | if (upd_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1876 | break; |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1877 | case 2: if (upd_cc) emit_get_eflags(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1878 | VG_(emit_nonshiftopv_lit_reg) ( 2, opcode, lit, reg ); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1879 | if (upd_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1880 | break; |
| 1881 | case 1: if (reg < 4) { |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1882 | if (upd_cc) emit_get_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1883 | emit_nonshiftopb_lit_reg ( opcode, lit, reg ); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1884 | if (upd_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1885 | } else { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1886 | VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1887 | if (upd_cc) emit_get_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1888 | emit_nonshiftopb_lit_reg ( opcode, lit, R_AL ); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1889 | if (upd_cc) emit_put_eflags(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1890 | VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1891 | } |
| 1892 | break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1893 | default: VG_(core_panic)("synth_nonshiftop_lit_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1894 | } |
| 1895 | } |
| 1896 | |
| 1897 | |
| 1898 | static void synth_push_reg ( Int size, Int reg ) |
| 1899 | { |
| 1900 | switch (size) { |
| 1901 | case 4: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1902 | VG_(emit_pushv_reg) ( 4, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1903 | break; |
| 1904 | case 2: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1905 | VG_(emit_pushv_reg) ( 2, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1906 | break; |
| 1907 | /* Pray that we don't have to generate this really cruddy bit of |
| 1908 | code very often. Could do better, but can I be bothered? */ |
| 1909 | case 1: |
| 1910 | vg_assert(reg != R_ESP); /* duh */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1911 | VG_(emit_add_lit_to_esp)(-1); |
| 1912 | if (reg != R_EAX) VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1913 | emit_movb_AL_zeroESPmem(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1914 | if (reg != R_EAX) VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1915 | break; |
| 1916 | default: |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1917 | VG_(core_panic)("synth_push_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1918 | } |
| 1919 | } |
| 1920 | |
| 1921 | |
| 1922 | static void synth_pop_reg ( Int size, Int reg ) |
| 1923 | { |
| 1924 | switch (size) { |
| 1925 | case 4: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1926 | VG_(emit_popv_reg) ( 4, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1927 | break; |
| 1928 | case 2: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1929 | VG_(emit_popv_reg) ( 2, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1930 | break; |
| 1931 | case 1: |
| 1932 | /* Same comment as above applies. */ |
| 1933 | vg_assert(reg != R_ESP); /* duh */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1934 | if (reg != R_EAX) VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1935 | emit_movb_zeroESPmem_AL(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1936 | if (reg != R_EAX) VG_(emit_swapl_reg_EAX) ( reg ); |
| 1937 | VG_(emit_add_lit_to_esp)(1); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1938 | break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1939 | default: VG_(core_panic)("synth_pop_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1940 | } |
| 1941 | } |
| 1942 | |
| 1943 | |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1944 | static void synth_shiftop_reg_reg ( Bool upd_cc, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1945 | Opcode opcode, Int size, |
| 1946 | Int regs, Int regd ) |
| 1947 | { |
| 1948 | synth_push_reg ( size, regd ); |
| 1949 | if (regs != R_ECX) emit_swapl_reg_ECX ( regs ); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1950 | if (upd_cc) emit_get_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1951 | switch (size) { |
| 1952 | case 4: emit_shiftopv_cl_stack0 ( 4, opcode ); break; |
| 1953 | case 2: emit_shiftopv_cl_stack0 ( 2, opcode ); break; |
| 1954 | case 1: emit_shiftopb_cl_stack0 ( opcode ); break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1955 | default: VG_(core_panic)("synth_shiftop_reg_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1956 | } |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1957 | if (upd_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1958 | if (regs != R_ECX) emit_swapl_reg_ECX ( regs ); |
| 1959 | synth_pop_reg ( size, regd ); |
| 1960 | } |
| 1961 | |
| 1962 | |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1963 | static void synth_shiftop_lit_reg ( Bool upd_cc, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1964 | Opcode opcode, Int size, |
| 1965 | UInt lit, Int reg ) |
| 1966 | { |
| 1967 | switch (size) { |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1968 | case 4: if (upd_cc) emit_get_eflags(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1969 | VG_(emit_shiftopv_lit_reg) ( 4, opcode, lit, reg ); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1970 | if (upd_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1971 | break; |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1972 | case 2: if (upd_cc) emit_get_eflags(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1973 | VG_(emit_shiftopv_lit_reg) ( 2, opcode, lit, reg ); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1974 | if (upd_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1975 | break; |
| 1976 | case 1: if (reg < 4) { |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1977 | if (upd_cc) emit_get_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1978 | emit_shiftopb_lit_reg ( opcode, lit, reg ); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1979 | if (upd_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1980 | } else { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1981 | VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1982 | if (upd_cc) emit_get_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1983 | emit_shiftopb_lit_reg ( opcode, lit, R_AL ); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 1984 | if (upd_cc) emit_put_eflags(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1985 | VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1986 | } |
| 1987 | break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1988 | default: VG_(core_panic)("synth_shiftop_lit_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1989 | } |
| 1990 | } |
| 1991 | |
| 1992 | |
| 1993 | static void synth_setb_reg ( Int reg, Condcode cond ) |
| 1994 | { |
| 1995 | emit_get_eflags(); |
| 1996 | if (reg < 4) { |
| 1997 | emit_setb_reg ( reg, cond ); |
| 1998 | } else { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1999 | VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2000 | emit_setb_reg ( R_AL, cond ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2001 | VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2002 | } |
| 2003 | } |
| 2004 | |
| 2005 | |
| 2006 | static void synth_fpu_regmem ( UChar first_byte, |
| 2007 | UChar second_byte_masked, |
| 2008 | Int reg ) |
| 2009 | { |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2010 | emit_fpu_regmem ( first_byte, second_byte_masked, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2011 | } |
| 2012 | |
| 2013 | |
| 2014 | static void synth_fpu_no_mem ( UChar first_byte, |
| 2015 | UChar second_byte ) |
| 2016 | { |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2017 | emit_fpu_no_mem ( first_byte, second_byte ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2018 | } |
| 2019 | |
| 2020 | |
| 2021 | static void synth_movl_reg_reg ( Int src, Int dst ) |
| 2022 | { |
| 2023 | emit_movl_reg_reg ( src, dst ); |
| 2024 | } |
| 2025 | |
| 2026 | static void synth_cmovl_reg_reg ( Condcode cond, Int src, Int dst ) |
| 2027 | { |
| 2028 | emit_get_eflags(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2029 | VG_(emit_jcondshort_delta) ( invertCondition(cond), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2030 | 2 /* length of the next insn */ ); |
| 2031 | emit_movl_reg_reg ( src, dst ); |
| 2032 | } |
| 2033 | |
| 2034 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2035 | /*----------------------------------------------------*/ |
| 2036 | /*--- Top level of the uinstr -> x86 translation. ---*/ |
| 2037 | /*----------------------------------------------------*/ |
| 2038 | |
| 2039 | /* Return the byte offset from %ebp (ie, into baseBlock) |
| 2040 | for the specified ArchReg or SpillNo. */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2041 | static Int spillOrArchOffset ( Int size, Tag tag, UInt value ) |
| 2042 | { |
| 2043 | if (tag == SpillNo) { |
| 2044 | vg_assert(size == 4); |
| 2045 | vg_assert(value >= 0 && value < VG_MAX_SPILLSLOTS); |
| 2046 | return 4 * (value + VGOFF_(spillslots)); |
| 2047 | } |
| 2048 | if (tag == ArchReg) { |
| 2049 | switch (value) { |
| 2050 | case R_EAX: return 4 * VGOFF_(m_eax); |
| 2051 | case R_ECX: return 4 * VGOFF_(m_ecx); |
| 2052 | case R_EDX: return 4 * VGOFF_(m_edx); |
| 2053 | case R_EBX: return 4 * VGOFF_(m_ebx); |
| 2054 | case R_ESP: |
| 2055 | if (size == 1) return 4 * VGOFF_(m_eax) + 1; |
| 2056 | else return 4 * VGOFF_(m_esp); |
| 2057 | case R_EBP: |
| 2058 | if (size == 1) return 4 * VGOFF_(m_ecx) + 1; |
| 2059 | else return 4 * VGOFF_(m_ebp); |
| 2060 | case R_ESI: |
| 2061 | if (size == 1) return 4 * VGOFF_(m_edx) + 1; |
| 2062 | else return 4 * VGOFF_(m_esi); |
| 2063 | case R_EDI: |
| 2064 | if (size == 1) return 4 * VGOFF_(m_ebx) + 1; |
| 2065 | else return 4 * VGOFF_(m_edi); |
| 2066 | } |
| 2067 | } |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2068 | VG_(core_panic)("spillOrArchOffset"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2069 | } |
| 2070 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2071 | static Int eflagsOffset ( void ) |
| 2072 | { |
| 2073 | return 4 * VGOFF_(m_eflags); |
| 2074 | } |
| 2075 | |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 2076 | static Int segRegOffset ( UInt archregs ) |
| 2077 | { |
| 2078 | switch (archregs) { |
| 2079 | case R_CS: return 4 * VGOFF_(m_cs); |
| 2080 | case R_SS: return 4 * VGOFF_(m_ss); |
| 2081 | case R_DS: return 4 * VGOFF_(m_ds); |
| 2082 | case R_ES: return 4 * VGOFF_(m_es); |
| 2083 | case R_FS: return 4 * VGOFF_(m_fs); |
| 2084 | case R_GS: return 4 * VGOFF_(m_gs); |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2085 | default: VG_(core_panic)("segRegOffset"); |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 2086 | } |
| 2087 | } |
| 2088 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2089 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2090 | /* Return the byte offset from %ebp (ie, into baseBlock) |
| 2091 | for the specified shadow register */ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2092 | Int VG_(shadow_reg_offset) ( Int arch ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2093 | { |
| 2094 | switch (arch) { |
| 2095 | case R_EAX: return 4 * VGOFF_(sh_eax); |
| 2096 | case R_ECX: return 4 * VGOFF_(sh_ecx); |
| 2097 | case R_EDX: return 4 * VGOFF_(sh_edx); |
| 2098 | case R_EBX: return 4 * VGOFF_(sh_ebx); |
| 2099 | case R_ESP: return 4 * VGOFF_(sh_esp); |
| 2100 | case R_EBP: return 4 * VGOFF_(sh_ebp); |
| 2101 | case R_ESI: return 4 * VGOFF_(sh_esi); |
| 2102 | case R_EDI: return 4 * VGOFF_(sh_edi); |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2103 | default: VG_(core_panic)( "shadowOffset"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2104 | } |
| 2105 | } |
| 2106 | |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2107 | Int VG_(shadow_flags_offset) ( void ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2108 | { |
| 2109 | return 4 * VGOFF_(sh_eflags); |
| 2110 | } |
| 2111 | |
| 2112 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2113 | |
| 2114 | static void synth_WIDEN_signed ( Int sz_src, Int sz_dst, Int reg ) |
| 2115 | { |
| 2116 | if (sz_src == 1 && sz_dst == 4) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2117 | VG_(emit_shiftopv_lit_reg) ( 4, SHL, 24, reg ); |
| 2118 | VG_(emit_shiftopv_lit_reg) ( 4, SAR, 24, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2119 | } |
| 2120 | else if (sz_src == 2 && sz_dst == 4) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2121 | VG_(emit_shiftopv_lit_reg) ( 4, SHL, 16, reg ); |
| 2122 | VG_(emit_shiftopv_lit_reg) ( 4, SAR, 16, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2123 | } |
| 2124 | else if (sz_src == 1 && sz_dst == 2) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2125 | VG_(emit_shiftopv_lit_reg) ( 2, SHL, 8, reg ); |
| 2126 | VG_(emit_shiftopv_lit_reg) ( 2, SAR, 8, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2127 | } |
| 2128 | else |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2129 | VG_(core_panic)("synth_WIDEN"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2130 | } |
| 2131 | |
| 2132 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2133 | static void synth_handle_esp_assignment ( Int i, Int reg, |
| 2134 | RRegSet regs_live_before, |
| 2135 | RRegSet regs_live_after ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2136 | { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2137 | UInt argv[] = { reg }; |
| 2138 | Tag tagv[] = { RealReg }; |
| 2139 | |
| 2140 | VG_(synth_ccall) ( (Addr) VG_(handle_esp_assignment), 1, 1, argv, tagv, |
| 2141 | INVALID_REALREG, regs_live_before, regs_live_after); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2142 | } |
| 2143 | |
| 2144 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2145 | /*----------------------------------------------------*/ |
| 2146 | /*--- Generate code for a single UInstr. ---*/ |
| 2147 | /*----------------------------------------------------*/ |
| 2148 | |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 2149 | static __inline__ |
| 2150 | Bool writeFlagUse ( UInstr* u ) |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 2151 | { |
| 2152 | return (u->flags_w != FlagsEmpty); |
| 2153 | } |
| 2154 | |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 2155 | static __inline__ |
| 2156 | Bool anyFlagUse ( UInstr* u ) |
| 2157 | { |
| 2158 | return (u->flags_r != FlagsEmpty || u->flags_w != FlagsEmpty); |
| 2159 | } |
| 2160 | |
| 2161 | |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2162 | /* fplive==True indicates that the simulated machine's FPU state is in |
| 2163 | the real FPU. If so we need to be very careful not to trash it. |
| 2164 | If FPU state is live and we deem it necessary to copy it back to |
| 2165 | the simulated machine's FPU state, we do so. The final state of |
| 2166 | fpliveness is returned. In short we _must_ do put_fpu_state if |
| 2167 | there is any chance at all that the code generated for a UInstr |
| 2168 | will change the real FPU state. |
| 2169 | */ |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 2170 | static Bool emitUInstr ( UCodeBlock* cb, Int i, |
| 2171 | RRegSet regs_live_before, Bool fplive ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2172 | { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2173 | Int old_emitted_code_used; |
| 2174 | UInstr* u = &cb->instrs[i]; |
| 2175 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2176 | if (dis) |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2177 | VG_(pp_UInstr_regs)(i, u); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2178 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2179 | old_emitted_code_used = emitted_code_used; |
| 2180 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2181 | switch (u->opcode) { |
sewardj | 7a5ebcf | 2002-11-13 22:42:13 +0000 | [diff] [blame] | 2182 | case NOP: case LOCK: case CALLM_S: case CALLM_E: break; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2183 | |
| 2184 | case INCEIP: { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2185 | /* Note: Redundant INCEIP merging. A potentially useful |
| 2186 | performance enhancementa, but currently disabled. Reason |
| 2187 | is that it needs a surefire way to know if a UInstr might |
| 2188 | give rise to a stack snapshot being taken. The logic below |
| 2189 | is correct (hopefully ...) for the core UInstrs, but is |
| 2190 | incorrect if a skin has its own UInstrs, since the logic |
| 2191 | currently assumes that none of them can cause a stack |
| 2192 | trace, and that's just wrong. Note this isn't |
| 2193 | mission-critical -- the system still functions -- but will |
| 2194 | cause incorrect source locations in some situations, |
| 2195 | specifically for the memcheck skin. This is known to |
| 2196 | confuse programmers, understandable. */ |
| 2197 | # if 0 |
| 2198 | Bool can_skip; |
| 2199 | Int j; |
| 2200 | |
| 2201 | /* Scan forwards to see if this INCEIP dominates (in the |
| 2202 | technical sense) a later one, AND there are no CCALLs in |
| 2203 | between. If so, skip this one and instead add its count |
| 2204 | with the later one. */ |
| 2205 | can_skip = True; |
| 2206 | j = i+1; |
| 2207 | while (True) { |
| 2208 | if (cb->instrs[j].opcode == CCALL |
| 2209 | || cb->instrs[j].opcode == CALLM) { |
| 2210 | /* CCALL -- we can't skip this INCEIP. */ |
| 2211 | can_skip = False; |
| 2212 | break; |
| 2213 | } |
| 2214 | if (cb->instrs[j].opcode == INCEIP) { |
| 2215 | /* Another INCEIP. Check that the sum will fit. */ |
| 2216 | if (cb->instrs[i].val1 + cb->instrs[j].val1 > 127) |
| 2217 | can_skip = False; |
| 2218 | break; |
| 2219 | } |
| 2220 | if (cb->instrs[j].opcode == JMP || cb->instrs[j].opcode == JIFZ) { |
| 2221 | /* Execution is not guaranteed to get beyond this |
| 2222 | point. Give up. */ |
| 2223 | can_skip = False; |
| 2224 | break; |
| 2225 | } |
| 2226 | j++; |
| 2227 | /* Assertion should hold because all blocks should end in an |
| 2228 | unconditional JMP, so the above test should get us out of |
| 2229 | the loop at the end of a block. */ |
| 2230 | vg_assert(j < cb->used); |
| 2231 | } |
| 2232 | if (can_skip) { |
| 2233 | /* yay! Accumulate the delta into the next INCEIP. */ |
| 2234 | // VG_(printf)("skip INCEIP %d\n", cb->instrs[i].val1); |
| 2235 | vg_assert(j > i); |
| 2236 | vg_assert(j < cb->used); |
| 2237 | vg_assert(cb->instrs[j].opcode == INCEIP); |
| 2238 | vg_assert(cb->instrs[i].opcode == INCEIP); |
| 2239 | vg_assert(cb->instrs[j].tag1 == Lit16); |
| 2240 | vg_assert(cb->instrs[i].tag1 == Lit16); |
| 2241 | cb->instrs[j].val1 += cb->instrs[i].val1; |
| 2242 | /* do nothing now */ |
| 2243 | } else |
| 2244 | # endif |
| 2245 | |
| 2246 | { |
| 2247 | /* no, we really have to do this, alas */ |
| 2248 | // VG_(printf)(" do INCEIP %d\n", cb->instrs[i].val1); |
| 2249 | vg_assert(u->tag1 == Lit16); |
| 2250 | emit_addlit8_offregmem ( u->val1, R_EBP, 4 * VGOFF_(m_eip) ); |
| 2251 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2252 | break; |
| 2253 | } |
| 2254 | |
| 2255 | case LEA1: { |
| 2256 | vg_assert(u->tag1 == RealReg); |
| 2257 | vg_assert(u->tag2 == RealReg); |
| 2258 | emit_lea_litreg_reg ( u->lit32, u->val1, u->val2 ); |
| 2259 | break; |
| 2260 | } |
| 2261 | |
| 2262 | case LEA2: { |
| 2263 | vg_assert(u->tag1 == RealReg); |
| 2264 | vg_assert(u->tag2 == RealReg); |
| 2265 | vg_assert(u->tag3 == RealReg); |
| 2266 | emit_lea_sib_reg ( u->lit32, u->extra4b, |
| 2267 | u->val1, u->val2, u->val3 ); |
| 2268 | break; |
| 2269 | } |
| 2270 | |
| 2271 | case WIDEN: { |
| 2272 | vg_assert(u->tag1 == RealReg); |
| 2273 | if (u->signed_widen) { |
| 2274 | synth_WIDEN_signed ( u->extra4b, u->size, u->val1 ); |
| 2275 | } else { |
| 2276 | /* no need to generate any code. */ |
| 2277 | } |
| 2278 | break; |
| 2279 | } |
| 2280 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2281 | case STORE: { |
| 2282 | vg_assert(u->tag1 == RealReg); |
| 2283 | vg_assert(u->tag2 == RealReg); |
| 2284 | synth_mov_reg_memreg ( u->size, u->val1, u->val2 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2285 | break; |
| 2286 | } |
| 2287 | |
| 2288 | case LOAD: { |
| 2289 | vg_assert(u->tag1 == RealReg); |
| 2290 | vg_assert(u->tag2 == RealReg); |
| 2291 | synth_mov_regmem_reg ( u->size, u->val1, u->val2 ); |
| 2292 | break; |
| 2293 | } |
| 2294 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2295 | case GET: { |
| 2296 | vg_assert(u->tag1 == ArchReg || u->tag1 == SpillNo); |
| 2297 | vg_assert(u->tag2 == RealReg); |
| 2298 | synth_mov_offregmem_reg ( |
| 2299 | u->size, |
| 2300 | spillOrArchOffset( u->size, u->tag1, u->val1 ), |
| 2301 | R_EBP, |
| 2302 | u->val2 |
| 2303 | ); |
| 2304 | break; |
| 2305 | } |
| 2306 | |
| 2307 | case PUT: { |
| 2308 | vg_assert(u->tag2 == ArchReg || u->tag2 == SpillNo); |
| 2309 | vg_assert(u->tag1 == RealReg); |
| 2310 | if (u->tag2 == ArchReg |
| 2311 | && u->val2 == R_ESP |
| 2312 | && u->size == 4 |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2313 | && (VG_(track_events).new_mem_stack || |
| 2314 | VG_(track_events).new_mem_stack_aligned || |
| 2315 | VG_(track_events).die_mem_stack || |
| 2316 | VG_(track_events).die_mem_stack_aligned || |
| 2317 | VG_(track_events).post_mem_write)) |
| 2318 | { |
| 2319 | synth_handle_esp_assignment ( i, u->val1, regs_live_before, |
| 2320 | u->regs_live_after ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2321 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2322 | else { |
| 2323 | synth_mov_reg_offregmem ( |
| 2324 | u->size, |
| 2325 | u->val1, |
| 2326 | spillOrArchOffset( u->size, u->tag2, u->val2 ), |
| 2327 | R_EBP |
| 2328 | ); |
| 2329 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2330 | break; |
| 2331 | } |
| 2332 | |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 2333 | case GETSEG: { |
| 2334 | vg_assert(u->tag1 == ArchRegS); |
| 2335 | vg_assert(u->tag2 == RealReg); |
| 2336 | vg_assert(u->size == 2); |
| 2337 | synth_mov_offregmem_reg ( |
| 2338 | 4, |
| 2339 | segRegOffset( u->val1 ), |
| 2340 | R_EBP, |
| 2341 | u->val2 |
| 2342 | ); |
| 2343 | break; |
| 2344 | } |
| 2345 | |
| 2346 | case PUTSEG: { |
| 2347 | vg_assert(u->tag1 == RealReg); |
| 2348 | vg_assert(u->tag2 == ArchRegS); |
| 2349 | vg_assert(u->size == 2); |
| 2350 | synth_mov_reg_offregmem ( |
| 2351 | 4, |
| 2352 | u->val1, |
| 2353 | segRegOffset( u->val2 ), |
| 2354 | R_EBP |
| 2355 | ); |
| 2356 | break; |
| 2357 | } |
| 2358 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2359 | case GETF: { |
| 2360 | vg_assert(u->size == 2 || u->size == 4); |
| 2361 | vg_assert(u->tag1 == RealReg); |
| 2362 | synth_mov_offregmem_reg ( |
| 2363 | u->size, |
| 2364 | eflagsOffset(), |
| 2365 | R_EBP, |
| 2366 | u->val1 |
| 2367 | ); |
| 2368 | break; |
| 2369 | } |
| 2370 | |
| 2371 | case PUTF: { |
| 2372 | vg_assert(u->size == 2 || u->size == 4); |
| 2373 | vg_assert(u->tag1 == RealReg); |
| 2374 | synth_mov_reg_offregmem ( |
| 2375 | u->size, |
| 2376 | u->val1, |
| 2377 | eflagsOffset(), |
| 2378 | R_EBP |
| 2379 | ); |
| 2380 | break; |
| 2381 | } |
| 2382 | |
| 2383 | case MOV: { |
| 2384 | vg_assert(u->tag1 == RealReg || u->tag1 == Literal); |
| 2385 | vg_assert(u->tag2 == RealReg); |
| 2386 | switch (u->tag1) { |
| 2387 | case RealReg: vg_assert(u->size == 4); |
| 2388 | if (u->val1 != u->val2) |
| 2389 | synth_movl_reg_reg ( u->val1, u->val2 ); |
| 2390 | break; |
| 2391 | case Literal: synth_mov_lit_reg ( u->size, u->lit32, u->val2 ); |
| 2392 | break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2393 | default: VG_(core_panic)("emitUInstr:mov"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2394 | } |
| 2395 | break; |
| 2396 | } |
| 2397 | |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 2398 | case USESEG: { |
| 2399 | /* Lazy: copy all three vals; synth_ccall ignores any unnecessary |
| 2400 | ones. */ |
sewardj | d077f53 | 2002-09-30 21:52:50 +0000 | [diff] [blame] | 2401 | UInt argv[] = { u->val1, u->val2 }; |
| 2402 | UInt tagv[] = { RealReg, RealReg }; |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 2403 | UInt ret_reg = u->val2; |
| 2404 | |
| 2405 | vg_assert(u->tag1 == RealReg); |
| 2406 | vg_assert(u->tag2 == RealReg); |
| 2407 | vg_assert(u->size == 0); |
| 2408 | |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2409 | if (fplive) { |
| 2410 | emit_put_fpu_state(); |
| 2411 | fplive = False; |
| 2412 | } |
| 2413 | |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 2414 | VG_(synth_ccall) ( (Addr) & VG_(do_useseg), |
| 2415 | 2, /* args */ |
| 2416 | 0, /* regparms_n */ |
| 2417 | argv, tagv, |
| 2418 | ret_reg, regs_live_before, u->regs_live_after ); |
| 2419 | break; |
| 2420 | } |
| 2421 | |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 2422 | case SBB: |
| 2423 | case ADC: |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2424 | case XOR: |
| 2425 | case OR: |
| 2426 | case AND: |
| 2427 | case SUB: |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 2428 | case ADD: { |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2429 | vg_assert(u->tag2 == RealReg); |
| 2430 | switch (u->tag1) { |
| 2431 | case Literal: synth_nonshiftop_lit_reg ( |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 2432 | anyFlagUse(u), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2433 | u->opcode, u->size, u->lit32, u->val2 ); |
| 2434 | break; |
| 2435 | case RealReg: synth_nonshiftop_reg_reg ( |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 2436 | anyFlagUse(u), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2437 | u->opcode, u->size, u->val1, u->val2 ); |
| 2438 | break; |
| 2439 | case ArchReg: synth_nonshiftop_offregmem_reg ( |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 2440 | anyFlagUse(u), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2441 | u->opcode, u->size, |
| 2442 | spillOrArchOffset( u->size, u->tag1, u->val1 ), |
| 2443 | R_EBP, |
| 2444 | u->val2 ); |
| 2445 | break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2446 | default: VG_(core_panic)("emitUInstr:non-shift-op"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2447 | } |
| 2448 | break; |
| 2449 | } |
| 2450 | |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 2451 | case RCR: |
| 2452 | case RCL: |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2453 | case ROR: |
| 2454 | case ROL: |
| 2455 | case SAR: |
| 2456 | case SHR: |
| 2457 | case SHL: { |
| 2458 | vg_assert(u->tag2 == RealReg); |
| 2459 | switch (u->tag1) { |
| 2460 | case Literal: synth_shiftop_lit_reg ( |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 2461 | anyFlagUse(u), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2462 | u->opcode, u->size, u->lit32, u->val2 ); |
| 2463 | break; |
| 2464 | case RealReg: synth_shiftop_reg_reg ( |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 2465 | anyFlagUse(u), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2466 | u->opcode, u->size, u->val1, u->val2 ); |
| 2467 | break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2468 | default: VG_(core_panic)("emitUInstr:non-shift-op"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2469 | } |
| 2470 | break; |
| 2471 | } |
| 2472 | |
| 2473 | case INC: |
| 2474 | case DEC: |
| 2475 | case NEG: |
| 2476 | case NOT: |
| 2477 | vg_assert(u->tag1 == RealReg); |
| 2478 | synth_unaryop_reg ( |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 2479 | anyFlagUse(u), u->opcode, u->size, u->val1 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2480 | break; |
| 2481 | |
| 2482 | case BSWAP: |
| 2483 | vg_assert(u->tag1 == RealReg); |
| 2484 | vg_assert(u->size == 4); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2485 | vg_assert(!VG_(any_flag_use)(u)); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2486 | emit_bswapl_reg ( u->val1 ); |
| 2487 | break; |
| 2488 | |
| 2489 | case CMOV: |
| 2490 | vg_assert(u->tag1 == RealReg); |
| 2491 | vg_assert(u->tag2 == RealReg); |
| 2492 | vg_assert(u->cond != CondAlways); |
| 2493 | vg_assert(u->size == 4); |
| 2494 | synth_cmovl_reg_reg ( u->cond, u->val1, u->val2 ); |
| 2495 | break; |
| 2496 | |
| 2497 | case JMP: { |
| 2498 | vg_assert(u->tag2 == NoValue); |
| 2499 | vg_assert(u->tag1 == RealReg || u->tag1 == Literal); |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2500 | if (fplive) { |
| 2501 | emit_put_fpu_state(); |
| 2502 | fplive = False; |
| 2503 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2504 | if (u->cond == CondAlways) { |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 2505 | switch (u->tag1) { |
| 2506 | case RealReg: |
| 2507 | synth_jmp_reg ( u->val1, u->jmpkind ); |
| 2508 | break; |
| 2509 | case Literal: |
| 2510 | synth_jmp_lit ( u->lit32, u->jmpkind ); |
| 2511 | break; |
| 2512 | default: |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2513 | VG_(core_panic)("emitUInstr(JMP, unconditional, default)"); |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 2514 | break; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2515 | } |
| 2516 | } else { |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 2517 | switch (u->tag1) { |
| 2518 | case RealReg: |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2519 | VG_(core_panic)("emitUInstr(JMP, conditional, RealReg)"); |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 2520 | break; |
| 2521 | case Literal: |
| 2522 | vg_assert(u->jmpkind == JmpBoring); |
| 2523 | synth_jcond_lit ( u->cond, u->lit32 ); |
| 2524 | break; |
| 2525 | default: |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2526 | VG_(core_panic)("emitUInstr(JMP, conditional, default)"); |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 2527 | break; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2528 | } |
| 2529 | } |
| 2530 | break; |
| 2531 | } |
| 2532 | |
| 2533 | case JIFZ: |
| 2534 | vg_assert(u->tag1 == RealReg); |
| 2535 | vg_assert(u->tag2 == Literal); |
| 2536 | vg_assert(u->size == 4); |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2537 | if (fplive) { |
| 2538 | emit_put_fpu_state(); |
| 2539 | fplive = False; |
| 2540 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2541 | synth_jmp_ifzero_reg_lit ( u->val1, u->lit32 ); |
| 2542 | break; |
| 2543 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2544 | case PUSH: |
| 2545 | vg_assert(u->tag1 == RealReg); |
| 2546 | vg_assert(u->tag2 == NoValue); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2547 | VG_(emit_pushv_reg) ( 4, u->val1 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2548 | break; |
| 2549 | |
| 2550 | case POP: |
| 2551 | vg_assert(u->tag1 == RealReg); |
| 2552 | vg_assert(u->tag2 == NoValue); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2553 | VG_(emit_popv_reg) ( 4, u->val1 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2554 | break; |
| 2555 | |
| 2556 | case CALLM: |
| 2557 | vg_assert(u->tag1 == Lit16); |
| 2558 | vg_assert(u->tag2 == NoValue); |
| 2559 | vg_assert(u->size == 0); |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2560 | if (fplive) { |
| 2561 | emit_put_fpu_state(); |
| 2562 | fplive = False; |
| 2563 | } |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 2564 | if (anyFlagUse ( u )) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2565 | emit_get_eflags(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2566 | VG_(synth_call) ( False, u->val1 ); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 2567 | if (writeFlagUse ( u )) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2568 | emit_put_eflags(); |
| 2569 | break; |
| 2570 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2571 | case CCALL: { |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 2572 | /* If you change this, remember to change USESEG above, since |
| 2573 | that's just a copy of this, slightly simplified. */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2574 | /* Lazy: copy all three vals; synth_ccall ignores any unnecessary |
| 2575 | ones. */ |
| 2576 | UInt argv[] = { u->val1, u->val2, u->val3 }; |
| 2577 | UInt tagv[] = { RealReg, RealReg, RealReg }; |
| 2578 | UInt ret_reg = ( u->has_ret_val ? u->val3 : INVALID_REALREG ); |
| 2579 | |
| 2580 | if (u->argc >= 1) vg_assert(u->tag1 == RealReg); |
| 2581 | else vg_assert(u->tag1 == NoValue); |
| 2582 | if (u->argc >= 2) vg_assert(u->tag2 == RealReg); |
| 2583 | else vg_assert(u->tag2 == NoValue); |
| 2584 | if (u->argc == 3 || u->has_ret_val) vg_assert(u->tag3 == RealReg); |
| 2585 | else vg_assert(u->tag3 == NoValue); |
njn | 6431be7 | 2002-07-28 09:53:34 +0000 | [diff] [blame] | 2586 | vg_assert(u->size == 0); |
| 2587 | |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2588 | if (fplive) { |
| 2589 | emit_put_fpu_state(); |
| 2590 | fplive = False; |
| 2591 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2592 | VG_(synth_ccall) ( u->lit32, u->argc, u->regparms_n, argv, tagv, |
| 2593 | ret_reg, regs_live_before, u->regs_live_after ); |
njn | 6431be7 | 2002-07-28 09:53:34 +0000 | [diff] [blame] | 2594 | break; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2595 | } |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 2596 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2597 | case CLEAR: |
| 2598 | vg_assert(u->tag1 == Lit16); |
| 2599 | vg_assert(u->tag2 == NoValue); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2600 | VG_(emit_add_lit_to_esp) ( u->val1 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2601 | break; |
| 2602 | |
| 2603 | case CC2VAL: |
| 2604 | vg_assert(u->tag1 == RealReg); |
| 2605 | vg_assert(u->tag2 == NoValue); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2606 | vg_assert(VG_(any_flag_use)(u)); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2607 | synth_setb_reg ( u->val1, u->cond ); |
| 2608 | break; |
| 2609 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2610 | case FPU_R: |
| 2611 | case FPU_W: |
| 2612 | vg_assert(u->tag1 == Lit16); |
| 2613 | vg_assert(u->tag2 == RealReg); |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2614 | if (!fplive) { |
| 2615 | emit_get_fpu_state(); |
| 2616 | fplive = True; |
| 2617 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2618 | synth_fpu_regmem ( (u->val1 >> 8) & 0xFF, |
| 2619 | u->val1 & 0xFF, |
| 2620 | u->val2 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2621 | break; |
| 2622 | |
| 2623 | case FPU: |
| 2624 | vg_assert(u->tag1 == Lit16); |
| 2625 | vg_assert(u->tag2 == NoValue); |
sewardj | 478335c | 2002-10-05 02:44:47 +0000 | [diff] [blame] | 2626 | if (anyFlagUse ( u )) |
sewardj | 4a7456e | 2002-03-24 13:52:19 +0000 | [diff] [blame] | 2627 | emit_get_eflags(); |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2628 | if (!fplive) { |
| 2629 | emit_get_fpu_state(); |
| 2630 | fplive = True; |
| 2631 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2632 | synth_fpu_no_mem ( (u->val1 >> 8) & 0xFF, |
| 2633 | u->val1 & 0xFF ); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 2634 | if (writeFlagUse ( u )) |
sewardj | 4a7456e | 2002-03-24 13:52:19 +0000 | [diff] [blame] | 2635 | emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2636 | break; |
| 2637 | |
| 2638 | default: |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2639 | if (VG_(needs).extended_UCode) { |
| 2640 | if (fplive) { |
| 2641 | emit_put_fpu_state(); |
| 2642 | fplive = False; |
| 2643 | } |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2644 | SK_(emit_XUInstr)(u, regs_live_before); |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2645 | } else { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2646 | VG_(printf)("\nError:\n" |
| 2647 | " unhandled opcode: %u. Perhaps " |
| 2648 | " VG_(needs).extended_UCode should be set?\n", |
| 2649 | u->opcode); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2650 | VG_(pp_UInstr)(0,u); |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2651 | VG_(core_panic)("emitUInstr: unimplemented opcode"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2652 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2653 | } |
| 2654 | |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2655 | if (0 && fplive) { |
| 2656 | emit_put_fpu_state(); |
| 2657 | fplive = False; |
| 2658 | } |
| 2659 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2660 | /* Update UInstr histogram */ |
| 2661 | vg_assert(u->opcode < 100); |
| 2662 | histogram[u->opcode].counts++; |
| 2663 | histogram[u->opcode].size += (emitted_code_used - old_emitted_code_used); |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2664 | |
| 2665 | return fplive; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2666 | } |
| 2667 | |
| 2668 | |
| 2669 | /* Emit x86 for the ucode in cb, returning the address of the |
| 2670 | generated code and setting *nbytes to its size. */ |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 2671 | UChar* VG_(emit_code) ( UCodeBlock* cb, Int* nbytes, UShort j[VG_MAX_JUMPS] ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2672 | { |
| 2673 | Int i; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2674 | UChar regs_live_before = 0; /* No regs live at BB start */ |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2675 | Bool fplive; |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 2676 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2677 | emitted_code_used = 0; |
| 2678 | emitted_code_size = 500; /* reasonable initial size */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2679 | emitted_code = VG_(arena_malloc)(VG_AR_JITTER, emitted_code_size); |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 2680 | jumpidx = 0; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2681 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2682 | if (dis) VG_(printf)("Generated x86 code:\n"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2683 | |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 2684 | /* Generate decl VG_(dispatch_ctr) and drop into dispatch if we hit |
| 2685 | zero. We have to do this regardless of whether we're t-chaining |
| 2686 | or not. */ |
| 2687 | VG_(new_emit)(); |
| 2688 | VG_(emitB) (0xFF); /* decl */ |
| 2689 | emit_amode_litmem_reg((Addr)&VG_(dispatch_ctr), 1); |
| 2690 | if (dis) |
| 2691 | VG_(printf)("\n\t\tdecl (%p)\n", &VG_(dispatch_ctr)); |
| 2692 | VG_(emit_jcondshort_delta)(CondNZ, 5+1); |
| 2693 | VG_(emit_movv_lit_reg) ( 4, VG_TRC_INNER_COUNTERZERO, R_EBP ); |
| 2694 | emit_ret(); |
| 2695 | |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2696 | fplive = False; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2697 | for (i = 0; i < cb->used; i++) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2698 | UInstr* u = &cb->instrs[i]; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2699 | if (cb->instrs[i].opcode != NOP) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2700 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2701 | /* Check on the sanity of this insn. */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2702 | Bool sane = VG_(saneUInstr)( False, False, u ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2703 | if (!sane) { |
| 2704 | VG_(printf)("\ninsane instruction\n"); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2705 | VG_(up_UInstr)( i, u ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2706 | } |
| 2707 | vg_assert(sane); |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2708 | fplive = emitUInstr( cb, i, regs_live_before, fplive ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2709 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2710 | regs_live_before = u->regs_live_after; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2711 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2712 | if (dis) VG_(printf)("\n"); |
sewardj | 1b7d802 | 2002-11-30 12:35:42 +0000 | [diff] [blame] | 2713 | vg_assert(!fplive); /* FPU state must be saved by end of BB */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2714 | |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 2715 | if (j != NULL) { |
| 2716 | vg_assert(jumpidx <= VG_MAX_JUMPS); |
| 2717 | for(i = 0; i < jumpidx; i++) |
| 2718 | j[i] = jumps[i]; |
| 2719 | } |
| 2720 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2721 | /* Returns a pointer to the emitted code. This will have to be |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2722 | copied by the caller into the translation cache, and then freed */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2723 | *nbytes = emitted_code_used; |
| 2724 | return emitted_code; |
| 2725 | } |
| 2726 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2727 | #undef dis |
| 2728 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2729 | /*--------------------------------------------------------------------*/ |
| 2730 | /*--- end vg_from_ucode.c ---*/ |
| 2731 | /*--------------------------------------------------------------------*/ |