Alek Du | 7eac544 | 2008-06-05 17:38:56 +0800 | [diff] [blame] | 1 | /* define spi-uart debug constrains */ |
| 2 | /* code for MRST early printk */ |
| 3 | #ifndef _SPI_UART |
| 4 | #define _SPI_UART |
| 5 | |
| 6 | #include "types.h" |
| 7 | |
| 8 | typedef volatile unsigned short vu16; |
| 9 | typedef volatile unsigned int vu32; |
| 10 | |
| 11 | #define MRST_REGBASE_SPI0 0xff128000 |
| 12 | #define MRST_REGBASE_SPI1 0xff128400 |
| 13 | #define MRST_REGBASE_SPI2 0xff128800 |
| 14 | |
| 15 | struct mrst_spi_reg { |
| 16 | vu32 ctrlr0; /* control reg 0 */ |
| 17 | vu32 ctrlr1; /* control reg 1 */ |
| 18 | vu32 ssienr; /* SSI enable reg */ |
| 19 | vu32 mwcr; /* Microwire control reg */ |
| 20 | |
| 21 | vu32 ser; /* slave enable reg */ |
| 22 | vu32 baudr; |
| 23 | vu32 txftlr; |
| 24 | vu32 rxftlr; |
| 25 | |
| 26 | vu32 txflr; |
| 27 | vu32 rxflr; |
| 28 | vu32 sr; |
| 29 | vu32 imr; |
| 30 | |
| 31 | vu32 isr; |
| 32 | vu32 risr; |
| 33 | vu32 txoicr; |
| 34 | vu32 rxoicr; |
| 35 | |
| 36 | vu32 rxuicr; |
| 37 | vu32 msticr; |
| 38 | vu32 icr; |
| 39 | vu32 dmacr; |
| 40 | |
| 41 | vu32 dmatdlr; |
| 42 | vu32 dmardlr; |
| 43 | vu32 idr; |
| 44 | vu32 ssi_comp_version; |
| 45 | |
| 46 | vu32 dr[16]; /* 16 bits access for each 32bit space */ |
| 47 | }; |
| 48 | |
| 49 | /* bit fields in CTRLR0 */ |
| 50 | #define SPI_DFS_OFFSET 0 |
| 51 | #define SPI_FRF_OFFSET 4 |
| 52 | #define FRF_SPI 0x0 |
| 53 | #define FRF_SSP 0x1 |
| 54 | #define FRF_MICROWIRE 0x2 |
| 55 | #define FRF_RESV 0x3 |
| 56 | #define SPI_SCPH_OFFSET 6 |
| 57 | #define SPI_SCOL_OFFSET 7 |
| 58 | #define SPI_TMOD_OFFSET 8 |
| 59 | #define TMOD_TR 0x0 /* xmit & recv */ |
| 60 | #define TMOD_TO 0x1 /* xmit only */ |
| 61 | #define TMOD_RO 0x2 /* recv only */ |
| 62 | #define TMOD_EPROMREAD 0x3 /* eeprom read mode */ |
| 63 | |
| 64 | #define SPI_SLVOE_OFFSET 10 |
| 65 | #define SPI_SRL_OFFSET 11 |
| 66 | #define SPI_CFS_OFFSET 12 |
| 67 | |
| 68 | /* bit fields in SR, 7 bits */ |
| 69 | #define SR_MASK 0x7f /* cover 7 bits */ |
| 70 | #define SR_BUSY (1 << 0) |
| 71 | #define SR_TF_NOT_FULL (1 << 1) |
| 72 | #define SR_TF_EMPT (1 << 2) |
| 73 | #define SR_RF_NOT_EMPT (1 << 3) |
| 74 | #define SR_RF_FULL (1 << 4) |
| 75 | #define SR_TX_ERR (1 << 5) |
| 76 | #define SR_DCOL (1 << 6) |
| 77 | |
| 78 | /* bit fields in ISR, IMR, RISR, 7 bits */ |
| 79 | #define SPI_INT_TXEI (1 << 0) |
| 80 | #define SPI_INT_TXOI (1 << 1) |
| 81 | #define SPI_INT_RXUI (1 << 2) |
| 82 | #define SPI_INT_RXOI (1 << 3) |
| 83 | #define SPI_INT_RXFI (1 << 4) |
| 84 | #define SPI_INT_MSTI (1 << 5) |
| 85 | |
| 86 | extern void bs_spi_printk(const char *str); |
| 87 | |
| 88 | #endif |