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Alek Du7eac5442008-06-05 17:38:56 +08001/*
2 * spi-uart debug routings
3 * Copyright (C) 2008, Feng Tang <feng.tang@intel.com> Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 */
19
20#include "spi-uart.h"
Alek Dua8cef7f2009-06-04 15:02:03 +080021#include "bootstub.h"
Alek Du7eac5442008-06-05 17:38:56 +080022
23#define MRST_SPI_TIMEOUT 0x200000
Alek Duc8496d12008-07-10 14:46:17 +080024static int spi_inited = 0;
Eric Ernstaecaba32013-04-02 12:02:59 -070025int no_uart_used = 0;
Alek Dua8cef7f2009-06-04 15:02:03 +080026static volatile struct mrst_spi_reg *pspi = 0;
Alek Du7eac5442008-06-05 17:38:56 +080027
28static void spi_init()
29{
30 u32 ctrlr0;
Jacob Pan438855b2009-08-20 12:37:15 -070031 u32 *clk_reg, clk_cdiv;
Alek Du7eac5442008-06-05 17:38:56 +080032
Alek Dua8cef7f2009-06-04 15:02:03 +080033 switch (*(int *)SPI_TYPE) {
Eric Ernstaecaba32013-04-02 12:02:59 -070034 case SPI_1:
35 if (mid_identify_cpu() == MID_CPU_CHIP_CLOVERVIEW)
Leonard Mai4c56e452011-10-06 12:27:46 -070036 pspi = (struct mrst_spi_reg *)CTP_REGBASE_SPI1;
37 else
38 pspi = (struct mrst_spi_reg *)MRST_REGBASE_SPI1;
Alek Dua8cef7f2009-06-04 15:02:03 +080039 break;
Eric Ernstaecaba32013-04-02 12:02:59 -070040
41 case SPI_0:
Alek Dua8cef7f2009-06-04 15:02:03 +080042 default:
Eric Ernstaecaba32013-04-02 12:02:59 -070043 if (mid_identify_cpu() == MID_CPU_CHIP_CLOVERVIEW)
Leonard Mai4c56e452011-10-06 12:27:46 -070044 pspi = (struct mrst_spi_reg *)CTP_REGBASE_SPI0;
45 else
46 pspi = (struct mrst_spi_reg *)MRST_REGBASE_SPI0;
Alek Dua8cef7f2009-06-04 15:02:03 +080047 }
Eric Ernstaecaba32013-04-02 12:02:59 -070048
Alek Du7eac5442008-06-05 17:38:56 +080049 /* disable SPI controller first */
50 pspi->ssienr = 0x0;
51
52 /* set control param, 16 bits, transmit only mode */
53 ctrlr0 = pspi->ctrlr0;
54
55 ctrlr0 &= 0xfcc0;
56 ctrlr0 |= (0xf | (FRF_SPI << SPI_FRF_OFFSET)
57 | (TMOD_TO << SPI_TMOD_OFFSET));
58 pspi->ctrlr0 = ctrlr0;
59
60 /* set a default baud rate, 115200 */
Jacob Pan438855b2009-08-20 12:37:15 -070061 /* get SPI controller operating freq info */
62 clk_reg = (u32 *)MRST_CLK_SPI0_REG;
63 clk_cdiv = ((*clk_reg) & CLK_SPI_CDIV_MASK) >> CLK_SPI_CDIV_OFFSET;
64 pspi->baudr = MRST_SPI_CLK_BASE / (clk_cdiv + 1) / 115200;
Alek Du7eac5442008-06-05 17:38:56 +080065
Alek Du7eac5442008-06-05 17:38:56 +080066 /* disable all INT for early phase */
67 pspi->imr &= 0xffffff00;
68
69 /* select one slave SPI device */
Alek Du3f5527f2008-06-17 14:08:35 +080070 pspi->ser = 0x2;
Alek Du7eac5442008-06-05 17:38:56 +080071
72 /* enable the HW, this should be the last step for HW init */
73 pspi->ssienr |= 0x1;
74
75 spi_inited = 1;
Eric Ernstaecaba32013-04-02 12:02:59 -070076
Alek Du7eac5442008-06-05 17:38:56 +080077}
78
79/* set the ratio rate, INT */
80static void max3110_write_config(void)
81{
82 u16 config;
83
84 /* 115200, TM not set, no parity, 8bit word */
Alek Dub7b30002008-08-21 09:49:20 +080085 config = 0xc001;
Alek Du7eac5442008-06-05 17:38:56 +080086 pspi->dr[0] = config;
87}
88
89/* transfer char to a eligibal word and send to max3110 */
Alek Duc8496d12008-07-10 14:46:17 +080090static void max3110_write_data(char c)
Alek Du7eac5442008-06-05 17:38:56 +080091{
92 u16 data;
Alek Du7eac5442008-06-05 17:38:56 +080093
94 data = 0x8000 | c;
95 pspi->dr[0] = data;
Alek Du7eac5442008-06-05 17:38:56 +080096}
97
98/* slave select should be called in the read/write function */
99static int spi_max3110_putc(char c)
100{
101 unsigned int timeout;
102 u32 sr;
Alek Du7eac5442008-06-05 17:38:56 +0800103
104 timeout = MRST_SPI_TIMEOUT;
Alek Dua24ea5c2009-05-26 09:56:47 +0800105 /* early putc need make sure the TX FIFO is not full*/
Alek Du7eac5442008-06-05 17:38:56 +0800106 while (timeout--) {
107 sr = pspi->sr;
Alek Dua8cef7f2009-06-04 15:02:03 +0800108 if (!(sr & SR_TF_NOT_FULL))
Alek Du7eac5442008-06-05 17:38:56 +0800109 continue;
110 else
111 break;
112 }
113
114 if (timeout == 0xffffffff)
115 return -1;
116
117 max3110_write_data(c);
118
119 return 0;
120}
121
Alek Du7eac5442008-06-05 17:38:56 +0800122void bs_spi_printk(const char *str)
123{
Eric Ernstaecaba32013-04-02 12:02:59 -0700124 if ( no_uart_used )
125 return;
126
Alek Dua8cef7f2009-06-04 15:02:03 +0800127 if (!spi_inited) {
Alek Du7eac5442008-06-05 17:38:56 +0800128 spi_init();
Alek Dua8cef7f2009-06-04 15:02:03 +0800129 max3110_write_config();
130 }
Alek Du7eac5442008-06-05 17:38:56 +0800131
132 if (!str)
133 return;
134
Alek Du7eac5442008-06-05 17:38:56 +0800135 while (*str) {
136 if (*str == '\n')
137 spi_max3110_putc('\r');
138 spi_max3110_putc(*str++);
139 }
140}