The Android Open Source Project | dd7bc33 | 2009-03-03 19:32:55 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2007 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #ifndef ANDROID_CUTILS_ATOMIC_H |
| 18 | #define ANDROID_CUTILS_ATOMIC_H |
| 19 | |
| 20 | #include <stdint.h> |
| 21 | #include <sys/types.h> |
| 22 | |
| 23 | #ifdef __cplusplus |
| 24 | extern "C" { |
| 25 | #endif |
| 26 | |
| 27 | /* |
Andy McFadden | 8dfa47d | 2010-05-27 10:10:18 -0700 | [diff] [blame^] | 28 | * A handful of basic atomic operations. The appropriate pthread |
| 29 | * functions should be used instead of these whenever possible. |
| 30 | * |
| 31 | * The "acquire" and "release" terms can be defined intuitively in terms |
| 32 | * of the placement of memory barriers in a simple lock implementation: |
| 33 | * - wait until compare-and-swap(lock-is-free --> lock-is-held) succeeds |
| 34 | * - barrier |
| 35 | * - [do work] |
| 36 | * - barrier |
| 37 | * - store(lock-is-free) |
| 38 | * In very crude terms, the initial (acquire) barrier prevents any of the |
| 39 | * "work" from happening before the lock is held, and the later (release) |
| 40 | * barrier ensures that all of the work happens before the lock is released. |
| 41 | * (Think of cached writes, cache read-ahead, and instruction reordering |
| 42 | * around the CAS and store instructions.) |
| 43 | * |
| 44 | * The barriers must apply to both the compiler and the CPU. Note it is |
| 45 | * legal for instructions that occur before an "acquire" barrier to be |
| 46 | * moved down below it, and for instructions that occur after a "release" |
| 47 | * barrier to be moved up above it. |
| 48 | * |
| 49 | * The ARM-driven implementation we use here is short on subtlety, |
| 50 | * and actually requests a full barrier from the compiler and the CPU. |
| 51 | * The only difference between acquire and release is in whether they |
| 52 | * are issued before or after the atomic operation with which they |
| 53 | * are associated. To ease the transition to C/C++ atomic intrinsics, |
| 54 | * you should not rely on this, and instead assume that only the minimal |
| 55 | * acquire/release protection is provided. |
| 56 | * |
| 57 | * NOTE: all int32_t* values are expected to be aligned on 32-bit boundaries. |
| 58 | * If they are not, atomicity is not guaranteed. |
The Android Open Source Project | dd7bc33 | 2009-03-03 19:32:55 -0800 | [diff] [blame] | 59 | */ |
| 60 | |
The Android Open Source Project | dd7bc33 | 2009-03-03 19:32:55 -0800 | [diff] [blame] | 61 | /* |
Andy McFadden | 8dfa47d | 2010-05-27 10:10:18 -0700 | [diff] [blame^] | 62 | * Basic arithmetic and bitwise operations. These all provide a |
| 63 | * barrier with "release" ordering, and return the previous value. |
| 64 | * |
| 65 | * These have the same characteristics (e.g. what happens on overflow) |
| 66 | * as the equivalent non-atomic C operations. |
The Android Open Source Project | dd7bc33 | 2009-03-03 19:32:55 -0800 | [diff] [blame] | 67 | */ |
The Android Open Source Project | dd7bc33 | 2009-03-03 19:32:55 -0800 | [diff] [blame] | 68 | int32_t android_atomic_inc(volatile int32_t* addr); |
| 69 | int32_t android_atomic_dec(volatile int32_t* addr); |
The Android Open Source Project | dd7bc33 | 2009-03-03 19:32:55 -0800 | [diff] [blame] | 70 | int32_t android_atomic_add(int32_t value, volatile int32_t* addr); |
| 71 | int32_t android_atomic_and(int32_t value, volatile int32_t* addr); |
| 72 | int32_t android_atomic_or(int32_t value, volatile int32_t* addr); |
| 73 | |
The Android Open Source Project | dd7bc33 | 2009-03-03 19:32:55 -0800 | [diff] [blame] | 74 | /* |
Andy McFadden | 8dfa47d | 2010-05-27 10:10:18 -0700 | [diff] [blame^] | 75 | * Perform an atomic load with "acquire" or "release" ordering. |
Andy McFadden | ac322da | 2010-05-19 22:33:28 -0700 | [diff] [blame] | 76 | * |
Andy McFadden | 8dfa47d | 2010-05-27 10:10:18 -0700 | [diff] [blame^] | 77 | * This is only necessary if you need the memory barrier. A 32-bit read |
| 78 | * from a 32-bit aligned address is atomic on all supported platforms. |
The Android Open Source Project | dd7bc33 | 2009-03-03 19:32:55 -0800 | [diff] [blame] | 79 | */ |
Andy McFadden | 8dfa47d | 2010-05-27 10:10:18 -0700 | [diff] [blame^] | 80 | int32_t android_atomic_acquire_load(volatile int32_t* addr); |
| 81 | int32_t android_atomic_release_load(volatile int32_t* addr); |
| 82 | |
| 83 | /* |
| 84 | * Perform an atomic store with "acquire" or "release" ordering. |
| 85 | * |
| 86 | * This is only necessary if you need the memory barrier. A 32-bit write |
| 87 | * to a 32-bit aligned address is atomic on all supported platforms. |
| 88 | */ |
| 89 | void android_atomic_acquire_store(int32_t value, volatile int32_t* addr); |
| 90 | void android_atomic_release_store(int32_t value, volatile int32_t* addr); |
| 91 | |
| 92 | /* |
| 93 | * Unconditional swap operation with "acquire" or "release" ordering. |
| 94 | * |
| 95 | * Stores the new value at *addr, and returns the previous value. |
| 96 | */ |
| 97 | int32_t android_atomic_acquire_swap(int32_t value, volatile int32_t* addr); |
| 98 | int32_t android_atomic_release_swap(int32_t value, volatile int32_t* addr); |
| 99 | |
| 100 | /* |
| 101 | * Compare-and-set operation with "acquire" or "release" ordering. |
| 102 | * |
| 103 | * This returns zero if the new value was successfully stored, which will |
| 104 | * only happen when *addr == oldvalue. |
| 105 | * |
| 106 | * (The return value is inverted from implementations on other platforms, |
| 107 | * but matches the ARM ldrex/strex result.) |
| 108 | * |
| 109 | * Implementations that use the release CAS in a loop may be less efficient |
| 110 | * than possible, because we re-issue the memory barrier on each iteration. |
| 111 | */ |
| 112 | int android_atomic_acquire_cas(int32_t oldvalue, int32_t newvalue, |
| 113 | volatile int32_t* addr); |
| 114 | int android_atomic_release_cas(int32_t oldvalue, int32_t newvalue, |
The Android Open Source Project | dd7bc33 | 2009-03-03 19:32:55 -0800 | [diff] [blame] | 115 | volatile int32_t* addr); |
| 116 | |
Andy McFadden | ac322da | 2010-05-19 22:33:28 -0700 | [diff] [blame] | 117 | /* |
Andy McFadden | 8dfa47d | 2010-05-27 10:10:18 -0700 | [diff] [blame^] | 118 | * Aliases for code using an older version of this header. These are now |
| 119 | * deprecated and should not be used. The definitions will be removed |
| 120 | * in a future release. |
Andy McFadden | ac322da | 2010-05-19 22:33:28 -0700 | [diff] [blame] | 121 | */ |
Andy McFadden | 8dfa47d | 2010-05-27 10:10:18 -0700 | [diff] [blame^] | 122 | #define android_atomic_write android_atomic_release_store |
| 123 | #define android_atomic_cmpxchg android_atomic_release_cas |
The Android Open Source Project | dd7bc33 | 2009-03-03 19:32:55 -0800 | [diff] [blame] | 124 | |
The Android Open Source Project | dd7bc33 | 2009-03-03 19:32:55 -0800 | [diff] [blame] | 125 | #ifdef __cplusplus |
| 126 | } // extern "C" |
| 127 | #endif |
| 128 | |
| 129 | #endif // ANDROID_CUTILS_ATOMIC_H |