Merge "platform: msm8952: add support for display clocks for 8956"
diff --git a/platform/msm8952/include/platform/clock.h b/platform/msm8952/include/platform/clock.h
index 6cda324..495914d 100644
--- a/platform/msm8952/include/platform/clock.h
+++ b/platform/msm8952/include/platform/clock.h
@@ -65,6 +65,19 @@
#define DSI_PIXEL0_N REG_MM(0x4D00C)
#define DSI_PIXEL0_D REG_MM(0x4D010)
+#define DSI_BYTE1_CMD_RCGR REG_MM(0x4D0B0)
+#define DSI_BYTE1_CFG_RCGR REG_MM(0x4D0B4)
+#define DSI_BYTE1_CBCR REG_MM(0x4D0A0)
+#define DSI_ESC1_CMD_RCGR REG_MM(0x4D0A8)
+#define DSI_ESC1_CFG_RCGR REG_MM(0x4D0AC)
+#define DSI_ESC1_CBCR REG_MM(0x4D09C)
+#define DSI_PIXEL1_CMD_RCGR REG_MM(0x4D0B8)
+#define DSI_PIXEL1_CFG_RCGR REG_MM(0x4D0BC)
+#define DSI_PIXEL1_CBCR REG_MM(0x4D0A4)
+#define DSI_PIXEL1_M REG_MM(0x4D0C0)
+#define DSI_PIXEL1_N REG_MM(0x4D0C4)
+#define DSI_PIXEL1_D REG_MM(0x4D0C8)
+
void platform_clock_init(void);
void clock_init_mmc(uint32_t interface);
diff --git a/platform/msm8952/include/platform/iomap.h b/platform/msm8952/include/platform/iomap.h
index f57deed..68b8227 100644
--- a/platform/msm8952/include/platform/iomap.h
+++ b/platform/msm8952/include/platform/iomap.h
@@ -99,6 +99,7 @@
#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x45004)
#define GPLL4_MODE (CLK_CTL_BASE + 0x24000)
#define GPLL4_STATUS (CLK_CTL_BASE + 0x24024)
+#define GPLL6_STATUS (CLK_CTL_BASE + 0x3701C)
/* SDCC */
#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x10A000)
diff --git a/platform/msm8952/msm8952-clock.c b/platform/msm8952/msm8952-clock.c
index fd1d6f7..b87406d 100644
--- a/platform/msm8952/msm8952-clock.c
+++ b/platform/msm8952/msm8952-clock.c
@@ -41,7 +41,8 @@
#define gpll0_source_val 1
#define gpll4_source_val 2
#define cxo_mm_source_val 0
-#define gpll0_mm_source_val 1
+#define gpll0_mm_source_val 6
+#define gpll6_mm_source_val 3
struct clk_freq_tbl rcg_dummy_freq = F_END;
@@ -126,6 +127,21 @@
},
};
+static struct pll_vote_clk gpll6_clk_src =
+{
+ .en_reg = (void *) APCS_GPLL_ENA_VOTE,
+ .en_mask = BIT(7),
+ .status_reg = (void *) GPLL6_STATUS,
+ .status_mask = BIT(17),
+ .parent = &cxo_clk_src.c,
+
+ .c = {
+ .rate = 1080000000,
+ .dbg_name = "gpll6_clk_src",
+ .ops = &clk_ops_pll_vote,
+ },
+};
+
/* SDCC Clocks */
static struct clk_freq_tbl ftbl_gcc_sdcc1_apps_clk[] =
{
@@ -346,11 +362,30 @@
F_END
};
+static struct clk_freq_tbl ftbl_mdss_esc1_1_clk[] = {
+ F_MM(19200000, cxo, 1, 0, 0),
+ F_END
+};
+
static struct clk_freq_tbl ftbl_mdp_clk[] = {
- F_MM( 80000000, gpll0, 10, 0, 0),
- F_MM( 100000000, gpll0, 8, 0, 0),
- F_MM( 200000000, gpll0, 4, 0, 0),
- F_MM( 320000000, gpll0, 2.5, 0, 0),
+ F( 80000000, gpll0, 10, 0, 0),
+ F( 100000000, gpll0, 8, 0, 0),
+ F( 200000000, gpll0, 4, 0, 0),
+ F( 320000000, gpll0, 2.5, 0, 0),
+ F_END
+};
+
+static struct clk_freq_tbl ftbl_mdp_clk_8956[] = {
+ F_MM( 50000000, gpll0, 16, 0, 0),
+ F_MM( 80000000, gpll0, 10, 0, 0),
+ F_MM( 100000000, gpll0, 8, 0, 0),
+ F_MM( 145454545, gpll0, 5.5, 0, 0),
+ F_MM( 160000000, gpll0, 5, 0, 0),
+ F_MM( 177777778, gpll0, 4.5, 0, 0),
+ F_MM( 200000000, gpll0, 4, 0, 0),
+ F_MM( 270000000, gpll6, 4, 0, 0),
+ F_MM( 320000000, gpll0, 2.5, 0, 0),
+ F_MM( 360000000, gpll6, 3, 0, 0),
F_END
};
@@ -366,6 +401,18 @@
},
};
+static struct rcg_clk dsi_esc1_clk_src = {
+ .cmd_reg = (uint32_t *) DSI_ESC1_CMD_RCGR,
+ .cfg_reg = (uint32_t *) DSI_ESC1_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_mdss_esc1_1_clk,
+
+ .c = {
+ .dbg_name = "dsi_esc1_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
static struct clk_freq_tbl ftbl_mdss_vsync_clk[] = {
F_MM(19200000, cxo, 1, 0, 0),
F_END
@@ -394,6 +441,17 @@
},
};
+static struct branch_clk mdss_esc1_clk = {
+ .cbcr_reg = (uint32_t *) DSI_ESC1_CBCR,
+ .parent = &dsi_esc1_clk_src.c,
+ .has_sibling = 0,
+
+ .c = {
+ .dbg_name = "mdss_esc1_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
static struct branch_clk mdss_axi_clk = {
.cbcr_reg = (uint32_t *) MDP_AXI_CBCR,
.has_sibling = 1,
@@ -517,6 +575,7 @@
CLK_LOOKUP("mdp_ahb_clk", mdp_ahb_clk.c),
CLK_LOOKUP("mdss_esc0_clk", mdss_esc0_clk.c),
+ CLK_LOOKUP("mdss_esc1_clk", mdss_esc1_clk.c),
CLK_LOOKUP("mdss_axi_clk", mdss_axi_clk.c),
CLK_LOOKUP("mdss_vsync_clk", mdss_vsync_clk.c),
CLK_LOOKUP("mdss_mdp_clk_src", mdss_mdp_clk_src.c),
@@ -532,6 +591,7 @@
{
gpll4_clk_src.status_reg = (void *)GPLL4_STATUS;
gpll4_clk_src.status_mask = BIT(17);
+ mdss_mdp_clk_src.freq_tbl = ftbl_mdp_clk_8956;
}
void platform_clock_init(void)