Merge "[msm_shared/mmc] Add persist partition in mmc partition table."
diff --git a/platform/msm7x30/acpuclock.c b/platform/msm7x30/acpuclock.c
index 9ee7b2e..1237a48 100644
--- a/platform/msm7x30/acpuclock.c
+++ b/platform/msm7x30/acpuclock.c
@@ -31,18 +31,14 @@
#include <platform/iomap.h>
#include <reg.h>
-/* 7x30 clock control and source registers */
-#define SCSS_CLK_CTL 0xC0101004
-#define SCSS_CLK_SEL 0xC0101008
-#define MSM_CLK_CTL_SH2_BASE 0xABA01000
-#define MSM_CLK_CTL_BASE 0xAB800000
-
#define REG_BASE(off) (MSM_CLK_CTL_BASE + (off))
#define REG(off) (MSM_CLK_CTL_SH2_BASE + (off))
#define PLL_ENA_REG REG(0x0264)
#define PLL2_STATUS_BASE_REG REG_BASE(0x0350)
+#define SH2_OWN_ROW2_BASE_REG REG_BASE(0x0424)
+
#define ACPU_SRC_SEL_PLL2 3
#define ACPU_SRC_DIV_PLL2 0
@@ -79,3 +75,46 @@
/* Program clock source selection. */
writel(reg_clksel, SCSS_CLK_SEL);
}
+
+void hsusb_clock_init(void)
+{
+ int val = 0;
+ unsigned sh2_own_row2;
+ unsigned sh2_own_row2_hsusb_mask = (1 << 11);
+
+ sh2_own_row2 = readl(SH2_OWN_ROW2_BASE_REG);
+ if(sh2_own_row2 & sh2_own_row2_hsusb_mask)
+ {
+ /* USB local clock control enabled */
+ /* Set value in MD register */
+ val = 0x5DF;
+ writel(val, SH2_USBH_MD_REG);
+
+ /* Set value in NS register */
+ val = 1 << 8;
+ val = val | readl(SH2_USBH_NS_REG);
+ writel(val, SH2_USBH_NS_REG);
+
+ val = 1 << 11;
+ val = val | readl(SH2_USBH_NS_REG);
+ writel(val, SH2_USBH_NS_REG);
+
+ val = 1 << 9;
+ val = val | readl(SH2_USBH_NS_REG);
+ writel(val, SH2_USBH_NS_REG);
+
+ val = 1 << 13;
+ val = val | readl(SH2_USBH_NS_REG);
+ writel(val, SH2_USBH_NS_REG);
+
+ /* Enable USBH_P_CLK */
+ val = 1 << 25;
+ val = val | readl(SH2_GLBL_CLK_ENA_SC);
+ writel(val, SH2_GLBL_CLK_ENA_SC);
+ }
+ else
+ {
+ /* USB local clock control not enabled; use proc comm */
+ usb_clock_init();
+ }
+}
diff --git a/platform/msm7x30/include/platform/iomap.h b/platform/msm7x30/include/platform/iomap.h
index 789d5d7..6abac3f 100644
--- a/platform/msm7x30/include/platform/iomap.h
+++ b/platform/msm7x30/include/platform/iomap.h
@@ -50,4 +50,14 @@
#define MSM_SHARED_BASE 0x00100000
+#define MSM_CLK_CTL_BASE 0xAB800000
+#define MSM_CLK_CTL_SH2_BASE 0xABA01000
+#define SCSS_CLK_CTL 0xC0101004
+#define SCSS_CLK_SEL 0xC0101008
+
+#define MSM_USB_BASE 0xA3600000
+#define SH2_USBH_MD_REG 0xABA012BC
+#define SH2_USBH_NS_REG 0xABA012C0
+#define SH2_GLBL_CLK_ENA_SC 0xABA013BC
+
#endif
diff --git a/platform/msm8x60/acpuclock.c b/platform/msm8x60/acpuclock.c
index cfe1be8..fbf0c58 100755
--- a/platform/msm8x60/acpuclock.c
+++ b/platform/msm8x60/acpuclock.c
@@ -35,3 +35,48 @@
void acpu_clock_init (void)
{
}
+
+void hsusb_clock_init(void)
+{
+ int val;
+ /* Vote for PLL8 */
+ val = readl(0x009034C0);
+ val |= (1<<8);
+ writel(val, 0x009034C0);
+ /* Wait until PLL is enabled. */
+ while (!(readl(0x00903158) & (1<<16)));
+
+ //Set 7th bit in NS Register
+ val = 1 << 7;
+ writel(val, USB_HS1_XVCR_FS_CLK_NS);
+
+ //Set rate specific value in MD
+ writel(0x000500DF, USB_HS1_XVCR_FS_CLK_MD);
+
+ //Set value in NS register
+ val = 1 << 7;
+ val |= 0x00E400C3;
+ writel(val, USB_HS1_XVCR_FS_CLK_NS);
+
+ // Clear 7th bit
+ val = 1 << 7;
+ val = ~val;
+ val = val & readl(USB_HS1_XVCR_FS_CLK_NS);
+ writel(val, USB_HS1_XVCR_FS_CLK_NS);
+
+ //set 11th bit
+ val = 1 << 11;
+ val |= readl(USB_HS1_XVCR_FS_CLK_NS);
+ writel(val, USB_HS1_XVCR_FS_CLK_NS);
+
+ //set 9th bit
+ val = 1 << 9;
+ val |= readl(USB_HS1_XVCR_FS_CLK_NS);
+ writel(val, USB_HS1_XVCR_FS_CLK_NS);
+
+ //set 8th bit
+ val = 1 << 8;
+ val |= readl(USB_HS1_XVCR_FS_CLK_NS);
+ writel(val, USB_HS1_XVCR_FS_CLK_NS);
+}
+
diff --git a/platform/msm8x60/include/platform/iomap.h b/platform/msm8x60/include/platform/iomap.h
index 5f7bda8..e53f24f 100755
--- a/platform/msm8x60/include/platform/iomap.h
+++ b/platform/msm8x60/include/platform/iomap.h
@@ -86,4 +86,9 @@
#define EBI2_CHIP_SELECT_CFG0 0x1A100000
#define EBI2_XMEM_CS3_CFG1 0x1A110034
+
+#define MSM_USB_BASE 0x12500000
+#define USB_HS1_XVCR_FS_CLK_MD 0x00902908
+#define USB_HS1_XVCR_FS_CLK_NS 0x0090290C
+
#endif
diff --git a/platform/msm_shared/hsusb.c b/platform/msm_shared/hsusb.c
index 88e4eae..bdd8e2e 100644
--- a/platform/msm_shared/hsusb.c
+++ b/platform/msm_shared/hsusb.c
@@ -113,7 +113,10 @@
/* end of common code */
-void hsusb_clock_init(void);
+__WEAK void hsusb_clock_init(void)
+{
+ return 0;
+}
#if 1
#define DBG(x...) do {} while(0)
@@ -518,95 +521,6 @@
writel(0x81000000, USB_PORTSC);
return 0;
}
-#define USB_HS1_XVCR_FS_CLK_MD 0x00902908
-#define USB_HS1_XVCR_FS_CLK_NS 0x0090290C
-
-void hsusb_8x60_clock_init(void)
-{
- int val;
- /* Vote for PLL8 */
- val = readl(0x009034C0);
- val |= (1<<8);
- writel(val, 0x009034C0);
- /* Wait until PLL is enabled. */
- while (!(readl(0x00903158) & (1<<16)));
-
- //Set 7th bit in NS Register
- val = 1 << 7;
- writel(val, USB_HS1_XVCR_FS_CLK_NS);
-
- //Set rate specific value in MD
- writel(0x000500DF, USB_HS1_XVCR_FS_CLK_MD);
-
- //Set value in NS register
- val = 1 << 7;
- val |= 0x00E400C3;
- writel(val, USB_HS1_XVCR_FS_CLK_NS);
-
- // Clear 7th bit
- val = 1 << 7;
- val = ~val;
- val = val & readl(USB_HS1_XVCR_FS_CLK_NS);
- writel(val, USB_HS1_XVCR_FS_CLK_NS);
-
- //set 11th bit
- val = 1 << 11;
- val |= readl(USB_HS1_XVCR_FS_CLK_NS);
- writel(val, USB_HS1_XVCR_FS_CLK_NS);
-
- //set 9th bit
- val = 1 << 9;
- val |= readl(USB_HS1_XVCR_FS_CLK_NS);
- writel(val, USB_HS1_XVCR_FS_CLK_NS);
-
- //set 8th bit
- val = 1 << 8;
- val |= readl(USB_HS1_XVCR_FS_CLK_NS);
- writel(val, USB_HS1_XVCR_FS_CLK_NS);
-}
-
-void hsusb_7x30_clock_init(void)
-{
- int val = 0;
-
- /* Enable USBH_P_CLK */
- val = 1 << 25;
- val = val | readl(SH2_GLBL_CLK_ENA_SC);
- writel(val, SH2_GLBL_CLK_ENA_SC);
-
- /* Set value in MD register */
- val = 0x5DF;
- writel(val, SH2_USBH_MD_REG);
-
- /* Set value in NS register */
- val = 1 << 8;
- val = val | readl(SH2_USBH_NS_REG);
- writel(val, SH2_USBH_NS_REG);
-
- val = 1 << 11;
- val = val | readl(SH2_USBH_NS_REG);
- writel(val, SH2_USBH_NS_REG);
-
- val = 1 << 9;
- val = val | readl(SH2_USBH_NS_REG);
- writel(val, SH2_USBH_NS_REG);
-
- val = 1 << 13;
- val = val | readl(SH2_USBH_NS_REG);
- writel(val, SH2_USBH_NS_REG);
-}
-
-void hsusb_clock_init(void)
-{
- // Enable usb clocks from apps processor for 7x30.
- // USB clocks already initialized for other targets
- // so skipping proc comm call to enable usb clocks.
-#ifdef PLATFORM_MSM7X30
- hsusb_7x30_clock_init();
-#elif PLATFORM_MSM8X60
- hsusb_8x60_clock_init();
-#endif
-}
void board_usb_init(void);
void board_ulpi_init(void);
diff --git a/platform/msm_shared/hsusb.h b/platform/msm_shared/hsusb.h
index 791d87b..23cf7ce 100644
--- a/platform/msm_shared/hsusb.h
+++ b/platform/msm_shared/hsusb.h
@@ -31,11 +31,7 @@
#ifndef _MSM7200_USB_H_
#define _MSM7200_USB_H_
-#ifdef PLATFORM_MSM7X30
-#define MSM_USB_BASE 0xA3600000
-#elif PLATFORM_MSM8X60
-#define MSM_USB_BASE 0x12500000
-#else
+#ifndef MSM_USB_BASE
#define MSM_USB_BASE 0xA0800000
#endif
@@ -172,10 +168,6 @@
#define ULPI_ADDR(n) (((n) & 255) << 16)
#define ULPI_DATA(n) ((n) & 255)
#define ULPI_DATA_READ(n) (((n) >> 8) & 255)
-/* For 7x30 */
-#define SH2_USBH_MD_REG (0xABA012BC)
-#define SH2_USBH_NS_REG (0xABA012C0)
-#define SH2_GLBL_CLK_ENA_SC (0xABA013BC)
/* for USB charging */
#define TRUE 1
diff --git a/platform/msm_shared/proc_comm.c b/platform/msm_shared/proc_comm.c
index 45ced64..d341346 100644
--- a/platform/msm_shared/proc_comm.c
+++ b/platform/msm_shared/proc_comm.c
@@ -223,6 +223,12 @@
}
}
+void usb_clock_init()
+{
+ clock_enable(USB_HS_PCLK);
+ clock_enable(USB_HS_CLK);
+}
+
void lcdc_clock_init(unsigned rate)
{
clock_set_rate(MDP_LCDC_PCLK_CLK, rate);