Merge "target: msm8226: Update framebuffer address as per the new memory map"
diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
index e1a4274..2f8aff1 100644
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -33,7 +33,6 @@
#include <app.h>
#include <debug.h>
#include <arch/arm.h>
-#include <dev/udc.h>
#include <string.h>
#include <stdlib.h>
#include <kernel/thread.h>
@@ -70,8 +69,6 @@
#include "scm.h"
extern bool target_use_signed_kernel(void);
-extern void dsb();
-extern void isb();
extern void platform_uninit(void);
extern void target_uninit(void);
@@ -122,15 +119,7 @@
/* Assuming unauthorized kernel image by default */
static int auth_kernel_img = 0;
-static device_info device = {DEVICE_MAGIC, 0, 0};
-
-static struct udc_device surf_udc_device = {
- .vendor_id = 0x18d1,
- .product_id = 0xD00D,
- .version_id = 0x0100,
- .manufacturer = "Google",
- .product = "Android",
-};
+static device_info device = {DEVICE_MAGIC, 0, 0, 0};
struct atag_ptbl_entry
{
@@ -164,6 +153,7 @@
};
char max_download_size[MAX_RSP_SIZE];
+char charger_screen_enabled[MAX_RSP_SIZE];
char sn_buf[13];
extern int emmc_recovery_init(void);
@@ -222,7 +212,8 @@
cmdline_len += strlen(ffbm_mode_string);
/* reduce kernel console messages to speed-up boot */
cmdline_len += strlen(loglevel);
- } else if (target_pause_for_battery_charge()) {
+ } else if (device.charger_screen_enabled &&
+ target_pause_for_battery_charge()) {
pause_at_bootup = 1;
cmdline_len += strlen(battchg_pause);
}
@@ -696,7 +687,7 @@
device.is_unlocked,
device.is_tampered);
- if(target_use_signed_kernel() && (!device.is_unlocked) && (!device.is_tampered))
+ if(target_use_signed_kernel() && (!device.is_unlocked))
{
offset = 0;
@@ -706,7 +697,7 @@
dt_actual = ROUND_TO_PAGE(hdr->dt_size, page_mask);
imagesize_actual = (page_size + kernel_actual + ramdisk_actual + dt_actual);
- if (check_aboot_addr_range_overlap(hdr->tags_addr, hdr->dt_size))
+ if (check_aboot_addr_range_overlap(hdr->tags_addr, dt_actual))
{
dprintf(CRITICAL, "Device tree addresses overlap with aboot addresses.\n");
return -1;
@@ -719,6 +710,12 @@
dprintf(INFO, "Loading boot image (%d): start\n", imagesize_actual);
bs_set_timestamp(BS_KERNEL_LOAD_START);
+ if (check_aboot_addr_range_overlap(image_addr, imagesize_actual))
+ {
+ dprintf(CRITICAL, "Boot image buffer address overlaps with aboot addresses.\n");
+ return -1;
+ }
+
/* Read image without signature */
if (mmc_read(ptn + offset, (void *)image_addr, imagesize_actual))
{
@@ -730,6 +727,13 @@
bs_set_timestamp(BS_KERNEL_LOAD_DONE);
offset = imagesize_actual;
+
+ if (check_aboot_addr_range_overlap(image_addr + offset, page_size))
+ {
+ dprintf(CRITICAL, "Signature read buffer address overlaps with aboot addresses.\n");
+ return -1;
+ }
+
/* Read signature */
if(mmc_read(ptn + offset, (void *)(image_addr + offset), page_size))
{
@@ -878,6 +882,9 @@
#endif
}
+ if (boot_into_recovery && !device.is_unlocked && !device.is_tampered)
+ target_load_ssd_keystore();
+
unified_boot:
boot_linux((void *)hdr->kernel_addr, (void *)hdr->tags_addr,
@@ -986,7 +993,7 @@
#endif
/* Authenticate Kernel */
- if(target_use_signed_kernel() && (!device.is_unlocked) && (!device.is_tampered))
+ if(target_use_signed_kernel() && (!device.is_unlocked))
{
image_addr = (unsigned char *)target_get_scratch_address();
offset = 0;
@@ -1187,6 +1194,7 @@
memcpy(info->magic, DEVICE_MAGIC, DEVICE_MAGIC_SIZE);
info->is_unlocked = 0;
info->is_tampered = 0;
+ info->charger_screen_enabled = 0;
write_device_info_mmc(info);
}
@@ -1829,6 +1837,22 @@
reboot_device(FASTBOOT_MODE);
}
+void cmd_oem_enable_charger_screen(const char *arg, void *data, unsigned size)
+{
+ dprintf(INFO, "Enabling charger screen check\n");
+ device.charger_screen_enabled = 1;
+ write_device_info(&device);
+ fastboot_okay("");
+}
+
+void cmd_oem_disable_charger_screen(const char *arg, void *data, unsigned size)
+{
+ dprintf(INFO, "Disabling charger screen check\n");
+ device.charger_screen_enabled = 0;
+ write_device_info(&device);
+ fastboot_okay("");
+}
+
void cmd_oem_unlock(const char *arg, void *data, unsigned sz)
{
if(!device.is_unlocked)
@@ -1842,9 +1866,11 @@
void cmd_oem_devinfo(const char *arg, void *data, unsigned sz)
{
char response[64];
- snprintf(response, 64, "\tDevice tampered: %s", (device.is_tampered ? "true" : "false"));
+ snprintf(response, sizeof(response), "\tDevice tampered: %s", (device.is_tampered ? "true" : "false"));
fastboot_info(response);
- snprintf(response, 64, "\tDevice unlocked: %s", (device.is_unlocked ? "true" : "false"));
+ snprintf(response, sizeof(response), "\tDevice unlocked: %s", (device.is_unlocked ? "true" : "false"));
+ fastboot_info(response);
+ snprintf(response, sizeof(response), "\tCharger screen enabled: %s", (device.charger_screen_enabled ? "true" : "false"));
fastboot_info(response);
fastboot_okay("");
}
@@ -1943,11 +1969,59 @@
}
}
+/* register commands and variables for fastboot */
+void aboot_fastboot_register_commands(void)
+{
+ if (target_is_emmc_boot())
+ {
+ fastboot_register("flash:", cmd_flash_mmc);
+ fastboot_register("erase:", cmd_erase_mmc);
+ }
+ else
+ {
+ fastboot_register("flash:", cmd_flash);
+ fastboot_register("erase:", cmd_erase);
+ }
+
+ fastboot_register("boot", cmd_boot);
+ fastboot_register("continue", cmd_continue);
+ fastboot_register("reboot", cmd_reboot);
+ fastboot_register("reboot-bootloader", cmd_reboot_bootloader);
+ fastboot_register("oem unlock", cmd_oem_unlock);
+ fastboot_register("oem device-info", cmd_oem_devinfo);
+ fastboot_register("preflash", cmd_preflash);
+ fastboot_register("oem enable-charger-screen",
+ cmd_oem_enable_charger_screen);
+ fastboot_register("oem disable-charger-screen",
+ cmd_oem_disable_charger_screen);
+ /* publish variables and their values */
+ fastboot_publish("product", TARGET(BOARD));
+ fastboot_publish("kernel", "lk");
+ fastboot_publish("serialno", sn_buf);
+
+ /*
+ * partition info is supported only for emmc partitions
+ * Calling this for NAND prints some error messages which
+ * is harmless but misleading. Avoid calling this for NAND
+ * devices.
+ */
+ if (target_is_emmc_boot())
+ publish_getvar_partition_info(part_info, ARRAY_SIZE(part_info));
+
+ /* Max download size supported */
+ snprintf(max_download_size, MAX_RSP_SIZE, "\t0x%x",
+ target_get_max_flash_size());
+ fastboot_publish("max-download-size", (const char *) max_download_size);
+ /* Is the charger screen check enabled */
+ snprintf(charger_screen_enabled, MAX_RSP_SIZE, "%d",
+ device.charger_screen_enabled);
+ fastboot_publish("charger-screen-enabled",
+ (const char *) charger_screen_enabled);
+}
+
void aboot_init(const struct app_descriptor *app)
{
unsigned reboot_mode = 0;
- unsigned usb_init = 0;
- unsigned sz = 0;
bool boot_into_fastboot = false;
/* Setup page size information for nand/emmc reads */
@@ -1964,15 +2038,10 @@
ASSERT((MEMBASE + MEMSIZE) > MEMBASE);
- if(target_use_signed_kernel())
- {
- read_device_info(&device);
-
- }
+ read_device_info(&device);
target_serialno((unsigned char *) sn_buf);
dprintf(SPEW,"serial number: %s\n",sn_buf);
- surf_udc_device.serialno = sn_buf;
/* Check if we should do something other than booting up */
if (keys_get_state(KEY_VOLUMEUP) && keys_get_state(KEY_VOLUMEDOWN))
@@ -2042,49 +2111,16 @@
"to fastboot mode.\n");
}
- sz = target_get_max_flash_size();
+ /* We are here means regular boot did not happen. Start fastboot. */
- target_fastboot_init();
+ /* register aboot specific fastboot commands */
+ aboot_fastboot_register_commands();
- if(!usb_init)
- udc_init(&surf_udc_device);
-
- fastboot_register("boot", cmd_boot);
-
- if (target_is_emmc_boot())
- {
- fastboot_register("flash:", cmd_flash_mmc);
- fastboot_register("erase:", cmd_erase_mmc);
- }
- else
- {
- fastboot_register("flash:", cmd_flash);
- fastboot_register("erase:", cmd_erase);
- }
-
- fastboot_register("continue", cmd_continue);
- fastboot_register("reboot", cmd_reboot);
- fastboot_register("reboot-bootloader", cmd_reboot_bootloader);
- fastboot_register("oem unlock", cmd_oem_unlock);
- fastboot_register("oem device-info", cmd_oem_devinfo);
- fastboot_register("preflash", cmd_preflash);
- fastboot_publish("product", TARGET(BOARD));
- fastboot_publish("kernel", "lk");
- fastboot_publish("serialno", sn_buf);
- /*
- * fastboot publish is supported only for emmc partitions
- * Calling this for NAND prints some error messages which
- * is harmless but misleading. Avoid calling this for NAND
- * devices.
- */
- if (target_is_emmc_boot())
- publish_getvar_partition_info(part_info, ARRAY_SIZE(part_info));
- /* Max download size supported */
- snprintf(max_download_size, MAX_RSP_SIZE, "\t0x%x", sz);
- fastboot_publish("max-download-size", (const char *) max_download_size);
+ /* dump partition table for debug info */
partition_dump();
- fastboot_init(target_get_scratch_address(), sz);
- udc_start();
+
+ /* initialize and start fastboot */
+ fastboot_init(target_get_scratch_address(), target_get_max_flash_size());
}
uint32_t get_page_size()
diff --git a/app/aboot/devinfo.h b/app/aboot/devinfo.h
index 1d87581..558aaf9 100644
--- a/app/aboot/devinfo.h
+++ b/app/aboot/devinfo.h
@@ -40,6 +40,7 @@
unsigned char magic[DEVICE_MAGIC_SIZE];
bool is_unlocked;
bool is_tampered;
+ bool charger_screen_enabled;
};
#endif
diff --git a/app/aboot/fastboot.c b/app/aboot/fastboot.c
index 262a08e..66d0437 100644
--- a/app/aboot/fastboot.c
+++ b/app/aboot/fastboot.c
@@ -32,6 +32,7 @@
#include <string.h>
#include <stdlib.h>
#include <platform.h>
+#include <target.h>
#include <kernel/thread.h>
#include <kernel/event.h>
#include <dev/udc.h>
@@ -40,6 +41,26 @@
#define MAX_USBFS_BULK_SIZE (32 * 1024)
void boot_linux(void *bootimg, unsigned sz);
+static void fastboot_notify(struct udc_gadget *gadget, unsigned event);
+static struct udc_endpoint *fastboot_endpoints[2];
+
+static struct udc_device surf_udc_device = {
+ .vendor_id = 0x18d1,
+ .product_id = 0xD00D,
+ .version_id = 0x0100,
+ .manufacturer = "Google",
+ .product = "Android",
+};
+
+static struct udc_gadget fastboot_gadget = {
+ .notify = fastboot_notify,
+ .ifc_class = 0xff,
+ .ifc_subclass = 0x42,
+ .ifc_protocol = 0x03,
+ .ifc_endpoints = 2,
+ .ifc_string = "fastboot",
+ .ept = fastboot_endpoints,
+};
/* todo: give lk strtoul and nuke this */
static unsigned hex2unsigned(const char *x)
@@ -81,7 +102,7 @@
const char *name;
const char *value;
};
-
+
static struct fastboot_cmd *cmdlist;
void fastboot_register(const char *prefix,
@@ -305,6 +326,14 @@
}
again:
while (fastboot_state != STATE_ERROR) {
+
+ /* Read buffer must be cleared first. If buffer is not cleared,
+ * the original data in buf trailing the received command is
+ * interpreted as part of the command.
+ */
+ memset(buffer, 0, MAX_RSP_SIZE);
+ arch_clean_invalidate_cache_range((addr_t) buffer, MAX_RSP_SIZE);
+
r = usb_read(buffer, MAX_RSP_SIZE);
if (r < 0) break;
buffer[r] = 0;
@@ -322,7 +351,7 @@
}
fastboot_fail("unknown command");
-
+
}
fastboot_state = STATE_OFFLINE;
dprintf(INFO,"fastboot: oops!\n");
@@ -345,26 +374,26 @@
}
}
-static struct udc_endpoint *fastboot_endpoints[2];
-
-static struct udc_gadget fastboot_gadget = {
- .notify = fastboot_notify,
- .ifc_class = 0xff,
- .ifc_subclass = 0x42,
- .ifc_protocol = 0x03,
- .ifc_endpoints = 2,
- .ifc_string = "fastboot",
- .ept = fastboot_endpoints,
-};
-
int fastboot_init(void *base, unsigned size)
{
+ char sn_buf[13];
thread_t *thr;
dprintf(INFO, "fastboot_init()\n");
download_base = base;
download_max = size;
+ /* target specific initialization before going into fastboot. */
+ target_fastboot_init();
+
+ /* setup serialno */
+ target_serialno((unsigned char *) sn_buf);
+ dprintf(SPEW,"serial number: %s\n",sn_buf);
+ surf_udc_device.serialno = sn_buf;
+
+ /* register udc device */
+ udc_init(&surf_udc_device);
+
event_init(&usb_online, 0, EVENT_FLAG_AUTOUNSIGNAL);
event_init(&txn_done, 0, EVENT_FLAG_AUTOUNSIGNAL);
@@ -382,6 +411,7 @@
if (!req)
goto fail_alloc_req;
+ /* register gadget */
if (udc_register_gadget(&fastboot_gadget))
goto fail_udc_register;
@@ -395,12 +425,15 @@
goto fail_alloc_in;
}
thread_resume(thr);
+
+ udc_start();
+
return 0;
fail_udc_register:
udc_request_free(req);
fail_alloc_req:
- udc_endpoint_free(out);
+ udc_endpoint_free(out);
fail_alloc_out:
udc_endpoint_free(in);
fail_alloc_in:
diff --git a/arch/arm/cache.c b/arch/arm/cache.c
index 0a403b5..b024d37 100644
--- a/arch/arm/cache.c
+++ b/arch/arm/cache.c
@@ -1,22 +1,43 @@
-/*
- * Copyright (c) 2008 Travis Geiselbrecht
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
*
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files
- * (the "Software"), to deal in the Software without restriction,
- * including without limitation the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
*
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+
+ #include <debug.h>
+ #include <arch/defines.h>
+ #include <stdlib.h>
+ #include <arch/ops.h>
+
+ void cache_clean_invalidate_unaligned_start_addr(addr_t start, size_t size)
+ {
+ addr_t actual_start;
+ size_t actual_size;
+
+ actual_start = GET_CAHE_LINE_START_ADDR(start);
+ actual_size = start - actual_start + size;
+
+ arch_clean_invalidate_cache_range(actual_start, actual_size);
+ }
diff --git a/arch/arm/include/arch/defines.h b/arch/arm/include/arch/defines.h
index 2041f39..f1e5228 100644
--- a/arch/arm/include/arch/defines.h
+++ b/arch/arm/include/arch/defines.h
@@ -41,5 +41,13 @@
#endif
#define IS_CACHE_LINE_ALIGNED(addr) !((uint32_t) (addr) & (CACHE_LINE - 1))
+
+#if ARM_ISA_ARMV7
+#define dsb() __asm__ volatile ("dsb" : : : "memory");
+#elif ARM_ISA_ARMV6
+#define dsb() __asm__ volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0): "memory");
#endif
+#define GET_CAHE_LINE_START_ADDR(addr) ROUNDDOWN(addr, CACHE_LINE)
+
+#endif
diff --git a/arch/arm/mmu.c b/arch/arm/mmu.c
index 3fc61bf..2027b41 100644
--- a/arch/arm/mmu.c
+++ b/arch/arm/mmu.c
@@ -25,6 +25,7 @@
#include <compiler.h>
#include <arch.h>
#include <arch/arm.h>
+#include <arch/defines.h>
#include <arch/arm/mmu.h>
#if ARM_WITH_MMU
@@ -94,6 +95,10 @@
void arch_disable_mmu(void)
{
+ /* Ensure all memory access are complete
+ * before disabling MMU
+ */
+ dsb();
arm_write_cr1(arm_read_cr1() & ~(1<<0));
arm_invalidate_tlb();
}
diff --git a/arch/arm/ops.S b/arch/arm/ops.S
index 2581273..6b9d966 100644
--- a/arch/arm/ops.S
+++ b/arch/arm/ops.S
@@ -209,6 +209,12 @@
/* void arm_write_cr1(uint32_t val) */
FUNCTION(arm_write_cr1)
mcr p15, 0, r0, c1, c0, 0
+#if ARM_CPU_CORTEX_A8
+ isb sy
+#elif ARM_CPU_ARM1136
+ mov r0, #0
+ mcr p15, 0, r0, c7, c5, 4
+#endif
bx lr
/* uint32_t arm_read_cr1_aux(void) */
@@ -235,6 +241,18 @@
FUNCTION(arm_invalidate_tlb)
mov r0, #0
mcr p15, 0, r0, c8, c7, 0
+#if ARM_CPU_CORTEX_A8
+ dsb sy
+#elif ARM_CPU_ARM1136
+ mov r0, #0
+ mcr p15, 0, r0, c7, c10, 4
+#endif
+#if ARM_CPU_CORTEX_A8
+ isb sy
+#elif ARM_CPU_ARM1136
+ mov r0, #0
+ mcr p15, 0, r0, c7, c5, 4
+#endif
bx lr
/* void arch_switch_stacks_and_call(addr_t call, addr_t stack) */
@@ -252,26 +270,6 @@
#endif
bx lr
-/*void isb(void) */
-FUNCTION(isb)
-#if ARM_CPU_CORTEX_A8
- isb sy
-#elif ARM_CPU_ARM1136
- mov r0, #0
- mcr p15, 0, r0, c7, c5, 4
-#endif
- bx lr
-
-/*void dsb(void) */
-FUNCTION(dsb)
-#if ARM_CPU_CORTEX_A8
- dsb sy
-#elif ARM_CPU_ARM1136
- mov r0, #0
- mcr p15, 0, r0, c7, c10, 4
-#endif
- bx lr
-
/* uint32_t arm_read_cycle_count(void); */
FUNCTION(arm_read_cycle_count)
diff --git a/dev/gcdb/display/include/panel_nt35521_720p_video.h b/dev/gcdb/display/include/panel_nt35521_720p_video.h
index e9e4104..ae70a50 100644
--- a/dev/gcdb/display/include/panel_nt35521_720p_video.h
+++ b/dev/gcdb/display/include/panel_nt35521_720p_video.h
@@ -1185,6 +1185,9 @@
0x53, 0x2C, 0xFF, 0xFF, };
+static char nt35521_720p_video_on_cmd205[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x51, 0xFF, 0xFF, 0xFF, };
static struct mipi_dsi_cmd nt35521_720p_video_on_command[] = {
@@ -1392,9 +1395,10 @@
{ 0x4 , nt35521_720p_video_on_cmd201},
{ 0xc , nt35521_720p_video_on_cmd202},
{ 0xc , nt35521_720p_video_on_cmd203},
-{ 0x8 , nt35521_720p_video_on_cmd204}
+{ 0x8 , nt35521_720p_video_on_cmd204},
+{ 0x8 , nt35521_720p_video_on_cmd205}
};
-#define NT35521_720P_VIDEO_ON_COMMAND 205
+#define NT35521_720P_VIDEO_ON_COMMAND 206
static char nt35521_720p_videooff_cmd0[] = {
diff --git a/dev/panel/msm/mipi_hx8379a_video_wvga.c b/dev/panel/msm/mipi_hx8379a_video_wvga.c
new file mode 100644
index 0000000..de04f2f
--- /dev/null
+++ b/dev/panel/msm/mipi_hx8379a_video_wvga.c
@@ -0,0 +1,263 @@
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <stdint.h>
+#include <msm_panel.h>
+#include <mipi_dsi.h>
+#include <sys/types.h>
+#include <err.h>
+#include <reg.h>
+#include <debug.h>
+#include <target/display.h>
+#include <platform/iomap.h>
+
+#define WVGA_MIPI_FB_WIDTH 480
+#define WVGA_MIPI_FB_HEIGHT 800
+
+#define HX8379A_PANEL_FRAME_RATE 60
+#define HX8379A_PANEL_NUM_OF_LANES 2
+#define HX8379A_PANEL_LANE_SWAP 1
+#define HX8379A_PANEL_T_CLK_PRE 0x41b
+#define HX8379A_PANEL_T_CLK_POST 0x0
+#define HX8379A_PANEL_BPP 24
+#define HX8379A_PANEL_CLK_RATE 499000000
+
+#define MIPI_HSYNC_PULSE_WIDTH 17
+#define MIPI_HSYNC_BACK_PORCH_DCLK 90
+#define MIPI_HSYNC_FRONT_PORCH_DCLK 90
+#define MIPI_VSYNC_PULSE_WIDTH 6
+#define MIPI_VSYNC_BACK_PORCH_LINES 10
+#define MIPI_VSYNC_FRONT_PORCH_LINES 15
+
+static char disp_on0[8] = {
+ 0x04, 0x00, 0x39, 0xC0,
+ 0xB9, 0xFF, 0x83, 0x79
+};
+static char disp_on1[4] = {
+ 0xBA, 0x51, 0x23, 0x80,
+};
+static char disp_on2[8] = {
+ 0x04, 0x00, 0x39, 0xC0,
+ 0xDE, 0x05, 0x50, 0x04
+};
+static char disp_on3[24] = {
+ 0x14, 0x00, 0x39, 0xC0,
+ 0xB1, 0x00, 0x50, 0x44,
+ 0xEA, 0x8D, 0x08, 0x11,
+ 0x11, 0x11, 0x27, 0x2F,
+ 0x9A, 0x1A, 0x42, 0x0B,
+ 0x6E, 0xF1, 0x00, 0xE6
+};
+static char disp_on4[20] = {
+ 0x0E, 0x00, 0x39, 0xC0,
+ 0xB2, 0x00, 0x00, 0x3C,
+ 0x08, 0x04, 0x19, 0x22,
+ 0x00, 0xFF, 0x08, 0x04,
+ 0x19, 0x20, 0xFF, 0xFF
+};
+static char disp_on5[36] = {
+ 0x20, 0x00, 0x39, 0xC0,
+ 0xB4, 0x82, 0x08, 0x00,
+ 0x32, 0x10, 0x03, 0x32,
+ 0x13, 0x70, 0x32, 0x10,
+ 0x08, 0x37, 0x01, 0x28,
+ 0x07, 0x37, 0x08, 0x3A,
+ 0x08, 0x42, 0x42, 0x08,
+ 0x00, 0x40, 0x08, 0x28,
+ 0x08, 0x30, 0x30, 0x04
+};
+static char disp_on6[52] = {
+ 0x30, 0x00, 0x39, 0xC0,
+ 0xD5, 0x00, 0x00, 0x0A,
+ 0x00, 0x01, 0x05, 0x00,
+ 0x03, 0x00, 0x88, 0x88,
+ 0x88, 0x88, 0x23, 0x01,
+ 0x67, 0x45, 0x02, 0x13,
+ 0x88, 0x88, 0x88, 0x88,
+ 0x88, 0x88, 0x88, 0x88,
+ 0x88, 0x88, 0x54, 0x76,
+ 0x10, 0x32, 0x31, 0x20,
+ 0x88, 0x88, 0x88, 0x88,
+ 0x88, 0x88, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00
+};
+static char disp_on7[40] = {
+ 0x24, 0x00, 0x39, 0xC0,
+ 0xE0, 0x79, 0x05, 0x0F,
+ 0x14, 0x26, 0x29, 0x3F,
+ 0x2B, 0x46, 0x04, 0x0E,
+ 0x12, 0x15, 0x18, 0x16,
+ 0x16, 0x11, 0x17, 0x05,
+ 0x0F, 0x14, 0x26, 0x29,
+ 0x3F, 0x2B, 0x46, 0x04,
+ 0x0E, 0x12, 0x15, 0x18,
+ 0x16, 0x16, 0x11, 0x17
+};
+static char disp_on8[4] = {
+ 0xCC, 0x02, 0x23, 0x80,
+};
+static char disp_on9[12] = {
+ 0x05, 0x00, 0x39, 0xC0,
+ 0xB6, 0x00, 0x9C, 0x00,
+ 0x9C, 0xFF, 0xFF, 0xFF
+};
+static char disp_on10[4] = {
+ 0x11, 0x00, 0x05, 0x80
+};
+static char disp_on11[4] = {
+ 0x29, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd hx8379a_wvga_panel_video_mode_cmds[] = {
+ {sizeof(disp_on0), (char *)disp_on0},
+ {sizeof(disp_on1), (char *)disp_on1},
+ {sizeof(disp_on2), (char *)disp_on2},
+ {sizeof(disp_on3), (char *)disp_on3},
+ {sizeof(disp_on4), (char *)disp_on4},
+ {sizeof(disp_on5), (char *)disp_on5},
+ {sizeof(disp_on6), (char *)disp_on6},
+ {sizeof(disp_on7), (char *)disp_on7},
+ {sizeof(disp_on8), (char *)disp_on8},
+ {sizeof(disp_on9), (char *)disp_on9},
+ {sizeof(disp_on10), (char *)disp_on10},
+ {sizeof(disp_on11), (char *)disp_on11},
+};
+
+int mipi_hx8379a_video_wvga_config(void *pdata)
+{
+ int ret = NO_ERROR;
+ /* 2 Lanes -- Enables Data Lane0, 1 */
+ unsigned char lane_en = 3;
+ unsigned long low_pwr_stop_mode = 0;
+
+ /* Needed or else will have blank line at top of display */
+ unsigned char eof_bllp_pwr = 0x9;
+
+ unsigned char interleav = 0;
+ struct lcdc_panel_info *lcdc = NULL;
+ struct msm_panel_info *pinfo = (struct msm_panel_info *) pdata;
+
+ if (pinfo == NULL)
+ return ERR_INVALID_ARGS;
+
+ lcdc = &(pinfo->lcdc);
+ if (lcdc == NULL)
+ return ERR_INVALID_ARGS;
+
+ ret = mdss_dsi_video_mode_config((pinfo->xres),
+ (pinfo->yres),
+ (pinfo->xres),
+ (pinfo->yres),
+ (lcdc->h_front_porch),
+ (lcdc->h_back_porch),
+ (lcdc->v_front_porch),
+ (lcdc->v_back_porch),
+ (lcdc->h_pulse_width),
+ (lcdc->v_pulse_width),
+ pinfo->mipi.dst_format,
+ pinfo->mipi.traffic_mode,
+ lane_en,
+ low_pwr_stop_mode,
+ eof_bllp_pwr,
+ interleav,
+ MIPI_DSI0_BASE);
+ return ret;
+}
+
+int mipi_hx8379a_video_wvga_on()
+{
+ int ret = NO_ERROR;
+ return ret;
+}
+
+int mipi_hx8379a_video_wvga_off()
+{
+ int ret = NO_ERROR;
+ return ret;
+}
+
+static struct mdss_dsi_phy_ctrl dsi_video_mode_phy_db = {
+ /* regulator */
+ {0x02, 0x08, 0x05, 0x00, 0x20, 0x03},
+ /* timing */
+ {0x5d, 0x12, 0x0c, 0x00, 0x33, 0x39,
+ 0x10, 0x16, 0x15, 0x03, 0x04, 0x00},
+ /* phy ctrl */
+ {0x7f, 0x00, 0x00, 0x00},
+ /* strength */
+ {0xff, 0x06},
+ /* bist */
+ {0x03, 0x03, 0x00, 0x00, 0x0f, 0x00},
+ /* lane config */
+ { 0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+ 0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+ 0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+ 0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+ 0x40, 0x67, 0x00, 0x00, 0x00, 0x01, 0x88, 0x00, 0x00},
+};
+
+void mipi_hx8379a_video_wvga_init(struct msm_panel_info *pinfo)
+{
+ if (!pinfo)
+ return;
+
+ pinfo->xres = WVGA_MIPI_FB_WIDTH;
+ pinfo->yres = WVGA_MIPI_FB_HEIGHT;
+ pinfo->lcdc.h_back_porch = MIPI_HSYNC_BACK_PORCH_DCLK;
+ pinfo->lcdc.h_front_porch = MIPI_HSYNC_FRONT_PORCH_DCLK;
+ pinfo->lcdc.h_pulse_width = MIPI_HSYNC_PULSE_WIDTH;
+ pinfo->lcdc.v_back_porch = MIPI_VSYNC_BACK_PORCH_LINES;
+ pinfo->lcdc.v_front_porch = MIPI_VSYNC_FRONT_PORCH_LINES;
+ pinfo->lcdc.v_pulse_width = MIPI_VSYNC_PULSE_WIDTH;
+ pinfo->mipi.num_of_lanes = HX8379A_PANEL_NUM_OF_LANES;
+ pinfo->mipi.frame_rate = HX8379A_PANEL_FRAME_RATE;
+
+ pinfo->type = MIPI_VIDEO_PANEL;
+ pinfo->wait_cycle = 0;
+ pinfo->bpp = HX8379A_PANEL_BPP;
+ pinfo->clk_rate = HX8379A_PANEL_CLK_RATE;
+
+ pinfo->mipi.mode = DSI_VIDEO_MODE;
+ pinfo->mipi.traffic_mode = 2;
+ pinfo->mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888;
+ pinfo->mipi.mdss_dsi_phy_db = &dsi_video_mode_phy_db;
+ pinfo->mipi.tx_eot_append = TRUE;
+
+ pinfo->mipi.lane_swap = HX8379A_PANEL_LANE_SWAP;
+ pinfo->mipi.t_clk_post = HX8379A_PANEL_T_CLK_POST;
+ pinfo->mipi.t_clk_pre = HX8379A_PANEL_T_CLK_PRE;
+ pinfo->mipi.panel_cmds = hx8379a_wvga_panel_video_mode_cmds;
+ pinfo->mipi.num_of_panel_cmds = ARRAY_SIZE(hx8379a_wvga_panel_video_mode_cmds);
+
+ pinfo->on = mipi_hx8379a_video_wvga_on;
+ pinfo->off = mipi_hx8379a_video_wvga_off;
+ pinfo->config = mipi_hx8379a_video_wvga_config;
+
+ return;
+};
diff --git a/dev/panel/msm/mipi_otm8018b_video_fwvga.c b/dev/panel/msm/mipi_otm8018b_video_fwvga.c
new file mode 100644
index 0000000..4a7a179
--- /dev/null
+++ b/dev/panel/msm/mipi_otm8018b_video_fwvga.c
@@ -0,0 +1,623 @@
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <stdint.h>
+#include <msm_panel.h>
+#include <mipi_dsi.h>
+#include <sys/types.h>
+#include <err.h>
+#include <reg.h>
+#include <debug.h>
+#include <target/display.h>
+#include <platform/iomap.h>
+
+#define WVGA_MIPI_FB_WIDTH 480
+#define WVGA_MIPI_FB_HEIGHT 854
+
+#define OTM8018B_PANEL_FRAME_RATE 60
+#define OTM8018B_PANEL_NUM_OF_LANES 2
+#define OTM8018B_PANEL_LANE_SWAP 1
+#define OTM8018B_PANEL_T_CLK_PRE 0x41b
+#define OTM8018B_PANEL_T_CLK_POST 0x0
+#define OTM8018B_PANEL_BPP 24
+#define OTM8018B_PANEL_CLK_RATE 499000000
+
+#define MIPI_HSYNC_PULSE_WIDTH 8
+#define MIPI_HSYNC_BACK_PORCH_DCLK 54
+#define MIPI_HSYNC_FRONT_PORCH_DCLK 80
+#define MIPI_VSYNC_PULSE_WIDTH 2
+#define MIPI_VSYNC_BACK_PORCH_LINES 16
+#define MIPI_VSYNC_FRONT_PORCH_LINES 12
+
+static char disp_on0[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0x00, 0xFF, 0xFF
+};
+
+static char disp_on1[8] = {
+ 0x04, 0x00, 0x29, 0xC0,
+ 0xFF, 0x80, 0x09, 0x01
+};
+static char disp_on2[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0x80, 0xFF, 0xFF
+};
+static char disp_on3[8] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xFF, 0x80, 0x09, 0xFF
+};
+
+static char disp_on4[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0x80, 0xFF, 0xFF
+};
+static char disp_on5[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xD6, 0x48, 0xFF, 0xFF
+};
+
+static char disp_on6[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0x03, 0xFF, 0xFF
+};
+static char disp_on7[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xFF, 0x01, 0xFF, 0xFF
+};
+
+static char disp_on8[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0xB4, 0xFF, 0xFF
+};
+
+static char disp_on9[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xC0, 0x10, 0xFF, 0xFF
+};
+
+static char disp_on10[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0x82, 0xFF, 0xFF
+};
+static char disp_on11[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xC5, 0xA3, 0xFF, 0xFF
+};
+static char disp_on12[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0x90, 0xFF, 0xFF
+};
+static char disp_on13[8] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xC5, 0x96, 0x87, 0xFF
+};
+static char disp_on14[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0x00, 0xFF, 0xFF
+};
+static char disp_on15[8] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xD8, 0x74, 0x72, 0xFF
+};
+static char disp_on16[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0x00, 0xFF, 0xFF
+};
+static char disp_on17[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xD9, 0x56, 0xFF, 0xFF
+};
+static char disp_on18[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0x00, 0xFF, 0xFF
+};
+static char disp_on19[24] = {
+ 0x11, 0x00, 0x29, 0xC0,
+ 0xE1, 0x00, 0x06, 0x0A,
+ 0x07, 0x03, 0x16, 0x08,
+ 0x0A, 0x04, 0x06, 0x07,
+ 0x08, 0x0F, 0x23, 0x22,
+ 0x05, 0xff, 0xff, 0xff
+};
+static char disp_on20[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0x00, 0xFF, 0xFF
+};
+static char disp_on21[24] = {
+ 0x11, 0x00, 0x29, 0xC0,
+ 0xE2, 0x00, 0x06, 0x0A,
+ 0x07, 0x03, 0x16, 0x08,
+ 0x0A, 0x04, 0x06, 0x07,
+ 0x08, 0x0F, 0x23, 0x22,
+ 0x05, 0xff, 0xff, 0xff
+};
+static char disp_on22[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0x81, 0xFF, 0xFF
+};
+static char disp_on23[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xC1, 0x77, 0xFF, 0xFF
+};
+static char disp_on24[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0xA0, 0xFF, 0xFF
+};
+static char disp_on25[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xC1, 0xEA, 0xFF, 0xFF
+};
+static char disp_on26[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0xA1, 0xFF, 0xFF
+};
+static char disp_on27[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xC1, 0x08, 0xFF, 0xFF
+};
+static char disp_on28[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0x89, 0xFF, 0xFF
+};
+static char disp_on29[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xC4, 0x08, 0xFF, 0xFF
+};
+static char disp_on30[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0x81, 0xFF, 0xFF
+};
+static char disp_on31[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xC4, 0x83, 0xFF, 0xFF
+};
+static char disp_on32[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0x92, 0xFF, 0xFF
+};
+static char disp_on33[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xC5, 0x01, 0xFF, 0xFF
+};
+static char disp_on34[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0xB1, 0xFF, 0xFF
+};
+static char disp_on35[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xC5, 0xA9, 0xFF, 0xFF
+};
+static char disp_on36[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0x92, 0xFF, 0xFF
+};
+static char disp_on37[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xB3, 0x45, 0xFF, 0xFF
+};
+static char disp_on38[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0x90, 0xFF, 0xFF
+};
+static char disp_on39[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xB3, 0x02, 0xFF, 0xFF
+};
+static char disp_on40[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0x80, 0xFF, 0xFF
+};
+static char disp_on41[12] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xC0, 0x00, 0x58, 0x00,
+ 0x14, 0x16, 0xff, 0xff
+};
+static char disp_on42[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0x80, 0xFF, 0xFF
+};
+static char disp_on43[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xC4, 0x30, 0xFF, 0xFF
+};
+static char disp_on44[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0x90, 0xFF, 0xFF
+};
+static char disp_on45[12] = {
+ 0x07, 0x00, 0x29, 0xC0,
+ 0xC0, 0x00, 0x44, 0x00,
+ 0x00, 0x00, 0x03, 0xff
+};
+static char disp_on46[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0xA6, 0xFF, 0xFF
+};
+static char disp_on47[8] = {
+ 0x04, 0x00, 0x29, 0xC0,
+ 0xC1, 0x01, 0x00, 0x00
+};
+static char disp_on48[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0x80, 0xFF, 0xFF
+};
+static char disp_on49[20] = {
+ 0x0D, 0x00, 0x29, 0xC0,
+ 0xCE, 0x87, 0x03, 0x00,
+ 0x85, 0x03, 0x00, 0x86,
+ 0x03, 0x00, 0x84, 0x03,
+ 0x00, 0xff, 0xff, 0xff
+};
+static char disp_on50[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0xA0, 0xFF, 0xFF
+};
+static char disp_on51[20] = {
+ 0x0F, 0x00, 0x29, 0xC0,
+ 0xCE, 0x38, 0x03, 0x03,
+ 0x58, 0x00, 0x00, 0x00,
+ 0x38, 0x02, 0x03, 0x59,
+ 0x00, 0x00, 0x00, 0xff
+};
+static char disp_on52[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0xB0, 0xFF, 0xFF
+};
+static char disp_on53[20] = {
+ 0x0F, 0x00, 0x29, 0xC0,
+ 0xCE, 0x38, 0x01, 0x03,
+ 0x5A, 0x00, 0x00, 0x00,
+ 0x38, 0x00, 0x03, 0x5B,
+ 0x00, 0x00, 0x00, 0xff
+};
+static char disp_on54[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0xC0, 0xFF, 0xFF
+};
+static char disp_on55[20] = {
+ 0x0F, 0x00, 0x29, 0xC0,
+ 0xCE, 0x30, 0x00, 0x03,
+ 0x5C, 0x00, 0x00, 0x00,
+ 0x30, 0x01, 0x03, 0x5D,
+ 0x00, 0x00, 0x00, 0xff
+};
+static char disp_on56[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0xD0, 0xFF, 0xFF
+};
+static char disp_on57[20] = {
+ 0x0F, 0x00, 0x29, 0xC0,
+ 0xCE, 0x30, 0x02, 0x03,
+ 0x5E, 0x00, 0x00, 0x00,
+ 0x30, 0x03, 0x03, 0x5F,
+ 0x00, 0x00, 0x00, 0xff
+};
+static char disp_on58[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0xC7, 0xFF, 0xFF
+};
+static char disp_on59[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xCF, 0x00, 0xFF, 0xFF
+};
+static char disp_on60[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0xC9, 0xFF, 0xFF
+};
+static char disp_on61[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xCF, 0x00, 0xFF, 0xFF
+};
+static char disp_on62[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0xD0, 0xFF, 0xFF
+};
+static char disp_on63[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xCF, 0x00, 0xFF, 0xFF
+};
+static char disp_on64[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0xC4, 0xFF, 0xFF
+};
+static char disp_on65[12] = {
+ 0x07, 0x00, 0x29, 0xC0,
+ 0xCB, 0x04, 0x04, 0x04,
+ 0x04, 0x04, 0x04, 0xff
+};
+static char disp_on66[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0xD9, 0xFF, 0xFF
+};
+static char disp_on67[12] = {
+ 0x07, 0x00, 0x29, 0xC0,
+ 0xCB, 0x04, 0x04, 0x04,
+ 0x04, 0x04, 0x04, 0xff
+};
+static char disp_on68[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0x84, 0xFF, 0xFF
+};
+static char disp_on69[12] = {
+ 0x07, 0x00, 0x29, 0xC0,
+ 0xCC, 0x0C, 0x0A, 0x10,
+ 0x0E, 0x03, 0x04, 0xFF
+};
+static char disp_on70[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0x9E, 0xFF, 0xFF
+};
+static char disp_on71[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xCC, 0x0B, 0xFF, 0xFF
+};
+static char disp_on72[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0xA0, 0xFF, 0xFF
+};
+static char disp_on73[12] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xCC, 0x09, 0x0F, 0x0D,
+ 0x01, 0x02, 0xFF, 0xFF
+};
+static char disp_on74[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0xB4, 0xFF, 0xFF
+};
+static char disp_on75[12] = {
+ 0x07, 0x00, 0x29, 0xC0,
+ 0xCC, 0x0D, 0x0F, 0x09,
+ 0x0B, 0x02, 0x01, 0xFF
+};
+static char disp_on76[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0xCE, 0xFF, 0xFF
+};
+static char disp_on77[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xCC, 0x0E, 0xFF, 0xFF
+};
+static char disp_on78[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0xD0, 0xFF, 0xFF
+};
+static char disp_on79[12] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xCC, 0x10, 0x0A, 0x0C,
+ 0x04, 0x03, 0xFF, 0xFF
+};
+static char disp_on80[8] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x00, 0x00, 0xFF, 0xFF
+};
+static char disp_on81[8] = {
+ 0x04, 0x00, 0x29, 0xC0,
+ 0xFF, 0xFF, 0xFF, 0xFF
+};
+static char disp_on82[4] = {
+ 0x11, 0x00, 0x05, 0x80
+};
+static char disp_on83[4] = {
+ 0x29, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd otm8018b_wvga_panel_video_mode_cmds[] = {
+ {sizeof(disp_on0), (char *)disp_on0},
+ {sizeof(disp_on1), (char *)disp_on1},
+ {sizeof(disp_on2), (char *)disp_on2},
+ {sizeof(disp_on3), (char *)disp_on3},
+ {sizeof(disp_on4), (char *)disp_on4},
+ {sizeof(disp_on5), (char *)disp_on5},
+ {sizeof(disp_on6), (char *)disp_on6},
+ {sizeof(disp_on7), (char *)disp_on7},
+ {sizeof(disp_on8), (char *)disp_on8},
+ {sizeof(disp_on9), (char *)disp_on9},
+ {sizeof(disp_on10), (char *)disp_on10},
+ {sizeof(disp_on11), (char *)disp_on11},
+ {sizeof(disp_on12), (char *)disp_on12},
+ {sizeof(disp_on13), (char *)disp_on13},
+ {sizeof(disp_on14), (char *)disp_on14},
+ {sizeof(disp_on15), (char *)disp_on15},
+ {sizeof(disp_on16), (char *)disp_on16},
+ {sizeof(disp_on17), (char *)disp_on17},
+ {sizeof(disp_on18), (char *)disp_on18},
+ {sizeof(disp_on19), (char *)disp_on19},
+ {sizeof(disp_on20), (char *)disp_on20},
+ {sizeof(disp_on21), (char *)disp_on21},
+ {sizeof(disp_on22), (char *)disp_on22},
+ {sizeof(disp_on23), (char *)disp_on23},
+ {sizeof(disp_on24), (char *)disp_on24},
+ {sizeof(disp_on25), (char *)disp_on25},
+ {sizeof(disp_on26), (char *)disp_on26},
+ {sizeof(disp_on27), (char *)disp_on27},
+ {sizeof(disp_on28), (char *)disp_on28},
+ {sizeof(disp_on29), (char *)disp_on29},
+ {sizeof(disp_on30), (char *)disp_on30},
+ {sizeof(disp_on31), (char *)disp_on31},
+ {sizeof(disp_on32), (char *)disp_on32},
+ {sizeof(disp_on33), (char *)disp_on33},
+ {sizeof(disp_on34), (char *)disp_on34},
+ {sizeof(disp_on35), (char *)disp_on35},
+ {sizeof(disp_on36), (char *)disp_on36},
+ {sizeof(disp_on37), (char *)disp_on37},
+ {sizeof(disp_on38), (char *)disp_on38},
+ {sizeof(disp_on39), (char *)disp_on39},
+ {sizeof(disp_on40), (char *)disp_on40},
+ {sizeof(disp_on41), (char *)disp_on41},
+ {sizeof(disp_on42), (char *)disp_on42},
+ {sizeof(disp_on43), (char *)disp_on43},
+ {sizeof(disp_on44), (char *)disp_on44},
+ {sizeof(disp_on45), (char *)disp_on45},
+ {sizeof(disp_on46), (char *)disp_on46},
+ {sizeof(disp_on47), (char *)disp_on47},
+ {sizeof(disp_on48), (char *)disp_on48},
+ {sizeof(disp_on49), (char *)disp_on49},
+ {sizeof(disp_on50), (char *)disp_on50},
+ {sizeof(disp_on51), (char *)disp_on51},
+ {sizeof(disp_on52), (char *)disp_on52},
+ {sizeof(disp_on53), (char *)disp_on53},
+ {sizeof(disp_on54), (char *)disp_on54},
+ {sizeof(disp_on55), (char *)disp_on55},
+ {sizeof(disp_on56), (char *)disp_on56},
+ {sizeof(disp_on57), (char *)disp_on57},
+ {sizeof(disp_on58), (char *)disp_on58},
+ {sizeof(disp_on59), (char *)disp_on59},
+ {sizeof(disp_on60), (char *)disp_on60},
+ {sizeof(disp_on61), (char *)disp_on61},
+ {sizeof(disp_on62), (char *)disp_on62},
+ {sizeof(disp_on63), (char *)disp_on63},
+ {sizeof(disp_on64), (char *)disp_on64},
+ {sizeof(disp_on65), (char *)disp_on65},
+ {sizeof(disp_on66), (char *)disp_on66},
+ {sizeof(disp_on67), (char *)disp_on67},
+ {sizeof(disp_on68), (char *)disp_on68},
+ {sizeof(disp_on69), (char *)disp_on69},
+ {sizeof(disp_on70), (char *)disp_on70},
+ {sizeof(disp_on71), (char *)disp_on71},
+ {sizeof(disp_on72), (char *)disp_on72},
+ {sizeof(disp_on73), (char *)disp_on73},
+ {sizeof(disp_on74), (char *)disp_on74},
+ {sizeof(disp_on75), (char *)disp_on75},
+ {sizeof(disp_on76), (char *)disp_on76},
+ {sizeof(disp_on77), (char *)disp_on77},
+ {sizeof(disp_on78), (char *)disp_on78},
+ {sizeof(disp_on79), (char *)disp_on79},
+ {sizeof(disp_on80), (char *)disp_on80},
+ {sizeof(disp_on81), (char *)disp_on81},
+ {sizeof(disp_on82), (char *)disp_on82},
+ {sizeof(disp_on83), (char *)disp_on83},
+};
+
+int mipi_otm8018b_video_wvga_config(void *pdata)
+{
+ int ret = NO_ERROR;
+ /* 2 Lanes -- Enables Data Lane0, 1 */
+ unsigned char lane_en = 3;
+ unsigned long low_pwr_stop_mode = 0;
+
+ /* Needed or else will have blank line at top of display */
+ unsigned char eof_bllp_pwr = 0x9;
+
+ unsigned char interleav = 0;
+ struct lcdc_panel_info *lcdc = NULL;
+ struct msm_panel_info *pinfo = (struct msm_panel_info *) pdata;
+
+ if (pinfo == NULL)
+ return ERR_INVALID_ARGS;
+
+ lcdc = &(pinfo->lcdc);
+ if (lcdc == NULL)
+ return ERR_INVALID_ARGS;
+
+ ret = mdss_dsi_video_mode_config((pinfo->xres),
+ (pinfo->yres),
+ (pinfo->xres),
+ (pinfo->yres),
+ (lcdc->h_front_porch),
+ (lcdc->h_back_porch),
+ (lcdc->v_front_porch),
+ (lcdc->v_back_porch),
+ (lcdc->h_pulse_width),
+ (lcdc->v_pulse_width),
+ pinfo->mipi.dst_format,
+ pinfo->mipi.traffic_mode,
+ lane_en,
+ low_pwr_stop_mode,
+ eof_bllp_pwr,
+ interleav,
+ MIPI_DSI0_BASE);
+ return ret;
+}
+
+int mipi_otm8018b_video_wvga_on()
+{
+ int ret = NO_ERROR;
+ return ret;
+}
+
+int mipi_otm8018b_video_wvga_off()
+{
+ int ret = NO_ERROR;
+ return ret;
+}
+
+static struct mdss_dsi_phy_ctrl dsi_video_mode_phy_db = {
+ {0x02, 0x08, 0x05, 0x00, 0x20, 0x03},
+ {0x8B, 0x1F, 0x05, 0x00, 0x45, 0x4A,
+ 0x19, 0x23, 0x23, 0x03, 0x04, 0x00},
+ {0x7f, 0x00, 0x00, 0x00},
+ {0xff, 0x06},
+ {0x03, 0x03, 0x00, 0x00, 0x0f, 0x00},
+ { 0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+ 0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+ 0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+ 0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+ 0x40, 0x67, 0x00, 0x00, 0x00, 0x01, 0x88, 0x00, 0x00},
+};
+
+void mipi_otm8018b_video_wvga_init(struct msm_panel_info *pinfo)
+{
+ if (!pinfo)
+ return;
+
+ pinfo->xres = WVGA_MIPI_FB_WIDTH;
+ pinfo->yres = WVGA_MIPI_FB_HEIGHT;
+ pinfo->lcdc.h_back_porch = MIPI_HSYNC_BACK_PORCH_DCLK;
+ pinfo->lcdc.h_front_porch = MIPI_HSYNC_FRONT_PORCH_DCLK;
+ pinfo->lcdc.h_pulse_width = MIPI_HSYNC_PULSE_WIDTH;
+ pinfo->lcdc.v_back_porch = MIPI_VSYNC_BACK_PORCH_LINES;
+ pinfo->lcdc.v_front_porch = MIPI_VSYNC_FRONT_PORCH_LINES;
+ pinfo->lcdc.v_pulse_width = MIPI_VSYNC_PULSE_WIDTH;
+ pinfo->mipi.num_of_lanes = OTM8018B_PANEL_NUM_OF_LANES;
+ pinfo->mipi.frame_rate = OTM8018B_PANEL_FRAME_RATE;
+
+ pinfo->type = MIPI_VIDEO_PANEL;
+ pinfo->wait_cycle = 0;
+ pinfo->bpp = OTM8018B_PANEL_BPP;
+ pinfo->clk_rate = OTM8018B_PANEL_CLK_RATE;
+
+ pinfo->mipi.mode = DSI_VIDEO_MODE;
+ pinfo->mipi.traffic_mode = 2;
+ pinfo->mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888;
+ pinfo->mipi.mdss_dsi_phy_db = &dsi_video_mode_phy_db;
+ pinfo->mipi.tx_eot_append = TRUE;
+
+ pinfo->mipi.lane_swap = OTM8018B_PANEL_LANE_SWAP;
+ pinfo->mipi.t_clk_post = OTM8018B_PANEL_T_CLK_POST;
+ pinfo->mipi.t_clk_pre = OTM8018B_PANEL_T_CLK_PRE;
+ pinfo->mipi.panel_cmds = otm8018b_wvga_panel_video_mode_cmds;
+ pinfo->mipi.num_of_panel_cmds =
+ ARRAY_SIZE(otm8018b_wvga_panel_video_mode_cmds);
+
+ pinfo->on = mipi_otm8018b_video_wvga_on;
+ pinfo->off = mipi_otm8018b_video_wvga_off;
+ pinfo->config = mipi_otm8018b_video_wvga_config;
+
+ return;
+};
diff --git a/dev/panel/msm/mipi_truly_cmd_wvga.c b/dev/panel/msm/mipi_truly_cmd_wvga.c
new file mode 100644
index 0000000..b1f6c31
--- /dev/null
+++ b/dev/panel/msm/mipi_truly_cmd_wvga.c
@@ -0,0 +1,314 @@
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <stdint.h>
+#include <msm_panel.h>
+#include <mipi_dsi.h>
+#include <sys/types.h>
+#include <err.h>
+#include <reg.h>
+#include <debug.h>
+#include <target/display.h>
+#include <platform/iomap.h>
+
+#define WVGA_MIPI_FB_WIDTH 480
+#define WVGA_MIPI_FB_HEIGHT 800
+
+#define TRULY_PANEL_FRAME_RATE 60
+#define TRULY_PANEL_NUM_OF_LANES 2
+#define TRULY_PANEL_LANE_SWAP 0
+#define TRULY_PANEL_T_CLK_PRE 0x41b
+#define TRULY_PANEL_T_CLK_POST 0x0
+#define TRULY_PANEL_BPP 24
+#define TRULY_PANEL_CLK_RATE 499000000
+
+static char disp_on0[4] = {
+ 0x01, 0x00, 0x05, 0x80
+};
+static char disp_on1[4] = {
+ 0xB0, 0x04, 0x23, 0x80
+};
+static char disp_on2[8] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB3, 0x02, 0x00, 0xFF
+};
+static char disp_on3[4] = {
+ 0xBD, 0x00, 0x23, 0x80
+};
+static char disp_on4[8] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xC0, 0x18, 0x66, 0xFF
+};
+static char disp_on5[20] = {
+ 0x10, 0x00, 0x29, 0xC0,
+ 0xC1, 0x23, 0x31, 0x99,
+ 0x21, 0x20, 0x00, 0x30,
+ 0x28, 0x0C, 0x0C, 0x00,
+ 0x00, 0x00, 0x21, 0x01
+};
+static char disp_on6[12] = {
+ 0x07, 0x00, 0x29, 0xC0,
+ 0xC2, 0x00, 0x06, 0x06,
+ 0x01, 0x03, 0x00, 0xFF
+};
+static char disp_on7[32] = {
+ 0x19, 0x00, 0x29, 0xC0,
+ 0xC8, 0x04, 0x10, 0x18,
+ 0x20, 0x2E, 0x46, 0x3C,
+ 0x28, 0x1F, 0x18, 0x10,
+ 0x04, 0x04, 0x10, 0x18,
+ 0x20, 0x2E, 0x46, 0x3C,
+ 0x28, 0x1F, 0x18, 0x10,
+ 0x04, 0xFF, 0xFF, 0xFF
+};
+static char disp_on8[32] = {
+ 0x19, 0x00, 0x29, 0xC0,
+ 0xC9, 0x04, 0x10, 0x18,
+ 0x20, 0x2E, 0x46, 0x3C,
+ 0x28, 0x1F, 0x18, 0x10,
+ 0x04, 0x04, 0x10, 0x18,
+ 0x20, 0x2E, 0x46, 0x3C,
+ 0x28, 0x1F, 0x18, 0x10,
+ 0x04, 0xFF, 0xFF, 0xFF
+};
+static char disp_on9[32] = {
+ 0x19, 0x00, 0x29, 0xC0,
+ 0xCA, 0x04, 0x10, 0x18,
+ 0x20, 0x2E, 0x46, 0x3C,
+ 0x28, 0x1F, 0x18, 0x10,
+ 0x04, 0x04, 0x10, 0x18,
+ 0x20, 0x2E, 0x46, 0x3C,
+ 0x28, 0x1F, 0x18, 0x10,
+ 0x04, 0xFF, 0xFF, 0xFF
+};
+static char disp_on10[24] = {
+ 0x11, 0x00, 0x29, 0xC0,
+ 0xD0, 0x29, 0x03, 0xce,
+ 0xa6, 0x00, 0x43, 0x20,
+ 0x10, 0x01, 0x00, 0x01,
+ 0x01, 0x00, 0x03, 0x01,
+ 0x00, 0xFF, 0xFF, 0xFF
+};
+static char disp_on11[12] = {
+ 0x08, 0x00, 0x29, 0xC0,
+ 0xD1, 0x18, 0x0C, 0x23,
+ 0x03, 0x75, 0x02, 0x50
+};
+static char disp_on12[4] = {
+ 0xD3, 0x11, 0x23, 0x80
+};
+static char disp_on13[8] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xD5, 0x2A, 0x2A, 0xFF
+};
+static char disp_on14[8] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xDE, 0x01, 0x51, 0xFF
+};
+static char disp_on15[4] = {
+ 0xE6, 0x51, 0x23, 0x80
+};
+static char disp_on16[4] = {
+ 0xFA, 0x03, 0x23, 0x80
+};
+static char disp_on17[4] = {
+ 0xD6, 0x28, 0x23, 0x80
+};
+static char disp_on18[4] = {
+ 0x36, 0x41, 0x15, 0x80
+};
+static char disp_on19[12] = {
+ 0x05, 0x00, 0x39, 0xC0,
+ 0x2A, 0x00, 0x00, 0x01,
+ 0xDF, 0xFF, 0xFF, 0xFF
+};
+static char disp_on20[12] = {
+ 0x05, 0x00, 0x39, 0xC0,
+ 0x2B, 0x00, 0x00, 0x03,
+ 0x1F, 0xFF, 0xFF, 0xFF
+};
+static char disp_on21[4] = {
+ 0x35, 0x00, 0x15, 0x80
+};
+static char disp_on22[8] = {
+ 0x03, 0x00, 0x39, 0xc0,
+ 0x44, 0x00, 0x50, 0xFF
+};
+static char disp_on23[4] = {
+ 0x3A, 0x77, 0x15, 0x80
+};
+static char disp_on24[4] = {
+ 0x11, 0x00, 0x05, 0x80
+};
+static char disp_on25[4] = {
+ 0x29, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd truly_wvga_panel_cmd_mode_cmds[] = {
+ {sizeof(disp_on0), (char *)disp_on0},
+ {sizeof(disp_on1), (char *)disp_on1},
+ {sizeof(disp_on2), (char *)disp_on2},
+ {sizeof(disp_on3), (char *)disp_on3},
+ {sizeof(disp_on4), (char *)disp_on4},
+ {sizeof(disp_on5), (char *)disp_on5},
+ {sizeof(disp_on6), (char *)disp_on6},
+ {sizeof(disp_on7), (char *)disp_on7},
+ {sizeof(disp_on8), (char *)disp_on8},
+ {sizeof(disp_on9), (char *)disp_on9},
+ {sizeof(disp_on10), (char *)disp_on10},
+ {sizeof(disp_on11), (char *)disp_on11},
+ {sizeof(disp_on12), (char *)disp_on12},
+ {sizeof(disp_on13), (char *)disp_on13},
+ {sizeof(disp_on14), (char *)disp_on14},
+ {sizeof(disp_on15), (char *)disp_on15},
+ {sizeof(disp_on16), (char *)disp_on16},
+ {sizeof(disp_on17), (char *)disp_on17},
+ {sizeof(disp_on18), (char *)disp_on18},
+ {sizeof(disp_on19), (char *)disp_on19},
+ {sizeof(disp_on20), (char *)disp_on20},
+ {sizeof(disp_on21), (char *)disp_on21},
+ {sizeof(disp_on22), (char *)disp_on22},
+ {sizeof(disp_on23), (char *)disp_on23},
+ {sizeof(disp_on24), (char *)disp_on24},
+ {sizeof(disp_on25), (char *)disp_on25},
+};
+
+int mipi_truly_cmd_wvga_config(void *pdata)
+{
+ int ret = NO_ERROR;
+ /* 2 Lanes -- Enables Data Lane0, 1 */
+ unsigned char lane_en = 0x3;
+ unsigned long low_pwr_stop_mode = 0;
+
+ /* Needed or else will have blank line at top of display */
+ unsigned char eof_bllp_pwr = 0x9;
+
+ unsigned char interleav = 0;
+ struct lcdc_panel_info *lcdc = NULL;
+ struct msm_panel_info *pinfo = (struct msm_panel_info *) pdata;
+
+ if (pinfo == NULL)
+ return ERR_INVALID_ARGS;
+
+ lcdc = &(pinfo->lcdc);
+ if (lcdc == NULL)
+ return ERR_INVALID_ARGS;
+
+ ret = mdss_dsi_cmd_mode_config((pinfo->xres + lcdc->xres_pad),
+ (pinfo->yres + lcdc->yres_pad),
+ (pinfo->xres),
+ (pinfo->yres),
+ pinfo->mipi.dst_format,
+ pinfo->bpp / 8,
+ lane_en,
+ 0);
+
+ return ret;
+}
+
+int mipi_truly_cmd_wvga_on()
+{
+ int ret = NO_ERROR;
+ return ret;
+}
+
+int mipi_truly_cmd_wvga_off()
+{
+ int ret = NO_ERROR;
+ return ret;
+}
+
+static struct mdss_dsi_phy_ctrl dsi_video_mode_phy_db = {
+ /* regulator */
+ {0x02, 0x08, 0x05, 0x00, 0x20, 0x03},
+ /* timing */
+ {0x5d, 0x12, 0x0c, 0x00, 0x33, 0x38,
+ 0x10, 0x16, 0x1e, 0x03, 0x04, 0x00},
+ /* phy ctrl */
+ {0x7f, 0x00, 0x00, 0x00},
+ /* strength */
+ {0xff, 0x06},
+ /* bist */
+ {0x03, 0x03, 0x00, 0x00, 0x0f, 0x00},
+ /* lane config */
+ {0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+ 0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+ 0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+ 0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+ 0x40, 0x67, 0x00, 0x00, 0x00, 0x01, 0x88, 0x00, 0x00},
+};
+
+void mipi_truly_cmd_wvga_init(struct msm_panel_info *pinfo)
+{
+ if (!pinfo)
+ return;
+
+ pinfo->xres = WVGA_MIPI_FB_WIDTH;
+ pinfo->yres = WVGA_MIPI_FB_HEIGHT;
+ pinfo->lcdc.h_back_porch = MIPI_HSYNC_BACK_PORCH_DCLK;
+ pinfo->lcdc.h_front_porch = MIPI_HSYNC_FRONT_PORCH_DCLK;
+ pinfo->lcdc.h_pulse_width = MIPI_HSYNC_PULSE_WIDTH;
+ pinfo->lcdc.v_back_porch = MIPI_VSYNC_BACK_PORCH_LINES;
+ pinfo->lcdc.v_front_porch = MIPI_VSYNC_FRONT_PORCH_LINES;
+ pinfo->lcdc.v_pulse_width = MIPI_VSYNC_PULSE_WIDTH;
+ pinfo->mipi.num_of_lanes = TRULY_PANEL_NUM_OF_LANES;
+ pinfo->mipi.frame_rate = TRULY_PANEL_FRAME_RATE;
+
+ pinfo->type = MIPI_CMD_PANEL;
+ pinfo->wait_cycle = 0;
+ pinfo->bpp = TRULY_PANEL_BPP;
+ pinfo->clk_rate = TRULY_PANEL_CLK_RATE;
+
+ pinfo->mipi.mode = DSI_CMD_MODE;
+ pinfo->mipi.traffic_mode = 1;
+ pinfo->mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888;
+ pinfo->mipi.vc = 0;
+ pinfo->mipi.lane_swap = TRULY_PANEL_LANE_SWAP;
+ pinfo->mipi.data_lane0 = TRUE;
+ pinfo->mipi.data_lane1 = TRUE;
+ pinfo->mipi.data_lane2 = FALSE;
+ pinfo->mipi.data_lane3 = FALSE;
+ pinfo->mipi.t_clk_post = TRULY_PANEL_T_CLK_POST;
+ pinfo->mipi.t_clk_pre = TRULY_PANEL_T_CLK_PRE;
+ pinfo->mipi.stream = 0;
+ pinfo->mipi.mdp_trigger = DSI_CMD_TRIGGER_NONE;
+ pinfo->mipi.dma_trigger = DSI_CMD_TRIGGER_SW;
+
+ pinfo->mipi.mdss_dsi_phy_db = &dsi_video_mode_phy_db;
+ pinfo->mipi.tx_eot_append = TRUE;
+
+ pinfo->mipi.panel_cmds = truly_wvga_panel_cmd_mode_cmds;
+ pinfo->mipi.num_of_panel_cmds = ARRAY_SIZE(truly_wvga_panel_cmd_mode_cmds);
+
+ pinfo->on = mipi_truly_cmd_wvga_on;
+ pinfo->off = mipi_truly_cmd_wvga_off;
+ pinfo->config = mipi_truly_cmd_wvga_config;
+
+ return;
+}
diff --git a/dev/panel/msm/rules.mk b/dev/panel/msm/rules.mk
index b3bdac3..ddeb6dd 100644
--- a/dev/panel/msm/rules.mk
+++ b/dev/panel/msm/rules.mk
@@ -35,5 +35,8 @@
ifeq ($(PLATFORM),msm8610)
OBJS += \
- $(LOCAL_DIR)/mipi_truly_video_wvga.o
+ $(LOCAL_DIR)/mipi_truly_video_wvga.o \
+ $(LOCAL_DIR)/mipi_truly_cmd_wvga.o \
+ $(LOCAL_DIR)/mipi_hx8379a_video_wvga.o \
+ $(LOCAL_DIR)/mipi_otm8018b_video_fwvga.o
endif
diff --git a/dev/pmic/pm8921/pm8921.c b/dev/pmic/pm8921/pm8921.c
index cafa6a8..9cf5e91 100644
--- a/dev/pmic/pm8921/pm8921.c
+++ b/dev/pmic/pm8921/pm8921.c
@@ -747,3 +747,23 @@
return 0;
}
+
+int pm8921_configure_wled(void)
+{
+ pm8921_masked_write(WLED_BOOST_CFG_REG, 0xFF, 0x47);
+ pm8921_masked_write(WLED_HIGH_POLE_CAP_REG, 0xFF, 0x2c);
+ pm8921_masked_write(SSBI_REG_ADDR_WLED_CTRL(2), 0xFF, 0x19);
+ pm8921_masked_write(SSBI_REG_ADDR_WLED_CTRL(3), 0xFF, 0x59);
+ pm8921_masked_write(SSBI_REG_ADDR_WLED_CTRL(4), 0xFF, 0x59);
+ pm8921_masked_write(SSBI_REG_ADDR_WLED_CTRL(5), 0xFF, 0x66);
+ pm8921_masked_write(SSBI_REG_ADDR_WLED_CTRL(6), 0xFF, 0x66);
+ pm8921_masked_write(SSBI_REG_ADDR_WLED_CTRL(7), 0xFF, 0x0f);
+ pm8921_masked_write(SSBI_REG_ADDR_WLED_CTRL(8), 0xFF, 0xff);
+ pm8921_masked_write(SSBI_REG_ADDR_WLED_CTRL(9), 0xFF, 0x0f);
+ pm8921_masked_write(SSBI_REG_ADDR_WLED_CTRL(10), 0xFF, 0xff);
+ pm8921_masked_write(SSBI_REG_ADDR_WLED_CTRL(12), 0xFF, 0x16);
+ pm8921_masked_write(SSBI_REG_ADDR_WLED_CTRL(13), 0xFF, 0x55);
+ pm8921_masked_write(WLED_MOD_CTRL_REG, 0xFF, 0x7f);
+ pm8921_masked_write(WLED_SYNC_REG, WLED_SYNC_MASK, WLED_SYNC_VAL);
+ pm8921_masked_write(WLED_SYNC_REG, WLED_SYNC_MASK, WLED_SYNC_RESET_VAL);
+}
diff --git a/dev/pmic/pm8921/pm8921_hw.h b/dev/pmic/pm8921/pm8921_hw.h
index ea3046f..02771ce 100644
--- a/dev/pmic/pm8921/pm8921_hw.h
+++ b/dev/pmic/pm8921/pm8921_hw.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2012, Linux Foundation. All rights reserved.
+ * Copyright (c) 2011-2013, Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -154,6 +154,18 @@
#define PLDO_TYPE 0
#define NLDO_TYPE 1
+#define SSBI_REG_ADDR_WLED_CTRL_BASE 0x25A
+#define SSBI_REG_ADDR_WLED_CTRL(n) (SSBI_REG_ADDR_WLED_CTRL_BASE + (n) - 1)
+
+/* wled control registers */
+#define WLED_MOD_CTRL_REG SSBI_REG_ADDR_WLED_CTRL(1)
+#define WLED_SYNC_REG SSBI_REG_ADDR_WLED_CTRL(11)
+#define WLED_BOOST_CFG_REG SSBI_REG_ADDR_WLED_CTRL(14)
+#define WLED_HIGH_POLE_CAP_REG SSBI_REG_ADDR_WLED_CTRL(16)
+#define WLED_SYNC_VAL 0x07
+#define WLED_SYNC_RESET_VAL 0x00
+#define WLED_SYNC_MASK 0xF8
+
#define PM8921_MVS_5V_HDMI_SWITCH 0x70
#define LDO(_name, _type, _test_reg, _ctrl_reg) \
diff --git a/dev/pmic/pm8x41/include/pm8x41.h b/dev/pmic/pm8x41/include/pm8x41.h
index b230549..236aed7 100644
--- a/dev/pmic/pm8x41/include/pm8x41.h
+++ b/dev/pmic/pm8x41/include/pm8x41.h
@@ -202,5 +202,5 @@
void pm8x41_config_output_mpp(struct pm8x41_mpp *mpp);
void pm8x41_enable_mpp(struct pm8x41_mpp *mpp, enum mpp_en_ctl enable);
uint8_t pm8x41_get_is_cold_boot();
-
+void pm8x41_diff_clock_ctrl(uint8_t enable);
#endif
diff --git a/dev/pmic/pm8x41/include/pm8x41_hw.h b/dev/pmic/pm8x41/include/pm8x41_hw.h
index 9c10ab8..c8c83ce 100644
--- a/dev/pmic/pm8x41/include/pm8x41_hw.h
+++ b/dev/pmic/pm8x41/include/pm8x41_hw.h
@@ -105,4 +105,8 @@
#define LDO_POWER_MODE 0x45
#define LDO_EN_CTL_REG 0x46
+/* USB3 phy clock */
+#define DIFF_CLK1_EN_CTL 0x5746
+#define DIFF_CLK1_EN_BIT 7
+
#endif
diff --git a/dev/pmic/pm8x41/pm8x41.c b/dev/pmic/pm8x41/pm8x41.c
index 0e1109b..915cf52 100644
--- a/dev/pmic/pm8x41/pm8x41.c
+++ b/dev/pmic/pm8x41/pm8x41.c
@@ -382,3 +382,22 @@
dprintf(INFO,"%s: cold boot\n", __func__);
return 1;
}
+
+/* api to control diff clock */
+void pm8x41_diff_clock_ctrl(uint8_t enable)
+{
+ uint8_t reg;
+
+ reg = REG_READ(DIFF_CLK1_EN_CTL);
+
+ if (enable)
+ {
+ reg |= BIT(DIFF_CLK1_EN_BIT);
+ }
+ else
+ {
+ reg &= ~BIT(DIFF_CLK1_EN_BIT);
+ }
+
+ REG_WRITE(DIFF_CLK1_EN_CTL, reg);
+}
diff --git a/include/arch/ops.h b/include/arch/ops.h
index 26d0642..9f95e2b 100644
--- a/include/arch/ops.h
+++ b/include/arch/ops.h
@@ -53,6 +53,7 @@
void arch_clean_invalidate_cache_range(addr_t start, size_t len);
void arch_invalidate_cache_range(addr_t start, size_t len);
void arch_sync_cache_range(addr_t start, size_t len);
+void cache_clean_invalidate_unaligned_start_addr(addr_t start, size_t size);
void arch_idle(void);
diff --git a/include/dev/udc.h b/include/dev/udc.h
index dc578a1..0dd1f86 100644
--- a/include/dev/udc.h
+++ b/include/dev/udc.h
@@ -1,6 +1,7 @@
/*
* Copyright (c) 2009, Google Inc.
* All rights reserved.
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -9,7 +10,7 @@
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
+ * the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
@@ -19,7 +20,7 @@
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
@@ -77,7 +78,7 @@
const char *product;
const char *serialno;
};
-
+
int udc_init(struct udc_device *devinfo);
int udc_register_gadget(struct udc_gadget *gadget);
int udc_start(void);
@@ -95,12 +96,16 @@
#define GET_INTERFACE 10
#define SET_INTERFACE 11
#define SYNCH_FRAME 12
+#define SET_SEL 48
#define TYPE_DEVICE 1
#define TYPE_CONFIGURATION 2
#define TYPE_STRING 3
#define TYPE_INTERFACE 4
#define TYPE_ENDPOINT 5
+#define TYPE_BOS 15
+#define TYPE_DEVICE_CAP 16
+#define TYPE_SS_EP_COMP 48
#define DEVICE_READ 0x80
#define DEVICE_WRITE 0x00
diff --git a/include/target.h b/include/target.h
index 19be4b6..dc86864 100644
--- a/include/target.h
+++ b/include/target.h
@@ -46,6 +46,8 @@
unsigned target_baseband(void);
void target_serialno(unsigned char *buf);
void target_fastboot_init(void);
+void target_load_ssd_keystore(void);
+bool target_is_ssd_enabled(void);
struct mmc_device *target_mmc_device();
diff --git a/platform/apq8084/acpuclock.c b/platform/apq8084/acpuclock.c
new file mode 100644
index 0000000..93921fb
--- /dev/null
+++ b/platform/apq8084/acpuclock.c
@@ -0,0 +1,88 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <debug.h>
+#include <reg.h>
+#include <mmc.h>
+#include <clock.h>
+#include <platform/clock.h>
+
+void hsusb_clock_init(void)
+{
+}
+
+void clock_init_mmc(uint32_t interface)
+{
+}
+
+/* Configure MMC clock */
+void clock_config_mmc(uint32_t interface, uint32_t freq)
+{
+ /* Disalbe MCI_CLK before changing the sdcc clock */
+ mmc_boot_mci_clk_disable();
+
+ /* Enable MCI CLK */
+ mmc_boot_mci_clk_enable();
+}
+
+/* Configure UART clock based on the UART block id*/
+void clock_config_uart_dm(uint8_t id)
+{
+}
+
+/* Function to asynchronously reset CE (Crypto Engine).
+ * Function assumes that all the CE clocks are off.
+ */
+static void ce_async_reset(uint8_t instance)
+{
+}
+
+void clock_ce_enable(uint8_t instance)
+{
+}
+
+void clock_ce_disable(uint8_t instance)
+{
+}
+
+void clock_config_ce(uint8_t instance)
+{
+ /* Need to enable the clock before disabling since the clk_disable()
+ * has a check to default to nop when the clk_enable() is not called
+ * on that particular clock.
+ */
+ clock_ce_enable(instance);
+
+ clock_ce_disable(instance);
+
+ ce_async_reset(instance);
+
+ clock_ce_enable(instance);
+
+}
diff --git a/platform/apq8084/apq8084-clock.c b/platform/apq8084/apq8084-clock.c
new file mode 100644
index 0000000..b40ee29
--- /dev/null
+++ b/platform/apq8084/apq8084-clock.c
@@ -0,0 +1,110 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <reg.h>
+#include <err.h>
+#include <clock.h>
+#include <clock_pll.h>
+#include <clock_lib2.h>
+#include <platform/clock.h>
+#include <platform/iomap.h>
+
+
+/* Mux source select values */
+#define cxo_source_val 0
+#define gpll0_source_val 1
+#define cxo_mm_source_val 0
+#define mmpll0_mm_source_val 1
+#define mmpll1_mm_source_val 2
+#define mmpll3_mm_source_val 3
+#define gpll0_mm_source_val 5
+
+struct clk_freq_tbl rcg_dummy_freq = F_END;
+
+
+/* Clock Operations */
+static struct clk_ops clk_ops_branch =
+{
+ .enable = clock_lib2_branch_clk_enable,
+ .disable = clock_lib2_branch_clk_disable,
+ .set_rate = clock_lib2_branch_set_rate,
+};
+
+static struct clk_ops clk_ops_rcg_mnd =
+{
+ .enable = clock_lib2_rcg_enable,
+ .set_rate = clock_lib2_rcg_set_rate,
+};
+
+static struct clk_ops clk_ops_rcg =
+{
+ .enable = clock_lib2_rcg_enable,
+ .set_rate = clock_lib2_rcg_set_rate,
+};
+
+static struct clk_ops clk_ops_cxo =
+{
+ .enable = cxo_clk_enable,
+ .disable = cxo_clk_disable,
+};
+
+static struct clk_ops clk_ops_pll_vote =
+{
+ .enable = pll_vote_clk_enable,
+ .disable = pll_vote_clk_disable,
+ .auto_off = pll_vote_clk_disable,
+ .is_enabled = pll_vote_clk_is_enabled,
+};
+
+static struct clk_ops clk_ops_vote =
+{
+ .enable = clock_lib2_vote_clk_enable,
+ .disable = clock_lib2_vote_clk_disable,
+};
+
+/* Clock Sources */
+static struct fixed_clk cxo_clk_src =
+{
+ .c = {
+ .rate = 19200000,
+ .dbg_name = "cxo_clk_src",
+ .ops = &clk_ops_cxo,
+ },
+};
+
+/* Clock lookup table */
+static struct clk_lookup msm_clocks_8084[] =
+{
+};
+
+
+void platform_clock_init(void)
+{
+ clk_init(msm_clocks_8084, ARRAY_SIZE(msm_clocks_8084));
+}
diff --git a/platform/apq8084/gpio.c b/platform/apq8084/gpio.c
new file mode 100644
index 0000000..32c55f4
--- /dev/null
+++ b/platform/apq8084/gpio.c
@@ -0,0 +1,61 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <reg.h>
+#include <platform/iomap.h>
+#include <platform/gpio.h>
+
+/* Remove the file after the gpio patch to move this to msm_shared gets merged. */
+void gpio_tlmm_config(uint32_t gpio, uint8_t func,
+ uint8_t dir, uint8_t pull,
+ uint8_t drvstr, uint32_t enable)
+{
+ uint32_t val = 0;
+ val |= pull;
+ val |= func << 2;
+ val |= drvstr << 6;
+ val |= enable << 9;
+ writel(val, (unsigned int *)GPIO_CONFIG_ADDR(gpio));
+ return;
+}
+
+void gpio_set(uint32_t gpio, uint32_t dir)
+{
+ writel(dir, (unsigned int *)GPIO_IN_OUT_ADDR(gpio));
+ return;
+}
+
+/* Configure gpio for blsp uart 2 */
+void gpio_config_uart_dm(uint8_t id)
+{
+}
+
+void gpio_config_blsp_i2c(uint8_t blsp_id, uint8_t qup_id)
+{
+}
diff --git a/platform/apq8084/include/platform/clock.h b/platform/apq8084/include/platform/clock.h
new file mode 100644
index 0000000..bf63755
--- /dev/null
+++ b/platform/apq8084/include/platform/clock.h
@@ -0,0 +1,49 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __APQ8084_CLOCK_H
+#define __APQ8084_CLOCK_H
+
+#include <clock.h>
+#include <clock_lib2.h>
+
+#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
+
+
+void platform_clock_init(void);
+
+void clock_init_mmc(uint32_t interface);
+void clock_config_mmc(uint32_t interface, uint32_t freq);
+void clock_config_uart_dm(uint8_t id);
+void hsusb_clock_init(void);
+void clock_config_ce(uint8_t instance);
+void mdp_clock_init(void);
+void clock_ce_enable(uint8_t instance);
+void clock_ce_disable(uint8_t instance);
+
+#endif
diff --git a/platform/apq8084/include/platform/gpio.h b/platform/apq8084/include/platform/gpio.h
new file mode 100644
index 0000000..fa4bb8e
--- /dev/null
+++ b/platform/apq8084/include/platform/gpio.h
@@ -0,0 +1,60 @@
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __PLATFORM_APQ8084_GPIO_H
+#define __PLATFORM_APQ8084_GPIO_H
+
+#include <gpio.h>
+
+/* GPIO TLMM: Direction */
+#define GPIO_INPUT 0
+#define GPIO_OUTPUT 1
+
+/* GPIO TLMM: Pullup/Pulldown */
+#define GPIO_NO_PULL 0
+#define GPIO_PULL_DOWN 1
+#define GPIO_KEEPER 2
+#define GPIO_PULL_UP 3
+
+/* GPIO TLMM: Drive Strength */
+#define GPIO_2MA 0
+#define GPIO_4MA 1
+#define GPIO_6MA 2
+#define GPIO_8MA 3
+#define GPIO_10MA 4
+#define GPIO_12MA 5
+#define GPIO_14MA 6
+#define GPIO_16MA 7
+
+/* GPIO TLMM: Status */
+#define GPIO_ENABLE 0
+#define GPIO_DISABLE 1
+
+void gpio_config_uart_dm(uint8_t id);
+void gpio_config_blsp_i2c(uint8_t, uint8_t);
+#endif
diff --git a/platform/apq8084/include/platform/iomap.h b/platform/apq8084/include/platform/iomap.h
new file mode 100644
index 0000000..d7dbb44
--- /dev/null
+++ b/platform/apq8084/include/platform/iomap.h
@@ -0,0 +1,98 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PLATFORM_APQ8084_IOMAP_H_
+#define _PLATFORM_APQ8084_IOMAP_H_
+
+#define MSM_SHARED_BASE 0x0FA00000
+
+#define KPSS_BASE 0xF9000000
+
+#define MSM_GIC_DIST_BASE KPSS_BASE
+#define MSM_GIC_CPU_BASE (KPSS_BASE + 0x2000)
+#define APCS_KPSS_ACS_BASE (KPSS_BASE + 0x00008000)
+#define APCS_APC_KPSS_PLL_BASE (KPSS_BASE + 0x0000A000)
+#define APCS_KPSS_CFG_BASE (KPSS_BASE + 0x00010000)
+#define APCS_KPSS_WDT_BASE (KPSS_BASE + 0x00017000)
+#define KPSS_APCS_QTMR_AC_BASE (KPSS_BASE + 0x00020000)
+#define KPSS_APCS_F0_QTMR_V1_BASE (KPSS_BASE + 0x00021000)
+#define QTMR_BASE KPSS_APCS_F0_QTMR_V1_BASE
+
+#define PERIPH_SS_BASE 0xF9800000
+
+#define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00024000)
+#define MSM_SDC1_SDHCI_BASE (PERIPH_SS_BASE + 0x00024900)
+#define MSM_SDC3_BASE (PERIPH_SS_BASE + 0x00064000)
+#define MSM_SDC3_SDHCI_BASE (PERIPH_SS_BASE + 0x00064900)
+#define MSM_SDC2_BASE (PERIPH_SS_BASE + 0x000A4000)
+#define MSM_SDC2_SDHCI_BASE (PERIPH_SS_BASE + 0x000A4900)
+#define MSM_SDC4_BASE (PERIPH_SS_BASE + 0x000E4000)
+#define MSM_SDC4_SDHCI_BASE (PERIPH_SS_BASE + 0x000E4900)
+
+#define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x0011D000)
+#define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x0011E000)
+#define BLSP1_UART2_BASE (PERIPH_SS_BASE + 0x0011F000)
+#define BLSP1_UART3_BASE (PERIPH_SS_BASE + 0x00120000)
+#define BLSP1_UART4_BASE (PERIPH_SS_BASE + 0x00121000)
+#define BLSP1_UART5_BASE (PERIPH_SS_BASE + 0x00122000)
+
+/* Addresses below this point needs to be verified.
+ * Included only for compilation purposes.
+ */
+#define MSM_USB_BASE (PERIPH_SS_BASE + 0x00255000)
+
+#define CLK_CTL_BASE 0xFC400000
+
+#define GCC_WDOG_DEBUG (CLK_CTL_BASE + 0x00001780)
+
+#define USB_HS_BCR (CLK_CTL_BASE + 0x480)
+
+#define SPMI_BASE 0xFC4C0000
+#define SPMI_GENI_BASE (SPMI_BASE + 0xA000)
+#define SPMI_PIC_BASE (SPMI_BASE + 0xB000)
+
+#define MSM_CE2_BAM_BASE 0xFD444000
+#define MSM_CE2_BASE 0xFD45A000
+#define USB2_PHY_SEL 0xFD4AB000
+
+#define TLMM_BASE_ADDR 0xFD510000
+#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10)
+#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x1004 + (x)*0x10)
+
+#define MPM2_MPM_CTRL_BASE 0xFC4A1000
+#define MPM2_MPM_PS_HOLD 0xFC4AB000
+#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0xFC4A3000
+
+/* DRV strength for sdcc */
+#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x00002044)
+
+/* SDHCI */
+#define SDCC_MCI_HC_MODE (PERIPH_SS_BASE + 0x00024078)
+#define SDCC_HC_PWRCTL_MASK_REG (PERIPH_SS_BASE + 0x000240E0)
+#define SDCC_HC_PWRCTL_CTL_REG (PERIPH_SS_BASE + 0x000240E8)
+#endif
diff --git a/platform/apq8084/include/platform/irqs.h b/platform/apq8084/include/platform/irqs.h
new file mode 100644
index 0000000..9db58bb
--- /dev/null
+++ b/platform/apq8084/include/platform/irqs.h
@@ -0,0 +1,66 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef __IRQS_APQ8084_H
+#define __IRQS_APQ8084_H
+
+/* MSM ACPU Interrupt Numbers */
+
+/* 0-15: STI/SGI (software triggered/generated interrupts)
+ * 16-31: PPI (private peripheral interrupts)
+ * 32+: SPI (shared peripheral interrupts)
+ */
+
+#define GIC_PPI_START 16
+#define GIC_SPI_START 32
+
+#define INT_QTMR_NON_SECURE_PHY_TIMER_EXP (GIC_PPI_START + 3)
+#define INT_QTMR_VIRTUAL_TIMER_EXP (GIC_PPI_START + 4)
+
+#define INT_QTMR_FRM_0_PHYSICAL_TIMER_EXP (GIC_SPI_START + 8)
+
+#define USB1_HS_BAM_IRQ (GIC_SPI_START + 135)
+#define USB1_HS_IRQ (GIC_SPI_START + 134)
+#define USB2_IRQ (GIC_SPI_START + 141)
+#define USB1_IRQ (GIC_SPI_START + 142)
+
+/* Retrofit universal macro names */
+#define INT_USB_HS USB1_HS_IRQ
+
+#define EE0_KRAIT_HLOS_SPMI_PERIPH_IRQ (GIC_SPI_START + 190)
+
+#define NR_MSM_IRQS 256
+#define NR_GPIO_IRQS 173
+#define NR_BOARD_IRQS 0
+
+#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + \
+ NR_BOARD_IRQS)
+
+#define SDCC_PWRCTRL_IRQ (GIC_SPI_START + 138)
+#endif /* __IRQS_APQ8084_H */
diff --git a/platform/apq8084/platform.c b/platform/apq8084/platform.c
new file mode 100644
index 0000000..d31a519
--- /dev/null
+++ b/platform/apq8084/platform.c
@@ -0,0 +1,61 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <reg.h>
+#include <platform/iomap.h>
+#include <qgic.h>
+#include <qtimer.h>
+#include <platform/clock.h>
+#include <mmu.h>
+#include <arch/arm/mmu.h>
+#include <smem.h>
+#include <board.h>
+
+void platform_early_init(void)
+{
+ /* Uncomment board_init when bootchain is available. */
+ /* board_init(); */
+ platform_clock_init();
+ qgic_init();
+ qtimer_init();
+}
+
+void platform_init(void)
+{
+ dprintf(INFO, "platform_init()\n");
+}
+
+void platform_uninit(void)
+{
+#if DISPLAY_SPLASH_SCREEN
+ display_shutdown();
+#endif
+
+ qtimer_uninit();
+}
diff --git a/platform/apq8084/rules.mk b/platform/apq8084/rules.mk
new file mode 100644
index 0000000..4738c69
--- /dev/null
+++ b/platform/apq8084/rules.mk
@@ -0,0 +1,29 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+ARCH := arm
+ARM_CPU := cortex-a8
+CPU := generic
+
+DEFINES += ARM_CPU_CORE_KRAIT
+
+MMC_SLOT := 1
+
+DEFINES += PERIPH_BLK_BLSP=1
+DEFINES += WITH_CPU_EARLY_INIT=0 WITH_CPU_WARM_BOOT=0 \
+ MMC_SLOT=$(MMC_SLOT)
+DEFINES += TZ_SAVE_KERNEL_HASH
+
+INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared/include
+
+DEVS += fbcon
+MODULES += dev/fbcon
+
+OBJS += \
+ $(LOCAL_DIR)/platform.o \
+ $(LOCAL_DIR)/acpuclock.o \
+ $(LOCAL_DIR)/apq8084-clock.o \
+ $(LOCAL_DIR)/gpio.o
+
+LINKER_SCRIPT += $(BUILDDIR)/system-onesegment.ld
+
+include platform/msm_shared/rules.mk
diff --git a/platform/fsm9900/acpuclock.c b/platform/fsm9900/acpuclock.c
new file mode 100644
index 0000000..f92f940
--- /dev/null
+++ b/platform/fsm9900/acpuclock.c
@@ -0,0 +1,338 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <err.h>
+#include <assert.h>
+#include <debug.h>
+#include <reg.h>
+#include <platform/timer.h>
+#include <platform/iomap.h>
+#include <mmc.h>
+#include <clock.h>
+#include <platform/clock.h>
+#include <blsp_qup.h>
+
+void hsusb_clock_init(void)
+{
+ int ret;
+ struct clk *iclk, *cclk;
+
+ ret = clk_get_set_enable("usb_iface_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_iface_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb_core_clk", 75000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_core_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ mdelay(20);
+
+ iclk = clk_get("usb_iface_clk");
+ cclk = clk_get("usb_core_clk");
+
+ clk_disable(iclk);
+ clk_disable(cclk);
+
+ mdelay(20);
+
+ /* Start the block reset for usb */
+ writel(1, USB_HS_BCR);
+
+ mdelay(20);
+
+ /* Take usb block out of reset */
+ writel(0, USB_HS_BCR);
+
+ mdelay(20);
+
+ ret = clk_enable(iclk);
+
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_enable(cclk);
+
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+}
+
+void clock_init_mmc(uint32_t interface)
+{
+ char clk_name[64];
+ int ret;
+
+ snprintf(clk_name, 64, "sdc%u_iface_clk", interface);
+
+ /* enable interface clock */
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set sdc1_iface_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+}
+
+/* Configure MMC clock */
+void clock_config_mmc(uint32_t interface, uint32_t freq)
+{
+ int ret;
+ uint32_t reg;
+ char clk_name[64];
+
+ snprintf(clk_name, 64, "sdc%u_core_clk", interface);
+
+ /* Disalbe MCI_CLK before changing the sdcc clock */
+#ifndef MMC_SDHCI_SUPPORT
+ mmc_boot_mci_clk_disable();
+#endif
+
+ if(freq == MMC_CLK_400KHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 400000, 1);
+ }
+ else if(freq == MMC_CLK_50MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 50000000, 1);
+ }
+ else if(freq == MMC_CLK_96MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 100000000, 1);
+ }
+ else if(freq == MMC_CLK_200MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 200000000, 1);
+ }
+ else
+ {
+ dprintf(CRITICAL, "sdc frequency (%d) is not supported\n", freq);
+ ASSERT(0);
+ }
+
+
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set sdc1_core_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Enalbe MCI clock */
+#ifndef MMC_SDHCI_SUPPORT
+ mmc_boot_mci_clk_enable();
+#endif
+}
+
+/* Configure UART clock based on the UART block id*/
+void clock_config_uart_dm(uint8_t id)
+{
+ int ret;
+ char str[256];
+
+ sprintf(str, "uart%d_iface_clk", id);
+ ret = clk_get_set_enable(str, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set uart2_iface_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ sprintf(str, "uart%d_core_clk", id);
+ ret = clk_get_set_enable(str, 7372800, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set uart1_core_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+}
+
+/* Function to asynchronously reset CE.
+ * Function assumes that all the CE clocks are off.
+ */
+static void ce_async_reset(uint8_t instance)
+{
+ if (instance == 1)
+ {
+ /* TODO: Add support for instance 1. */
+ dprintf(CRITICAL, "CE instance not supported instance = %d", instance);
+ ASSERT(0);
+ }
+ else if (instance == 2)
+ {
+ /* Start the block reset for CE */
+ writel(1, GCC_CE2_BCR);
+
+ udelay(2);
+
+ /* Take CE block out of reset */
+ writel(0, GCC_CE2_BCR);
+
+ udelay(2);
+ }
+ else
+ {
+ dprintf(CRITICAL, "CE instance not supported instance = %d", instance);
+ ASSERT(0);
+ }
+}
+
+void clock_ce_enable(uint8_t instance)
+{
+ int ret;
+ char clk_name[64];
+
+ snprintf(clk_name, 64, "ce%u_src_clk", instance);
+ ret = clk_get_set_enable(clk_name, 100000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set ce_src_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ snprintf(clk_name, 64, "ce%u_core_clk", instance);
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set ce_core_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ snprintf(clk_name, 64, "ce%u_ahb_clk", instance);
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set ce_ahb_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ snprintf(clk_name, 64, "ce%u_axi_clk", instance);
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set ce_axi_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Wait for 48 * #pipes cycles.
+ * This is necessary as immediately after an access control reset (boot up)
+ * or a debug re-enable, the Crypto core sequentially clears its internal
+ * pipe key storage memory. If pipe key initialization writes are attempted
+ * during this time, they may be overwritten by the internal clearing logic.
+ */
+ udelay(1);
+}
+
+void clock_ce_disable(uint8_t instance)
+{
+ struct clk *ahb_clk;
+ struct clk *cclk;
+ struct clk *axi_clk;
+ struct clk *src_clk;
+ char clk_name[64];
+
+ snprintf(clk_name, 64, "ce%u_src_clk", instance);
+ src_clk = clk_get(clk_name);
+
+ snprintf(clk_name, 64, "ce%u_ahb_clk", instance);
+ ahb_clk = clk_get(clk_name);
+
+ snprintf(clk_name, 64, "ce%u_axi_clk", instance);
+ axi_clk = clk_get(clk_name);
+
+ snprintf(clk_name, 64, "ce%u_core_clk", instance);
+ cclk = clk_get(clk_name);
+
+ clk_disable(ahb_clk);
+ clk_disable(axi_clk);
+ clk_disable(cclk);
+ clk_disable(src_clk);
+
+ /* Some delay for the clocks to stabalize. */
+ udelay(1);
+}
+
+void clock_config_ce(uint8_t instance)
+{
+ /* Need to enable the clock before disabling since the clk_disable()
+ * has a check to default to nop when the clk_enable() is not called
+ * on that particular clock.
+ */
+ clock_ce_enable(instance);
+
+ clock_ce_disable(instance);
+
+ ce_async_reset(instance);
+
+ clock_ce_enable(instance);
+
+}
+
+void clock_config_blsp_i2c(uint8_t blsp_id, uint8_t qup_id)
+{
+ uint8_t ret = 0;
+ char clk_name[64];
+
+ struct clk *qup_clk;
+
+ snprintf(clk_name, 64, "blsp%u_ahb_clk", blsp_id);
+
+ ret = clk_get_set_enable(clk_name, 0 , 1);
+
+ if (ret) {
+ dprintf(CRITICAL, "Failed to enable %s clock\n", clk_name);
+ return;
+ }
+
+ snprintf(clk_name, 64, "blsp%u_qup%u_i2c_apps_clk", blsp_id,
+ (qup_id + 1));
+
+ qup_clk = clk_get(clk_name);
+
+ if (!qup_clk) {
+ dprintf(CRITICAL, "Failed to get %s\n", clk_name);
+ return;
+ }
+
+ ret = clk_enable(qup_clk);
+
+ if (ret) {
+ dprintf(CRITICAL, "Failed to enable %s\n", clk_name);
+ return;
+ }
+}
diff --git a/platform/fsm9900/fsm9900-clock.c b/platform/fsm9900/fsm9900-clock.c
new file mode 100644
index 0000000..a9955fc
--- /dev/null
+++ b/platform/fsm9900/fsm9900-clock.c
@@ -0,0 +1,815 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <reg.h>
+#include <err.h>
+#include <clock.h>
+#include <clock_pll.h>
+#include <clock_lib2.h>
+#include <platform/clock.h>
+#include <platform/iomap.h>
+
+
+/* Mux source select values */
+#define cxo_source_val 0
+#define gpll0_source_val 1
+#define cxo_mm_source_val 0
+#define mmpll0_mm_source_val 1
+#define mmpll1_mm_source_val 2
+#define mmpll3_mm_source_val 3
+#define gpll0_mm_source_val 5
+
+struct clk_freq_tbl rcg_dummy_freq = F_END;
+
+
+/* Clock Operations */
+static struct clk_ops clk_ops_branch =
+{
+ .enable = clock_lib2_branch_clk_enable,
+ .disable = clock_lib2_branch_clk_disable,
+ .set_rate = clock_lib2_branch_set_rate,
+};
+
+static struct clk_ops clk_ops_rcg_mnd =
+{
+ .enable = clock_lib2_rcg_enable,
+ .set_rate = clock_lib2_rcg_set_rate,
+};
+
+static struct clk_ops clk_ops_rcg =
+{
+ .enable = clock_lib2_rcg_enable,
+ .set_rate = clock_lib2_rcg_set_rate,
+};
+
+static struct clk_ops clk_ops_cxo =
+{
+ .enable = cxo_clk_enable,
+ .disable = cxo_clk_disable,
+};
+
+static struct clk_ops clk_ops_pll_vote =
+{
+ .enable = pll_vote_clk_enable,
+ .disable = pll_vote_clk_disable,
+ .auto_off = pll_vote_clk_disable,
+ .is_enabled = pll_vote_clk_is_enabled,
+};
+
+static struct clk_ops clk_ops_vote =
+{
+ .enable = clock_lib2_vote_clk_enable,
+ .disable = clock_lib2_vote_clk_disable,
+};
+
+/* Clock Sources */
+static struct fixed_clk cxo_clk_src =
+{
+ .c = {
+ .rate = 19200000,
+ .dbg_name = "cxo_clk_src",
+ .ops = &clk_ops_cxo,
+ },
+};
+
+static struct pll_vote_clk gpll0_clk_src =
+{
+ .en_reg = (void *) APCS_GPLL_ENA_VOTE,
+ .en_mask = BIT(0),
+ .status_reg = (void *) GPLL0_STATUS,
+ .status_mask = BIT(17),
+ .parent = &cxo_clk_src.c,
+
+ .c = {
+ .rate = 600000000,
+ .dbg_name = "gpll0_clk_src",
+ .ops = &clk_ops_pll_vote,
+ },
+};
+
+/* SDCC Clocks */
+static struct clk_freq_tbl ftbl_gcc_sdcc1_2_apps_clk[] =
+{
+ F( 144000, cxo, 16, 3, 25),
+ F( 400000, cxo, 12, 1, 4),
+ F( 20000000, gpll0, 15, 1, 2),
+ F( 25000000, gpll0, 12, 1, 2),
+ F( 50000000, gpll0, 12, 0, 0),
+ F(100000000, gpll0, 6, 0, 0),
+ F(200000000, gpll0, 3, 0, 0),
+ F_END
+};
+
+static struct rcg_clk sdcc1_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) SDCC1_CMD_RCGR,
+ .cfg_reg = (uint32_t *) SDCC1_CFG_RCGR,
+ .m_reg = (uint32_t *) SDCC1_M,
+ .n_reg = (uint32_t *) SDCC1_N,
+ .d_reg = (uint32_t *) SDCC1_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "sdc1_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_sdcc1_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) SDCC1_APPS_CBCR,
+ .parent = &sdcc1_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_sdcc1_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_sdcc1_ahb_clk =
+{
+ .cbcr_reg = (uint32_t *) SDCC1_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_sdcc1_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct rcg_clk sdcc2_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) SDCC2_CMD_RCGR,
+ .cfg_reg = (uint32_t *) SDCC2_CFG_RCGR,
+ .m_reg = (uint32_t *) SDCC2_M,
+ .n_reg = (uint32_t *) SDCC2_N,
+ .d_reg = (uint32_t *) SDCC2_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "sdc2_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_sdcc2_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) SDCC2_APPS_CBCR,
+ .parent = &sdcc2_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_sdcc2_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_sdcc2_ahb_clk =
+{
+ .cbcr_reg = (uint32_t *) SDCC2_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_sdcc2_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+/* UART Clocks */
+static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] =
+{
+ F( 3686400, gpll0, 1, 96, 15625),
+ F( 7372800, gpll0, 1, 192, 15625),
+ F(14745600, gpll0, 1, 384, 15625),
+ F(16000000, gpll0, 5, 2, 15),
+ F(19200000, cxo, 1, 0, 0),
+ F(24000000, gpll0, 5, 1, 5),
+ F(32000000, gpll0, 1, 4, 75),
+ F(40000000, gpll0, 15, 0, 0),
+ F(46400000, gpll0, 1, 29, 375),
+ F(48000000, gpll0, 12.5, 0, 0),
+ F(51200000, gpll0, 1, 32, 375),
+ F(56000000, gpll0, 1, 7, 75),
+ F(58982400, gpll0, 1, 1536, 15625),
+ F(60000000, gpll0, 10, 0, 0),
+ F_END
+};
+
+static struct rcg_clk blsp1_uart0_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) BLSP1_UART0_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP1_UART0_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP1_UART0_APPS_M,
+ .n_reg = (uint32_t *) BLSP1_UART0_APPS_N,
+ .d_reg = (uint32_t *) BLSP1_UART0_APPS_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "blsp1_uart0_apps_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_blsp1_uart0_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) BLSP1_UART0_APPS_CBCR,
+ .parent = &blsp1_uart0_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_uart0_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct rcg_clk blsp1_uart1_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) BLSP1_UART1_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP1_UART1_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP1_UART1_APPS_M,
+ .n_reg = (uint32_t *) BLSP1_UART1_APPS_N,
+ .d_reg = (uint32_t *) BLSP1_UART1_APPS_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "blsp1_uart1_apps_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_blsp1_uart1_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) BLSP1_UART1_APPS_CBCR,
+ .parent = &blsp1_uart1_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_uart1_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct rcg_clk blsp1_uart2_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP1_UART2_APPS_M,
+ .n_reg = (uint32_t *) BLSP1_UART2_APPS_N,
+ .d_reg = (uint32_t *) BLSP1_UART2_APPS_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "blsp1_uart2_apps_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_blsp1_uart2_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) BLSP1_UART2_APPS_CBCR,
+ .parent = &blsp1_uart2_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_uart2_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct rcg_clk blsp1_uart3_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) BLSP1_UART3_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP1_UART3_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP1_UART3_APPS_M,
+ .n_reg = (uint32_t *) BLSP1_UART3_APPS_N,
+ .d_reg = (uint32_t *) BLSP1_UART3_APPS_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "blsp1_uart3_apps_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_blsp1_uart3_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) BLSP1_UART3_APPS_CBCR,
+ .parent = &blsp1_uart3_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_uart3_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct rcg_clk blsp1_uart4_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) BLSP1_UART4_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP1_UART4_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP1_UART4_APPS_M,
+ .n_reg = (uint32_t *) BLSP1_UART4_APPS_N,
+ .d_reg = (uint32_t *) BLSP1_UART4_APPS_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "blsp1_uart4_apps_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_blsp1_uart4_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) BLSP1_UART4_APPS_CBCR,
+ .parent = &blsp1_uart4_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_uart4_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct rcg_clk blsp1_uart5_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) BLSP1_UART5_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP1_UART5_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP1_UART5_APPS_M,
+ .n_reg = (uint32_t *) BLSP1_UART5_APPS_N,
+ .d_reg = (uint32_t *) BLSP1_UART5_APPS_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "blsp1_uart5_apps_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_blsp1_uart5_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) BLSP1_UART5_APPS_CBCR,
+ .parent = &blsp1_uart5_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_uart5_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct rcg_clk blsp2_uart0_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) BLSP2_UART0_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP2_UART0_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP2_UART0_APPS_M,
+ .n_reg = (uint32_t *) BLSP2_UART0_APPS_N,
+ .d_reg = (uint32_t *) BLSP2_UART0_APPS_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "blsp2_uart0_apps_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_blsp2_uart0_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) BLSP2_UART0_APPS_CBCR,
+ .parent = &blsp2_uart0_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp2_uart0_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct rcg_clk blsp2_uart1_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) BLSP2_UART1_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP2_UART1_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP2_UART1_APPS_M,
+ .n_reg = (uint32_t *) BLSP2_UART1_APPS_N,
+ .d_reg = (uint32_t *) BLSP2_UART1_APPS_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "blsp2_uart1_apps_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_blsp2_uart1_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) BLSP2_UART1_APPS_CBCR,
+ .parent = &blsp2_uart1_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp2_uart1_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct rcg_clk blsp2_uart2_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) BLSP2_UART2_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP2_UART2_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP2_UART2_APPS_M,
+ .n_reg = (uint32_t *) BLSP2_UART2_APPS_N,
+ .d_reg = (uint32_t *) BLSP2_UART2_APPS_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "blsp2_uart2_apps_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_blsp2_uart2_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) BLSP2_UART2_APPS_CBCR,
+ .parent = &blsp2_uart2_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp2_uart2_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct rcg_clk blsp2_uart3_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) BLSP2_UART3_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP2_UART3_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP2_UART3_APPS_M,
+ .n_reg = (uint32_t *) BLSP2_UART3_APPS_N,
+ .d_reg = (uint32_t *) BLSP2_UART3_APPS_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "blsp2_uart3_apps_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_blsp2_uart3_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) BLSP2_UART3_APPS_CBCR,
+ .parent = &blsp2_uart3_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp2_uart3_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct rcg_clk blsp2_uart4_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) BLSP2_UART4_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP2_UART4_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP2_UART4_APPS_M,
+ .n_reg = (uint32_t *) BLSP2_UART4_APPS_N,
+ .d_reg = (uint32_t *) BLSP2_UART4_APPS_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "blsp2_uart4_apps_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_blsp2_uart4_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) BLSP2_UART4_APPS_CBCR,
+ .parent = &blsp2_uart4_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp2_uart4_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct rcg_clk blsp2_uart5_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) BLSP2_UART5_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP2_UART5_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP2_UART5_APPS_M,
+ .n_reg = (uint32_t *) BLSP2_UART5_APPS_N,
+ .d_reg = (uint32_t *) BLSP2_UART5_APPS_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "blsp2_uart5_apps_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_blsp2_uart5_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) BLSP2_UART5_APPS_CBCR,
+ .parent = &blsp2_uart5_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp2_uart5_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct vote_clk gcc_blsp1_ahb_clk = {
+ .cbcr_reg = (uint32_t *) BLSP1_AHB_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(17),
+
+ .c = {
+ .dbg_name = "gcc_blsp1_ahb_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+static struct vote_clk gcc_blsp2_ahb_clk = {
+ .cbcr_reg = (uint32_t *) BLSP2_AHB_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(15),
+
+ .c = {
+ .dbg_name = "gcc_blsp2_ahb_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+/* USB Clocks */
+static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] =
+{
+ F(75000000, gpll0, 8, 0, 0),
+ F_END
+};
+
+static struct rcg_clk usb_hs_system_clk_src =
+{
+ .cmd_reg = (uint32_t *) USB_HS_SYSTEM_CMD_RCGR,
+ .cfg_reg = (uint32_t *) USB_HS_SYSTEM_CFG_RCGR,
+
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_usb_hs_system_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "usb_hs_system_clk",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_usb_hs_system_clk =
+{
+ .cbcr_reg = (uint32_t *) USB_HS_SYSTEM_CBCR,
+ .parent = &usb_hs_system_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_usb_hs_system_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_usb_hs_ahb_clk =
+{
+ .cbcr_reg = (uint32_t *) USB_HS_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_usb_hs_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+/* CE Clocks */
+static struct clk_freq_tbl ftbl_gcc_ce2_clk[] = {
+ F( 50000000, gpll0, 12, 0, 0),
+ F(100000000, gpll0, 6, 0, 0),
+ F_END
+};
+
+static struct rcg_clk ce2_clk_src = {
+ .cmd_reg = (uint32_t *) GCC_CE2_CMD_RCGR,
+ .cfg_reg = (uint32_t *) GCC_CE2_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_ce2_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "ce2_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct vote_clk gcc_ce2_clk = {
+ .cbcr_reg = (uint32_t *) GCC_CE2_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(2),
+
+ .c = {
+ .dbg_name = "gcc_ce2_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+static struct vote_clk gcc_ce2_ahb_clk = {
+ .cbcr_reg = (uint32_t *) GCC_CE2_AHB_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(0),
+
+ .c = {
+ .dbg_name = "gcc_ce2_ahb_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+static struct vote_clk gcc_ce2_axi_clk = {
+ .cbcr_reg = (uint32_t *) GCC_CE2_AXI_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(1),
+
+ .c = {
+ .dbg_name = "gcc_ce2_axi_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = {
+ F( 50000000, gpll0, 12, 0, 0),
+ F(100000000, gpll0, 6, 0, 0),
+ F_END
+};
+
+static struct rcg_clk ce1_clk_src = {
+ .cmd_reg = (uint32_t *) GCC_CE1_CMD_RCGR,
+ .cfg_reg = (uint32_t *) GCC_CE1_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_ce1_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "ce1_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct vote_clk gcc_ce1_clk = {
+ .cbcr_reg = (uint32_t *) GCC_CE1_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(5),
+
+ .c = {
+ .dbg_name = "gcc_ce1_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+static struct vote_clk gcc_ce1_ahb_clk = {
+ .cbcr_reg = (uint32_t *) GCC_CE1_AHB_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(3),
+
+ .c = {
+ .dbg_name = "gcc_ce1_ahb_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+static struct vote_clk gcc_ce1_axi_clk = {
+ .cbcr_reg = (uint32_t *) GCC_CE1_AXI_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(4),
+
+ .c = {
+ .dbg_name = "gcc_ce1_axi_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+
+struct branch_clk gcc_blsp2_qup5_i2c_apps_clk = {
+ .cbcr_reg = BLSP2_QUP5_I2C_APPS_CBCR,
+ .parent = &cxo_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp2_qup5_i2c_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+/* Clock lookup table */
+static struct clk_lookup msm_clocks_fsm9900[] =
+{
+ CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
+ CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c),
+
+ CLK_LOOKUP("sdc2_iface_clk", gcc_sdcc2_ahb_clk.c),
+ CLK_LOOKUP("sdc2_core_clk", gcc_sdcc2_apps_clk.c),
+
+ CLK_LOOKUP("uart0_iface_clk", gcc_blsp1_ahb_clk.c),
+ CLK_LOOKUP("uart0_core_clk", gcc_blsp1_uart0_apps_clk.c),
+ CLK_LOOKUP("uart1_iface_clk", gcc_blsp1_ahb_clk.c),
+ CLK_LOOKUP("uart1_core_clk", gcc_blsp1_uart1_apps_clk.c),
+ CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c),
+ CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c),
+ CLK_LOOKUP("uart3_iface_clk", gcc_blsp1_ahb_clk.c),
+ CLK_LOOKUP("uart3_core_clk", gcc_blsp1_uart3_apps_clk.c),
+ CLK_LOOKUP("uart4_iface_clk", gcc_blsp1_ahb_clk.c),
+ CLK_LOOKUP("uart4_core_clk", gcc_blsp1_uart4_apps_clk.c),
+ CLK_LOOKUP("uart5_iface_clk", gcc_blsp1_ahb_clk.c),
+ CLK_LOOKUP("uart5_core_clk", gcc_blsp1_uart5_apps_clk.c),
+ CLK_LOOKUP("uart6_iface_clk", gcc_blsp2_ahb_clk.c),
+ CLK_LOOKUP("uart6_core_clk", gcc_blsp2_uart0_apps_clk.c),
+ CLK_LOOKUP("uart7_iface_clk", gcc_blsp2_ahb_clk.c),
+ CLK_LOOKUP("uart7_core_clk", gcc_blsp2_uart1_apps_clk.c),
+ CLK_LOOKUP("uart8_iface_clk", gcc_blsp2_ahb_clk.c),
+ CLK_LOOKUP("uart8_core_clk", gcc_blsp2_uart2_apps_clk.c),
+ CLK_LOOKUP("uart9_iface_clk", gcc_blsp2_ahb_clk.c),
+ CLK_LOOKUP("uart9_core_clk", gcc_blsp2_uart3_apps_clk.c),
+ CLK_LOOKUP("uart10_iface_clk", gcc_blsp2_ahb_clk.c),
+ CLK_LOOKUP("uart10_core_clk", gcc_blsp2_uart4_apps_clk.c),
+ CLK_LOOKUP("uart11_iface_clk", gcc_blsp2_ahb_clk.c),
+ CLK_LOOKUP("uart11_core_clk", gcc_blsp2_uart5_apps_clk.c),
+
+ CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c),
+ CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c),
+
+ CLK_LOOKUP("ce2_ahb_clk", gcc_ce2_ahb_clk.c),
+ CLK_LOOKUP("ce2_axi_clk", gcc_ce2_axi_clk.c),
+ CLK_LOOKUP("ce2_core_clk", gcc_ce2_clk.c),
+ CLK_LOOKUP("ce2_src_clk", ce2_clk_src.c),
+
+ CLK_LOOKUP("ce1_ahb_clk", gcc_ce1_ahb_clk.c),
+ CLK_LOOKUP("ce1_axi_clk", gcc_ce1_axi_clk.c),
+ CLK_LOOKUP("ce1_core_clk", gcc_ce1_clk.c),
+ CLK_LOOKUP("ce1_src_clk", ce1_clk_src.c),
+
+
+ CLK_LOOKUP("blsp2_ahb_clk", gcc_blsp2_ahb_clk.c),
+ CLK_LOOKUP("blsp2_qup5_i2c_apps_clk", gcc_blsp2_qup5_i2c_apps_clk.c),
+};
+
+
+void platform_clock_init(void)
+{
+ clk_init(msm_clocks_fsm9900, ARRAY_SIZE(msm_clocks_fsm9900));
+}
diff --git a/platform/fsm9900/gpio.c b/platform/fsm9900/gpio.c
new file mode 100644
index 0000000..bbe4beb
--- /dev/null
+++ b/platform/fsm9900/gpio.c
@@ -0,0 +1,109 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <reg.h>
+#include <platform/iomap.h>
+#include <platform/gpio.h>
+#include <gsbi.h>
+#include <blsp_qup.h>
+
+void gpio_tlmm_config(uint32_t gpio, uint8_t func,
+ uint8_t dir, uint8_t pull,
+ uint8_t drvstr, uint32_t enable)
+{
+ uint32_t val = 0;
+ val |= pull;
+ val |= func << 2;
+ val |= drvstr << 6;
+ val |= enable << 9;
+ writel(val, (unsigned int *)GPIO_CONFIG_ADDR(gpio));
+ return;
+}
+
+void gpio_set(uint32_t gpio, uint32_t dir)
+{
+ writel(dir, (unsigned int *)GPIO_IN_OUT_ADDR(gpio));
+ return;
+}
+
+void gpio_config_uart_dm(uint8_t id)
+{
+ static struct {
+ unsigned int gpio_tx;
+ unsigned int gpio_rx;
+ } gpio_table[] = {
+ { 0, 1 },
+ { 4, 5 },
+ { 8, 9 },
+ { 12, 13 },
+ { 16, 17 },
+ { 20, 21 },
+ { 24, 25 },
+ { 28, 29 },
+ { 32, 33 },
+ { 36, 37 },
+ };
+
+ if (id >= ARRAY_SIZE(gpio_table))
+ return;
+
+ /* configure rx gpio */
+ gpio_tlmm_config(gpio_table[id].gpio_rx, 2, GPIO_INPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+
+ /* configure tx gpio */
+ gpio_tlmm_config(gpio_table[id].gpio_tx, 2, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+}
+
+void gpio_config_blsp_i2c(uint8_t blsp_id, uint8_t qup_id)
+{
+ if (blsp_id == BLSP_ID_2) {
+ switch (qup_id) {
+ case QUP_ID_4:
+ gpio_tlmm_config(83, 3, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_6MA, GPIO_DISABLE);
+ gpio_tlmm_config(84, 3, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_6MA, GPIO_DISABLE);
+ break;
+ default:
+ dprintf(CRITICAL, "Configure gpios for QUP instance: %u\n",
+ qup_id);
+ ASSERT(0);
+ };
+ }
+ else if (blsp_id == BLSP_ID_1) {
+ switch (qup_id) {
+ default:
+ dprintf(CRITICAL, "Configure gpios for QUP instance: %u\n",
+ qup_id);
+ ASSERT(0);
+ };
+ }
+}
diff --git a/platform/fsm9900/include/platform/clock.h b/platform/fsm9900/include/platform/clock.h
new file mode 100644
index 0000000..e19920d
--- /dev/null
+++ b/platform/fsm9900/include/platform/clock.h
@@ -0,0 +1,47 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSM9900_CLOCK_H
+#define __FSM9900_CLOCK_H
+
+#include <clock.h>
+#include <clock_lib2.h>
+
+#define UART_DM_CLK_RX_TX_BIT_RATE 0xFF
+
+void platform_clock_init(void);
+
+void clock_init_mmc(uint32_t interface);
+void clock_config_mmc(uint32_t interface, uint32_t freq);
+void clock_config_uart_dm(uint8_t id);
+void hsusb_clock_init(void);
+void clock_config_ce(uint8_t instance);
+void clock_ce_enable(uint8_t instance);
+void clock_ce_disable(uint8_t instance);
+
+#endif
diff --git a/platform/fsm9900/include/platform/gpio.h b/platform/fsm9900/include/platform/gpio.h
new file mode 100644
index 0000000..334ba7c
--- /dev/null
+++ b/platform/fsm9900/include/platform/gpio.h
@@ -0,0 +1,60 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __PLATFORM_FSM9900_GPIO_H
+#define __PLATFORM_FSM9900_GPIO_H
+
+#include <gpio.h>
+
+/* GPIO TLMM: Direction */
+#define GPIO_INPUT 0
+#define GPIO_OUTPUT 1
+
+/* GPIO TLMM: Pullup/Pulldown */
+#define GPIO_NO_PULL 0
+#define GPIO_PULL_DOWN 1
+#define GPIO_KEEPER 2
+#define GPIO_PULL_UP 3
+
+/* GPIO TLMM: Drive Strength */
+#define GPIO_2MA 0
+#define GPIO_4MA 1
+#define GPIO_6MA 2
+#define GPIO_8MA 3
+#define GPIO_10MA 4
+#define GPIO_12MA 5
+#define GPIO_14MA 6
+#define GPIO_16MA 7
+
+/* GPIO TLMM: Status */
+#define GPIO_ENABLE 0
+#define GPIO_DISABLE 1
+
+void gpio_config_uart_dm(uint8_t id);
+void gpio_config_blsp_i2c(uint8_t, uint8_t);
+#endif
diff --git a/platform/fsm9900/include/platform/iomap.h b/platform/fsm9900/include/platform/iomap.h
new file mode 100644
index 0000000..4cc017b
--- /dev/null
+++ b/platform/fsm9900/include/platform/iomap.h
@@ -0,0 +1,269 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PLATFORM_FSM9900_IOMAP_H_
+#define _PLATFORM_FSM9900_IOMAP_H_
+
+#define MSM_IOMAP_BASE 0xF9000000
+#define MSM_IOMAP_END 0xFEFFFFFF
+
+#define SDRAM_START_ADDR 0x00000000
+#define SDRAM_SEC_BANK_START_ADDR 0x10000000
+
+#define MSM_SHARED_BASE 0x0FA00000
+
+#define RPM_MSG_RAM_BASE 0xFC42B000
+#define SYSTEM_IMEM_BASE 0xFE800000
+#define MSM_SHARED_IMEM_BASE 0xFE805000
+
+#define RESTART_REASON_ADDR (RPM_MSG_RAM_BASE + 0x65C)
+#define RESTART_REASON_ADDR_V2 (MSM_SHARED_IMEM_BASE + 0x65C)
+#define DLOAD_MODE_ADDR_V2 (MSM_SHARED_IMEM_BASE + 0x0)
+#define EMERGENCY_DLOAD_MODE_ADDR_V2 (MSM_SHARED_IMEM_BASE + 0xFE0)
+
+#define KPSS_BASE 0xF9000000
+
+#define MSM_GIC_DIST_BASE KPSS_BASE
+#define MSM_GIC_CPU_BASE (KPSS_BASE + 0x2000)
+#define APCS_KPSS_ACS_BASE (KPSS_BASE + 0x00008000)
+#define APCS_APC_KPSS_PLL_BASE (KPSS_BASE + 0x0000A000)
+#define APCS_KPSS_CFG_BASE (KPSS_BASE + 0x00010000)
+#define APCS_KPSS_WDT_BASE (KPSS_BASE + 0x00017000)
+#define KPSS_APCS_QTMR_AC_BASE (KPSS_BASE + 0x00020000)
+#define KPSS_APCS_F0_QTMR_V1_BASE (KPSS_BASE + 0x00021000)
+#define QTMR_BASE KPSS_APCS_F0_QTMR_V1_BASE
+
+#define PERIPH_SS_BASE 0xF9800000
+
+#define MSM_SDC1_BAM_BASE (PERIPH_SS_BASE + 0x00004000)
+#define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00024000)
+#define MSM_SDC1_DML_BASE (PERIPH_SS_BASE + 0x00024800)
+#define MSM_SDC1_SDHCI_BASE (PERIPH_SS_BASE + 0x00024900)
+#define MSM_SDC2_BAM_BASE (PERIPH_SS_BASE + 0x00084000)
+#define MSM_SDC2_BASE (PERIPH_SS_BASE + 0x000A4000)
+#define MSM_SDC2_DML_BASE (PERIPH_SS_BASE + 0x000A4800)
+#define MSM_SDC2_SDHCI_BASE (PERIPH_SS_BASE + 0x000A4900)
+
+/* BLSP1_UART[0:5] */
+#define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x0011D000)
+#define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x0011E000)
+#define BLSP1_UART2_BASE (PERIPH_SS_BASE + 0x0011F000)
+#define BLSP1_UART3_BASE (PERIPH_SS_BASE + 0x00120000)
+#define BLSP1_UART4_BASE (PERIPH_SS_BASE + 0x00121000)
+#define BLSP1_UART5_BASE (PERIPH_SS_BASE + 0x00122000)
+
+/* BLSP2_UART[0:5] */
+#define BLSP2_UART0_BASE (PERIPH_SS_BASE + 0x0015D000)
+#define BLSP2_UART1_BASE (PERIPH_SS_BASE + 0x0015E000)
+#define BLSP2_UART2_BASE (PERIPH_SS_BASE + 0x0015F000)
+#define BLSP2_UART3_BASE (PERIPH_SS_BASE + 0x00160000)
+#define BLSP2_UART4_BASE (PERIPH_SS_BASE + 0x00161000)
+#define BLSP2_UART5_BASE (PERIPH_SS_BASE + 0x00162000)
+
+#define MSM_USB_BASE (PERIPH_SS_BASE + 0x00255000)
+
+#define CLK_CTL_BASE 0xFC400000
+
+#define GCC_WDOG_DEBUG (CLK_CTL_BASE + 0x00001780)
+
+#define USB_HS_BCR (CLK_CTL_BASE + 0x480)
+
+#define SPMI_BASE 0xFC4C0000
+#define SPMI_GENI_BASE (SPMI_BASE + 0xA000)
+#define SPMI_PIC_BASE (SPMI_BASE + 0xB000)
+
+#define MSM_CE2_BAM_BASE 0xFD444000
+#define MSM_CE2_BASE 0xFD45A000
+
+#define TLMM_BASE_ADDR 0xFD510000
+#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10)
+#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x1004 + (x)*0x10)
+
+#define MPM2_MPM_CTRL_BASE 0xFC4A1000
+#define MPM2_MPM_PS_HOLD 0xFC4AB000
+#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0xFC4A3000
+
+/* CE 1 */
+#define GCC_CE1_BCR (CLK_CTL_BASE + 0x1040)
+#define GCC_CE1_CMD_RCGR (CLK_CTL_BASE + 0x1050)
+#define GCC_CE1_CFG_RCGR (CLK_CTL_BASE + 0x1054)
+#define GCC_CE1_CBCR (CLK_CTL_BASE + 0x1044)
+#define GCC_CE1_AXI_CBCR (CLK_CTL_BASE + 0x1048)
+#define GCC_CE1_AHB_CBCR (CLK_CTL_BASE + 0x104C)
+
+/* CE 2 */
+#define GCC_CE2_BCR (CLK_CTL_BASE + 0x1080)
+#define GCC_CE2_CMD_RCGR (CLK_CTL_BASE + 0x1090)
+#define GCC_CE2_CFG_RCGR (CLK_CTL_BASE + 0x1094)
+#define GCC_CE2_CBCR (CLK_CTL_BASE + 0x1084)
+#define GCC_CE2_AXI_CBCR (CLK_CTL_BASE + 0x1088)
+#define GCC_CE2_AHB_CBCR (CLK_CTL_BASE + 0x108C)
+
+/* GPLL */
+#define GPLL0_STATUS (CLK_CTL_BASE + 0x001C)
+#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x1480)
+#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x1484)
+
+/* SDCC 1 */
+#define SDCC1_BCR (CLK_CTL_BASE + 0x4C0) /* block reset */
+#define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x4C4) /* branch control */
+#define SDCC1_AHB_CBCR (CLK_CTL_BASE + 0x4C8)
+#define SDCC1_INACTIVITY_TIMER_CBCR (CLK_CTL_BASE + 0x4CC)
+#define SDCC1_CMD_RCGR (CLK_CTL_BASE + 0x4D0) /* cmd */
+#define SDCC1_CFG_RCGR (CLK_CTL_BASE + 0x4D4) /* cfg */
+#define SDCC1_M (CLK_CTL_BASE + 0x4D8) /* m */
+#define SDCC1_N (CLK_CTL_BASE + 0x4DC) /* n */
+#define SDCC1_D (CLK_CTL_BASE + 0x4E0) /* d */
+
+/* SDCC2 */
+#define SDCC2_BCR (CLK_CTL_BASE + 0x500) /* block reset */
+#define SDCC2_APPS_CBCR (CLK_CTL_BASE + 0x504) /* branch control */
+#define SDCC2_AHB_CBCR (CLK_CTL_BASE + 0x508)
+#define SDCC2_INACTIVITY_TIMER_CBCR (CLK_CTL_BASE + 0x50C)
+#define SDCC2_CMD_RCGR (CLK_CTL_BASE + 0x510) /* cmd */
+#define SDCC2_CFG_RCGR (CLK_CTL_BASE + 0x514) /* cfg */
+#define SDCC2_M (CLK_CTL_BASE + 0x518) /* m */
+#define SDCC2_N (CLK_CTL_BASE + 0x51C) /* n */
+#define SDCC2_D (CLK_CTL_BASE + 0x520) /* d */
+
+/* UART
+ BLSP1_UART[0:5]
+ BLSP2_UART[0:5]
+*/
+#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x5C4)
+#define BLSP2_AHB_CBCR (CLK_CTL_BASE + 0x944)
+
+#define BLSP1_UART0_APPS_CBCR (CLK_CTL_BASE + 0x684)
+#define BLSP1_UART0_APPS_CMD_RCGR (CLK_CTL_BASE + 0x68C)
+#define BLSP1_UART0_APPS_CFG_RCGR (CLK_CTL_BASE + 0x690)
+#define BLSP1_UART0_APPS_M (CLK_CTL_BASE + 0x694)
+#define BLSP1_UART0_APPS_N (CLK_CTL_BASE + 0x698)
+#define BLSP1_UART0_APPS_D (CLK_CTL_BASE + 0x69C)
+
+#define BLSP1_UART1_APPS_CBCR (CLK_CTL_BASE + 0x704)
+#define BLSP1_UART1_APPS_CMD_RCGR (CLK_CTL_BASE + 0x70C)
+#define BLSP1_UART1_APPS_CFG_RCGR (CLK_CTL_BASE + 0x710)
+#define BLSP1_UART1_APPS_M (CLK_CTL_BASE + 0x714)
+#define BLSP1_UART1_APPS_N (CLK_CTL_BASE + 0x718)
+#define BLSP1_UART1_APPS_D (CLK_CTL_BASE + 0x71C)
+
+#define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x784)
+#define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x78C)
+#define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x790)
+#define BLSP1_UART2_APPS_M (CLK_CTL_BASE + 0x794)
+#define BLSP1_UART2_APPS_N (CLK_CTL_BASE + 0x798)
+#define BLSP1_UART2_APPS_D (CLK_CTL_BASE + 0x79C)
+
+#define BLSP1_UART3_APPS_CBCR (CLK_CTL_BASE + 0x804)
+#define BLSP1_UART3_APPS_CMD_RCGR (CLK_CTL_BASE + 0x80C)
+#define BLSP1_UART3_APPS_CFG_RCGR (CLK_CTL_BASE + 0x810)
+#define BLSP1_UART3_APPS_M (CLK_CTL_BASE + 0x814)
+#define BLSP1_UART3_APPS_N (CLK_CTL_BASE + 0x818)
+#define BLSP1_UART3_APPS_D (CLK_CTL_BASE + 0x81C)
+
+#define BLSP1_UART4_APPS_CBCR (CLK_CTL_BASE + 0x884)
+#define BLSP1_UART4_APPS_CMD_RCGR (CLK_CTL_BASE + 0x88C)
+#define BLSP1_UART4_APPS_CFG_RCGR (CLK_CTL_BASE + 0x890)
+#define BLSP1_UART4_APPS_M (CLK_CTL_BASE + 0x894)
+#define BLSP1_UART4_APPS_N (CLK_CTL_BASE + 0x898)
+#define BLSP1_UART4_APPS_D (CLK_CTL_BASE + 0x89C)
+
+#define BLSP1_UART5_APPS_CBCR (CLK_CTL_BASE + 0x904)
+#define BLSP1_UART5_APPS_CMD_RCGR (CLK_CTL_BASE + 0x90C)
+#define BLSP1_UART5_APPS_CFG_RCGR (CLK_CTL_BASE + 0x910)
+#define BLSP1_UART5_APPS_M (CLK_CTL_BASE + 0x914)
+#define BLSP1_UART5_APPS_N (CLK_CTL_BASE + 0x918)
+#define BLSP1_UART5_APPS_D (CLK_CTL_BASE + 0x91C)
+
+#define BLSP2_UART0_APPS_CBCR (CLK_CTL_BASE + 0x9C4)
+#define BLSP2_UART0_APPS_CMD_RCGR (CLK_CTL_BASE + 0x9CC)
+#define BLSP2_UART0_APPS_CFG_RCGR (CLK_CTL_BASE + 0x9D0)
+#define BLSP2_UART0_APPS_M (CLK_CTL_BASE + 0x9D4)
+#define BLSP2_UART0_APPS_N (CLK_CTL_BASE + 0x9D8)
+#define BLSP2_UART0_APPS_D (CLK_CTL_BASE + 0x9DC)
+
+#define BLSP2_UART1_APPS_CBCR (CLK_CTL_BASE + 0xA44)
+#define BLSP2_UART1_APPS_CMD_RCGR (CLK_CTL_BASE + 0xA4C)
+#define BLSP2_UART1_APPS_CFG_RCGR (CLK_CTL_BASE + 0xA50)
+#define BLSP2_UART1_APPS_M (CLK_CTL_BASE + 0xA54)
+#define BLSP2_UART1_APPS_N (CLK_CTL_BASE + 0xA58)
+#define BLSP2_UART1_APPS_D (CLK_CTL_BASE + 0xA5C)
+
+#define BLSP2_UART2_APPS_CBCR (CLK_CTL_BASE + 0xAC4)
+#define BLSP2_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0xACC)
+#define BLSP2_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0xAD0)
+#define BLSP2_UART2_APPS_M (CLK_CTL_BASE + 0xAD4)
+#define BLSP2_UART2_APPS_N (CLK_CTL_BASE + 0xAD8)
+#define BLSP2_UART2_APPS_D (CLK_CTL_BASE + 0xADC)
+
+#define BLSP2_UART3_APPS_CBCR (CLK_CTL_BASE + 0xB44)
+#define BLSP2_UART3_APPS_CMD_RCGR (CLK_CTL_BASE + 0xB4C)
+#define BLSP2_UART3_APPS_CFG_RCGR (CLK_CTL_BASE + 0xB50)
+#define BLSP2_UART3_APPS_M (CLK_CTL_BASE + 0xB54)
+#define BLSP2_UART3_APPS_N (CLK_CTL_BASE + 0xB58)
+#define BLSP2_UART3_APPS_D (CLK_CTL_BASE + 0xB5C)
+
+#define BLSP2_UART4_APPS_CBCR (CLK_CTL_BASE + 0xBC4)
+#define BLSP2_UART4_APPS_CMD_RCGR (CLK_CTL_BASE + 0xBCC)
+#define BLSP2_UART4_APPS_CFG_RCGR (CLK_CTL_BASE + 0xBD0)
+#define BLSP2_UART4_APPS_M (CLK_CTL_BASE + 0xBD4)
+#define BLSP2_UART4_APPS_N (CLK_CTL_BASE + 0xBD8)
+#define BLSP2_UART4_APPS_D (CLK_CTL_BASE + 0xBDC)
+
+#define BLSP2_UART5_APPS_CBCR (CLK_CTL_BASE + 0xC44)
+#define BLSP2_UART5_APPS_CMD_RCGR (CLK_CTL_BASE + 0xC4C)
+#define BLSP2_UART5_APPS_CFG_RCGR (CLK_CTL_BASE + 0xC50)
+#define BLSP2_UART5_APPS_M (CLK_CTL_BASE + 0xC54)
+#define BLSP2_UART5_APPS_N (CLK_CTL_BASE + 0xC58)
+#define BLSP2_UART5_APPS_D (CLK_CTL_BASE + 0xC5C)
+
+/* USB */
+#define USB_HS_SYSTEM_CBCR (CLK_CTL_BASE + 0x484)
+#define USB_HS_AHB_CBCR (CLK_CTL_BASE + 0x488)
+#define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x490)
+#define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x494)
+
+/* I2C */
+#define BLSP2_QUP5_I2C_APPS_CBCR (CLK_CTL_BASE + 0xB88)
+
+#define BLSP_QUP_BASE(blsp_id, qup_id) ((blsp_id == 1) ? \
+ (PERIPH_SS_BASE + 0x00123000 \
+ + (qup_id * 0x1000)) :\
+ (PERIPH_SS_BASE + 0x00163000 + \
+ (qup_id * 0x1000)))
+
+/* DRV strength for sdcc */
+#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x00002044)
+
+/* SDHCI */
+#define SDCC_MCI_HC_MODE (0x00000078)
+#define SDCC_HC_PWRCTL_STATUS_REG (0x000000DC)
+#define SDCC_HC_PWRCTL_MASK_REG (0x000000E0)
+#define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4)
+#define SDCC_HC_PWRCTL_CTL_REG (0x000000E8)
+#endif
diff --git a/platform/fsm9900/include/platform/irqs.h b/platform/fsm9900/include/platform/irqs.h
new file mode 100644
index 0000000..955438b
--- /dev/null
+++ b/platform/fsm9900/include/platform/irqs.h
@@ -0,0 +1,70 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef __IRQS_FSM9900_H
+#define __IRQS_FSM9900_H
+
+/* MSM ACPU Interrupt Numbers */
+
+/* 0-15: STI/SGI (software triggered/generated interrupts)
+ * 16-31: PPI (private peripheral interrupts)
+ * 32+: SPI (shared peripheral interrupts)
+ */
+
+#define GIC_PPI_START 16
+#define GIC_SPI_START 32
+
+#define INT_QTMR_NON_SECURE_PHY_TIMER_EXP (GIC_PPI_START + 3)
+#define INT_QTMR_VIRTUAL_TIMER_EXP (GIC_PPI_START + 4)
+
+#define INT_QTMR_FRM_0_PHYSICAL_TIMER_EXP (GIC_SPI_START + 8)
+
+#define USB1_HS_BAM_IRQ (GIC_SPI_START + 135)
+#define USB1_HS_IRQ (GIC_SPI_START + 134)
+#define USB1_IRQ (GIC_SPI_START + 142)
+
+/* Retrofit universal macro names */
+#define INT_USB_HS USB1_HS_IRQ
+
+#define EE0_KRAIT_HLOS_SPMI_PERIPH_IRQ (GIC_SPI_START + 190)
+
+#define NR_MSM_IRQS 256
+#define NR_GPIO_IRQS 173
+#define NR_BOARD_IRQS 0
+
+#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + \
+ NR_BOARD_IRQS)
+
+#define BLSP_QUP_IRQ(blsp_id, qup_id) ((blsp_id == 1) ? \
+ ((GIC_SPI_START + 95) + qup_id):\
+ ((GIC_SPI_START + 101) + qup_id))
+
+#define SDCC1_PWRCTL_IRQ (GIC_SPI_START + 138)
+#define SDCC2_PWRCTL_IRQ (GIC_SPI_START + 221)
+#endif /* __IRQS_FSM9900_H */
diff --git a/platform/fsm9900/platform.c b/platform/fsm9900/platform.c
new file mode 100644
index 0000000..7a1791e
--- /dev/null
+++ b/platform/fsm9900/platform.c
@@ -0,0 +1,171 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <reg.h>
+#include <platform/iomap.h>
+#include <qgic.h>
+#include <qtimer.h>
+#include <platform/clock.h>
+#include <mmu.h>
+#include <arch/arm/mmu.h>
+#include <smem.h>
+#include <board.h>
+#include <boot_stats.h>
+
+#define MB (1024*1024)
+
+#define MSM_IOMAP_SIZE ((MSM_IOMAP_END - MSM_IOMAP_BASE)/MB)
+
+/* LK memory - cacheable, write through */
+#define LK_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_WRITE)
+
+/* Peripherals - non-shared device */
+#define IOMAP_MEMORY (MMU_MEMORY_TYPE_DEVICE_SHARED | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
+/* IMEM memory - cacheable, write through */
+#define IMEM_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
+static mmu_section_t mmu_section_table[] = {
+/* Physical addr, Virtual addr, Size (in MB), Flags */
+ {MEMBASE, MEMBASE, (MEMSIZE / MB), LK_MEMORY},
+ {MSM_IOMAP_BASE, MSM_IOMAP_BASE, MSM_IOMAP_SIZE, IOMAP_MEMORY},
+ /* IMEM needs a seperate entry in the table as it's length is only 0x8000. */
+ {SYSTEM_IMEM_BASE, SYSTEM_IMEM_BASE, 1, IMEM_MEMORY},
+};
+
+static struct smem_ram_ptable ram_ptable;
+
+/* Boot timestamps */
+#define BS_INFO_OFFSET (0x6B0)
+#define BS_INFO_ADDR_V1 (RPM_MSG_RAM_BASE + BS_INFO_OFFSET)
+#define BS_INFO_ADDR_V2 (MSM_SHARED_IMEM_BASE + BS_INFO_OFFSET)
+
+void platform_early_init(void)
+{
+ board_init();
+ platform_clock_init();
+ qgic_init();
+ qtimer_init();
+}
+
+void platform_init(void)
+{
+ dprintf(INFO, "platform_init()\n");
+}
+
+uint32_t platform_get_sclk_count(void)
+{
+ return readl(MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL);
+}
+
+addr_t get_bs_info_addr()
+{
+ uint32_t soc_ver = board_soc_version();
+
+ if (soc_ver < BOARD_SOC_VERSION2)
+ return ((addr_t)BS_INFO_ADDR_V1);
+ else
+ return ((addr_t)BS_INFO_ADDR_V2);
+
+}
+
+void platform_uninit(void)
+{
+ qtimer_uninit();
+}
+
+int platform_use_identity_mmu_mappings(void)
+{
+ /* Use only the mappings specified in this file. */
+ return 0;
+}
+
+addr_t platform_get_virt_to_phys_mapping(addr_t virt_addr)
+{
+ /* Return same address as we are using 1-1 mapping. */
+ return virt_addr;
+}
+
+addr_t platform_get_phys_to_virt_mapping(addr_t phys_addr)
+{
+ /* Return same address as we are using 1-1 mapping. */
+ return phys_addr;
+}
+
+
+/* Setup memory for this platform */
+void platform_init_mmu_mappings(void)
+{
+ uint32_t i;
+ uint32_t sections;
+ uint32_t table_size = ARRAY_SIZE(mmu_section_table);
+
+ ASSERT(smem_ram_ptable_init(&ram_ptable));
+
+ /* Configure the MMU page entries for SDRAM and IMEM memory read
+ from the smem ram table*/
+ for(i = 0; i < ram_ptable.len; i++)
+ {
+ if(ram_ptable.parts[i].type == SYS_MEMORY)
+ {
+ if((ram_ptable.parts[i].category == SDRAM) ||
+ (ram_ptable.parts[i].category == IMEM))
+ {
+ /* Check to ensure that start address is 1MB aligned */
+ ASSERT((ram_ptable.parts[i].start & 0xFFFFF) == 0);
+
+ sections = (ram_ptable.parts[i].size) / MB;
+ while(sections--) {
+ arm_mmu_map_section(ram_ptable.parts[i].start +
+ sections * MB,
+ ram_ptable.parts[i].start +
+ sections * MB,
+ (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN));
+ }
+ }
+ }
+ }
+ /* Configure the MMU page entries for memory read from the
+ mmu_section_table */
+ for (i = 0; i < table_size; i++) {
+ sections = mmu_section_table[i].num_of_sections;
+
+ while (sections--) {
+ arm_mmu_map_section(mmu_section_table[i].paddress +
+ sections * MB,
+ mmu_section_table[i].vaddress +
+ sections * MB,
+ mmu_section_table[i].flags);
+ }
+ }
+}
diff --git a/platform/fsm9900/rules.mk b/platform/fsm9900/rules.mk
new file mode 100644
index 0000000..e115234
--- /dev/null
+++ b/platform/fsm9900/rules.mk
@@ -0,0 +1,28 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+ARCH := arm
+ARM_CPU := cortex-a8
+CPU := generic
+
+DEFINES += ARM_CPU_CORE_KRAIT
+
+MMC_SLOT := 1
+
+DEFINES += PERIPH_BLK_BLSP=1
+DEFINES += WITH_CPU_EARLY_INIT=0 WITH_CPU_WARM_BOOT=0 \
+ MMC_SLOT=$(MMC_SLOT) SSD_ENABLE
+
+INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared/include
+
+DEVS += fbcon
+MODULES += dev/fbcon
+
+OBJS += \
+ $(LOCAL_DIR)/platform.o \
+ $(LOCAL_DIR)/acpuclock.o \
+ $(LOCAL_DIR)/fsm9900-clock.o \
+ $(LOCAL_DIR)/gpio.o
+
+LINKER_SCRIPT += $(BUILDDIR)/system-onesegment.ld
+
+include platform/msm_shared/rules.mk
diff --git a/platform/msm8226/include/platform/clock.h b/platform/msm8226/include/platform/clock.h
index fbbd77a..399c765 100755
--- a/platform/msm8226/include/platform/clock.h
+++ b/platform/msm8226/include/platform/clock.h
@@ -79,6 +79,8 @@
void clock_config_uart_dm(uint8_t id);
void hsusb_clock_init(void);
void clock_config_ce(uint8_t instance);
+void clock_ce_enable(uint8_t instance);
+void clock_ce_disable(uint8_t instance);
void mdp_clock_init(void);
void mdp_gdsc_ctrl(uint8_t enable);
diff --git a/platform/msm8226/rules.mk b/platform/msm8226/rules.mk
index 91e3395..4efec0e 100644
--- a/platform/msm8226/rules.mk
+++ b/platform/msm8226/rules.mk
@@ -11,7 +11,7 @@
DEFINES += PERIPH_BLK_BLSP=1
DEFINES += WITH_CPU_EARLY_INIT=0 WITH_CPU_WARM_BOOT=0 \
- MMC_SLOT=$(MMC_SLOT)
+ MMC_SLOT=$(MMC_SLOT) SSD_ENABLE
INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared/include
diff --git a/platform/msm8974/acpuclock.c b/platform/msm8974/acpuclock.c
index 6131e61..5284d0f 100644
--- a/platform/msm8974/acpuclock.c
+++ b/platform/msm8974/acpuclock.c
@@ -142,14 +142,14 @@
}
else
{
- dprintf(CRITICAL, "sdc frequency (%d) is not supported\n", freq);
+ dprintf(CRITICAL, "sdc frequency (%u) is not supported\n", freq);
ASSERT(0);
}
if(ret)
{
- dprintf(CRITICAL, "failed to set sdc1_core_clk ret = %d\n", ret);
+ dprintf(CRITICAL, "failed to set sdc%u_core_clk ret = %d\n", interface, ret);
ASSERT(0);
}
@@ -502,3 +502,83 @@
clk_disable(clk_get("mmss_mmssnoc_axi_clk"));
}
+
+/* enables usb30 interface and master clocks */
+void clock_usb30_init(void)
+{
+ int ret;
+
+ /* interface clock */
+ ret = clk_get_set_enable("usb30_iface_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_iface_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* master clock */
+ ret = clk_get_set_enable("usb30_master_clk", 125000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_master_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+}
+
+void edp_clk_enable(void)
+{
+ int ret;
+
+ /* Configure MMSSNOC AXI clock */
+ ret = clk_get_set_enable("mmss_mmssnoc_axi_clk", 100000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set mmssnoc_axi_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Configure MMSSNOC AXI clock */
+ ret = clk_get_set_enable("mmss_s0_axi_clk", 100000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set mmss_s0_axi_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Configure AXI clock */
+ ret = clk_get_set_enable("mdss_axi_clk", 100000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set mdss_axi_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("edp_pixel_clk", 138500000, 1);
+ if (ret) {
+ dprintf(CRITICAL, "failed to set edp_pixel_clk ret = %d\n",
+ ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("edp_link_clk", 270000000, 1);
+ if (ret) {
+ dprintf(CRITICAL, "failed to set edp_link_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("edp_aux_clk", 19200000, 1);
+ if (ret) {
+ dprintf(CRITICAL, "failed to set edp_aux_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+}
+
+void edp_clk_disable(void)
+{
+
+ writel(0x0, MDSS_EDPPIXEL_CBCR);
+ writel(0x0, MDSS_EDPLINK_CBCR);
+ clk_disable(clk_get("edp_pixel_clk"));
+ clk_disable(clk_get("edp_link_clk"));
+ clk_disable(clk_get("edp_aux_clk"));
+}
diff --git a/platform/msm8974/include/platform/clock.h b/platform/msm8974/include/platform/clock.h
index e9f8d08..f83c2ae 100644
--- a/platform/msm8974/include/platform/clock.h
+++ b/platform/msm8974/include/platform/clock.h
@@ -81,6 +81,19 @@
#define DSI_PIXEL1_CFG_RCGR REG_MM(0x2024)
#define DSI_PIXEL1_CBCR REG_MM(0x2318)
+#define MDSS_EDPPIXEL_CBCR REG_MM(0x232C)
+#define MDSS_EDPLINK_CBCR REG_MM(0x2330)
+#define MDSS_EDPAUX_CBCR REG_MM(0x2334)
+#define EDPPIXEL_M REG_MM(0x20A8)
+#define EDPPIXEL_N REG_MM(0x20AC)
+#define EDPPIXEL_D REG_MM(0x20B0)
+#define EDPPIXEL_CFG_RCGR REG_MM(0x20A4)
+#define EDPPIXEL_CMD_RCGR REG_MM(0x20A0)
+#define EDPLINK_CFG_RCGR REG_MM(0x20C4)
+#define EDPLINK_CMD_RCGR REG_MM(0x20C0)
+#define EDPAUX_CFG_RCGR REG_MM(0x20E4)
+#define EDPAUX_CMD_RCGR REG_MM(0x20E0)
+
void platform_clock_init(void);
void clock_init_mmc(uint32_t interface);
@@ -90,7 +103,9 @@
void clock_config_ce(uint8_t instance);
void mdp_clock_init(void);
void mdp_gdsc_ctrl(uint8_t enable);
+void edp_clk_enable(void);
void clock_ce_enable(uint8_t instance);
void clock_ce_disable(uint8_t instance);
+void clock_usb30_init(void);
#endif
diff --git a/platform/msm8974/include/platform/iomap.h b/platform/msm8974/include/platform/iomap.h
index 3e27c3b..42a436f 100644
--- a/platform/msm8974/include/platform/iomap.h
+++ b/platform/msm8974/include/platform/iomap.h
@@ -85,10 +85,32 @@
#define BLSP1_UART5_BASE (PERIPH_SS_BASE + 0x00122000)
#define MSM_USB_BASE (PERIPH_SS_BASE + 0x00255000)
+#define MSM_USB30_BASE 0xF9200000
+#define MSM_USB30_QSCRATCH_BASE 0xF92F8800
+
#define CLK_CTL_BASE 0xFC400000
#define GCC_WDOG_DEBUG (CLK_CTL_BASE + 0x00001780)
+/* USB 3.0 clocks */
+#define SYS_NOC_USB3_AXI_CBCR (CLK_CTL_BASE + 0x0108)
+
+#define GCC_USB_30_BCR 0xFC4003C0
+#define GCC_USB_30_MISC 0xFC4003C4
+
+#define GCC_USB30_MASTER_CBCR 0xFC4003C8
+#define GCC_USB30_SLEEP_CBCR 0xFC4003CC
+#define GCC_USB30_MOCK_UTMI_CBCR 0xFC4003D0
+
+#define GCC_USB30_MASTER_CMD_RCGR 0xFC4003D4
+#define GCC_USB30_MASTER_CFG_RCGR 0xFC4003D8
+#define GCC_USB30_MASTER_M 0xFC4003DC
+#define GCC_USB30_MASTER_N 0xFC4003E0
+#define GCC_USB30_MASTER_D 0xFC4003E4
+
+#define GCC_USB3_PHY_BCR 0xFC4003FC
+
+
#define USB_HS_BCR (CLK_CTL_BASE + 0x480)
#define SPMI_BASE 0xFC4C0000
@@ -150,6 +172,17 @@
#define SDCC2_N (CLK_CTL_BASE + 0x51C) /* n */
#define SDCC2_D (CLK_CTL_BASE + 0x520) /* d */
+/* SDCC3 */
+#define SDCC3_BCR (CLK_CTL_BASE + 0x540) /* block reset */
+#define SDCC3_APPS_CBCR (CLK_CTL_BASE + 0x544) /* branch control */
+#define SDCC3_AHB_CBCR (CLK_CTL_BASE + 0x548)
+#define SDCC3_INACTIVITY_TIMER_CBCR (CLK_CTL_BASE + 0x54C)
+#define SDCC3_CMD_RCGR (CLK_CTL_BASE + 0x550) /* cmd */
+#define SDCC3_CFG_RCGR (CLK_CTL_BASE + 0x554) /* cfg */
+#define SDCC3_M (CLK_CTL_BASE + 0x558) /* m */
+#define SDCC3_N (CLK_CTL_BASE + 0x55C) /* n */
+#define SDCC3_D (CLK_CTL_BASE + 0x560) /* d */
+
/* UART */
#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x5C4)
#define BLSP2_AHB_CBCR (CLK_CTL_BASE + 0x944)
@@ -182,6 +215,8 @@
#define MIPI_DSI1_BASE (0xFD922E00)
#define REG_DSI(off) (MIPI_DSI_BASE + 0x04 + (off))
+#define EDP_BASE (0xFD923400)
+
#define MDP_BASE (0xfd900000)
#define REG_MDP(off) (MDP_BASE + (off))
diff --git a/platform/msm8974/include/platform/irqs.h b/platform/msm8974/include/platform/irqs.h
index e9b2d06..c0637d0 100644
--- a/platform/msm8974/include/platform/irqs.h
+++ b/platform/msm8974/include/platform/irqs.h
@@ -45,6 +45,7 @@
#define INT_QTMR_FRM_0_PHYSICAL_TIMER_EXP (GIC_SPI_START + 8)
+#define USB30_EE1_IRQ (GIC_SPI_START + 131)
#define USB1_HS_BAM_IRQ (GIC_SPI_START + 135)
#define USB1_HS_IRQ (GIC_SPI_START + 134)
#define USB2_IRQ (GIC_SPI_START + 141)
diff --git a/platform/msm8974/msm8974-clock.c b/platform/msm8974/msm8974-clock.c
index dbba8c4..68000d5 100644
--- a/platform/msm8974/msm8974-clock.c
+++ b/platform/msm8974/msm8974-clock.c
@@ -44,6 +44,8 @@
#define mmpll1_mm_source_val 2
#define mmpll3_mm_source_val 3
#define gpll0_mm_source_val 5
+#define edppll_270_mm_source_val 4
+#define edppll_350_mm_source_val 4
struct clk_freq_tbl rcg_dummy_freq = F_END;
@@ -624,6 +626,135 @@
},
};
+static struct clk_freq_tbl ftbl_mdss_edpaux_clk[] = {
+ F_MM(19200000, cxo, 1, 0, 0),
+ F_END
+};
+
+static struct rcg_clk edpaux_clk_src = {
+ .cmd_reg = (uint32_t *) EDPAUX_CMD_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_mdss_edpaux_clk,
+
+ .c = {
+ .dbg_name = "edpaux_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk mdss_edpaux_clk = {
+ .cbcr_reg = MDSS_EDPAUX_CBCR,
+ .parent = &edpaux_clk_src.c,
+ .has_sibling = 0,
+
+ .c = {
+ .dbg_name = "mdss_edpaux_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct clk_freq_tbl ftbl_mdss_edplink_clk[] = {
+ F_MDSS(162000000, edppll_270, 2, 0, 0),
+ F_MDSS(270000000, edppll_270, 11, 0, 0),
+ F_END
+};
+
+static struct rcg_clk edplink_clk_src = {
+ .cmd_reg = (uint32_t *)EDPLINK_CMD_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_mdss_edplink_clk,
+ .current_freq = &rcg_dummy_freq,
+ .c = {
+ .dbg_name = "edplink_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct clk_freq_tbl ftbl_mdss_edppixel_clk[] = {
+ F_MDSS(138500000, edppll_350, 2, 0, 0),
+ F_MDSS(350000000, edppll_350, 11, 0, 0),
+ F_END
+};
+
+static struct rcg_clk edppixel_clk_src = {
+ .cmd_reg = (uint32_t *)EDPPIXEL_CMD_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_mdss_edppixel_clk,
+ .current_freq = &rcg_dummy_freq,
+ .c = {
+ .dbg_name = "edppixel_clk_src",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk mdss_edplink_clk = {
+ .cbcr_reg = (uint32_t *)MDSS_EDPLINK_CBCR,
+ .has_sibling = 0,
+ .parent = &edplink_clk_src.c,
+ .c = {
+ .dbg_name = "mdss_edplink_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk mdss_edppixel_clk = {
+ .cbcr_reg = (uint32_t *)MDSS_EDPPIXEL_CBCR,
+ .has_sibling = 0,
+ .parent = &edppixel_clk_src.c,
+ .c = {
+ .dbg_name = "mdss_edppixel_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+/* USB 3.0 Clocks */
+static struct clk_freq_tbl ftbl_gcc_usb30_master_clk[] =
+{
+ F(125000000, gpll0, 1, 5, 24),
+ F_END
+};
+
+static struct rcg_clk usb30_master_clk_src =
+{
+ .cmd_reg = (uint32_t *) GCC_USB30_MASTER_CMD_RCGR,
+ .cfg_reg = (uint32_t *) GCC_USB30_MASTER_CFG_RCGR,
+ .m_reg = (uint32_t *) GCC_USB30_MASTER_M,
+ .n_reg = (uint32_t *) GCC_USB30_MASTER_N,
+ .d_reg = (uint32_t *) GCC_USB30_MASTER_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_usb30_master_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "usb30_master_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+
+static struct branch_clk gcc_usb30_master_clk =
+{
+ .cbcr_reg = (uint32_t *) GCC_USB30_MASTER_CBCR,
+ .parent = &usb30_master_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_usb30_master_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_sys_noc_usb30_axi_clk =
+{
+ .cbcr_reg = (uint32_t *) SYS_NOC_USB3_AXI_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_sys_noc_usb3_axi_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
/* Clock lookup table */
static struct clk_lookup msm_clocks_8974[] =
{
@@ -663,6 +794,14 @@
CLK_LOOKUP("mdss_mdp_clk_src", mdss_mdp_clk_src.c),
CLK_LOOKUP("mdss_mdp_clk", mdss_mdp_clk.c),
CLK_LOOKUP("mdss_mdp_lut_clk", mdss_mdp_lut_clk.c),
+
+ CLK_LOOKUP("edp_pixel_clk", mdss_edppixel_clk.c),
+ CLK_LOOKUP("edp_link_clk", mdss_edplink_clk.c),
+ CLK_LOOKUP("edp_aux_clk", mdss_edpaux_clk.c),
+
+ /* USB 3.0 */
+ CLK_LOOKUP("usb30_iface_clk", gcc_sys_noc_usb30_axi_clk.c),
+ CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c),
};
diff --git a/platform/msm_shared/crypto4_eng.c b/platform/msm_shared/crypto4_eng.c
index 84fbc9f..a19c224 100644
--- a/platform/msm_shared/crypto4_eng.c
+++ b/platform/msm_shared/crypto4_eng.c
@@ -26,6 +26,7 @@
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#include <arch/defines.h>
#include <string.h>
#include <endian.h>
#include <debug.h>
@@ -37,7 +38,6 @@
#include <scm.h>
#include <smem.h>
-extern void dsb(void);
extern void ce_async_reset();
void wr_ce(uint32_t val,uint32_t reg)
diff --git a/platform/msm_shared/crypto5_eng.c b/platform/msm_shared/crypto5_eng.c
index ed5c8ad..3fecd61 100644
--- a/platform/msm_shared/crypto5_eng.c
+++ b/platform/msm_shared/crypto5_eng.c
@@ -466,6 +466,10 @@
{
CLEAR_STATUS(dev);
+ /* reset the pipes. */
+ bam_pipe_reset(&(dev->bam), CRYPTO_READ_PIPE_INDEX);
+ bam_pipe_reset(&(dev->bam), CRYPTO_WRITE_PIPE_INDEX);
+
/* Free all related memory. */
free(dev->dump);
free(dev->ce_array);
diff --git a/platform/msm_shared/dev_tree.c b/platform/msm_shared/dev_tree.c
index 28530b8..4e1d44f 100644
--- a/platform/msm_shared/dev_tree.c
+++ b/platform/msm_shared/dev_tree.c
@@ -59,7 +59,10 @@
uint32_t soc_rev;
};
-static bool is_dev_tree_compatible(void *dtb)
+/* Returns soc version if platform id and hardware id matches
+ otherwise return 0xFFFFFFFF */
+#define INVALID_SOC_REV_ID 0XFFFFFFFF
+static uint32_t dev_tree_compatible(void *dtb)
{
int root_offset;
const void *prop;
@@ -97,8 +100,7 @@
msm_id.platform_id, msm_id.hardware_id, msm_id.soc_rev);
if (msm_id.platform_id != board_platform_id() ||
- msm_id.hardware_id != board_hardware_id() ||
- msm_id.soc_rev != board_soc_version()) {
+ msm_id.hardware_id != board_hardware_id()) {
dprintf(INFO, "Device tree's msm_id doesn't match the board: <%d %d 0x%x> != <%d %d 0x%x>\n",
msm_id.platform_id,
msm_id.hardware_id,
@@ -106,10 +108,17 @@
board_platform_id(),
board_hardware_id(),
board_soc_version());
- return false;
+ return INVALID_SOC_REV_ID;
}
- return true;
+ dprintf(INFO, "Device tree's msm_id matches the board: <%d %d 0x%x> == <%d %d 0x%x>\n",
+ msm_id.platform_id,
+ msm_id.hardware_id,
+ msm_id.soc_rev,
+ board_platform_id(),
+ board_hardware_id(),
+ board_soc_version());
+ return msm_id.soc_rev;
}
/*
@@ -128,12 +137,15 @@
void *kernel_end = kernel + kernel_size;
uint32_t app_dtb_offset = 0;
void *dtb;
+ void *bestmatch_tag = NULL;
+ uint32_t bestmatch_tag_size;
+ uint32_t bestmatch_soc_rev_id = INVALID_SOC_REV_ID;
memcpy((void*) &app_dtb_offset, (void*) (kernel + DTB_OFFSET), sizeof(uint32_t));
dtb = kernel + app_dtb_offset;
while (dtb + sizeof(struct fdt_header) < kernel_end) {
- bool compat;
+ uint32_t dtb_soc_rev_id;
struct fdt_header dtb_hdr;
uint32_t dtb_size;
@@ -149,17 +161,36 @@
* it somewhere aligned, like tags */
memcpy(tags, dtb, dtb_size);
- compat = is_dev_tree_compatible(tags);
- if (compat) {
+ dtb_soc_rev_id = dev_tree_compatible(tags);
+ if (dtb_soc_rev_id == board_soc_version()) {
/* clear out the old DTB magic so kernel doesn't find it */
*((uint32_t *)(kernel + app_dtb_offset)) = 0;
return tags;
+ } else if ((dtb_soc_rev_id != INVALID_SOC_REV_ID) &&
+ (dtb_soc_rev_id < board_soc_version())) {
+ /* if current bestmatch is less than new dtb_soc_rev_id then update
+ bestmatch_tag */
+ if((bestmatch_soc_rev_id == INVALID_SOC_REV_ID) ||
+ (bestmatch_soc_rev_id < dtb_soc_rev_id)) {
+ bestmatch_tag = dtb;
+ bestmatch_tag_size = dtb_size;
+ bestmatch_soc_rev_id = dtb_soc_rev_id;
+ }
}
/* goto the next device tree if any */
dtb += dtb_size;
}
+ if(bestmatch_tag) {
+ dprintf(INFO,"DTB found with bestmatch soc rev id 0x%x.Board soc rev id 0x%x\n",
+ bestmatch_soc_rev_id, board_soc_version());
+ memcpy(tags, bestmatch_tag, bestmatch_tag_size);
+ /* clear out the old DTB magic so kernel doesn't find it */
+ *((uint32_t *)(kernel + app_dtb_offset)) = 0;
+ return tags;
+ }
+
dprintf(CRITICAL, "DTB offset is incorrect, kernel image does not have appended DTB\n");
return NULL;
diff --git a/platform/msm_shared/display.c b/platform/msm_shared/display.c
index 3768ca8..c420af6 100644
--- a/platform/msm_shared/display.c
+++ b/platform/msm_shared/display.c
@@ -136,6 +136,12 @@
if (ret)
goto msm_display_config_out;
break;
+ case EDP_PANEL:
+ dprintf(INFO, "Config EDP PANEL.\n");
+ ret = mdp_edp_config(pinfo, &(panel->fb));
+ if (ret)
+ goto msm_display_config_out;
+ break;
default:
return ERR_INVALID_ARGS;
};
@@ -207,7 +213,12 @@
if (ret)
goto msm_display_on_out;
break;
-
+ case EDP_PANEL:
+ dprintf(INFO, "Turn on EDP PANEL.\n");
+ ret = mdp_edp_on();
+ if (ret)
+ goto msm_display_on_out;
+ break;
default:
return ERR_INVALID_ARGS;
};
@@ -247,6 +258,19 @@
if (ret)
goto msm_display_init_out;
+ /* pinfo prepare */
+ if (pdata->panel_info.prepare) {
+ /* this is for edp which pinfo derived from edid */
+ ret = pdata->panel_info.prepare();
+ panel->fb.width = panel->panel_info.xres;
+ panel->fb.height = panel->panel_info.yres;
+ panel->fb.stride = panel->panel_info.xres;
+ panel->fb.bpp = panel->panel_info.bpp;
+ }
+
+ if (ret)
+ goto msm_display_init_out;
+
ret = msm_fb_alloc(&(panel->fb));
if (ret)
goto msm_display_init_out;
@@ -302,6 +326,12 @@
dprintf(INFO, "Turn off LCDC PANEL.\n");
mdp_lcdc_off();
break;
+ case EDP_PANEL:
+ dprintf(INFO, "Turn off EDP PANEL.\n");
+ ret = mdp_edp_off();
+ if (ret)
+ goto msm_display_off_out;
+ break;
default:
return ERR_INVALID_ARGS;
};
diff --git a/platform/msm_shared/dload_util.c b/platform/msm_shared/dload_util.c
index 06140f2..7455a19 100644
--- a/platform/msm_shared/dload_util.c
+++ b/platform/msm_shared/dload_util.c
@@ -37,8 +37,6 @@
#define EMERGENCY_DLOAD_COOKIE_1 0xC67E4350
#define EMERGENCY_DLOAD_COOKIE_2 0x77777777
-extern void dsb();
-
void dload_util_write_cookie(uint32_t target_dload_mode_addr,
enum dload_mode mode)
{
diff --git a/platform/msm_shared/edp.c b/platform/msm_shared/edp.c
new file mode 100644
index 0000000..d7c3067
--- /dev/null
+++ b/platform/msm_shared/edp.c
@@ -0,0 +1,210 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "edp.h"
+#include "mdp5.h"
+
+#define RGB_COMPONENTS 3
+#define MAX_NUMBER_EDP_LANES 4
+
+static struct msm_panel_info *edp_pinfo;
+
+static void edp_config_sync(void)
+{
+ int ret = 0;
+
+ ret = edp_read(EDP_BASE + 0xc); /* EDP_CONFIGURATION_CTRL */
+ ret &= ~0x733;
+ ret |= (0x55 & 0x733);
+ edp_write(EDP_BASE + 0xc, ret);
+ edp_write(EDP_BASE + 0xc, 0x55); /* EDP_CONFIGURATION_CTRL */
+}
+
+static void edp_config_sw_div(void)
+{
+ edp_write(EDP_BASE + 0x14, 0x13b); /* EDP_SOFTWARE_MVID */
+ edp_write(EDP_BASE + 0x18, 0x266); /* EDP_SOFTWARE_NVID */
+}
+
+static void edp_config_static_mdiv(void)
+{
+ int ret = 0;
+
+ ret = edp_read(EDP_BASE + 0xc); /* EDP_CONFIGURATION_CTRL */
+ edp_write(EDP_BASE + 0xc, ret | 0x2); /* EDP_CONFIGURATION_CTRL */
+ edp_write(EDP_BASE + 0xc, 0x57); /* EDP_CONFIGURATION_CTRL */
+}
+
+static void edp_config_tu(void)
+{
+ /* temporary */
+ edp_write(EDP_BASE + 0x160, 0x2b);
+ edp_write(EDP_BASE + 0x15c, 0x00320033);
+ edp_write(EDP_BASE + 0x34, 0x0023001a);
+
+}
+
+static void edp_config_timing(struct msm_panel_info *pinfo)
+{
+ unsigned long total_ver, total_hor;
+ unsigned long data;
+
+ dprintf(INFO, "%s: width=%d hporch= %d %d %d\n", __func__,
+ pinfo->xres, pinfo->lcdc.h_back_porch,
+ pinfo->lcdc.h_front_porch, pinfo->lcdc.h_pulse_width);
+
+ dprintf(INFO, "%s: height=%d vporch= %d %d %d\n", __func__,
+ pinfo->yres, pinfo->lcdc.v_back_porch,
+ pinfo->lcdc.v_front_porch, pinfo->lcdc.v_pulse_width);
+
+ total_hor = pinfo->xres + pinfo->lcdc.h_back_porch +
+ pinfo->lcdc.h_front_porch + pinfo->lcdc.h_pulse_width;
+
+ total_ver = pinfo->yres + pinfo->lcdc.v_back_porch +
+ pinfo->lcdc.v_front_porch + pinfo->lcdc.v_pulse_width;
+
+ data = total_ver;
+ data <<= 16;
+ data |= total_hor;
+ edp_write(EDP_BASE + 0x1c, data); /* EDP_TOTAL_HOR_VER */
+
+ data = (pinfo->lcdc.v_back_porch + pinfo->lcdc.v_pulse_width);
+ data <<= 16;
+ data |= (pinfo->lcdc.h_back_porch + pinfo->lcdc.h_pulse_width);
+ edp_write(EDP_BASE + 0x20, data); /* EDP_START_HOR_VER_FROM_SYNC */
+
+ data = pinfo->lcdc.v_pulse_width;
+ data <<= 16;
+ data |= pinfo->lcdc.h_pulse_width;
+ edp_write(EDP_BASE + 0x24, data); /* EDP_HSYNC_VSYNC_WIDTH_POLARITY */
+
+ data = pinfo->yres;
+ data <<= 16;
+ data |= pinfo->xres;
+ edp_write(EDP_BASE + 0x28, data); /* EDP_ACTIVE_HOR_VER */
+}
+
+static void edp_enable(int enable)
+{
+ edp_write(EDP_BASE + 0x8, 0x0); /* EDP_STATE_CTRL */
+ edp_write(EDP_BASE + 0x8, 0x40); /* EDP_STATE_CTRL */
+ edp_write(EDP_BASE + 0x4, 0x01); /* EDP_MAINLINK_CTRL */
+}
+
+static void edp_disable(int enable)
+{
+ edp_write(EDP_BASE + 0x8, 0x0); /* EDP_STATE_CTRL */
+ edp_write(EDP_BASE + 0x4, 0x00); /* EDP_MAINLINK_CTRL */
+}
+
+int edp_on(void)
+{
+ mdss_edp_pll_configure();
+ mdss_edp_phy_pll_ready();
+ edp_phy_misc_cfg();
+ edp_config_sync();
+ edp_config_sw_div();
+ edp_config_static_mdiv();
+ edp_config_timing(edp_pinfo);
+ edp_config_tu();
+
+ edp_config_clk();
+ mdss_edp_lane_power_ctrl(1);
+
+ edp_enable_mainlink(1);
+
+ mdss_edp_link_train();
+
+ edp_enable(1);
+
+ mdss_edp_wait_for_video_ready();
+
+ mdss_edp_irq_disable();
+ dprintf(INFO, "%s:\n", __func__);
+
+ return 0;
+}
+
+int edp_off(void)
+{
+ mdss_edp_irq_disable();
+ edp_enable_mainlink(0);
+ edp_phy_pll_reset();
+ edp_mainlink_reset();
+ edp_aux_reset();
+
+ edp_disable(1);
+ edp_unconfig_clk();
+
+ mdss_edp_lane_power_ctrl(0);
+ edp_phy_powerup(0);
+
+ dprintf(INFO, "%s:\n", __func__);
+
+
+ return 0;
+}
+
+int edp_prepare(void)
+{
+
+ mdss_edp_aux_init();
+ edp_phy_pll_reset();
+ edp_mainlink_reset();
+ edp_aux_reset();
+ edp_phy_powerup(1);
+ edp_aux_enable();
+ mdss_edp_irq_enable();
+
+ mdss_edp_wait_for_hpd();
+
+ mdss_edp_edid_read();
+ mdss_edp_dpcd_cap_read();
+
+ edp_edid2pinfo(edp_pinfo);
+ edp_cap2pinfo(edp_pinfo);
+
+ dprintf(INFO, "%s:\n", __func__);
+
+ return 0;
+}
+
+void edp_panel_init(struct msm_panel_info *pinfo)
+{
+ if (!pinfo)
+ return;
+
+ pinfo->lcdc.dual_pipe = 1;
+ pinfo->lcdc.split_display = 0;
+
+ edp_pinfo = pinfo;
+ edp_pinfo->on = edp_on;
+ edp_pinfo->off = edp_off;
+ edp_pinfo->prepare = edp_prepare;
+}
diff --git a/platform/msm_shared/edp_aux.c b/platform/msm_shared/edp_aux.c
new file mode 100644
index 0000000..f7b5cfc
--- /dev/null
+++ b/platform/msm_shared/edp_aux.c
@@ -0,0 +1,1024 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "edp.h"
+
+struct edp_aux_ctrl edpctrl;
+
+int edp_hpd_done = 0;
+int edp_video_ready = 0;
+
+/*
+ * edid
+ */
+static char edid_hdr[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00};
+
+
+int edp_edid_buf_error(char *buf, int len)
+{
+ char *bp;
+ int i;
+ char csum = 0;
+ int ret = 0;
+
+ bp = buf;
+ if (len < 128) {
+ dprintf(INFO, "edp_edid_bur_error: Error: len=%x\n", len);
+ return -1;
+ }
+
+ for (i = 0; i < 128; i++)
+ csum += *bp++;
+
+ if (csum != 0) {
+ dprintf(INFO, "edp_edid_bur_error: Error: csum=%x\n", csum);
+ return -1;
+ }
+
+ if (buf[1] != 0xff) {
+ dprintf(INFO, "edp_edid_buf_error: Error: header\n");
+ return -1;
+ }
+
+ return ret;
+}
+
+
+void edp_extract_edid_manufacturer(struct edp_edid *edid, char *buf)
+{
+ char *bp;
+ char data;
+
+ bp = &buf[8];
+ data = *bp & 0x7f;
+ data >>= 2;
+ edid->id_name[0] = 'A' + data - 1;
+ data = *bp & 0x03;
+ data <<= 3;
+ bp++;
+ data |= (*bp >> 5);
+ edid->id_name[1] = 'A' + data - 1;
+ data = *bp & 0x1f;
+ edid->id_name[2] = 'A' + data - 1;
+ edid->id_name[3] = 0;
+
+ dprintf(INFO, "%s: edid manufacturer = %s", __func__,edid->id_name);
+}
+
+void edp_extract_edid_product(struct edp_edid *edid, char *buf)
+{
+ char *bp;
+ int data;
+
+ bp = &buf[0x0a];
+ data = *bp;
+ edid->id_product = *bp++;
+ edid->id_product &= 0x0ff;
+ data = *bp & 0x0ff;
+ data <<= 8;
+ edid->id_product |= data;
+
+ dprintf(INFO, "edid product = 0x%x", edid->id_product);
+};
+
+void edp_extract_edid_version(struct edp_edid *edid, char *buf)
+{
+ edid->version = buf[0x12];
+ edid->revision = buf[0x13];
+ dprintf(INFO, "edid version = %d.%d", edid->version,
+ edid->revision);
+};
+
+void edp_extract_edid_ext_block_cnt(struct edp_edid *edid, char *buf)
+{
+ edid->ext_block_cnt = buf[0x7e];
+ dprintf(INFO, "edid extension = %d", edid->ext_block_cnt);
+};
+
+void edp_extract_edid_video_support(struct edp_edid *edid, char *buf)
+{
+ char *bp;
+
+ bp = &buf[0x14];
+ if (*bp & 0x80) {
+ edid->video_intf = *bp & 0x0f;
+ /* 6, 8, 10, 12, 14 and 16 bit per component */
+ edid->color_depth = ((*bp & 0x70) >> 4); /* color bit depth */
+ if (edid->color_depth) {
+ edid->color_depth *= 2;
+ edid->color_depth += 4;
+ }
+ dprintf(INFO, "Digital Video intf=%d color_depth=%d\n",
+ edid->video_intf, edid->color_depth);
+ return;
+ }
+ dprintf(INFO, "Error, Analog video interface");
+};
+
+void edp_extract_edid_feature(struct edp_edid *edid, char *buf)
+{
+ char *bp;
+ char data;
+
+ bp = &buf[0x18];
+ data = *bp;
+ data &= 0xe0;
+ data >>= 5;
+ if (data == 0x01)
+ edid->dpm = 1; /* display power management */
+
+ if (edid->video_intf) {
+ if (*bp & 0x80) {
+ /* RGB 4:4:4, YcrCb 4:4:4 and YCrCb 4:2:2 */
+ edid->color_format = *bp & 0x18;
+ edid->color_format >>= 3;
+ }
+ }
+
+ dprintf(INFO, "edid dpm=%d color_format=%d",
+ edid->dpm, edid->color_format);
+};
+
+void edp_extract_edid_detailed_timing_description(struct edp_edid *edid,
+ char *buf)
+{
+ char *bp;
+ int data;
+ struct display_timing_desc *dp;
+
+ dp = &edid->timing[0];
+
+ bp = &buf[0x36];
+ dp->pclk = 0;
+ dp->pclk = *bp++; /* byte 0x36 */
+ dp->pclk |= (*bp++ << 8); /* byte 0x37 */
+
+ dp->h_addressable = *bp++; /* byte 0x38 */
+
+ if (dp->pclk == 0 && dp->h_addressable == 0)
+ return; /* Not detailed timing definition */
+
+ dp->pclk *= 10000;
+
+ dp->h_blank = *bp++;/* byte 0x39 */
+ data = *bp & 0xf0; /* byte 0x3A */
+ data <<= 4;
+ dp->h_addressable |= data;
+
+ data = *bp++ & 0x0f;
+ data <<= 8;
+ dp->h_blank |= data;
+
+ dp->v_addressable = *bp++; /* byte 0x3B */
+ dp->v_blank = *bp++; /* byte 0x3C */
+ data = *bp & 0xf0; /* byte 0x3D */
+ data <<= 4;
+ dp->v_addressable |= data;
+
+ data = *bp++ & 0x0f;
+ data <<= 8;
+ dp->v_blank |= data;
+
+ dp->h_fporch = *bp++; /* byte 0x3E */
+ dp->h_sync_pulse = *bp++; /* byte 0x3F */
+
+ dp->v_fporch = *bp & 0x0f0; /* byte 0x40 */
+ dp->v_fporch >>= 4;
+ dp->v_sync_pulse = *bp & 0x0f;
+
+ bp++;
+ data = *bp & 0xc0; /* byte 0x41 */
+ data <<= 2;
+ dp->h_fporch |= data;
+
+ data = *bp & 0x30;
+ data <<= 4;
+ dp->h_sync_pulse |= data;
+
+ data = *bp & 0x0c;
+ data <<= 2;
+ dp->v_fporch |= data;
+
+ data = *bp & 0x03;
+ data <<= 4;
+ dp->v_sync_pulse |= data;
+
+ bp++;
+ dp->width_mm = *bp++; /* byte 0x42 */
+ dp->height_mm = *bp++; /* byte 0x43 */
+ data = *bp & 0x0f0; /* byte 0x44 */
+ data <<= 4;
+ dp->width_mm |= data;
+ data = *bp & 0x0f;
+ data <<= 8;
+ dp->height_mm |= data;
+
+ bp++;
+ dp->h_border = *bp++; /* byte 0x45 */
+ dp->v_border = *bp++; /* byte 0x46 */
+
+ dp->interlaced = *bp & 0x80; /* byte 0x47 */
+
+ dp->stereo = *bp & 0x60;
+ dp->stereo >>= 5;
+
+ data = *bp & 0x1e; /* bit 4,3,2 1*/
+ data >>= 1;
+ dp->sync_type = data & 0x08;
+ dp->sync_type >>= 3; /* analog or digital */
+ if (dp->sync_type) {
+ dp->sync_separate = data & 0x04;
+ dp->sync_separate >>= 2;
+ if (dp->sync_separate) {
+ if (data & 0x02)
+ dp->vsync_pol = 1; /* positive */
+ else
+ dp->vsync_pol = 0;/* negative */
+
+ if (data & 0x01)
+ dp->hsync_pol = 1; /* positive */
+ else
+ dp->hsync_pol = 0; /* negative */
+ }
+ }
+
+ dprintf(INFO, "pixel_clock = %d\n", dp->pclk);
+
+ dprintf(INFO, "horizontal=%d, blank=%d, porch=%d, sync=%d\n"
+ , dp->h_addressable, dp->h_blank,
+ dp->h_fporch, dp->h_sync_pulse);
+ dprintf(INFO, "vertical=%d, blank=%d, porch=%d, vsync=%d\n"
+ , dp->v_addressable, dp->v_blank,
+ dp->v_fporch, dp->v_sync_pulse);
+ dprintf(INFO, "panel size in mm, width=%d height=%d\n",
+ dp->width_mm, dp->height_mm);
+ dprintf(INFO, "panel border horizontal=%d vertical=%d\n",
+ dp->h_border, dp->v_border);
+ dprintf(INFO, "flags: interlaced=%d stereo=%d sync_type=%d sync_sep=%d\n"
+ , dp->interlaced, dp->stereo,
+ dp->sync_type, dp->sync_separate);
+ dprintf(INFO, "polarity vsync=%d, hsync=%d\n",
+ dp->vsync_pol, dp->hsync_pol);
+}
+
+
+/*
+ * EDID structure can be found in VESA standart here:
+ * http://read.pudn.com/downloads110/ebook/456020/E-EDID%20Standard.pdf
+ *
+ * following table contains default edid
+ * static char edid_raw_data[128] = {
+ * 0, 255, 255, 255, 255, 255, 255, 0,
+ * 6, 175, 93, 48, 0, 0, 0, 0, 0, 22,
+ * 1, 4,
+ * 149, 26, 14, 120, 2,
+ * 164, 21,158, 85, 78, 155, 38, 15, 80, 84,
+ * 0, 0, 0,
+ * 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ * 29, 54, 128, 160, 112, 56, 30, 64, 48, 32, 142, 0, 0, 144, 16,0,0,24,
+ * 19, 36, 128, 160, 112, 56, 30, 64, 48, 32, 142, 0, 0, 144, 16,0,0,24,
+ * 0, 0, 0, 254, 0, 65, 85, 79, 10, 32, 32, 32, 32, 32, 32, 32, 32, 32,
+ * 0, 0, 0, 254, 0, 66, 49, 49, 54, 72, 65, 78, 48, 51, 46, 48, 32, 10,
+ * 0, 75 };
+ */
+
+static int edp_aux_chan_ready(struct edp_aux_ctrl *ep)
+{
+ int cnt, ret;
+ char data = 0;
+
+ cnt = 5;
+ while(cnt--) {
+ ret = edp_aux_write_buf(ep, 0x50, &data, 1, 1);
+ dprintf(INFO, "edp_aux_chan_ready: ret=%d\n", ret);
+ if (ret >= 0)
+ break;
+ dprintf(INFO, "edp_aux_chan_ready: failed in write\n");
+ mdelay(100);
+ }
+
+ if (cnt == 0)
+ return 0;
+
+ return 1;
+}
+
+static int edp_sink_edid_read(struct edp_aux_ctrl *ep, int block)
+{
+ struct edp_buf *rp;
+ int cnt, rlen;
+ char data = 0;
+ int ret = 0;
+
+start:
+ cnt = 5;
+dprintf(INFO, "%s: cnt=%d\n", __func__, cnt);
+ /* need to write a dummy byte before read edid */
+ while(cnt--) {
+ ret = edp_aux_write_buf(ep, 0x50, &data, 1, 1);
+ if (ret >= 0)
+ break;
+ dprintf(INFO, "edp_sink_edid_read: failed in write\n");
+ mdelay(100);
+ }
+
+ if (cnt == 0)
+ return -1;
+
+ rlen = edp_aux_read_buf(ep, 0x50, 128, 1);
+
+dprintf(INFO, "edp_sink_edid_read: rlen=%d\n", rlen);
+
+ if (rlen < 0)
+ goto start;
+
+ rp = &ep->rxp;
+ if (edp_edid_buf_error(rp->data, rp->len))
+ goto start;
+
+ edp_extract_edid_manufacturer(&ep->edid, rp->data);
+ edp_extract_edid_product(&ep->edid, rp->data);
+ edp_extract_edid_version(&ep->edid, rp->data);
+ edp_extract_edid_ext_block_cnt(&ep->edid, rp->data);
+ edp_extract_edid_video_support(&ep->edid, rp->data);
+ edp_extract_edid_feature(&ep->edid, rp->data);
+ edp_extract_edid_detailed_timing_description(&ep->edid, rp->data);
+
+ return 128;
+}
+
+/*
+ * Converts from EDID struct to msm_panel_info
+ */
+void edp_edid2pinfo(struct msm_panel_info *pinfo)
+{
+ struct display_timing_desc *dp;
+
+ dp = &edpctrl.edid.timing[0];
+
+ pinfo->clk_rate = dp->pclk;
+
+ dprintf(SPEW, "%s: pclk=%d\n", __func__, pinfo->clk_rate);
+
+ pinfo->xres = dp->h_addressable + dp->h_border * 2;
+ pinfo->yres = dp->v_addressable + dp->v_border * 2;
+
+ pinfo->lcdc.h_back_porch = dp->h_blank - dp->h_fporch \
+ - dp->h_sync_pulse;
+ pinfo->lcdc.h_front_porch = dp->h_fporch;
+ pinfo->lcdc.h_pulse_width = dp->h_sync_pulse;
+
+ pinfo->lcdc.v_back_porch = dp->v_blank - dp->v_fporch \
+ - dp->v_sync_pulse;
+ pinfo->lcdc.v_front_porch = dp->v_fporch;
+ pinfo->lcdc.v_pulse_width = dp->v_sync_pulse;
+
+ pinfo->type = EDP_PANEL;
+ pinfo->wait_cycle = 0;
+ pinfo->bpp = 24;
+
+ pinfo->lcdc.border_clr = 0; /* black */
+ pinfo->lcdc.underflow_clr = 0xff; /* blue */
+ pinfo->lcdc.hsync_skew = 0;
+}
+
+void edp_cap2pinfo(struct msm_panel_info *pinfo)
+{
+ struct dpcd_cap *cap;
+
+ cap = &edpctrl.dpcd;
+
+ pinfo->edp.max_lane_count = cap->max_lane_count;
+ pinfo->edp.max_link_clk = cap->max_link_rate;
+
+ dprintf(SPEW, "%s: clk=%d lane=%d\n", __func__,
+ pinfo->edp.max_lane_count, pinfo->edp.max_link_clk);
+}
+
+static void edp_sink_capability_read(struct edp_aux_ctrl *ep,
+ int len)
+{
+ char *bp;
+ char data;
+ struct dpcd_cap *cap;
+ struct edp_buf *rp;
+ int rlen;
+
+ dprintf(INFO, "%s:\n",__func__);
+
+ rlen = edp_aux_read_buf(ep, 0, len, 0);
+ if (rlen <= 0) {
+ dprintf(INFO, "edp_sink_capability_read: edp aux read failed\n");
+ return;
+ }
+ rp = &ep->rxp;
+ cap = &ep->dpcd;
+ bp = rp->data;
+
+ data = *bp++; /* byte 0 */
+ cap->major = (data >> 4) & 0x0f;
+ cap->minor = data & 0x0f;
+ if (--rlen <= 0)
+ return;
+ dprintf(INFO, "edp_sink_cap_read: version: %d.%d\n", cap->major, cap->minor);
+
+ data = *bp++; /* byte 1 */
+ /* 162, 270 and 540 MB, symbol rate, NOT bit rate */
+ cap->max_link_rate = data * 27;
+ if (--rlen <= 0)
+ return;
+ dprintf(INFO, "edp_sink_cap_read: link_rate=%d\n", cap->max_link_rate);
+
+ data = *bp++; /* byte 2 */
+ if (data & BIT(7))
+ cap->flags |= DPCD_ENHANCED_FRAME;
+ if (data & 0x40)
+ cap->flags |= DPCD_TPS3;
+ data &= 0x0f;
+ cap->max_lane_count = data;
+ if (--rlen <= 0)
+ return;
+ dprintf(INFO, "edp_sink_cap_read: lane_count=%d\n", cap->max_lane_count);
+
+ data = *bp++; /* byte 3 */
+ if (data & BIT(0)) {
+ cap->flags |= DPCD_MAX_DOWNSPREAD_0_5;
+ dprintf(INFO, "edp_sink_cap_read: max_downspread\n");
+ }
+
+ if (data & BIT(6)) {
+ cap->flags |= DPCD_NO_AUX_HANDSHAKE;
+ dprintf(INFO, "edp_sink_cap_read: NO Link Training\n");
+ }
+ if (--rlen <= 0)
+ return;
+
+ data = *bp++; /* byte 4 */
+ cap->num_rx_port = (data & BIT(0)) + 1;
+ dprintf(INFO, "edp_sink_cap_read: rx_ports=%d", cap->num_rx_port);
+ if (--rlen <= 0)
+ return;
+
+ bp += 3; /* skip 5, 6 and 7 */
+ rlen -= 3;
+ if (rlen <= 0)
+ return;
+
+ data = *bp++; /* byte 8 */
+ if (data & BIT(1)) {
+ cap->flags |= DPCD_PORT_0_EDID_PRESENTED;
+ dprintf(INFO, "edp_sink_cap_read: edid presented\n");
+ }
+ if (--rlen <= 0)
+ return;
+
+ data = *bp++; /* byte 9 */
+ cap->rx_port0_buf_size = (data + 1) * 32;
+ dprintf(INFO, "edp_sink_cap_read: lane_buf_size=%d", cap->rx_port0_buf_size);
+ if (--rlen <= 0)
+ return;
+
+ bp += 2; /* skip 10, 11 port1 capability */
+ rlen -= 2;
+ if (rlen <= 0)
+ return;
+
+ data = *bp++; /* byte 12 */
+ cap->i2c_speed_ctrl = data;
+ if (cap->i2c_speed_ctrl > 0)
+ dprintf(INFO, "edp_sink_cap_read: i2c_rate=%d", cap->i2c_speed_ctrl);
+ if (--rlen <= 0)
+ return;
+
+ data = *bp++; /* byte 13 */
+ cap->scrambler_reset = data & BIT(0);
+ dprintf(INFO, "edp_sink_cap_read: scrambler_reset=%d\n",
+ cap->scrambler_reset);
+
+ cap->enhanced_frame = data & BIT(1);
+ dprintf(INFO, "edp_sink_cap_read: enhanced_framing=%d\n",
+ cap->enhanced_frame);
+ if (--rlen <= 0)
+ return;
+
+ data = *bp++; /* byte 14 */
+ if (data == 0)
+ cap->training_read_interval = 100; /* us */
+ else
+ cap->training_read_interval = 4000 * data; /* us */
+ dprintf(INFO, "edp_sink_cap_read: training_interval=%d\n",
+ cap->training_read_interval);
+}
+
+static void edp_link_status_read(struct edp_aux_ctrl *ep, int len)
+{
+ char *bp;
+ char data;
+ struct dpcd_link_status *sp;
+ struct edp_buf *rp;
+ int rlen;
+
+
+ /* skip byte 0x200 and 0x201 */
+ rlen = edp_aux_read_buf(ep, 0x202, len, 0);
+ dprintf(INFO, "%s: rlen=%d\n", __func__, rlen);
+ if (rlen <= 0) {
+ dprintf(INFO, "edp_link_status_read: edp aux read failed\n");
+ return;
+ }
+ rp = &ep->rxp;
+ bp = rp->data;
+ sp = &ep->link_status;
+
+ data = *bp++; /* byte 0x202 */
+ sp->lane_01_status = data; /* lane 0, 1 */
+ if (--rlen <= 0)
+ return;
+
+ data = *bp++; /* byte 0x203 */
+ sp->lane_23_status = data; /* lane 2, 3 */
+ if (--rlen <= 0)
+ return;
+
+ data = *bp++; /* byte 0x204 */
+ sp->interlane_align_done = (data & BIT(0));
+ sp->downstream_port_status_changed = (data & BIT(6));
+ sp->link_status_updated = (data & BIT(7));
+ if (--rlen <= 0)
+ return;
+
+ data = *bp++; /* byte 0x205 */
+ sp->port_0_in_sync = (data & BIT(0));
+ sp->port_1_in_sync = (data & BIT(1));
+ if (--rlen <= 0)
+ return;
+
+ data = *bp++; /* byte 0x206 */
+ sp->req_voltage_swing[0] = data & 0x03;
+ data >>= 2;
+ sp->req_pre_emphasis[0] = data & 0x03;
+ data >>= 2;
+ sp->req_voltage_swing[1] = data & 0x03;
+ data >>= 2;
+ sp->req_pre_emphasis[1] = data & 0x03;
+ if (--rlen <= 0)
+ return;
+
+ data = *bp++; /* byte 0x207 */
+ sp->req_voltage_swing[2] = data & 0x03;
+ data >>= 2;
+ sp->req_pre_emphasis[2] = data & 0x03;
+ data >>= 2;
+ sp->req_voltage_swing[3] = data & 0x03;
+ data >>= 2;
+ sp->req_pre_emphasis[3] = data & 0x03;
+
+ bp = rp->data;
+dprintf(INFO, "%s: %x %x %x %x %x %x\n", __func__, *bp,
+ *(bp+1), *(bp+2), *(bp+3), *(bp+4), *(bp+5));
+
+ dprintf(INFO, "%s: align=%d v=%d p=%d\n", __func__,
+ sp->interlane_align_done, sp->req_voltage_swing[0], sp->req_pre_emphasis[0]);
+}
+
+
+static int edp_cap_lane_rate_set(struct edp_aux_ctrl *ep)
+{
+ char buf[4];
+ int len = 0;
+
+ dprintf(INFO, "cap_lane_set: bw=%x lane=%d\n", ep->link_rate, ep->lane_cnt);
+ buf[0] = ep->link_rate;
+ buf[1] = ep->lane_cnt;
+ len = edp_aux_write_buf(ep, 0x100, buf, 2, 0);
+
+ return len;
+}
+
+static int edp_lane_set_write(struct edp_aux_ctrl *ep, int voltage_level,
+ int pre_emphasis_level)
+{
+ int i;
+ char buf[4];
+
+
+ if (voltage_level >= DPCD_LINK_VOLTAGE_MAX)
+ voltage_level |= 0x04;
+
+ if (pre_emphasis_level >= DPCD_LINK_PRE_EMPHASIS_MAX)
+ pre_emphasis_level |= 0x04;
+
+ pre_emphasis_level <<= 3;
+
+ for (i = 0; i < 4; i++)
+ buf[i] = voltage_level | pre_emphasis_level;
+
+ dprintf(INFO, "%s: p|v=0x%x\n", __func__, voltage_level | pre_emphasis_level);
+ return edp_aux_write_buf(ep, 0x103, buf, 4, 0);
+}
+
+static int edp_powerstate_write(struct edp_aux_ctrl *ep,
+ char powerstate)
+{
+ return edp_aux_write_buf(ep, 0x600, &powerstate, 1, 0);
+}
+
+static int edp_train_pattern_set_write(struct edp_aux_ctrl *ep,
+ int pattern)
+{
+ char buf[4];
+
+ buf[0] = pattern;
+ return edp_aux_write_buf(ep, 0x102, buf, 1, 0);
+}
+
+static int edp_sink_clock_recovery_done(struct edp_aux_ctrl *ep)
+{
+ int mask;
+ int data;
+
+
+ if (ep->lane_cnt == 1) {
+ mask = 0x01; /* lane 0 */
+ data = ep->link_status.lane_01_status;
+ } else if (ep->lane_cnt == 2) {
+ mask = 0x011; /*B lane 0, 1 */
+ data = ep->link_status.lane_01_status;
+ } else {
+ mask = 0x01111; /*B lane 0, 1 */
+ data = ep->link_status.lane_23_status;
+ data <<= 8;
+ data |= ep->link_status.lane_01_status;
+ }
+
+dprintf(INFO, "clock_recovery_done: data=%x mask=%x\n", data, mask);
+ data &= mask;
+ if (data == mask) /* all done */
+ return 1;
+
+ return 0;
+}
+
+static int edp_sink_channel_eq_done(struct edp_aux_ctrl *ep)
+{
+ int mask;
+ int data;
+
+
+ if (!ep->link_status.interlane_align_done) /* not align */
+ return 0;
+
+ if (ep->lane_cnt == 1) {
+ mask = 0x7;
+ data = ep->link_status.lane_01_status;
+ } else if (ep->lane_cnt == 2) {
+ mask = 0x77;
+ data = ep->link_status.lane_01_status;
+ } else {
+ mask = 0x7777;
+ data = ep->link_status.lane_23_status;
+ data <<= 8;
+ data |= ep->link_status.lane_01_status;
+ }
+
+dprintf(INFO, "%s: data=%x mask=%x\n", __func__, data, mask);
+
+ data &= mask;
+ if (data == mask)/* all done */
+ return 1;
+
+ return 0;
+}
+
+void edp_sink_train_set_adjust(struct edp_aux_ctrl *ep)
+{
+ int i;
+ int max = 0;
+
+
+ /* use the max level across lanes */
+ for (i = 0; i < ep->lane_cnt; i++) {
+ if (max < ep->link_status.req_voltage_swing[i])
+ max = ep->link_status.req_voltage_swing[i];
+ }
+
+ ep->v_level = max;
+
+ /* use the max level across lanes */
+ max = 0;
+ for (i = 0; i < ep->lane_cnt; i++) {
+ if (max < ep->link_status.req_pre_emphasis[i])
+ max = ep->link_status.req_pre_emphasis[i];
+ }
+
+ ep->p_level = max;
+ dprintf(INFO, "train_set_adjust: v_level=%d, p_level=%d\n",
+ ep->v_level, ep->p_level);
+}
+
+static void edp_host_train_set(struct edp_aux_ctrl *ep, int train)
+{
+ int bit, cnt;
+ int data;
+
+
+ bit = 1;
+ bit <<= (train - 1);
+ edp_write(EDP_BASE + EDP_STATE_CTRL, bit);
+
+ bit = 8;
+ bit <<= (train - 1);
+ cnt = 10;
+ while (cnt--) {
+ data = edp_read(EDP_BASE + EDP_MAINLINK_READY);
+ if (data & bit)
+ break;
+ }
+
+ if (cnt == 0)
+ dprintf(INFO, "%s: set link_train=%d failed\n", __func__, train);
+}
+
+char vm_pre_emphasis[4][4] = {
+ {0x03, 0x06, 0x09, 0x0C},
+ {0x03, 0x06, 0x09, 0xFF},
+ {0x03, 0x06, 0xFF, 0xFF},
+ {0x03, 0xFF, 0xFF, 0xFF}
+};
+
+char vm_voltage_swing[4][4] = {
+ {0x64, 0x68, 0x6A, 0x6E},
+ {0x68, 0x6A, 0x6E, 0xFF},
+ {0x6A, 0x6E, 0xFF, 0xFF},
+ {0x6E, 0xFF, 0xFF, 0xFF}
+};
+
+static void edp_voltage_pre_emphasise_set(struct edp_aux_ctrl *ep)
+{
+ int value0 = 0;
+ int value1 = 0;
+
+ dprintf(INFO, "voltage_pre_emphasis_set: v=%d p=%d\n", ep->v_level, ep->p_level);
+
+ value0 = vm_pre_emphasis[(int)(ep->v_level)][(int)(ep->p_level)];
+ value1 = vm_voltage_swing[(int)(ep->v_level)][(int)(ep->p_level)];
+
+ /* Configure host and panel only if both values are allowed */
+ if (value0 != 0xFF && value1 != 0xFF) {
+ edp_write(EDP_BASE + EDP_PHY_EDPPHY_GLB_VM_CFG0, value0);
+ edp_write(EDP_BASE + EDP_PHY_EDPPHY_GLB_VM_CFG1, value1);
+ dprintf(INFO, "voltage_pre_emphasis_set: value0=0x%x value1=0x%x\n",
+ value0, value1);
+ edp_lane_set_write(ep, ep->v_level, ep->p_level);
+ }
+
+}
+
+static int edp_start_link_train_1(struct edp_aux_ctrl *ep)
+{
+ int tries, old_v_level;
+ int ret = 0;
+
+ dprintf(INFO, "link_train_1\n");
+
+ edp_host_train_set(ep, 0x01); /* train_1 */
+ edp_voltage_pre_emphasise_set(ep);
+ edp_train_pattern_set_write(ep, 0x21); /* train_1 */
+
+ tries = 0;
+ old_v_level = ep->v_level;
+ while (1) {
+ udelay(ep->dpcd.training_read_interval * 10);
+
+ edp_link_status_read(ep, 6);
+ if (edp_sink_clock_recovery_done(ep)) {
+ ret = 0;
+ break;
+ }
+
+ if (ep->v_level == DPCD_LINK_VOLTAGE_MAX) {
+ ret = -1;
+ break; /* quit */
+ }
+
+ if (old_v_level == ep->v_level) {
+ tries++;
+ if (tries >= 5) {
+ ret = -1;
+ break; /* quit */
+ }
+ } else {
+ tries = 0;
+ old_v_level = ep->v_level;
+ }
+
+ edp_sink_train_set_adjust(ep);
+ edp_voltage_pre_emphasise_set(ep);
+ }
+
+ return ret;
+}
+
+static int edp_start_link_train_2(struct edp_aux_ctrl *ep)
+{
+ int tries;
+ int ret = 0;
+ char pattern;
+
+ dprintf(INFO, "link_train_2\n");
+
+ if (ep->dpcd.flags & DPCD_TPS3)
+ pattern = 0x03;
+ else
+ pattern = 0x02;
+
+ edp_host_train_set(ep, pattern); /* train_2 */
+ edp_voltage_pre_emphasise_set(ep);
+ edp_train_pattern_set_write(ep, pattern | 0x20);/* train_2 */
+
+ tries = 0;
+ while (1) {
+ udelay(ep->dpcd.training_read_interval);
+
+ edp_link_status_read(ep, 6);
+
+ if (edp_sink_channel_eq_done(ep)) {
+ ret = 0;
+ break;
+ }
+
+ tries++;
+ if (tries > 5) {
+ ret = -1;
+ break;
+ }
+
+ edp_sink_train_set_adjust(ep);
+ edp_voltage_pre_emphasise_set(ep);
+ }
+
+ return ret;
+}
+
+static int edp_link_rate_shift(struct edp_aux_ctrl *ep)
+{
+ /* add calculation later */
+ return -1;
+}
+
+static void edp_clear_training_pattern(struct edp_aux_ctrl *ep)
+{
+ dprintf(INFO, "clear_training_pattern:\n");
+ edp_write(EDP_BASE + EDP_STATE_CTRL, 0);
+ edp_train_pattern_set_write(ep, 0);
+ udelay(ep->dpcd.training_read_interval);
+}
+
+static int edp_aux_link_train(struct edp_aux_ctrl *ep)
+{
+ int ret = 0;
+
+ dprintf(INFO, "%s:\n", __func__);
+ ret = edp_aux_chan_ready(ep);
+ if (ret == 0) {
+ dprintf(INFO, "link_train: LINK Train failed: aux chan NOT ready\n");
+ return ret;
+ }
+
+ /* start with max rate and lane */
+ ep->lane_cnt = ep->dpcd.max_lane_count;
+ ep->link_rate = ep->dpcd.max_link_rate;
+ edp_write(EDP_BASE + EDP_MAINLINK_CTRL, 0x1);
+
+train_start:
+ ep->v_level = 0; /* start from default level */
+ ep->p_level = 0;
+ edp_cap_lane_rate_set(ep);
+
+ edp_clear_training_pattern(ep);
+ udelay(ep->dpcd.training_read_interval);
+ edp_powerstate_write(ep, 1);
+
+ ret = edp_start_link_train_1(ep);
+ if (ret < 0) {
+ if (edp_link_rate_shift(ep) == 0) {
+ goto train_start;
+ } else {
+ dprintf(INFO, "Training 1 failed\n");
+ ret = -1;
+ goto clear;
+ }
+ }
+
+ dprintf(INFO, "%s: Training 1 completed successfully\n", __func__);
+
+ edp_clear_training_pattern(ep);
+ ret = edp_start_link_train_2(ep);
+ if (ret < 0) {
+ if (edp_link_rate_shift(ep) == 0) {
+ goto train_start;
+ } else {
+ dprintf(INFO, "Training 2 failed\n");
+ ret = -1;
+ goto clear;
+ }
+ }
+
+ dprintf(INFO, "%s: Training 2 completed successfully\n", __func__);
+
+clear:
+ edp_clear_training_pattern(ep);
+
+ return ret;
+}
+
+void mdss_edp_wait_for_hpd(void)
+{
+ while(1) {
+ udelay(1000);
+ edp_isr_poll();
+ if (edp_hpd_done) {
+ edp_hpd_done = 0;
+ break;
+ }
+ }
+}
+
+void mdss_edp_wait_for_video_ready(void)
+{
+ while(1) {
+ udelay(1000);
+ edp_isr_poll();
+ if (edp_video_ready) {
+ edp_video_ready = 0;
+ break;
+ }
+ }
+}
+
+void mdss_edp_dpcd_cap_read(void)
+{
+ edp_sink_capability_read(&edpctrl, 16);
+}
+void mdss_edp_pll_configure(void)
+{
+ struct display_timing_desc *dp;
+
+ dp = &edpctrl.edid.timing[0];
+ edp_pll_configure(dp->pclk);
+}
+
+void mdss_edp_lane_power_ctrl(int up)
+{
+
+ dprintf(SPEW, "%s: max_lane=%d\n", __func__, edpctrl.dpcd.max_lane_count);
+ edp_lane_power_ctrl(edpctrl.dpcd.max_lane_count, up);
+
+}
+
+void mdss_edp_dpcd_status_read(void)
+{
+ edp_link_status_read(&edpctrl, 6);
+}
+
+void mdss_edp_edid_read(void)
+{
+ edp_sink_edid_read(&edpctrl, 0);
+}
+
+int mdss_edp_link_train(void)
+{
+ return edp_aux_link_train(&edpctrl);
+}
+
+void mdss_edp_aux_init(void)
+{
+ edp_buf_init(&edpctrl.txp, edpctrl.txbuf, sizeof(edpctrl.txbuf));
+ edp_buf_init(&edpctrl.rxp, edpctrl.rxbuf, sizeof(edpctrl.rxbuf));
+}
diff --git a/platform/msm_shared/edp_phy.c b/platform/msm_shared/edp_phy.c
new file mode 100644
index 0000000..decef57
--- /dev/null
+++ b/platform/msm_shared/edp_phy.c
@@ -0,0 +1,334 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+#include "edp.h"
+
+/* EDP phy configuration settings */
+
+void edp_phy_pll_reset(void)
+{
+ /* EDP_PHY_CTRL */
+ edp_write(EDP_BASE + 0x74, 0x005); /* bit 0, 2 */
+ dmb();
+ udelay(1);
+ edp_write(EDP_BASE + 0x74, 0x000); /* EDP_PHY_CTRL */
+}
+
+void edp_mainlink_reset(void)
+{
+ edp_write(EDP_BASE + 0x04, 0x02 ); /* EDP_MAINLINK_CTRL */
+ dmb();
+ udelay(1);
+ edp_write(EDP_BASE + 0x04, 0 ); /* EDP_MAINLINK_CTRL */
+}
+
+void edp_aux_reset(void)
+{
+ /*reset AUX */
+ edp_write(EDP_BASE + 0x300, BIT(1)); /* EDP_AUX_CTRL */
+ dmb();
+ udelay(1);
+ edp_write(EDP_BASE + 0x300, 0); /* EDP_AUX_CTRL */
+}
+
+void edp_aux_enable(void)
+{
+ edp_write(EDP_BASE + 0x300, 0x01); /* EDP_AUX_CTRL */
+ dmb();
+ udelay(1);
+}
+
+void edp_phy_powerup(int enable)
+{
+ if (enable) {
+ /* EDP_PHY_EDPPHY_GLB_PD_CTL */
+ edp_write(EDP_BASE + 0x52c, 0x3f);
+ /* EDP_PHY_EDPPHY_GLB_CFG */
+ edp_write(EDP_BASE + 0x528, 0x1);
+ /* EDP_PHY_PLL_UNIPHY_PLL_GLB_CFG */
+ edp_write(EDP_BASE + 0x620, 0xf);
+ } else {
+ /* EDP_PHY_EDPPHY_GLB_PD_CTL */
+ edp_write(EDP_BASE + 0x52c, 0xc0);
+ edp_write(EDP_BASE + 0x620, 0x0);
+ }
+}
+
+void edp_lane_power_ctrl(int max_lane, int up)
+{
+ int i, off;
+ unsigned int data;
+
+ if (up)
+ data = 0; /* power up */
+ else
+ data = 0x7; /* power down */
+
+ /* EDP_PHY_EDPPHY_LNn_PD_CTL */
+ for (i = 0; i < max_lane; i++) {
+ off = 0x40 * i;
+ edp_write(EDP_BASE + 0x404 + off , data);
+ }
+}
+
+void edp_phy_sw_reset(void)
+{
+ /* phy sw reset */
+ edp_write(EDP_BASE + 0x74, 0x100); /* EDP_PHY_CTRL */
+ dmb();
+ udelay(1);
+ edp_write(EDP_BASE + 0x74, 0x000); /* EDP_PHY_CTRL */
+ dmb();
+ udelay(1);
+
+ /* phy PLL sw reset */
+ edp_write(EDP_BASE + 0x74, 0x001); /* EDP_PHY_CTRL */
+ dmb();
+ udelay(1);
+ edp_write(EDP_BASE + 0x74, 0x000); /* EDP_PHY_CTRL */
+ dmb();
+ udelay(1);
+}
+
+void edp_hw_powerup(int enable)
+{
+ int ret = 0;
+
+ if (enable) {
+ /* EDP_PHY_EDPPHY_GLB_PD_CTL */
+ edp_write(EDP_BASE + 0x52c, 0x3f);
+ /* EDP_PHY_EDPPHY_GLB_CFG */
+ edp_write(EDP_BASE + 0x528, 0x1);
+ /* EDP_PHY_PLL_UNIPHY_PLL_GLB_CFG */
+ edp_write(EDP_BASE + 0x620, 0xf);
+ /* EDP_AUX_CTRL */
+ ret = edp_read(EDP_BASE + 0x300);
+ ret = edp_read(EDP_BASE + 0x300);
+ edp_write(EDP_BASE + 0x300, ret | 0x1);
+ } else {
+ /* EDP_PHY_EDPPHY_GLB_PD_CTL */
+ edp_write(EDP_BASE + 0x52c, 0xc0);
+ }
+}
+
+void edp_pll_configure(unsigned int rate)
+{
+
+ if (rate == 810000000) {
+ edp_write(EDP_BASE + 0x60c, 0x18);
+ edp_write(EDP_BASE + 0x664, 0x5);
+ edp_write(EDP_BASE + 0x600, 0x0);
+ edp_write(EDP_BASE + 0x638, 0x36);
+ edp_write(EDP_BASE + 0x63c, 0x69);
+ edp_write(EDP_BASE + 0x640, 0xff);
+ edp_write(EDP_BASE + 0x644, 0x2f);
+ edp_write(EDP_BASE + 0x648, 0x0);
+ edp_write(EDP_BASE + 0x66c, 0x0a);
+ edp_write(EDP_BASE + 0x674, 0x01);
+ edp_write(EDP_BASE + 0x684, 0x5a);
+ edp_write(EDP_BASE + 0x688, 0x0);
+ edp_write(EDP_BASE + 0x68c, 0x60);
+ edp_write(EDP_BASE + 0x690, 0x0);
+ edp_write(EDP_BASE + 0x694, 0x2a);
+ edp_write(EDP_BASE + 0x698, 0x3);
+ edp_write(EDP_BASE + 0x65c, 0x10);
+ edp_write(EDP_BASE + 0x660, 0x1a);
+ edp_write(EDP_BASE + 0x604, 0x0);
+ edp_write(EDP_BASE + 0x624, 0x0);
+ edp_write(EDP_BASE + 0x628, 0x0);
+
+ edp_write(EDP_BASE + 0x620, 0x1);
+ edp_write(EDP_BASE + 0x620, 0x5);
+ edp_write(EDP_BASE + 0x620, 0x7);
+ edp_write(EDP_BASE + 0x620, 0xf);
+
+ } else if (rate == 138530000) {
+ edp_write(EDP_BASE + 0x664, 0x5); /* UNIPHY_PLL_LKDET_CFG2 */
+ edp_write(EDP_BASE + 0x600, 0x1); /* UNIPHY_PLL_REFCLK_CFG */
+ edp_write(EDP_BASE + 0x638, 0x36); /* UNIPHY_PLL_SDM_CFG0 */
+ edp_write(EDP_BASE + 0x63c, 0x62); /* UNIPHY_PLL_SDM_CFG1 */
+ edp_write(EDP_BASE + 0x640, 0x0); /* UNIPHY_PLL_SDM_CFG2 */
+ edp_write(EDP_BASE + 0x644, 0x28); /* UNIPHY_PLL_SDM_CFG3 */
+ edp_write(EDP_BASE + 0x648, 0x0); /* UNIPHY_PLL_SDM_CFG4 */
+ edp_write(EDP_BASE + 0x64c, 0x80); /* UNIPHY_PLL_SSC_CFG0 */
+ edp_write(EDP_BASE + 0x650, 0x0); /* UNIPHY_PLL_SSC_CFG1 */
+ edp_write(EDP_BASE + 0x654, 0x0); /* UNIPHY_PLL_SSC_CFG2 */
+ edp_write(EDP_BASE + 0x658, 0x0); /* UNIPHY_PLL_SSC_CFG3 */
+ edp_write(EDP_BASE + 0x66c, 0xa); /* UNIPHY_PLL_CAL_CFG0 */
+ edp_write(EDP_BASE + 0x674, 0x1); /* UNIPHY_PLL_CAL_CFG2 */
+ edp_write(EDP_BASE + 0x684, 0x5a); /* UNIPHY_PLL_CAL_CFG6 */
+ edp_write(EDP_BASE + 0x688, 0x0); /* UNIPHY_PLL_CAL_CFG7 */
+ edp_write(EDP_BASE + 0x68c, 0x60); /* UNIPHY_PLL_CAL_CFG8 */
+ edp_write(EDP_BASE + 0x690, 0x0); /* UNIPHY_PLL_CAL_CFG9 */
+ edp_write(EDP_BASE + 0x694, 0x46); /* UNIPHY_PLL_CAL_CFG10 */
+ edp_write(EDP_BASE + 0x698, 0x5); /* UNIPHY_PLL_CAL_CFG11 */
+ edp_write(EDP_BASE + 0x65c, 0x10); /* UNIPHY_PLL_LKDET_CFG0 */
+ edp_write(EDP_BASE + 0x660, 0x1a); /* UNIPHY_PLL_LKDET_CFG1 */
+ edp_write(EDP_BASE + 0x604, 0x0); /* UNIPHY_PLL_POSTDIV1_CFG */
+ edp_write(EDP_BASE + 0x624, 0x0); /* UNIPHY_PLL_POSTDIV2_CFG */
+ edp_write(EDP_BASE + 0x628, 0x0); /* UNIPHY_PLL_POSTDIV3_CFG */
+
+ edp_write(EDP_BASE + 0x620, 0x1); /* UNIPHY_PLL_GLB_CFG */
+ edp_write(EDP_BASE + 0x620, 0x5); /* UNIPHY_PLL_GLB_CFG */
+ edp_write(EDP_BASE + 0x620, 0x7); /* UNIPHY_PLL_GLB_CFG */
+ edp_write(EDP_BASE + 0x620, 0xf); /* UNIPHY_PLL_GLB_CFG */
+ } else {
+ dprintf(INFO, "%s: rate=%d is NOT supported\n", __func__, rate);
+
+ }
+}
+
+
+int mdss_edp_phy_pll_ready(void)
+{
+ int cnt;
+ int status;
+
+ cnt = 10;
+ while(cnt--) {
+ status = edp_read(EDP_BASE + 0x6c0);
+ if (status & 0x01)
+ break;
+ udelay(100);
+ }
+
+ if(cnt == 0) {
+ dprintf("%s: PLL NOT ready\n", __func__);
+ return 0;
+ }
+ else
+ return 1;
+}
+
+void edp_enable_mainlink(int enable)
+{
+ uint32_t data;
+
+ data = edp_read(EDP_BASE + 0x004);
+ data &= ~BIT(0);
+
+ if (enable) {
+ data |= 0x1;
+ edp_write(EDP_BASE + 0x004, data);
+ edp_write(EDP_BASE + 0x004, 0x1);
+ } else {
+ data |= 0x0;
+ edp_write(EDP_BASE + 0x004, data);
+ }
+}
+
+void edp_enable_lane_bist(int lane, int enable)
+{
+ unsigned char *addr_ln_bist_cfg, *addr_ln_pd_ctrl;
+
+ /* EDP_PHY_EDPPHY_LNn_PD_CTL */
+ addr_ln_pd_ctrl = (unsigned char *)(EDP_BASE + 0x404 + (0x40 * lane));
+ /* EDP_PHY_EDPPHY_LNn_BIST_CFG0 */
+ addr_ln_bist_cfg = (unsigned char *)(EDP_BASE + 0x408 + (0x40 * lane));
+
+ if (enable) {
+ edp_write(addr_ln_pd_ctrl, 0x0);
+ edp_write(addr_ln_bist_cfg, 0x10);
+
+ } else {
+ edp_write(addr_ln_pd_ctrl, 0xf);
+ edp_write(addr_ln_bist_cfg, 0x10);
+ }
+}
+
+void edp_enable_pixel_clk(int enable)
+{
+ if (!enable) {
+ edp_write(MDSS_EDPPIXEL_CBCR, 0); /* CBCR */
+ return;
+ }
+
+ edp_write(EDP_BASE + 0x624, 0x1); /* PostDiv2 */
+
+ /* Configuring MND for Pixel */
+ edp_write(EDPPIXEL_M, 0x3f); /* M value */
+ edp_write(EDPPIXEL_N, 0xb); /* N value */
+ edp_write(EDPPIXEL_D, 0x0); /* D value */
+
+ /* CFG RCGR */
+ edp_write(EDPPIXEL_CFG_RCGR, (5 << 8) | (2 << 12));
+ edp_write(EDPPIXEL_CMD_RCGR, 3); /* CMD RCGR */
+
+ edp_write(MDSS_EDPPIXEL_CBCR, 1); /* CBCR */
+}
+
+void edp_enable_link_clk(int enable)
+{
+ if (!enable) {
+ edp_write(MDSS_EDPLINK_CBCR, 0); /* CBCR */
+ return;
+ }
+
+ edp_write(EDPLINK_CFG_RCGR, (4 << 8) | 0x01); /* CFG RCGR */
+ edp_write(EDPLINK_CMD_RCGR, 3); /* CMD RCGR */
+
+ edp_write(MDSS_EDPLINK_CBCR, 1); /* CBCR */
+}
+
+void edp_enable_aux_clk(int enable)
+{
+ if (!enable) {
+ edp_write(MDSS_EDPAUX_CBCR, 0); /* CBCR */
+ return;
+ }
+
+ edp_write(EDPAUX_CFG_RCGR, 0x01); /* CFG RCGR */
+
+ edp_write(MDSS_EDPAUX_CBCR, 1); /* CBCR */
+}
+
+void edp_config_clk(void)
+{
+ edp_enable_link_clk(1);
+ edp_enable_pixel_clk(1);
+ edp_enable_aux_clk(1);
+}
+
+void edp_unconfig_clk(void)
+{
+ edp_enable_link_clk(0);
+ edp_enable_pixel_clk(0);
+ edp_enable_aux_clk(0);
+}
+
+void edp_phy_misc_cfg(void)
+{
+ /* EDP_PHY_EDPPHY_GLB_VM_CFG0 */
+ edp_write(EDP_BASE + 0x510, 0x3);
+ /* EDP_PHY_EDPPHY_GLB_VM_CFG1 */
+ edp_write(EDP_BASE + 0x514, 0x64);
+ /* EDP_PHY_EDPPHY_GLB_MISC9 */
+ edp_write(EDP_BASE + 0x518, 0x6c);
+ /* EDP_MISC1_MISC0 */
+ edp_write(EDP_BASE + 0x2c, 0x1);
+}
diff --git a/platform/msm_shared/edp_util.c b/platform/msm_shared/edp_util.c
new file mode 100644
index 0000000..f40abf9
--- /dev/null
+++ b/platform/msm_shared/edp_util.c
@@ -0,0 +1,459 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "edp.h"
+
+extern struct edp_aux_ctrl edpctrl;
+
+extern int edp_hpd_done;
+extern int edp_video_ready;
+
+/*
+ * edp buffer operation
+ */
+char *edp_buf_init(struct edp_buf *eb, char *buf, int size)
+{
+ eb->start = buf;
+ eb->size = size;
+ eb->data = eb->start;
+ eb->end = eb->start + eb->size;
+ eb->len = 0;
+ eb->trans_num = 0;
+ eb->i2c = 0;
+ return eb->data;
+}
+
+static char *edp_buf_reset(struct edp_buf *eb)
+{
+ eb->data = eb->start;
+ eb->len = 0;
+ eb->trans_num = 0;
+ eb->i2c = 0;
+ return eb->data;
+}
+
+static char *edp_buf_push(struct edp_buf *eb, int len)
+{
+ eb->data += len;
+ eb->len += len;
+ return eb->data;
+}
+
+static int edp_buf_trailing(struct edp_buf *eb)
+{
+ return (int)(eb->end - eb->data);
+}
+
+/*
+ * edp aux edp_buf_add_cmd:
+ * NO native and i2c command mix allowed
+ */
+static int edp_buf_add_cmd(struct edp_buf *eb, struct edp_cmd *cmd)
+{
+ char data;
+ char *bp, *cp;
+ int i, len;
+
+ if (cmd->read) /* read */
+ len = 4;
+ else
+ len = cmd->len + 4;
+
+ if (edp_buf_trailing(eb) < len)
+ return 0;
+
+ /*
+ * cmd fifo only has depth of 144 bytes
+ * limit buf length to 128 bytes here
+ */
+ if ((eb->len + len) > 128)
+ return 0;
+
+ bp = eb->data;
+ data = cmd->addr >> 16;
+ data &= 0x0f; /* 4 addr bits */
+ if (cmd->read)
+ data |= BIT(4);
+ *bp++ = data;
+ *bp++ = cmd->addr >> 8;
+ *bp++ = cmd->addr;
+ *bp++ = cmd->len - 1;
+
+ if (!cmd->read) { /* write */
+ cp = cmd->datap;
+ for (i = 0; i < cmd->len; i++)
+ *bp++ = *cp++;
+ }
+ edp_buf_push(eb, len);
+
+ if (cmd->i2c)
+ eb->i2c++;
+
+ eb->trans_num++; /* Increase transaction number */
+
+ return cmd->len - 1;
+}
+
+static int edp_cmd_fifo_tx(struct edp_buf *tp)
+{
+ int data;
+ char *dp;
+ int len, cnt;
+
+ len = tp->len; /* total byte to cmd fifo */
+ if (len == 0)
+ return 0;
+
+ cnt = 0;
+ dp = tp->start;
+
+ while (cnt < len) {
+ data = *dp; /* data byte */
+ data <<= 8;
+ data &= 0x00ff00; /* index = 0, write */
+ if (cnt == 0)
+ data |= BIT(31); /* INDEX_WRITE */
+ dprintf(SPEW, "%s: data=%x\n",__func__, data);
+ edp_write(EDP_BASE + EDP_AUX_DATA, data);
+ cnt++;
+ dp++;
+ }
+
+ data = (tp->trans_num - 1);
+ if (tp->i2c)
+ data |= BIT(8); /* I2C */
+
+ data |= BIT(9); /* GO */
+ dprintf(SPEW, "%s: data=%x\n",__func__, data);
+ edp_write(EDP_BASE + EDP_AUX_TRANS_CTRL, data);
+
+ return tp->len;
+}
+
+static int edp_cmd_fifo_rx(struct edp_buf *rp, int len)
+{
+ int data;
+ char *dp;
+ int i;
+
+ data = 0; /* index = 0 */
+ data |= BIT(31); /* INDEX_WRITE */
+ data |= BIT(0); /* read */
+ edp_write(EDP_BASE + EDP_AUX_DATA, data);
+
+ dp = rp->data;
+
+ /* discard first byte */
+ data = edp_read(EDP_BASE + EDP_AUX_DATA);
+ for (i = 0; i < len; i++) {
+ data = edp_read(EDP_BASE + EDP_AUX_DATA);
+ dprintf(SPEW, "%s: data=%x\n", __func__, data);
+ *dp++ = (char)((data >> 8) & 0xff);
+ }
+
+ rp->len = len;
+ return len;
+}
+
+
+void edp_aux_native_handler(unsigned int isr)
+{
+
+ dprintf(SPEW, "%s: isr=%x\n", __func__, isr);
+
+ if (isr & EDP_INTR_AUX_I2C_DONE)
+ edpctrl.aux_error_num = EDP_AUX_ERR_NONE;
+ else if (isr & EDP_INTR_WRONG_ADDR)
+ edpctrl.aux_error_num = EDP_AUX_ERR_ADDR;
+ else if (isr & EDP_INTR_TIMEOUT)
+ edpctrl.aux_error_num = EDP_AUX_ERR_TOUT;
+ if (isr & EDP_INTR_NACK_DEFER)
+ edpctrl.aux_error_num = EDP_AUX_ERR_NACK;
+}
+
+void edp_aux_i2c_handler(unsigned int isr)
+{
+
+ dprintf(SPEW, "%s: isr=%x\n", __func__, isr);
+
+ if (isr & EDP_INTR_AUX_I2C_DONE) {
+ if (isr & (EDP_INTR_I2C_NACK | EDP_INTR_I2C_DEFER))
+ edpctrl.aux_error_num = EDP_AUX_ERR_NACK;
+ else
+ edpctrl.aux_error_num = EDP_AUX_ERR_NONE;
+ } else {
+ if (isr & EDP_INTR_WRONG_ADDR)
+ edpctrl.aux_error_num = EDP_AUX_ERR_ADDR;
+ else if (isr & EDP_INTR_TIMEOUT)
+ edpctrl.aux_error_num = EDP_AUX_ERR_TOUT;
+ if (isr & EDP_INTR_NACK_DEFER)
+ edpctrl.aux_error_num = EDP_AUX_ERR_NACK;
+ if (isr & EDP_INTR_I2C_NACK)
+ edpctrl.aux_error_num = EDP_AUX_ERR_NACK;
+ if (isr & EDP_INTR_I2C_DEFER)
+ edpctrl.aux_error_num = EDP_AUX_ERR_NACK;
+ }
+}
+
+void mdss_edp_irq_enable(void)
+{
+ edp_write(EDP_BASE + 0x308, EDP_INTR_MASK1);
+ edp_write(EDP_BASE + 0x30c, EDP_INTR_MASK2);
+}
+
+void mdss_edp_irq_disable(void)
+{
+ edp_write(EDP_BASE + 0x308, 0);
+ edp_write(EDP_BASE + 0x30c, 0);
+}
+
+int edp_isr_read(unsigned int *isr1, unsigned int *isr2)
+{
+ unsigned int data1, data2, mask1, mask2;
+ unsigned int ack;
+
+ data1 = edp_read(EDP_BASE + 0x308);
+ data2 = edp_read(EDP_BASE + 0x30c);
+
+ if (data1 == 0 && data2 == 0)
+ return 0;
+
+ mask1 = data1 & EDP_INTR_MASK1;
+ mask2 = data2 & EDP_INTR_MASK2;
+
+ data1 &= ~mask1; /* remove masks bit */
+ data2 &= ~mask2;
+
+ dprintf(SPEW, "%s: isr=%x mask=%x isr2=%x mask2=%x\n",
+ __func__, data1, mask1, data2, mask2);
+
+ if (data1 == 0 && data2 == 0) /* no irq set */
+ return 0;
+
+ ack = data1 & EDP_INTR_STATUS1;
+ ack <<= 1; /* ack bits */
+ ack |= mask1;
+ edp_write(EDP_BASE + 0x308, ack);
+
+ ack = data2 & EDP_INTR_STATUS2;
+ ack <<= 1; /* ack bits */
+ ack |= mask2;
+ edp_write(EDP_BASE + 0x30c, ack);
+
+ if (data1 & EDP_INTR_HPD) {
+ edp_hpd_done++;
+ dprintf(INFO, "%s: got EDP_INTR_HOD\n", __func__);
+ data1 &= ~EDP_INTR_HPD;
+ }
+
+ if (data2 & EDP_INTR_READY_FOR_VIDEO) {
+ edp_video_ready++;
+ dprintf(INFO, "%s: got EDP_INTR_READY_FOR_VIDEO\n", __func__);
+ data2 &= ~EDP_INTR_READY_FOR_VIDEO;
+ }
+
+ if (data1 == 0 && data2 == 0) /* only hpd set */
+ return 0;
+
+ *isr1 = data1;
+ *isr2 = data2;
+
+ return 1;
+}
+
+void edp_isr_poll(void)
+{
+ int cnt;
+ unsigned int isr1, isr2;
+
+ isr1 = 0;
+ isr2 = 0;
+
+ /* one second loop here to cover
+ * the worst case for i2c edid 128 bytes read
+ */
+ cnt = 1000;
+ while(cnt--) {
+ if (edp_isr_read(&isr1, &isr2))
+ break;
+ udelay(1000);
+ }
+
+ if(cnt <= 0) {
+ dprintf(INFO, "%s: NO isr\n", __func__);
+ return;
+ }
+
+ dprintf(SPEW, "%s: isr1=%x isr2=%x\n", __func__, isr1, isr2);
+
+ if (isr2 & EDP_INTR_READY_FOR_VIDEO) {
+ }
+
+ if (isr1 && edpctrl.aux_cmd_busy) {
+ /* clear EDP_AUX_TRANS_CTRL */
+ edp_write(EDP_BASE + 0x318, 0);
+ /* read EDP_INTERRUPT_TRANS_NUM */
+ edpctrl.aux_trans_num = edp_read(EDP_BASE + 0x310);
+
+ if (edpctrl.aux_cmd_i2c)
+ edp_aux_i2c_handler(isr1);
+ else
+ edp_aux_native_handler(isr1);
+ }
+}
+
+int edp_aux_write_cmds(struct edp_aux_ctrl *ep,
+ struct edp_cmd *cmd)
+{
+ struct edp_cmd *cm;
+ struct edp_buf *tp;
+ int len, ret;
+
+ ep->aux_cmd_busy = 1;
+
+ tp = &ep->txp;
+ edp_buf_reset(tp);
+
+ cm = cmd;
+ while (cm) {
+ dprintf(SPEW, "%s: i2c=%d read=%d addr=%x len=%d next=%d\n",
+ __func__, cm->i2c, cm->read, cm->addr, cm->len, cm->next);
+ ret = edp_buf_add_cmd(tp, cm);
+ if (ret <= 0)
+ break;
+ if (cm->next == 0)
+ break;
+ cm++;
+ }
+
+ if (tp->i2c)
+ ep->aux_cmd_i2c = 1;
+ else
+ ep->aux_cmd_i2c = 0;
+
+ len = edp_cmd_fifo_tx(&ep->txp);
+
+ edp_isr_poll();
+
+ if (ep->aux_error_num == EDP_AUX_ERR_NONE)
+ ret = len;
+ else
+ ret = ep->aux_error_num;
+
+ ep->aux_cmd_busy = 0;
+ return ret;
+}
+
+int edp_aux_read_cmds(struct edp_aux_ctrl *ep,
+ struct edp_cmd *cmds)
+{
+ struct edp_cmd *cm;
+ struct edp_buf *tp;
+ struct edp_buf *rp;
+ int len, ret;
+
+ ep->aux_cmd_busy = 1;
+
+ tp = &ep->txp;
+ rp = &ep->rxp;
+ edp_buf_reset(tp);
+ edp_buf_reset(rp);
+
+ cm = cmds;
+ len = 0;
+ while (cm) {
+ dprintf(SPEW, "%s: i2c=%d read=%d addr=%x len=%d next=%d\n",
+ __func__, cm->i2c, cm->read, cm->addr, cm->len, cm->next);
+ ret = edp_buf_add_cmd(tp, cm);
+ len += cm->len;
+ if (ret <= 0)
+ break;
+ if (cm->next == 0)
+ break;
+ cm++;
+ }
+
+ if (tp->i2c)
+ ep->aux_cmd_i2c = 1;
+ else
+ ep->aux_cmd_i2c = 0;
+{
+ unsigned int isr1, isr2;
+
+ isr1 = edp_read(EDP_BASE + 0x308);
+ isr2 = edp_read(EDP_BASE + 0x30c);
+
+ if (isr1 != EDP_INTR_MASK1)
+ dprintf(INFO, "%s: BEFORE: isr1=%x isr2=%x\n", __func__, isr1, isr2);
+}
+
+ edp_cmd_fifo_tx(tp);
+
+ edp_isr_poll();
+
+ if (ep->aux_error_num == EDP_AUX_ERR_NONE)
+ ret = edp_cmd_fifo_rx(rp, len);
+ else
+ ret = ep->aux_error_num;
+
+ ep->aux_cmd_busy = 0;
+
+ return ret;
+}
+
+
+int edp_aux_write_buf(struct edp_aux_ctrl *ep, int addr,
+ char *buf, int len, int i2c)
+{
+ struct edp_cmd cmd;
+
+ cmd.read = 0;
+ cmd.i2c = i2c;
+ cmd.addr = addr;
+ cmd.datap = buf;
+ cmd.len = len & 0x0ff;
+ cmd.next = 0;
+
+ return edp_aux_write_cmds(ep, &cmd);
+}
+
+int edp_aux_read_buf(struct edp_aux_ctrl *ep, int addr,
+ int len, int i2c)
+{
+ struct edp_cmd cmd;
+
+ cmd.read = 1;
+ cmd.i2c = i2c;
+ cmd.addr = addr;
+ cmd.datap = NULL;
+ cmd.len = len & 0x0ff;
+ cmd.next = 0;
+
+ return edp_aux_read_cmds(ep, &cmd);
+}
diff --git a/platform/msm_shared/include/clock_lib2.h b/platform/msm_shared/include/clock_lib2.h
index a7606bc..008d5fa 100644
--- a/platform/msm_shared/include/clock_lib2.h
+++ b/platform/msm_shared/include/clock_lib2.h
@@ -70,6 +70,16 @@
| BVAL(10, 8, s##_mm_source_val), \
}
+#define F_MDSS(f, s, div, m, n) \
+ { \
+ .freq_hz = (f), \
+ .m_val = (m), \
+ .n_val = ~((n)-(m)) * !!(n), \
+ .d_val = ~(n),\
+ .div_src_val = BVAL(4, 0, (int)(2*(div) - 1)) \
+ | BVAL(10, 8, s##_mm_source_val), \
+ }
+
/* Branch Clock Bits */
#define CBCR_BRANCH_ENABLE_BIT BIT(0)
#define CBCR_BRANCH_OFF_BIT BIT(31)
diff --git a/platform/msm_shared/include/edp.h b/platform/msm_shared/include/edp.h
new file mode 100644
index 0000000..61a5755
--- /dev/null
+++ b/platform/msm_shared/include/edp.h
@@ -0,0 +1,298 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+#ifndef EDP_H
+#define EDP_H
+
+#include <reg.h>
+#include <debug.h>
+#include <err.h>
+#include <platform/iomap.h>
+#include <platform/clock.h>
+#include <platform/timer.h>
+
+#include "msm_panel.h"
+
+#define edp_read(offset) readl_relaxed((offset))
+#define edp_write(offset, data) writel_relaxed((data), (offset))
+
+
+#define AUX_CMD_FIFO_LEN 144
+#define AUX_CMD_MAX 16
+#define AUX_CMD_I2C_MAX 128
+
+#define EDP_PORT_MAX 1
+#define EDP_SINK_CAP_LEN 16
+
+#define EDP_AUX_ERR_NONE 0
+#define EDP_AUX_ERR_ADDR -1
+#define EDP_AUX_ERR_TOUT -2
+#define EDP_AUX_ERR_NACK -3
+
+/* 4 bits of aux command */
+#define EDP_CMD_AUX_WRITE 0x8
+#define EDP_CMD_AUX_READ 0x9
+
+/* 4 bits of i2c command */
+#define EDP_CMD_I2C_MOT 0x4 /* i2c middle of transaction */
+#define EDP_CMD_I2C_WRITE 0x0
+#define EDP_CMD_I2C_READ 0x1
+#define EDP_CMD_I2C_STATUS 0x2 /* i2c write status request */
+
+/* cmd reply: bit 0, 1 for aux */
+#define EDP_AUX_ACK 0x0
+#define EDP_AUX_NACK 0x1
+#define EDP_AUX_DEFER 0x2
+
+/* cmd reply: bit 2, 3 for i2c */
+#define EDP_I2C_ACK 0x0
+#define EDP_I2C_NACK 0x4
+#define EDP_I2C_DEFER 0x8
+
+#define EDP_CMD_TIMEOUT 400 /* us */
+#define EDP_CMD_LEN 16
+
+
+/* isr */
+#define EDP_INTR_HPD BIT(0)
+#define EDP_INTR_AUX_I2C_DONE BIT(3)
+#define EDP_INTR_WRONG_ADDR BIT(6)
+#define EDP_INTR_TIMEOUT BIT(9)
+#define EDP_INTR_NACK_DEFER BIT(12)
+#define EDP_INTR_WRONG_DATA_CNT BIT(15)
+#define EDP_INTR_I2C_NACK BIT(18)
+#define EDP_INTR_I2C_DEFER BIT(21)
+#define EDP_INTR_PLL_UNLOCKED BIT(24)
+#define EDP_INTR_AUX_ERROR BIT(27)
+
+
+#define EDP_INTR_STATUS1 \
+ (EDP_INTR_HPD | EDP_INTR_AUX_I2C_DONE| \
+ EDP_INTR_WRONG_ADDR | EDP_INTR_TIMEOUT | \
+ EDP_INTR_NACK_DEFER | EDP_INTR_WRONG_DATA_CNT | \
+ EDP_INTR_I2C_NACK | EDP_INTR_I2C_DEFER | \
+ EDP_INTR_PLL_UNLOCKED | EDP_INTR_AUX_ERROR)
+
+#define EDP_INTR_MASK1 (EDP_INTR_STATUS1 << 2)
+
+
+#define EDP_INTR_READY_FOR_VIDEO BIT(0)
+#define EDP_INTR_IDLE_PATTERNs_SENT BIT(3)
+#define EDP_INTR_FRAME_END BIT(6)
+#define EDP_INTR_CRC_UPDATED BIT(9)
+
+#define EDP_INTR_STATUS2 \
+ (EDP_INTR_READY_FOR_VIDEO | EDP_INTR_IDLE_PATTERNs_SENT | \
+ EDP_INTR_FRAME_END | EDP_INTR_CRC_UPDATED)
+
+#define EDP_INTR_MASK2 (EDP_INTR_STATUS2 << 2)
+
+
+
+
+
+#define EDP_MAINLINK_CTRL 0x004
+#define EDP_STATE_CTRL 0x008
+#define EDP_MAINLINK_READY 0x084
+
+#define EDP_AUX_CTRL 0x300
+#define EDP_INTERRUPT_STATUS 0x308
+#define EDP_INTERRUPT_STATUS_2 0x30c
+#define EDP_AUX_DATA 0x314
+#define EDP_AUX_TRANS_CTRL 0x318
+#define EDP_AUX_STATUS 0x324
+
+#define EDP_PHY_EDPPHY_GLB_VM_CFG0 0x510
+#define EDP_PHY_EDPPHY_GLB_VM_CFG1 0x514
+
+struct edp_cmd{
+ char read; /* 1 == read, 0 == write */
+ char i2c; /* 1 == i2c cmd, 0 == native cmd */
+ int addr; /* 20 bits */
+ char *datap;
+ int len; /* len to be tx OR len to be rx for read */
+ char next; /* next command */
+};
+
+struct edp_buf {
+ char *start; /* buffer start addr */
+ char *end; /* buffer end addr */
+ int size; /* size of buffer */
+ char *data; /* data pointer */
+ int len; /* dara length */
+ char trans_num; /* transaction number */
+ char i2c; /* 1 == i2c cmd, 0 == native cmd */
+};
+
+#define DPCD_ENHANCED_FRAME BIT(0)
+#define DPCD_TPS3 BIT(1)
+#define DPCD_MAX_DOWNSPREAD_0_5 BIT(2)
+#define DPCD_NO_AUX_HANDSHAKE BIT(3)
+#define DPCD_PORT_0_EDID_PRESENTED BIT(4)
+
+
+
+#define DPCD_LINK_VOLTAGE_MAX 4
+#define DPCD_LINK_PRE_EMPHASIS_MAX 4
+
+struct dpcd_cap {
+ char major;
+ char minor;
+ char max_lane_count;
+ char num_rx_port;
+ char i2c_speed_ctrl;
+ char scrambler_reset;
+ char enhanced_frame;
+ int max_link_rate; /* 162, 270 and 540 Mb, divided by 10 */
+ int flags;
+ int rx_port0_buf_size;
+ int training_read_interval;/* us */
+};
+
+
+struct display_timing_desc {
+ uint32_t pclk;
+ uint32_t h_addressable; /* addressable + boder = active */
+ uint32_t h_border;
+ uint32_t h_blank; /* fporch + bporch + sync_pulse = blank */
+ uint32_t h_fporch;
+ uint32_t h_sync_pulse;
+ uint32_t v_addressable; /* addressable + boder = active */
+ uint32_t v_border;
+ uint32_t v_blank; /* fporch + bporch + sync_pulse = blank */
+ uint32_t v_fporch;
+ uint32_t v_sync_pulse;
+ uint32_t width_mm;
+ uint32_t height_mm;
+ uint32_t interlaced;
+ uint32_t stereo;
+ uint32_t sync_type;
+ uint32_t sync_separate;
+ uint32_t vsync_pol;
+ uint32_t hsync_pol;
+};
+
+
+struct edp_edid {
+ char id_name[4];
+ short id_product;
+ char version;
+ char revision;
+ char video_intf; /* edp == 0x5 */
+ char color_depth; /* 6, 8, 10, 12 and 14 bits */
+ char color_format; /* RGB 4:4:4, YCrCb 4:4:4, Ycrcb 4:2:2 */
+ char dpm; /* display power management */
+ char sync_digital; /* 1 = digital */
+ char sync_separate; /* 1 = separate */
+ char vsync_pol; /* 0 = negative, 1 = positive */
+ char hsync_pol; /* 0 = negative, 1 = positive */
+ char ext_block_cnt;
+ struct display_timing_desc timing[4];
+};
+
+struct dpcd_link_status {
+ char lane_01_status;
+ char lane_23_status;
+ char interlane_align_done;
+ char downstream_port_status_changed;
+ char link_status_updated;
+ char port_0_in_sync;
+ char port_1_in_sync;
+ char req_voltage_swing[4];
+ char req_pre_emphasis[4];
+};
+
+struct edp_aux_ctrl {
+ int aux_cmd_busy;
+ int aux_cmd_i2c;
+ int aux_trans_num;
+ int aux_error_num;
+ int aux_ctrl_reg;
+ struct edp_buf txp;
+ struct edp_buf rxp;
+ char txbuf[256];
+ char rxbuf[256];
+ struct dpcd_link_status link_status;
+ char link_rate;
+ char lane_cnt;
+ char v_level;
+ char p_level;
+
+ /* transfer unit */
+ char tu_desired;
+ char valid_boundary;
+ char delay_start;
+ int bpp;
+
+ struct edp_edid edid;
+ struct dpcd_cap dpcd;
+};
+
+
+void edp_phy_pll_reset(void);
+void edp_mainlink_reset(void);
+void edp_aux_reset(void);
+void edp_phy_powerup(int enable);
+void edp_lane_power_ctrl(int max_lane, int up);
+
+void edp_phy_sw_reset(void);
+void edp_pll_configure(unsigned int rate);
+void edp_enable_lane_bist(int lane, int enable);
+void edp_enable_mainlink(int enable);
+void edp_hw_powerup(int enable);
+void edp_config_clk(void);
+void edp_unconfig_clk(void);
+void edp_phy_misc_cfg(void);
+int edp_on(void);
+int edp_off(void);
+int edp_config(void *pdata);
+void mdss_edp_dpcd_cap_read(void);
+void mdss_edp_dpcd_status_read(void);
+void mdss_edp_edid_read(void);
+int mdss_edp_link_train(void);
+void mdss_edp_aux_init(void);
+void mdss_edp_irq_enable(void);
+void mdss_edp_irq_disable(void);
+void mdss_edp_wait_for_hpd(void);
+void mdss_edp_wait_for_video_ready(void);
+void mdss_edp_lane_power_ctrl(int up);
+int mdss_edp_phy_pll_ready(void);
+void mdss_edp_pll_configure(void);
+void edp_cap2pinfo(struct msm_panel_info *pinfo);
+void edp_edid2pinfo(struct msm_panel_info *pinfo);
+int edp_aux_write_cmds(struct edp_aux_ctrl *ep,
+ struct edp_cmd *cmd);
+int edp_aux_read_cmds(struct edp_aux_ctrl *ep,
+ struct edp_cmd *cmds);
+int edp_aux_write_buf(struct edp_aux_ctrl *ep, int addr,
+ char *buf, int len, int i2c);
+int edp_aux_read_buf(struct edp_aux_ctrl *ep, int addr,
+ int len, int i2c);
+char *edp_buf_init(struct edp_buf *eb, char *buf, int size);
+
+#endif /* EDP_H */
diff --git a/platform/msm_shared/include/mdp3.h b/platform/msm_shared/include/mdp3.h
index 813b4ba..8dff686 100644
--- a/platform/msm_shared/include/mdp3.h
+++ b/platform/msm_shared/include/mdp3.h
@@ -28,6 +28,8 @@
*/
#include <dev/fbcon.h>
+#include <msm_panel.h>
+
//TODO: Make a global PASS / FAIL define
#define PASS 0
#define FAIL 1
@@ -51,3 +53,8 @@
void mdp_shutdown(void);
void mdp_set_revision(int rev);
int mdp_get_revision();
+
+/* defining no-op functions that are implemented only for mdp5 */
+int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb);
+int mdp_edp_on(void);
+int mdp_edp_off(void);
diff --git a/platform/msm_shared/include/mdp4.h b/platform/msm_shared/include/mdp4.h
index e0fc2c7..c988dee 100644
--- a/platform/msm_shared/include/mdp4.h
+++ b/platform/msm_shared/include/mdp4.h
@@ -111,4 +111,10 @@
int mdp_lcdc_off();
void mdp_set_revision(int rev);
int mdp_get_revision();
+
+/* defining no-op functions that are implemented only for mdp5 */
+int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb);
+int mdp_edp_on(void);
+int mdp_edp_off(void);
+
#endif
diff --git a/platform/msm_shared/include/mdp5.h b/platform/msm_shared/include/mdp5.h
index 994d54e..75e4e0d 100644
--- a/platform/msm_shared/include/mdp5.h
+++ b/platform/msm_shared/include/mdp5.h
@@ -76,6 +76,7 @@
#define MDP_UPPER_NEW_ROI_PRIOR_RO_START REG_MDP(0x02EC)
#define MDP_LOWER_NEW_ROI_PRIOR_TO_START REG_MDP(0x04F8)
+#define MDP_INTF_0_TIMING_ENGINE_EN REG_MDP(0x12500)
#define MDP_INTF_1_TIMING_ENGINE_EN REG_MDP(0x12700)
#define MDP_CTL_0_BASE REG_MDP(0x600)
@@ -91,6 +92,7 @@
#define MDP_REG_SPLIT_DISPLAY_EN REG_MDP(0x3F4)
#define MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL REG_MDP(0x3F8)
+#define MDP_INTF_0_BASE REG_MDP(0x12500)
#define MDP_INTF_1_BASE REG_MDP(0x12700)
#define MDP_INTF_2_BASE REG_MDP(0x12900)
@@ -156,6 +158,9 @@
unsigned short num_of_lanes);
int mdp_dsi_video_on(void);
int mdp_dma_on(void);
+int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb);
+int mdp_edp_on(void);
+int mdp_edp_off(void);
void mdp_disable(void);
#endif
diff --git a/platform/msm_shared/include/mipi_dsi.h b/platform/msm_shared/include/mipi_dsi.h
index 4f90f96..2a6d067 100755
--- a/platform/msm_shared/include/mipi_dsi.h
+++ b/platform/msm_shared/include/mipi_dsi.h
@@ -659,6 +659,7 @@
struct mipi_dsi_cmd {
int size;
char *payload;
+ int wait;
};
struct mipi_dsi_panel_config {
diff --git a/platform/msm_shared/include/mmc_sdhci.h b/platform/msm_shared/include/mmc_sdhci.h
index 79d3965..feae9f3 100644
--- a/platform/msm_shared/include/mmc_sdhci.h
+++ b/platform/msm_shared/include/mmc_sdhci.h
@@ -281,7 +281,7 @@
/* mmc device config data */
struct mmc_config_data {
uint8_t slot; /* Sdcc slot used */
- uint8_t pwr_irq; /* Power Irq from card to host */
+ uint32_t pwr_irq; /* Power Irq from card to host */
uint32_t sdhc_base; /* Base address for the sdhc */
uint32_t pwrctl_base; /* Base address for power control registers */
uint16_t bus_width; /* Bus width used */
diff --git a/platform/msm_shared/include/msm_panel.h b/platform/msm_shared/include/msm_panel.h
index 22a47ad..1cf0e64 100755
--- a/platform/msm_shared/include/msm_panel.h
+++ b/platform/msm_shared/include/msm_panel.h
@@ -49,6 +49,7 @@
#define MIPI_CMD_PANEL 9 /* MIPI */
#define WRITEBACK_PANEL 10 /* Wifi display */
#define LVDS_PANEL 11 /* LVDS */
+#define EDP_PANEL 12 /* EDP */
enum msm_mdp_hw_revision {
MDP_REV_20 = 1,
@@ -101,6 +102,7 @@
/* Pad height */
uint32_t yres_pad;
uint8_t dual_pipe;
+ uint8_t split_display;
uint8_t pipe_swap;
};
@@ -160,6 +162,11 @@
uint8_t broadcast;
};
+struct edp_panel_info {
+ int max_lane_count;
+ unsigned long max_link_clk;
+};
+
enum lvds_mode {
LVDS_SINGLE_CHANNEL_MODE,
LVDS_DUAL_CHANNEL_MODE,
@@ -187,9 +194,11 @@
struct mipi_panel_info mipi;
struct lvds_panel_info lvds;
struct hdmi_panel_info hdmi;
+ struct edp_panel_info edp;
int (*on) (void);
int (*off) (void);
+ int (*prepare) (void);
int (*early_config) (void *pdata);
int (*config) (void *pdata);
int (*rotate) (void);
@@ -207,6 +216,4 @@
int (*pll_clk_func) (int enable, struct msm_panel_info *);
};
-
-int msm_display_init(struct msm_fb_panel_data *pdata);
#endif
diff --git a/platform/msm_shared/include/sdhci.h b/platform/msm_shared/include/sdhci.h
index ef48d1d..976b5e3 100644
--- a/platform/msm_shared/include/sdhci.h
+++ b/platform/msm_shared/include/sdhci.h
@@ -160,6 +160,7 @@
#define SDHCI_SOFT_RESET BIT(0)
#define SOFT_RESET_CMD BIT(1)
#define SOFT_RESET_DATA BIT(2)
+#define SDHCI_RESET_MAX_TIMEOUT 0x64
#define SDHCI_1_8_VOL_SET BIT(3)
/*
@@ -281,7 +282,6 @@
/*
* Power control relatd macros
*/
-#define SDHCI_SOFT_RESET_MASK (BIT(0) | BIT(1) | BIT(2))
#define SDCC_HC_PWR_CTRL_INT 0xF
#define SDCC_HC_BUS_ON BIT(0)
#define SDCC_HC_BUS_OFF BIT(1)
diff --git a/platform/msm_shared/lvds.c b/platform/msm_shared/lvds.c
index 85ab7fb..0a16c34 100644
--- a/platform/msm_shared/lvds.c
+++ b/platform/msm_shared/lvds.c
@@ -31,6 +31,7 @@
#include <reg.h>
#include <err.h>
#include <bits.h>
+#include <arch/defines.h>
#include <platform/iomap.h>
#include <platform/clock.h>
#include <dev/fbcon.h>
diff --git a/platform/msm_shared/mdp3.c b/platform/msm_shared/mdp3.c
index fa3c28a..169dce5 100644
--- a/platform/msm_shared/mdp3.c
+++ b/platform/msm_shared/mdp3.c
@@ -180,3 +180,18 @@
return ret;
}
+
+int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb)
+{
+ return NO_ERROR;
+}
+
+int mdp_edp_on(void)
+{
+ return NO_ERROR;
+}
+
+int mdp_edp_off(void)
+{
+ return NO_ERROR;
+}
diff --git a/platform/msm_shared/mdp4.c b/platform/msm_shared/mdp4.c
index e347438..b3ade80 100644
--- a/platform/msm_shared/mdp4.c
+++ b/platform/msm_shared/mdp4.c
@@ -408,3 +408,18 @@
{
return mdp_rev;
}
+
+int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb)
+{
+ return NO_ERROR;
+}
+
+int mdp_edp_on(void)
+{
+ return NO_ERROR;
+}
+
+int mdp_edp_off(void)
+{
+ return NO_ERROR;
+}
diff --git a/platform/msm_shared/mdp5.c b/platform/msm_shared/mdp5.c
index e86c8df..314d19c 100644
--- a/platform/msm_shared/mdp5.c
+++ b/platform/msm_shared/mdp5.c
@@ -222,7 +222,7 @@
return ERR_INVALID_ARGS;
adjust_xres = pinfo->xres;
- if (pinfo->lcdc.dual_pipe) {
+ if (pinfo->lcdc.split_display) {
adjust_xres /= 2;
if (intf_base == MDP_INTF_1_BASE) {
writel(BIT(8), MDP_TG_SINK);
@@ -253,6 +253,11 @@
display_vend = ((vsync_period - lcdc->v_front_porch) * hsync_period)
+lcdc->hsync_skew - 1;
+ if (intf_base == MDP_INTF_0_BASE) { /* eDP */
+ display_vstart += lcdc->h_pulse_width + lcdc->h_back_porch;
+ display_vend -= lcdc->h_front_porch;
+ }
+
hsync_ctl = (hsync_period << 16) | lcdc->h_pulse_width;
display_hctl = (hsync_end_x << 16) | hsync_start_x;
@@ -278,8 +283,10 @@
writel(0x00, MDP_ACTIVE_V_END_F1 + mdss_mdp_intf_off);
writel(0xFF, MDP_UNDERFFLOW_COLOR + mdss_mdp_intf_off);
- writel(0x213F, MDP_PANEL_FORMAT + mdss_mdp_intf_off);
-
+ if (intf_base == MDP_INTF_0_BASE) /* eDP */
+ writel(0x212A, MDP_PANEL_FORMAT + mdss_mdp_intf_off);
+ else
+ writel(0x213F, MDP_PANEL_FORMAT + mdss_mdp_intf_off);
}
void mdss_layer_mixer_setup(struct fbcon_config *fb, struct msm_panel_info
@@ -322,8 +329,11 @@
writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND_OP);
writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND0_FG_ALPHA);
- /* Baselayer for layer mixer 0 */
- writel(0x04000, MDP_CTL_1_BASE + CTL_LAYER_1);
+ /* Baselayer for layer mixer 1 */
+ if (pinfo->lcdc.split_display)
+ writel(0x04000, MDP_CTL_1_BASE + CTL_LAYER_1);
+ else
+ writel(0x01000, MDP_CTL_0_BASE + CTL_LAYER_1);
}
}
@@ -368,6 +378,41 @@
return 0;
}
+int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb)
+{
+ int ret = NO_ERROR;
+ struct lcdc_panel_info *lcdc = NULL;
+
+ mdss_intf_tg_setup(pinfo, MDP_INTF_0_BASE);
+
+ mdp_clk_gating_ctrl();
+
+ mdss_vbif_setup();
+ mdss_smp_setup(pinfo);
+
+ writel(0x0E9, MDP_QOS_REMAPPER_CLASS_0);
+
+ mdss_rgb_pipe_config(fb, pinfo, MDP_VP_0_RGB_0_BASE);
+ if (pinfo->lcdc.dual_pipe)
+ mdss_rgb_pipe_config(fb, pinfo, MDP_VP_0_RGB_1_BASE);
+
+
+ mdss_layer_mixer_setup(fb, pinfo);
+
+
+ if (pinfo->lcdc.dual_pipe)
+ writel(0x181F10, MDP_CTL_0_BASE + CTL_TOP);
+ else
+ writel(0x1F10, MDP_CTL_0_BASE + CTL_TOP);
+
+ writel(0x9, MDP_DISP_INTF_SEL);
+ writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL);
+ writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START);
+ writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START);
+
+ return 0;
+}
+
int mdp_dsi_cmd_config(struct msm_panel_info *pinfo,
struct fbcon_config *fb)
{
@@ -452,3 +497,28 @@
{
}
+
+int mdp_edp_on(void)
+{
+ writel(0x32048, MDP_CTL_0_BASE + CTL_FLUSH);
+ writel(0x01, MDP_INTF_0_TIMING_ENGINE_EN + mdss_mdp_intf_offset());
+ return NO_ERROR;
+}
+
+int mdp_edp_off(void)
+{
+ if (!target_cont_splash_screen()) {
+
+ writel(0x00000000, MDP_INTF_0_TIMING_ENGINE_EN +
+ mdss_mdp_intf_offset());
+ mdelay(60);
+ /* Ping-Pong done Tear Check Read/Write */
+ /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */
+ writel(0xFF777713, MDP_INTR_CLEAR);
+ writel(0x00000000, MDP_INTR_EN);
+ }
+
+ writel(0x00000000, MDP_INTR_EN);
+
+ return NO_ERROR;
+}
diff --git a/platform/msm_shared/mipi_dsi.c b/platform/msm_shared/mipi_dsi.c
index 6b6e6c6..92d575e 100644
--- a/platform/msm_shared/mipi_dsi.c
+++ b/platform/msm_shared/mipi_dsi.c
@@ -46,7 +46,6 @@
unsigned short num_of_lanes);
extern void mdp_shutdown(void);
extern void mdp_start_dma(void);
-extern void dsb(void);
#if (DISPLAY_TYPE_MDSS == 0)
#define MIPI_DSI0_BASE MIPI_DSI_BASE
@@ -229,7 +228,11 @@
writel(cm->size, DSI_DMA_CMD_LENGTH); // reg 0x48 for this build
dsb();
ret += dsi_cmd_dma_trigger_for_panel();
- udelay(80);
+ dsb();
+ if (cm->wait)
+ mdelay(cm->wait);
+ else
+ udelay(80);
cm++;
}
return ret;
diff --git a/platform/msm_shared/mmc_sdhci.c b/platform/msm_shared/mmc_sdhci.c
index cb00a3c..5487d94 100644
--- a/platform/msm_shared/mmc_sdhci.c
+++ b/platform/msm_shared/mmc_sdhci.c
@@ -287,7 +287,7 @@
mmc_cid.pnm[6] = 0;
mmc_cid.prv = UNPACK_BITS(raw_cid, 56, 8, mmc_sizeof);
- mmc_cid.psn = UNPACK_BITS(raw_cid, 24, 31, mmc_sizeof);
+ mmc_cid.psn = UNPACK_BITS(raw_cid, 24, 32, mmc_sizeof);
mmc_cid.month = UNPACK_BITS(raw_cid, 8, 4, mmc_sizeof);
mmc_cid.year = UNPACK_BITS(raw_cid, 12, 8, mmc_sizeof);
mmc_cid.year += 2000;
@@ -302,7 +302,7 @@
mmc_cid.pnm[6] = 0;
mmc_cid.prv = UNPACK_BITS(raw_cid, 48, 8, mmc_sizeof);
- mmc_cid.psn = UNPACK_BITS(raw_cid, 16, 31, mmc_sizeof);
+ mmc_cid.psn = UNPACK_BITS(raw_cid, 16, 32, mmc_sizeof);
mmc_cid.month = UNPACK_BITS(raw_cid, 8, 4, mmc_sizeof);
mmc_cid.year = UNPACK_BITS(raw_cid, 12, 4, mmc_sizeof);
mmc_cid.year += 1997;
@@ -907,6 +907,11 @@
data.pwrctl_base = cfg->pwrctl_base;
data.pwr_irq = cfg->pwr_irq;
+ /* Initialize any clocks needed for SDC controller */
+ clock_init_mmc(cfg->slot);
+
+ clock_config_mmc(cfg->slot, cfg->max_clk_rate);
+
/*
* MSM specific sdhc init
*/
@@ -918,12 +923,7 @@
*/
sdhci_init(host);
- /* Initialize any clocks needed for SDC controller */
- clock_init_mmc(cfg->slot);
-
/* Setup initial freq to 400KHz */
- clock_config_mmc(cfg->slot, cfg->max_clk_rate);
-
mmc_ret = sdhci_clk_supply(host, SDHCI_CLK_400KHZ);
return mmc_ret;
diff --git a/platform/msm_shared/partition_parser.c b/platform/msm_shared/partition_parser.c
index 5cca931..6c0ae6c 100644
--- a/platform/msm_shared/partition_parser.c
+++ b/platform/msm_shared/partition_parser.c
@@ -227,7 +227,10 @@
/* Print out the GPT first */
ret = mmc_read(PROTECTIVE_MBR_SIZE, (unsigned int *)data, BLOCK_SIZE);
if (ret)
+ {
dprintf(CRITICAL, "GPT: Could not read primary gpt from mmc\n");
+ return ret;
+ }
ret = partition_parse_gpt_header(data, &first_usable_lba,
&partition_entry_size, &header_size,
@@ -441,7 +444,7 @@
{
int byte_length = 8; /*length of unit (i.e. byte) */
int msb = 0;
- int polynomial = 0x104C11DB7; /* IEEE 32bit polynomial */
+ int polynomial = 0x04C11DB7; /* IEEE 32bit polynomial */
unsigned int regs = 0xFFFFFFFF; /* init to all ones */
int regs_mask = 0xFFFFFFFF; /* ensure only 32 bit answer */
int regs_msb = 0;
diff --git a/platform/msm_shared/qpic_nand.c b/platform/msm_shared/qpic_nand.c
index 16a498b..44e3c35 100644
--- a/platform/msm_shared/qpic_nand.c
+++ b/platform/msm_shared/qpic_nand.c
@@ -64,6 +64,7 @@
/* Flash ID ID Mask Density(MB) Wid Pgsz Blksz oobsz 8-bit ECCf */
{0x1590AC2C, 0xFFFFFFFF, 0x20000000, 0, 2048, 0x00020000, 0x40, 0},
{0x2690AC2C, 0xFFFFFFFF, 0x20000000, 0, 4096, 0x00040000, 0xE0, 1},
+ {0x1590ACAD, 0xFFFFFFFF, 0x20000000, 0, 2048, 0x00020000, 0x80, 0},
/* Note: Width flag is 0 for 8 bit Flash and 1 for 16 bit flash */
};
diff --git a/platform/msm_shared/qtimer_mmap.c b/platform/msm_shared/qtimer_mmap.c
index ef76075..bcd9a9a 100644
--- a/platform/msm_shared/qtimer_mmap.c
+++ b/platform/msm_shared/qtimer_mmap.c
@@ -30,6 +30,7 @@
#include <reg.h>
#include <compiler.h>
#include <qtimer.h>
+#include <arch/defines.h>
#include <platform/irqs.h>
#include <platform/iomap.h>
#include <platform/interrupts.h>
@@ -42,7 +43,6 @@
static volatile uint32_t current_time;
static uint32_t tick_count;
-extern void dsb();
static void qtimer_enable();
static enum handler_return qtimer_irq(void *arg)
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index f43f1f6..9b7ff98 100755
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -98,7 +98,11 @@
$(LOCAL_DIR)/crypto5_wrapper.o \
$(LOCAL_DIR)/i2c_qup.o \
$(LOCAL_DIR)/gpio.o \
- $(LOCAL_DIR)/dload_util.o
+ $(LOCAL_DIR)/dload_util.o \
+ $(LOCAL_DIR)/edp.o \
+ $(LOCAL_DIR)/edp_util.o \
+ $(LOCAL_DIR)/edp_aux.o \
+ $(LOCAL_DIR)/edp_phy.o
endif
ifeq ($(PLATFORM),msm8226)
@@ -169,6 +173,23 @@
$(LOCAL_DIR)/gpio.o
endif
+ifeq ($(PLATFORM),apq8084)
+ OBJS += $(LOCAL_DIR)/qgic.o \
+ $(LOCAL_DIR)/qtimer.o \
+ $(LOCAL_DIR)/qtimer_mmap.o \
+ $(LOCAL_DIR)/interrupts.o \
+ $(LOCAL_DIR)/clock.o \
+ $(LOCAL_DIR)/clock_pll.o \
+ $(LOCAL_DIR)/clock_lib2.o \
+ $(LOCAL_DIR)/uart_dm.o \
+ $(LOCAL_DIR)/board.o \
+ $(LOCAL_DIR)/spmi.o \
+ $(LOCAL_DIR)/bam.o \
+ $(LOCAL_DIR)/qpic_nand.o \
+ $(LOCAL_DIR)/dev_tree.o \
+ $(LOCAL_DIR)/gpio.o
+endif
+
ifeq ($(PLATFORM),msm7x27a)
OBJS += $(LOCAL_DIR)/uart.o \
$(LOCAL_DIR)/nand.o \
@@ -233,3 +254,28 @@
$(LOCAL_DIR)/clock_pll.o \
$(LOCAL_DIR)/clock_lib2.o
endif
+
+ifeq ($(PLATFORM),fsm9900)
+ OBJS += $(LOCAL_DIR)/qgic.o \
+ $(LOCAL_DIR)/qtimer.o \
+ $(LOCAL_DIR)/qtimer_mmap.o \
+ $(LOCAL_DIR)/interrupts.o \
+ $(LOCAL_DIR)/clock.o \
+ $(LOCAL_DIR)/clock_pll.o \
+ $(LOCAL_DIR)/clock_lib2.o \
+ $(LOCAL_DIR)/uart_dm.o \
+ $(LOCAL_DIR)/board.o \
+ $(LOCAL_DIR)/scm.o \
+ $(LOCAL_DIR)/spmi.o \
+ $(LOCAL_DIR)/bam.o \
+ $(LOCAL_DIR)/qpic_nand.o \
+ $(LOCAL_DIR)/dev_tree.o \
+ $(LOCAL_DIR)/certificate.o \
+ $(LOCAL_DIR)/image_verify.o \
+ $(LOCAL_DIR)/crypto_hash.o \
+ $(LOCAL_DIR)/crypto5_eng.o \
+ $(LOCAL_DIR)/crypto5_wrapper.o \
+ $(LOCAL_DIR)/i2c_qup.o \
+ $(LOCAL_DIR)/gpio.o \
+ $(LOCAL_DIR)/dload_util.o
+endif
diff --git a/platform/msm_shared/scm.c b/platform/msm_shared/scm.c
index adeecc8..26e203e 100644
--- a/platform/msm_shared/scm.c
+++ b/platform/msm_shared/scm.c
@@ -308,10 +308,11 @@
if(parse_rsp.status == SSD_PMD_ENCRYPTED)
{
*ctx_id = parse_rsp.md_ctx_id;
- *img_len_ptr = *img_len_ptr - (parse_rsp.md_end_ptr - *img_ptr);
+ *img_len_ptr = *img_len_ptr - ((uint8_t*)parse_rsp.md_end_ptr - (uint8_t*)*img_ptr);
*img_ptr = (uint32_t*)parse_rsp.md_end_ptr;
- ret = 1;
}
+
+ ret = parse_rsp.status;
}
else
{
@@ -330,43 +331,62 @@
ssd_decrypt_img_frag_req decrypt_req;
ssd_decrypt_img_frag_rsp decrypt_rsp;
- if(ssd_image_is_encrypted(img_ptr,img_len_ptr,&ctx_id))
+ ret = ssd_image_is_encrypted(img_ptr,img_len_ptr,&ctx_id);
+ switch(ret)
{
+ case SSD_PMD_ENCRYPTED:
+ /* Image data is operated upon by TZ, which accesses only the main memory.
+ * It must be flushed/invalidated before and after TZ call.
+ */
- /* Image data is operated upon by TZ, which accesses only the main memory.
- * It must be flushed/invalidated before and after TZ call.
- */
+ arch_clean_invalidate_cache_range((addr_t) *img_ptr, *img_len_ptr);
- arch_clean_invalidate_cache_range((addr_t) *img_ptr, *img_len_ptr);
+ /*decrypt the image here*/
- /*decrypt the image here*/
+ decrypt_req.md_ctx_id = ctx_id;
+ decrypt_req.last_frag = 1;
+ decrypt_req.frag_len = *img_len_ptr;
+ decrypt_req.frag = *img_ptr;
- decrypt_req.md_ctx_id = ctx_id;
- decrypt_req.last_frag = 1;
- decrypt_req.frag_len = *img_len_ptr;
- decrypt_req.frag = *img_ptr;
+ ret = scm_call(SCM_SVC_SSD,
+ SSD_DECRYPT_IMG_FRAG_ID,
+ &decrypt_req,
+ sizeof(decrypt_req),
+ &decrypt_rsp,
+ sizeof(decrypt_rsp));
- ret = scm_call(SCM_SVC_SSD,
- SSD_DECRYPT_IMG_FRAG_ID,
- &decrypt_req,
- sizeof(decrypt_req),
- &decrypt_rsp,
- sizeof(decrypt_rsp));
+ if(!ret){
+ ret = decrypt_rsp.status;
+ }
- if(!ret){
- ret = decrypt_rsp.status;
- }
+ /* Values at img_ptr and img_len_ptr are updated by TZ. Must be invalidated
+ * before we use them.
+ */
+ arch_invalidate_cache_range((addr_t) img_ptr, sizeof(img_ptr));
+ arch_invalidate_cache_range((addr_t) img_len_ptr, sizeof(img_len_ptr));
- /* Values at img_ptr and img_len_ptr are updated by TZ. Must be invalidated
- * before we use them.
- */
- arch_invalidate_cache_range((addr_t) img_ptr, sizeof(img_ptr));
- arch_invalidate_cache_range((addr_t) img_len_ptr, sizeof(img_len_ptr));
+ /* Invalidate the updated image data */
+ arch_invalidate_cache_range((addr_t) *img_ptr, *img_len_ptr);
- /* Invalidate the updated image data */
- arch_invalidate_cache_range((addr_t) *img_ptr, *img_len_ptr);
+ break;
+
+ case SSD_PMD_NOT_ENCRYPTED:
+ case SSD_PMD_NO_MD_FOUND:
+ ret = 0;
+ break;
+
+ case SSD_PMD_BUSY:
+ case SSD_PMD_BAD_MD_PTR_OR_LEN:
+ case SSD_PMD_PARSING_INCOMPLETE:
+ case SSD_PMD_PARSING_FAILED:
+ case SSD_PMD_SETUP_CIPHER_FAILED:
+ dprintf(CRITICAL,"decrypt_scm_v2: failed status %d\n",ret);
+ break;
+
+ default:
+ dprintf(CRITICAL,"decrypt_scm_v2: case default: failed status %d\n",ret);
+ break;
}
-
return ret;
}
diff --git a/platform/msm_shared/sdhci.c b/platform/msm_shared/sdhci.c
index ce54433..03996f9 100644
--- a/platform/msm_shared/sdhci.c
+++ b/platform/msm_shared/sdhci.c
@@ -40,6 +40,38 @@
/*
+ * Function: sdhci reset
+ * Arg : Host structure & mask to write to reset register
+ * Return : None
+ * Flow: : Reset the host controller
+ */
+static void sdhci_reset(struct sdhci_host *host, uint8_t mask)
+{
+ uint32_t reg;
+ uint32_t timeout = SDHCI_RESET_MAX_TIMEOUT;
+
+ REG_WRITE8(host, mask, SDHCI_RESET_REG);
+
+ /* Wait for the reset to complete */
+ do {
+ reg = REG_READ8(host, SDHCI_RESET_REG);
+ reg &= mask;
+
+ if (!reg)
+ break;
+ if (!timeout)
+ {
+ dprintf(CRITICAL, "Error: sdhci reset failed for: %x\n", mask);
+ break;
+ }
+
+ timeout--;
+ mdelay(1);
+
+ } while(1);
+}
+
+/*
* Function: sdhci error status enable
* Arg : Host structure
* Return : None
@@ -424,14 +456,14 @@
if (sdhci_cmd_err_status(host)) {
dprintf(CRITICAL, "Error: Command completed with errors\n");
/* Reset the command & Data line */
- REG_WRITE8(host, (SOFT_RESET_CMD | SOFT_RESET_DATA), SDHCI_RESET_REG);
+ sdhci_reset(host, (SOFT_RESET_CMD | SOFT_RESET_DATA));
return 1;
}
}
/* Reset data & command line */
if (cmd->data_present)
- REG_WRITE8(host, (SOFT_RESET_CMD | SOFT_RESET_DATA), SDHCI_RESET_REG);
+ sdhci_reset(host, (SOFT_RESET_CMD | SOFT_RESET_DATA));
return 0;
}
@@ -714,28 +746,6 @@
}
/*
- * Function: sdhci reset
- * Arg : Host structure
- * Return : None
- * Flow: : Reset the host controller
- */
-static void sdhci_reset(struct sdhci_host *host)
-{
- uint32_t reg;
-
- REG_WRITE8(host, SDHCI_SOFT_RESET, SDHCI_RESET_REG);
-
- /* Wait for the reset to complete */
- do {
- reg = REG_READ8(host, SDHCI_RESET_REG);
- reg &= SDHCI_SOFT_RESET_MASK;
-
- if (!reg)
- break;
- } while(1);
-}
-
-/*
* Function: sdhci init
* Arg : Host structure
* Return : None
@@ -754,7 +764,7 @@
/*
* Reset the controller
*/
- sdhci_reset(host);
+ sdhci_reset(host, SDHCI_SOFT_RESET);
/* Read the capabilities register & store the info */
caps[0] = REG_READ32(host, SDHCI_CAPS_REG1);
diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h
index 8ebbce8..ba77c86 100755
--- a/platform/msm_shared/smem.h
+++ b/platform/msm_shared/smem.h
@@ -300,6 +300,7 @@
APQ8074 = 184,
MSM8274 = 185,
MSM8674 = 186,
+ FSM9900 = 188,
MSM8974AC = 194,
MSM8126 = 198,
APQ8026 = 199,
diff --git a/platform/msm_shared/uart_dm.c b/platform/msm_shared/uart_dm.c
index 01bcbb6..f551a7a 100644
--- a/platform/msm_shared/uart_dm.c
+++ b/platform/msm_shared/uart_dm.c
@@ -43,7 +43,6 @@
#define NULL 0
#endif
-extern void dsb(void);
static int uart_init_flag = 0;
diff --git a/project/apq8084.mk b/project/apq8084.mk
new file mode 100644
index 0000000..cbf43c8
--- /dev/null
+++ b/project/apq8084.mk
@@ -0,0 +1,27 @@
+# top level project rules for the apq8084 project
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+TARGET := apq8084
+
+MODULES += app/aboot
+
+DEBUG := 1
+EMMC_BOOT := 1
+ENABLE_SDHCI_SUPPORT := 0
+
+#DEFINES += WITH_DEBUG_DCC=1
+DEFINES += WITH_DEBUG_UART=1
+#DEFINES += WITH_DEBUG_FBCON=1
+DEFINES += DEVICE_TREE=1
+
+#Disable thumb mode
+ENABLE_THUMB := false
+
+ifeq ($(EMMC_BOOT),1)
+DEFINES += _EMMC_BOOT=1
+endif
+
+ifeq ($(ENABLE_SDHCI_SUPPORT),1)
+DEFINES += MMC_SDHCI_SUPPORT=1
+endif
diff --git a/project/fsm9900.mk b/project/fsm9900.mk
new file mode 100644
index 0000000..8945556
--- /dev/null
+++ b/project/fsm9900.mk
@@ -0,0 +1,35 @@
+# top level project rules for the fsm9900 project
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+TARGET := fsm9900
+
+MODULES += app/aboot
+
+DEBUG := 1
+EMMC_BOOT := 1
+ENABLE_SDHCI_SUPPORT := 0
+
+#DEFINES += WITH_DEBUG_DCC=1
+DEFINES += WITH_DEBUG_UART=1
+#DEFINES += WITH_DEBUG_FBCON=1
+DEFINES += DEVICE_TREE=1
+#DEFINES += MMC_BOOT_BAM=1
+DEFINES += CRYPTO_BAM=1
+DEFINES += CRYPTO_REG_ACCESS=1
+DEFINES += ABOOT_IGNORE_BOOT_HEADER_ADDRS=1
+
+#Disable thumb mode
+ENABLE_THUMB := false
+
+DEFINES += ABOOT_FORCE_KERNEL_ADDR=0x00008000
+DEFINES += ABOOT_FORCE_RAMDISK_ADDR=0x02000000
+DEFINES += ABOOT_FORCE_TAGS_ADDR=0x01e00000
+
+ifeq ($(EMMC_BOOT),1)
+DEFINES += _EMMC_BOOT=1
+endif
+
+ifeq ($(ENABLE_SDHCI_SUPPORT),1)
+DEFINES += MMC_SDHCI_SUPPORT=1
+endif
diff --git a/project/msm8974.mk b/project/msm8974.mk
index 17f564b..80b310c 100644
--- a/project/msm8974.mk
+++ b/project/msm8974.mk
@@ -8,7 +8,7 @@
DEBUG := 1
EMMC_BOOT := 1
-ENABLE_SDHCI_SUPPORT := 0
+ENABLE_SDHCI_SUPPORT := 1
#DEFINES += WITH_DEBUG_DCC=1
DEFINES += WITH_DEBUG_UART=1
diff --git a/scripts/aboot_test.py b/scripts/aboot_test.py
new file mode 100755
index 0000000..c43364c
--- /dev/null
+++ b/scripts/aboot_test.py
@@ -0,0 +1,189 @@
+# Copyright (c) 2013, The Linux Foundation. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# * Redistributions in binary form must reproduce the above
+# copyright notice, this list of conditions and the following
+# disclaimer in the documentation and/or other materials provided
+# with the distribution.
+# * Neither the name of The Linux Foundation nor the names of its
+# contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+# BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+# * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+# IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+#!/usr/bin/python
+
+import os
+import sys
+import time
+import re
+import subprocess
+import getopt
+
+#
+# Erase routine, erase a parition & print the time taken for erase
+#
+def fastboot_erase(partition):
+ start_time = time.time()
+ exe = subprocess.Popen(['fastboot', 'erase', partition], stdout=subprocess.PIPE,stderr=subprocess.STDOUT).stdout.read()
+ print exe
+ print "Time Taken for erase:", partition, ":", time.time() - start_time, "seconds"
+ print("")
+ return
+
+#
+# Flash routine, flash a parition & print the time taken to flash the image
+#
+def fastboot_flash(image_name, partition):
+ start_time = time.time()
+ exe = subprocess.Popen(['fastboot', 'flash', partition, image_name], stdout=subprocess.PIPE,stderr=subprocess.STDOUT).stdout.read()
+ print exe
+ print "Time Taken for flashing:", partition, ":", time.time() - start_time, "seconds"
+ print("")
+ return
+
+#
+# Execute any other fasboot command & print the time taken
+#
+def fastboot_exec(command):
+ start_time = time.time()
+ exe = subprocess.Popen(['fastboot', command], stdout=subprocess.PIPE, stderr=subprocess.STDOUT).stdout.read()
+ print exe
+ print "Time Taken for fastboot:", command, time.time() - start_time, "seconds"
+ print("")
+ return
+
+#
+# Aboot test, Test aboot with different use cases
+#
+def test_aboot(iteration, input_path):
+ system=''
+ userdata=''
+ boot=''
+
+ print ("ABOOT TEST START")
+ t0 = time.clock()
+
+ boot = os.path.join(input_path, 'boot.img')
+ system = os.path.join(input_path, 'system.img')
+ userdata = os.path.join(input_path, 'userdata.img')
+
+ print("")
+ getstate = subprocess.Popen(["fastboot", "devices"], stdout=subprocess.PIPE).communicate()[0]
+ if(re.search("fastboot",getstate) == None):
+ print("Device is not in fastboot, please make sure device is in fastboot mode ... [FAIL]")
+ sys.exit(-1)
+ else:
+ print ("fastboot devices ... [OKAY]")
+ print ("Executing other fastboot tests ...")
+ print("")
+
+ fastboot_erase("boot")
+ time.sleep(2)
+
+ fastboot_exec("reboot")
+ time.sleep(2)
+ fastboot_exec("devices")
+ time.sleep(2)
+ getstate = subprocess.Popen(["fastboot", "devices"], stdout=subprocess.PIPE).communicate()[0]
+ if(re.search("fastboot",getstate) == None):
+ print("fastboot reboot ... [FAIL]")
+ sys.exit(-1)
+
+ iteration = int(iteration)
+
+ # Flash images in a loop
+ i = 0
+ while i < iteration:
+ print "Iteration ", i
+ print ("fastboot flash boot boot.img...")
+ fastboot_flash(boot, 'boot')
+ print("")
+ print ("fastboot flash system system.img ...")
+ fastboot_flash(system, 'system')
+ print("")
+ print ("fastboot flash userdata userdata.img ...")
+ fastboot_flash(userdata, 'userdata')
+ print("")
+ i+=1
+
+ fastboot_exec("reboot")
+ print ("fastboot reboot ... [OKAY]")
+ print("")
+ time.sleep(1)
+ print("Waiting for adb to come up ...")
+ print("")
+ i = 0
+ while i < 10:
+ getstate = subprocess.Popen(["adb", "get-state"], stdout=subprocess.PIPE).communicate()[0]
+ if(re.search("device",getstate) == None):
+ i+=1
+ time.sleep(2)
+ else:
+ print("Device Online")
+ print("")
+ break
+
+ os.system("adb reboot-bootloader")
+ time.sleep(4)
+ getstate = subprocess.Popen(["fastboot", "devices"], stdout=subprocess.PIPE).communicate()[0]
+ if(re.search("fastboot",getstate) == None):
+ print ("adb reboot-bootloader ... [FAIL]")
+ sys.exit(-1)
+ else:
+ print ("adb reboot-bootloader ... [PASS]")
+
+ print("")
+ fastboot_exec("devices")
+ print ("fastboot devices ... [OKAY]")
+ print("")
+
+ fastboot_erase("system")
+ fastboot_erase("userdata")
+
+ fastboot_exec("continue")
+ print ("fastboot continue ... [OKAY]")
+ print("")
+
+ print ("ABOOT TEST DONE")
+ return
+
+# Main function to parse i/p args
+def main(argv):
+ input_path = ''
+ iteration = ''
+ if len(sys.argv) < 2:
+ print "aboot_test.py -i <iterations> -p <Binary Image Path>"
+ sys.exit(2)
+ try:
+ opts, args = getopt.getopt(argv, "hi:p:",["iter=","opath="])
+ except getopt.GetoptError:
+ print "aboot_test.py -i <iterations> -p <Binary Image Path>"
+ sys.exit(2)
+ for opt, arg in opts:
+ if opt == '-h':
+ print "aboot_test.py -i <iterations> -o <Binary Image Path>"
+ sys.exit(2)
+ elif opt in ("-i", "--iter"):
+ iteration = arg
+ elif opt in ("-p", "--opath"):
+ input_path = arg
+ test_aboot(iteration, input_path)
+
+if __name__ == "__main__":
+ main(sys.argv[1:])
diff --git a/target/apq8084/init.c b/target/apq8084/init.c
new file mode 100644
index 0000000..da3ca04
--- /dev/null
+++ b/target/apq8084/init.c
@@ -0,0 +1,229 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <platform/iomap.h>
+#include <platform/gpio.h>
+#include <reg.h>
+#include <target.h>
+#include <platform.h>
+#include <dload_util.h>
+#include <uart_dm.h>
+#include <mmc.h>
+#include <spmi.h>
+#include <board.h>
+#include <smem.h>
+#include <baseband.h>
+#include <dev/keys.h>
+#include <pm8x41.h>
+#include <crypto5_wrapper.h>
+#include <hsusb.h>
+#include <clock.h>
+#include <partition_parser.h>
+#include <scm.h>
+#include <platform/clock.h>
+#include <platform/gpio.h>
+#include <stdlib.h>
+
+static uint32_t mmc_sdc_base[] =
+ { MSM_SDC1_BASE, MSM_SDC2_BASE, MSM_SDC3_BASE, MSM_SDC4_BASE };
+
+void target_early_init(void)
+{
+#if WITH_DEBUG_UART
+ uart_dm_init(1, 0, BLSP1_UART1_BASE);
+#endif
+}
+
+/* Return 1 if vol_up pressed */
+static int target_volume_up()
+{
+ return 0;
+}
+
+/* Return 1 if vol_down pressed */
+uint32_t target_volume_down()
+{
+ return 0;
+}
+
+static void target_keystatus()
+{
+ keys_init();
+
+ if(target_volume_down())
+ keys_post_event(KEY_VOLUMEDOWN, 1);
+
+ if(target_volume_up())
+ keys_post_event(KEY_VOLUMEUP, 1);
+}
+
+static void target_mmc_mci_init()
+{
+ uint32_t base_addr;
+ uint8_t slot;
+
+ slot = MMC_SLOT;
+ base_addr = mmc_sdc_base[slot - 1];
+
+ if (mmc_boot_main(slot, base_addr))
+ {
+ dprintf(CRITICAL, "mmc init failed!");
+ ASSERT(0);
+ }
+}
+
+/*
+ * Function to set the capabilities for the host
+ */
+void target_mmc_caps(struct mmc_host *host)
+{
+ host->caps.bus_width = MMC_BOOT_BUS_WIDTH_8_BIT;
+ host->caps.ddr_mode = 1;
+ host->caps.hs200_mode = 1;
+ host->caps.hs_clk_rate = MMC_CLK_96MHZ;
+}
+
+static void set_sdc_power_ctrl()
+{
+ /* Drive strength configs for sdc pins */
+ struct tlmm_cfgs sdc1_hdrv_cfg[] =
+ {
+ { SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK },
+ { SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
+ { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
+ };
+
+ /* Pull configs for sdc pins */
+ struct tlmm_cfgs sdc1_pull_cfg[] =
+ {
+ { SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK },
+ { SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
+ { SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
+ };
+
+ /* Set the drive strength & pull control values */
+ tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg));
+ tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg));
+}
+
+void target_init(void)
+{
+ dprintf(INFO, "target_init()\n");
+
+ target_keystatus();
+
+ /*
+ * Set drive strength & pull ctrl for
+ * emmc
+ */
+ /*Uncomment during bringup after the pull up values are finalized*/
+ //set_sdc_power_ctrl();
+
+ target_mmc_mci_init();
+
+ /*
+ * MMC initialization is complete, read the partition table info
+ */
+ if (partition_read_table())
+ {
+ dprintf(CRITICAL, "Error reading the partition table info\n");
+ ASSERT(0);
+ }
+}
+
+unsigned board_machtype(void)
+{
+ return LINUX_MACHTYPE_UNKNOWN;
+}
+
+void target_fastboot_init(void)
+{
+ /* Set the BOOT_DONE flag in PM8921 */
+}
+
+/* Detect the target type */
+void target_detect(struct board_data *board)
+{
+ board->target = LINUX_MACHTYPE_UNKNOWN;
+}
+
+/* Detect the modem type */
+void target_baseband_detect(struct board_data *board)
+{
+ uint32_t platform;
+ uint32_t platform_subtype;
+
+ platform = board->platform;
+ platform_subtype = board->platform_subtype;
+
+ /*
+ * Look for platform subtype if present, else
+ * check for platform type to decide on the
+ * baseband type
+ */
+ switch(platform_subtype) {
+ case HW_PLATFORM_SUBTYPE_UNKNOWN:
+ break;
+
+ default:
+ dprintf(CRITICAL, "Platform Subtype : %u is not supported\n",platform_subtype);
+ ASSERT(0);
+ };
+
+ switch(platform) {
+ case APQ8084:
+ board->baseband = BASEBAND_APQ;
+ break;
+ default:
+ dprintf(CRITICAL, "Platform type: %u is not supported\n",platform);
+ ASSERT(0);
+ }
+}
+
+unsigned target_baseband()
+{
+ return board_baseband();
+}
+
+void target_serialno(unsigned char *buf)
+{
+ unsigned int serialno;
+ if (target_is_emmc_boot()) {
+ serialno = mmc_get_psn();
+ snprintf((char *)buf, 13, "%x", serialno);
+ }
+}
+
+unsigned check_reboot_mode(void)
+{
+}
+
+void reboot_device(unsigned reboot_reason)
+{
+}
diff --git a/target/apq8084/meminfo.c b/target/apq8084/meminfo.c
new file mode 100644
index 0000000..745657b
--- /dev/null
+++ b/target/apq8084/meminfo.c
@@ -0,0 +1,87 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <reg.h>
+#include <debug.h>
+#include <malloc.h>
+#include <smem.h>
+#include <stdint.h>
+#include <libfdt.h>
+#include <platform/iomap.h>
+#include <dev_tree.h>
+
+/* Funtion to add the ram partition entries into device tree.
+ * The function assumes that all the entire fixed memory regions should
+ * be listed in the first bank of the passed in ddr regions.
+ */
+uint32_t target_dev_tree_mem(void *fdt, uint32_t memory_node_offset)
+{
+ struct smem_ram_ptable ram_ptable;
+ unsigned int i;
+ int ret = 0;
+
+ /* Make sure RAM partition table is initialized */
+ ASSERT(smem_ram_ptable_init(&ram_ptable));
+
+ /* Calculating the size of the mem_info_ptr */
+ for (i = 0 ; i < ram_ptable.len; i++)
+ {
+ if((ram_ptable.parts[i].category == SDRAM) &&
+ (ram_ptable.parts[i].type == SYS_MEMORY))
+ {
+
+ /* Pass along all other usable memory regions to Linux */
+ ret = dev_tree_add_mem_info(fdt,
+ memory_node_offset,
+ ram_ptable.parts[i].start,
+ ram_ptable.parts[i].size);
+
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to add secondary banks memory addresses\n"
+);
+ goto target_dev_tree_mem_err;
+ }
+
+ }
+ }
+
+target_dev_tree_mem_err:
+
+ return ret;
+}
+
+void *target_get_scratch_address(void)
+{
+ return ((void *)SCRATCH_ADDR);
+}
+
+unsigned target_get_max_flash_size(void)
+{
+ return (512 * 1024 * 1024);
+}
diff --git a/target/apq8084/rules.mk b/target/apq8084/rules.mk
new file mode 100644
index 0000000..aa2abf1
--- /dev/null
+++ b/target/apq8084/rules.mk
@@ -0,0 +1,36 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared
+
+PLATFORM := apq8084
+
+MEMBASE := 0x0F900000 # SDRAM
+MEMSIZE := 0x00100000 # 1MB
+
+BASE_ADDR := 0x0000000
+
+SCRATCH_ADDR := 0xFF00000
+
+DEFINES += DISPLAY_SPLASH_SCREEN=0
+DEFINES += DISPLAY_TYPE_MIPI=1
+DEFINES += DISPLAY_TYPE_DSI6G=1
+
+MODULES += \
+ dev/keys \
+ dev/pmic/pm8x41 \
+ lib/ptable \
+ lib/libfdt
+
+DEFINES += \
+ MEMSIZE=$(MEMSIZE) \
+ MEMBASE=$(MEMBASE) \
+ BASE_ADDR=$(BASE_ADDR) \
+ TAGS_ADDR=$(TAGS_ADDR) \
+ KERNEL_ADDR=$(KERNEL_ADDR) \
+ RAMDISK_ADDR=$(RAMDISK_ADDR) \
+ SCRATCH_ADDR=$(SCRATCH_ADDR)
+
+
+OBJS += \
+ $(LOCAL_DIR)/init.o \
+ $(LOCAL_DIR)/meminfo.o \
diff --git a/target/apq8084/tools/makefile b/target/apq8084/tools/makefile
new file mode 100644
index 0000000..2757e07
--- /dev/null
+++ b/target/apq8084/tools/makefile
@@ -0,0 +1,44 @@
+#Makefile to generate appsboot.mbn
+
+ifeq ($(BOOTLOADER_OUT),.)
+APPSBOOTHEADER_DIR := $(BUILDDIR)
+else
+APPSBOOTHEADER_DIR := $(BOOTLOADER_OUT)/../..
+endif
+
+SRC_DIR := target/$(TARGET)/tools
+COMPILER := gcc
+
+ifeq ($(EMMC_BOOT), 1)
+ APPSBOOTHDR_FILES := EMMCBOOT.MBN
+else
+ ifeq ($(BUILD_NANDWRITE), 1)
+ APPSBOOTHDR_FILES :=
+ else
+ APPSBOOTHDR_FILES := appsboot.mbn
+ endif
+endif
+
+APPSBOOTHEADER: $(APPSBOOTHDR_FILES)
+
+
+appsboot.mbn: appsboothd.mbn $(OUTBIN)
+ cp $(OUTBIN) $(APPSBOOTHEADER_DIR)/appsboot.raw
+ cat $(APPSBOOTHEADER_DIR)/appsboothd.mbn $(OUTBIN) > $(APPSBOOTHEADER_DIR)/appsboot.mbn
+ rm -f $(APPSBOOTHEADER_DIR)/appsboothd.mbn
+
+appsboothd.mbn: mkheader $(OUTBIN)
+ $(BUILDDIR)/mkheader $(OUTBIN) $(APPSBOOTHEADER_DIR)/appsboothd.mbn
+
+EMMCBOOT.MBN: emmc_appsboothd.mbn $(OUTBIN)
+ cp $(OUTBIN) $(APPSBOOTHEADER_DIR)/emmc_appsboot.raw
+ cat $(APPSBOOTHEADER_DIR)/emmc_appsboothd.mbn $(OUTBIN) > $(APPSBOOTHEADER_DIR)/EMMCBOOT.MBN
+ cat $(APPSBOOTHEADER_DIR)/emmc_appsboothd.mbn $(OUTBIN) > $(APPSBOOTHEADER_DIR)/emmc_appsboot.mbn
+ rm -f $(APPSBOOTHEADER_DIR)/emmc_appsboothd.mbn
+
+emmc_appsboothd.mbn: mkheader $(OUTBIN)
+ $(BUILDDIR)/mkheader $(OUTBIN) $(APPSBOOTHEADER_DIR)/emmc_appsboothd.mbn
+
+mkheader: $(SRC_DIR)/mkheader.c
+ @mkdir -p $(BUILDDIR)
+ ${COMPILER} -DMEMBASE=$(MEMBASE) $(SRC_DIR)/mkheader.c -o $(BUILDDIR)/mkheader
diff --git a/target/apq8084/tools/mkheader.c b/target/apq8084/tools/mkheader.c
new file mode 100644
index 0000000..4a84bd6
--- /dev/null
+++ b/target/apq8084/tools/mkheader.c
@@ -0,0 +1,344 @@
+/*
+ * Copyright (c) 2007, Google Inc.
+ * All rights reserved.
+ *
+ * Copyright (c) 2009-2011, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Google, Inc. nor the names of its contributors
+ * may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <string.h>
+
+#include <sys/stat.h>
+
+int print_usage()
+{
+ fprintf(stderr, "usage: mkheader <bin> <hdr> <none|unified-boot>\n");
+ fprintf(stderr, " mkheader <bin> <hdr> <unsecure-boot>"
+ " <outbin>\n");
+ fprintf(stderr, " mkheader <bin> <hdr> <secure-boot> <outbin>"
+ " <maxsize>\n");
+ fprintf(stderr, " mkheader <bin> <hdr> <secure-boot> <outbin>"
+ " <maxsize> <certchain> <files...>\n\n");
+ fprintf(stderr, "bin: Input raw appsbl binary\n");
+ fprintf(stderr,
+ "hdr: Output of appsbl header location\n");
+ fprintf(stderr,
+ "outbin: Output of the signed or unsigned"
+ " apps boot location\n");
+ fprintf(stderr,
+ "maxsize: Maximum size for certificate" " chain\n");
+ fprintf(stderr,
+ "certchain: Output of the certchain location\n");
+ fprintf(stderr,
+ "files: Input format <bin signature>"
+ " <certifcate file(s) for certificate chain>...\n");
+ fprintf(stderr,
+ "certificate chain: Files will be concatenated in order"
+ " to create the certificate chain\n\n");
+ return -1;
+}
+
+int cat(FILE * in, FILE * out, unsigned size, unsigned buff_size)
+{
+ unsigned bytes_left = size;
+ char buf[buff_size];
+ int ret = 0;
+
+ while (bytes_left) {
+ fread(buf, sizeof(char), buff_size, in);
+ if (!feof(in)) {
+ bytes_left -= fwrite(buf, sizeof(char), buff_size, out);
+ } else
+ bytes_left = 0;
+ }
+ ret = ferror(in) | ferror(out);
+ if (ret)
+ fprintf(stderr, "ERROR: Occured during file concatenation\n");
+ return ret;
+}
+
+int main(int argc, char *argv[])
+{
+ struct stat s;
+ unsigned size, base;
+ int unified_boot = 0;
+ unsigned unified_boot_magic[20];
+ unsigned non_unified_boot_magic[10];
+ unsigned magic_len = 0;
+ unsigned *magic;
+ unsigned cert_chain_size = 0;
+ unsigned signature_size = 0;
+ int secure_boot = 0;
+ int fd;
+
+ if (argc < 3) {
+ return print_usage();
+ }
+
+ if (argc == 4) {
+ if (!strcmp("unified-boot", argv[3])) {
+ unified_boot = 1;
+ } else if (!strcmp("secure-boot", argv[3])) {
+ fprintf(stderr,
+ "ERROR: Missing arguments: [outbin maxsize] |"
+ " [outbin, maxsize, certchain,"
+ " signature + certifcate(s)]\n");
+ return print_usage();
+ } else if (!strcmp("unsecure-boot", argv[3])) {
+ fprintf(stderr, "ERROR: Missing arguments:"
+ " outbin directory\n");
+ return print_usage();
+ }
+ }
+
+ if (argc > 4) {
+ if (!strcmp("secure-boot", argv[3])) {
+ if (argc < 9 && argc != 6) {
+ fprintf(stderr,
+ "ERROR: Missing argument(s):"
+ " [outbin maxsize] | [outbin, maxsize,"
+ " certchain,"
+ " signature + certifcate(s)]\n");
+ return print_usage();
+ }
+ secure_boot = 1;
+ signature_size = 256; //Support SHA 256
+ cert_chain_size = atoi(argv[5]);
+ }
+ }
+
+ if (stat(argv[1], &s)) {
+ perror("cannot stat binary");
+ return -1;
+ }
+
+ if (unified_boot) {
+ magic = unified_boot_magic;
+ magic_len = sizeof(unified_boot_magic);
+ } else {
+ magic = non_unified_boot_magic;
+ magic_len = sizeof(non_unified_boot_magic);
+ }
+
+ size = s.st_size;
+#if MEMBASE
+ base = MEMBASE;
+#else
+ base = 0;
+#endif
+
+ printf("Image Destination Pointer: 0x%x\n", base);
+
+ magic[0] = 0x00000005; /* appsbl */
+ magic[1] = 0x00000003; //Flash_partition_version /* nand */
+ magic[2] = 0x00000000; //image source pointer
+ magic[3] = base; //image destination pointer
+ magic[4] = size + cert_chain_size + signature_size; //image size
+ magic[5] = size; //code size
+ magic[6] = base + size;
+ magic[7] = signature_size;
+ magic[8] = size + base + signature_size;
+ magic[9] = cert_chain_size;
+
+ if (unified_boot == 1) {
+ magic[10] = 0x33836685; /* cookie magic number */
+ magic[11] = 0x00000001; /* cookie version */
+ magic[12] = 0x00000002; /* file formats */
+ magic[13] = 0x00000000;
+ magic[14] = 0x00000000; /* not setting size for boot.img */
+ magic[15] = 0x00000000;
+ magic[16] = 0x00000000;
+ magic[17] = 0x00000000;
+ magic[18] = 0x00000000;
+ magic[19] = 0x00000000;
+ }
+
+ fd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, 0644);
+ if (fd < 0) {
+ perror("cannot open header for writing");
+ return -1;
+ }
+ if (write(fd, magic, magic_len) != magic_len) {
+ perror("cannot write header");
+ close(fd);
+ unlink(argv[2]);
+ return -1;
+ }
+ close(fd);
+
+ if (secure_boot && argc > 6) {
+ FILE *input_file;
+ FILE *output_file;
+ unsigned buff_size = 1;
+ char buf[buff_size];
+ unsigned bytes_left;
+ unsigned current_cert_chain_size = 0;
+ int padding_size = 0;
+ int i;
+
+ if ((output_file = fopen(argv[6], "wb")) == NULL) {
+ perror("ERROR: Occured during fopen");
+ return -1;
+ }
+ printf("Certificate Chain Output File: %s\n", argv[6]);
+
+ for (i = 8; i < argc; i++) {
+ if ((input_file = fopen(argv[i], "rb")) == NULL) {
+ perror("ERROR: Occured during fopen");
+ return -1;
+ }
+ stat(argv[i], &s);
+ bytes_left = s.st_size;
+ current_cert_chain_size += bytes_left;
+ if (cat(input_file, output_file, bytes_left, buff_size))
+ return -1;
+ fclose(input_file);
+ }
+
+ //Pad certifcate chain to the max expected size from input
+ memset(buf, 0xFF, sizeof(buf));
+ padding_size = cert_chain_size - current_cert_chain_size;
+
+ if (padding_size < 0) {
+ fprintf(stderr, "ERROR: Input certificate chain"
+ " (Size=%d) is larger than the maximum"
+ " specified (Size=%d)\n",
+ current_cert_chain_size, cert_chain_size);
+ return -1;
+ }
+
+ bytes_left = (padding_size > 0) ? padding_size : 0;
+ while (bytes_left) {
+ if (!ferror(output_file))
+ bytes_left -= fwrite(buf,
+ sizeof(buf),
+ buff_size, output_file);
+ else {
+ fprintf(stderr, "ERROR: Occured during"
+ " certifcate chain padding\n");
+ return -1;
+ }
+ }
+ fclose(output_file);
+
+ /* Concat and combine to signed image.
+ * Format [HDR][RAW APPSBOOT][PADDED CERT CHAIN]
+ */
+ if ((output_file = fopen(argv[4], "wb")) == NULL) {
+ perror("ERROR: Occured during fopen");
+ return -1;
+ }
+ printf("Image Output File: %s\n", argv[4]);
+
+ //Header
+ if ((input_file = fopen(argv[2], "rb")) == NULL) {
+ perror("ERROR: Occured during fopen");
+ return -1;
+ }
+ stat(argv[2], &s);
+ if (cat(input_file, output_file, s.st_size, buff_size))
+ return -1;
+ fclose(input_file);
+
+ //Raw Appsbl
+ if ((input_file = fopen(argv[1], "rb")) == NULL) {
+ perror("ERROR: Occured during fopen");
+ return -1;
+ }
+ stat(argv[1], &s);
+ if (cat(input_file, output_file, s.st_size, buff_size))
+ return -1;
+ fclose(input_file);
+
+ //Signature
+ if ((input_file = fopen(argv[7], "rb")) == NULL) {
+ perror("ERROR: Occured during fopen");
+ return -1;
+ }
+ stat(argv[7], &s);
+ if (cat(input_file, output_file, s.st_size, buff_size))
+ return -1;
+ fclose(input_file);
+
+ //Certifcate Chain
+ if ((input_file = fopen(argv[6], "rb")) == NULL) {
+ perror("ERROR: Occured during fopen");
+ return -1;
+ }
+ if (cat(input_file, output_file,
+ (current_cert_chain_size + padding_size), buff_size))
+ return -1;
+ fclose(input_file);
+
+ fclose(output_file);
+
+ } else if (argc == 5 || argc == 6) {
+ FILE *input_file;
+ FILE *output_file;
+ unsigned buff_size = 1;
+ char buf[buff_size];
+
+ /* Concat and combine to unsigned image.
+ * Format [HDR][RAW APPSBOOT]
+ */
+ if ((output_file = fopen(argv[4], "wb")) == NULL) {
+ perror("ERROR: Occured during fopen");
+ return -1;
+ }
+ printf("Image Output File: %s\n", argv[4]);
+
+ //Header
+ if ((input_file = fopen(argv[2], "rb")) == NULL) {
+ perror("ERROR: Occured during fopen");
+ return -1;
+ }
+ stat(argv[2], &s);
+ if (cat(input_file, output_file, s.st_size, buff_size))
+ return -1;
+ fclose(input_file);
+
+ //Raw Appsbl
+ if ((input_file = fopen(argv[1], "rb")) == NULL) {
+ perror("ERROR: Occured during fopen");
+ return -1;
+ }
+ stat(argv[1], &s);
+ if (cat(input_file, output_file, s.st_size, buff_size))
+ return -1;
+ fclose(input_file);
+ fclose(output_file);
+ }
+
+ printf("Done execution\n");
+
+ return 0;
+}
diff --git a/target/fsm9900/init.c b/target/fsm9900/init.c
new file mode 100644
index 0000000..8bfc791
--- /dev/null
+++ b/target/fsm9900/init.c
@@ -0,0 +1,486 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <platform/iomap.h>
+#include <platform/irqs.h>
+#include <platform/gpio.h>
+#include <reg.h>
+#include <target.h>
+#include <platform.h>
+#include <dload_util.h>
+#include <uart_dm.h>
+#include <mmc.h>
+#include <spmi.h>
+#include <board.h>
+#include <smem.h>
+#include <baseband.h>
+#include <dev/keys.h>
+#include <crypto5_wrapper.h>
+#include <hsusb.h>
+#include <clock.h>
+#include <partition_parser.h>
+#include <scm.h>
+#include <platform/clock.h>
+#include <platform/gpio.h>
+#include <stdlib.h>
+
+extern bool target_use_signed_kernel(void);
+static void set_sdc_power_ctrl();
+
+static unsigned int target_id;
+
+#if MMC_SDHCI_SUPPORT
+struct mmc_device *dev;
+#endif
+
+#define PMIC_ARB_CHANNEL_NUM 0
+#define PMIC_ARB_OWNER_ID 0
+
+#define WDOG_DEBUG_DISABLE_BIT 17
+
+#define CE_INSTANCE 2
+#define CE_EE 1
+#define CE_FIFO_SIZE 64
+#define CE_READ_PIPE 3
+#define CE_WRITE_PIPE 2
+#define CE_READ_PIPE_LOCK_GRP 0
+#define CE_WRITE_PIPE_LOCK_GRP 0
+#define CE_ARRAY_SIZE 20
+
+#ifdef SSD_ENABLE
+#define SSD_CE_INSTANCE_1 1
+#define SSD_PARTITION_SIZE 8192
+#endif
+
+#define FASTBOOT_MODE 0x77665500
+
+#define BOARD_SOC_VERSION1(soc_rev) (soc_rev >= 0x10000 && soc_rev < 0x20000)
+
+#if MMC_SDHCI_SUPPORT
+static uint32_t mmc_sdhci_base[] =
+ { MSM_SDC1_SDHCI_BASE, MSM_SDC2_SDHCI_BASE };
+#endif
+
+static uint32_t mmc_sdc_base[] =
+ { MSM_SDC1_BASE, MSM_SDC2_BASE };
+
+static uint32_t mmc_sdc_pwrctl_irq[] =
+ { SDCC1_PWRCTL_IRQ, SDCC2_PWRCTL_IRQ };
+
+void target_early_init(void)
+{
+#if WITH_DEBUG_UART
+ uart_dm_init(9, 0, BLSP2_UART3_BASE);
+#endif
+}
+
+/* Return 1 if vol_up pressed */
+static int target_volume_up()
+{
+ return 0;
+}
+
+/* Return 1 if vol_down pressed */
+uint32_t target_volume_down()
+{
+ return 0;
+}
+
+static void target_keystatus()
+{
+ keys_init();
+
+ if (target_volume_down())
+ keys_post_event(KEY_VOLUMEDOWN, 1);
+
+ if (target_volume_up())
+ keys_post_event(KEY_VOLUMEUP, 1);
+}
+
+/* Set up params for h/w CE. */
+void target_crypto_init_params()
+{
+ struct crypto_init_params ce_params;
+
+ /* Set up base addresses and instance. */
+ ce_params.crypto_instance = CE_INSTANCE;
+ ce_params.crypto_base = MSM_CE2_BASE;
+ ce_params.bam_base = MSM_CE2_BAM_BASE;
+
+ /* Set up BAM config. */
+ ce_params.bam_ee = CE_EE;
+ ce_params.pipes.read_pipe = CE_READ_PIPE;
+ ce_params.pipes.write_pipe = CE_WRITE_PIPE;
+ ce_params.pipes.read_pipe_grp = CE_READ_PIPE_LOCK_GRP;
+ ce_params.pipes.write_pipe_grp = CE_WRITE_PIPE_LOCK_GRP;
+
+ /* Assign buffer sizes. */
+ ce_params.num_ce = CE_ARRAY_SIZE;
+ ce_params.read_fifo_size = CE_FIFO_SIZE;
+ ce_params.write_fifo_size = CE_FIFO_SIZE;
+
+ /* BAM is initialized by TZ for this platform.
+ * Do not do it again as the initialization address space
+ * is locked.
+ */
+ ce_params.do_bam_init = 0;
+
+ crypto_init_params(&ce_params);
+}
+
+crypto_engine_type board_ce_type(void)
+{
+ return CRYPTO_ENGINE_TYPE_HW;
+}
+
+#if MMC_SDHCI_SUPPORT
+static void target_mmc_sdhci_init()
+{
+ struct mmc_config_data config = {0};
+
+ config.bus_width = DATA_BUS_WIDTH_8BIT;
+ config.max_clk_rate = MMC_CLK_200MHZ;
+
+ /* Trying Slot 1*/
+ config.slot = 1;
+ config.sdhc_base = mmc_sdhci_base[config.slot - 1];
+ config.pwrctl_base = mmc_sdc_base[config.slot - 1];
+ config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
+
+ if (!(dev = mmc_init(&config))) {
+ /* Trying Slot 2 next */
+ config.slot = 2;
+ config.sdhc_base = mmc_sdhci_base[config.slot - 1];
+ config.pwrctl_base = mmc_sdc_base[config.slot - 1];
+ config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
+
+ if (!(dev = mmc_init(&config))) {
+ dprintf(CRITICAL, "mmc init failed!");
+ ASSERT(0);
+ }
+ }
+
+ /*
+ * MMC initialization is complete, read the partition table info
+ */
+ if (partition_read_table()) {
+ dprintf(CRITICAL, "Error reading the partition table info\n");
+ ASSERT(0);
+ }
+}
+
+struct mmc_device *target_mmc_device()
+{
+ return dev;
+}
+
+#else
+
+static void target_mmc_mci_init()
+{
+ uint32_t base_addr;
+ uint8_t slot;
+
+ /* Trying Slot 1 */
+ slot = 1;
+ base_addr = mmc_sdc_base[slot - 1];
+
+ if (mmc_boot_main(slot, base_addr))
+ {
+ /* Trying Slot 2 next */
+ slot = 2;
+ base_addr = mmc_sdc_base[slot - 1];
+ if (mmc_boot_main(slot, base_addr)) {
+ dprintf(CRITICAL, "mmc init failed!");
+ ASSERT(0);
+ }
+ }
+}
+
+/*
+ * Function to set the capabilities for the host
+ */
+void target_mmc_caps(struct mmc_host *host)
+{
+ host->caps.bus_width = MMC_BOOT_BUS_WIDTH_8_BIT;
+ host->caps.ddr_mode = 1;
+ host->caps.hs200_mode = 1;
+ host->caps.hs_clk_rate = MMC_CLK_96MHZ;
+}
+
+#endif
+
+void target_init(void)
+{
+ dprintf(INFO, "target_init()\n");
+
+ target_keystatus();
+
+ if (target_use_signed_kernel())
+ target_crypto_init_params();
+
+ /*
+ * Set drive strength & pull ctrl for
+ * emmc
+ */
+ set_sdc_power_ctrl();
+
+#if MMC_SDHCI_SUPPORT
+ target_mmc_sdhci_init();
+#else
+ target_mmc_mci_init();
+#endif
+}
+
+unsigned board_machtype(void)
+{
+ return target_id;
+}
+
+/* Do any target specific intialization needed before entering fastboot mode */
+#ifdef SSD_ENABLE
+static void ssd_load_keystore_from_emmc()
+{
+ uint64_t ptn = 0;
+ int index = -1;
+ uint32_t size = SSD_PARTITION_SIZE;
+ int ret = -1;
+
+ uint32_t *buffer = (uint32_t *)memalign(CACHE_LINE,
+ ROUNDUP(SSD_PARTITION_SIZE, CACHE_LINE));
+
+ if (!buffer) {
+ dprintf(CRITICAL, "Error Allocating memory for SSD buffer\n");
+ ASSERT(0);
+ }
+
+ index = partition_get_index("ssd");
+
+ ptn = partition_get_offset(index);
+ if(ptn == 0){
+ dprintf(CRITICAL,"ERROR: ssd parition not found");
+ return;
+ }
+
+ if(mmc_read(ptn, buffer, size)){
+ dprintf(CRITICAL,"ERROR:Cannot read data\n");
+ return;
+ }
+
+ ret = scm_protect_keystore((uint32_t *)&buffer[0],size);
+ if(ret != 0)
+ dprintf(CRITICAL,"ERROR: scm_protect_keystore Failed");
+
+ free(buffer);
+}
+#endif
+
+void target_fastboot_init(void)
+{
+#ifdef SSD_ENABLE
+ clock_ce_enable(SSD_CE_INSTANCE_1);
+ ssd_load_keystore_from_emmc();
+#endif
+}
+
+/* Detect the target type */
+void target_detect(struct board_data *board)
+{
+ board->target = LINUX_MACHTYPE_UNKNOWN;
+}
+
+/* Detect the modem type */
+void target_baseband_detect(struct board_data *board)
+{
+ uint32_t platform;
+ uint32_t platform_subtype;
+
+ platform = board->platform;
+ platform_subtype = board->platform_subtype;
+
+ /*
+ * Look for platform subtype if present, else
+ * check for platform type to decide on the
+ * baseband type
+ */
+ switch (platform_subtype) {
+ case HW_PLATFORM_SUBTYPE_UNKNOWN:
+ break;
+ default:
+ dprintf(CRITICAL, "Platform Subtype : %u is not supported\n",platform_subtype);
+ ASSERT(0);
+ };
+
+ switch (platform) {
+ case FSM9900:
+ board->baseband = BASEBAND_MSM;
+ break;
+ default:
+ dprintf(CRITICAL, "Platform type: %u is not supported\n",platform);
+ ASSERT(0);
+ };
+}
+
+unsigned target_baseband()
+{
+ return board_baseband();
+}
+
+void target_serialno(unsigned char *buf)
+{
+ unsigned int serialno;
+ if (target_is_emmc_boot()) {
+ serialno = mmc_get_psn();
+ snprintf((char *)buf, 13, "%x", serialno);
+ }
+}
+
+unsigned check_reboot_mode(void)
+{
+ uint32_t restart_reason = 0;
+ uint32_t restart_reason_addr;
+
+ restart_reason_addr = RESTART_REASON_ADDR;
+
+ /* Read reboot reason and scrub it */
+ restart_reason = readl(restart_reason_addr);
+ writel(0x00, restart_reason_addr);
+
+ return restart_reason;
+}
+
+void reboot_device(unsigned reboot_reason)
+{
+ /* Write the reboot reason */
+ writel(reboot_reason, RESTART_REASON_ADDR);
+
+ /* Disable Watchdog Debug.
+ * Required becuase of a H/W bug which causes the system to
+ * reset partially even for non watchdog resets.
+ */
+ writel(readl(GCC_WDOG_DEBUG) & ~(1 << WDOG_DEBUG_DISABLE_BIT), GCC_WDOG_DEBUG);
+
+ dsb();
+
+ /* Wait until the write takes effect. */
+ while(readl(GCC_WDOG_DEBUG) & (1 << WDOG_DEBUG_DISABLE_BIT));
+
+ /* Drop PS_HOLD for MSM */
+ writel(0x00, MPM2_MPM_PS_HOLD);
+
+ mdelay(5000);
+
+ dprintf(CRITICAL, "Rebooting failed\n");
+}
+
+int set_download_mode(enum dload_mode mode)
+{
+ dload_util_write_cookie(mode == NORMAL_DLOAD ?
+ DLOAD_MODE_ADDR_V2 : EMERGENCY_DLOAD_MODE_ADDR_V2, mode);
+
+ return 0;
+}
+
+/* Check if MSM needs VBUS mimic for USB */
+static int target_needs_vbus_mimic()
+{
+ return 0;
+}
+
+/* Do target specific usb initialization */
+void target_usb_init(void)
+{
+}
+
+/* Returns 1 if target supports continuous splash screen. */
+int target_cont_splash_screen()
+{
+ return 0;
+}
+
+unsigned target_pause_for_battery_charge(void)
+{
+ return 0;
+}
+
+void target_uninit(void)
+{
+#if MMC_SDHCI_SUPPORT
+ mmc_put_card_to_sleep(dev);
+#else
+ mmc_put_card_to_sleep();
+#endif
+#ifdef SSD_ENABLE
+ clock_ce_disable(SSD_CE_INSTANCE_1);
+#endif
+}
+
+void shutdown_device()
+{
+ dprintf(CRITICAL, "Going down for shutdown.\n");
+
+ /* Drop PS_HOLD for MSM */
+ writel(0x00, MPM2_MPM_PS_HOLD);
+
+ mdelay(5000);
+
+ dprintf(CRITICAL, "Shutdown failed\n");
+}
+
+static void set_sdc_power_ctrl()
+{
+ /* Drive strength configs for sdc pins */
+ struct tlmm_cfgs sdc1_hdrv_cfg[] =
+ {
+ { SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK },
+ { SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
+ { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
+ };
+
+ /* Pull configs for sdc pins */
+ struct tlmm_cfgs sdc1_pull_cfg[] =
+ {
+ { SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK },
+ { SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
+ { SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
+ };
+
+ /* Set the drive strength & pull control values */
+ tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg));
+ tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg));
+}
+
+int emmc_recovery_init(void)
+{
+ return _emmc_recovery_init();
+}
+
+void target_usb_stop(void)
+{
+}
diff --git a/target/fsm9900/meminfo.c b/target/fsm9900/meminfo.c
new file mode 100644
index 0000000..5f9c490
--- /dev/null
+++ b/target/fsm9900/meminfo.c
@@ -0,0 +1,89 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if DEVICE_TREE /* If using device tree */
+
+#include <reg.h>
+#include <debug.h>
+#include <malloc.h>
+#include <smem.h>
+#include <stdint.h>
+#include <libfdt.h>
+#include <platform/iomap.h>
+#include <dev_tree.h>
+
+/* Funtion to add the ram partition entries into device tree.
+ * The function assumes that all the entire fixed memory regions should
+ * be listed in the first bank of the passed in ddr regions.
+ */
+uint32_t target_dev_tree_mem(void *fdt, uint32_t memory_node_offset)
+{
+ struct smem_ram_ptable ram_ptable;
+ unsigned int i;
+ int ret = 0;
+
+ /* Make sure RAM partition table is initialized */
+ ASSERT(smem_ram_ptable_init(&ram_ptable));
+
+ /* Calculating the size of the mem_info_ptr */
+ for (i = 0 ; i < ram_ptable.len; i++)
+ {
+ if((ram_ptable.parts[i].category == SDRAM) &&
+ (ram_ptable.parts[i].type == SYS_MEMORY))
+ {
+
+ /* Pass along all other usable memory regions to Linux */
+ ret = dev_tree_add_mem_info(fdt,
+ memory_node_offset,
+ ram_ptable.parts[i].start,
+ ram_ptable.parts[i].size);
+
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to add secondary banks memory addresses\n");
+ goto target_dev_tree_mem_err;
+ }
+
+ }
+ }
+
+target_dev_tree_mem_err:
+
+ return ret;
+}
+
+void *target_get_scratch_address(void)
+{
+ return ((void *)SCRATCH_ADDR);
+}
+
+unsigned target_get_max_flash_size(void)
+{
+ return (512 * 1024 * 1024);
+}
+#endif /* DEVICE_TREE */
diff --git a/target/fsm9900/rules.mk b/target/fsm9900/rules.mk
new file mode 100644
index 0000000..64f97aa
--- /dev/null
+++ b/target/fsm9900/rules.mk
@@ -0,0 +1,35 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared
+
+PLATFORM := fsm9900
+
+MEMBASE := 0x0F900000 # SDRAM
+MEMSIZE := 0x00100000 # 1MB
+
+BASE_ADDR := 0x00000
+
+TAGS_ADDR := BASE_ADDR+0x00000100
+KERNEL_ADDR := BASE_ADDR+0x00008000
+RAMDISK_ADDR := BASE_ADDR+0x01000000
+SCRATCH_ADDR := 0x11000000
+
+MODULES += \
+ dev/keys \
+ dev/panel/msm \
+ lib/ptable \
+ lib/libfdt
+
+DEFINES += \
+ MEMSIZE=$(MEMSIZE) \
+ MEMBASE=$(MEMBASE) \
+ BASE_ADDR=$(BASE_ADDR) \
+ TAGS_ADDR=$(TAGS_ADDR) \
+ KERNEL_ADDR=$(KERNEL_ADDR) \
+ RAMDISK_ADDR=$(RAMDISK_ADDR) \
+ SCRATCH_ADDR=$(SCRATCH_ADDR)
+
+
+OBJS += \
+ $(LOCAL_DIR)/init.o \
+ $(LOCAL_DIR)/meminfo.o
diff --git a/target/fsm9900/tools/makefile b/target/fsm9900/tools/makefile
new file mode 100644
index 0000000..2757e07
--- /dev/null
+++ b/target/fsm9900/tools/makefile
@@ -0,0 +1,44 @@
+#Makefile to generate appsboot.mbn
+
+ifeq ($(BOOTLOADER_OUT),.)
+APPSBOOTHEADER_DIR := $(BUILDDIR)
+else
+APPSBOOTHEADER_DIR := $(BOOTLOADER_OUT)/../..
+endif
+
+SRC_DIR := target/$(TARGET)/tools
+COMPILER := gcc
+
+ifeq ($(EMMC_BOOT), 1)
+ APPSBOOTHDR_FILES := EMMCBOOT.MBN
+else
+ ifeq ($(BUILD_NANDWRITE), 1)
+ APPSBOOTHDR_FILES :=
+ else
+ APPSBOOTHDR_FILES := appsboot.mbn
+ endif
+endif
+
+APPSBOOTHEADER: $(APPSBOOTHDR_FILES)
+
+
+appsboot.mbn: appsboothd.mbn $(OUTBIN)
+ cp $(OUTBIN) $(APPSBOOTHEADER_DIR)/appsboot.raw
+ cat $(APPSBOOTHEADER_DIR)/appsboothd.mbn $(OUTBIN) > $(APPSBOOTHEADER_DIR)/appsboot.mbn
+ rm -f $(APPSBOOTHEADER_DIR)/appsboothd.mbn
+
+appsboothd.mbn: mkheader $(OUTBIN)
+ $(BUILDDIR)/mkheader $(OUTBIN) $(APPSBOOTHEADER_DIR)/appsboothd.mbn
+
+EMMCBOOT.MBN: emmc_appsboothd.mbn $(OUTBIN)
+ cp $(OUTBIN) $(APPSBOOTHEADER_DIR)/emmc_appsboot.raw
+ cat $(APPSBOOTHEADER_DIR)/emmc_appsboothd.mbn $(OUTBIN) > $(APPSBOOTHEADER_DIR)/EMMCBOOT.MBN
+ cat $(APPSBOOTHEADER_DIR)/emmc_appsboothd.mbn $(OUTBIN) > $(APPSBOOTHEADER_DIR)/emmc_appsboot.mbn
+ rm -f $(APPSBOOTHEADER_DIR)/emmc_appsboothd.mbn
+
+emmc_appsboothd.mbn: mkheader $(OUTBIN)
+ $(BUILDDIR)/mkheader $(OUTBIN) $(APPSBOOTHEADER_DIR)/emmc_appsboothd.mbn
+
+mkheader: $(SRC_DIR)/mkheader.c
+ @mkdir -p $(BUILDDIR)
+ ${COMPILER} -DMEMBASE=$(MEMBASE) $(SRC_DIR)/mkheader.c -o $(BUILDDIR)/mkheader
diff --git a/target/fsm9900/tools/mkheader.c b/target/fsm9900/tools/mkheader.c
new file mode 100644
index 0000000..4a84bd6
--- /dev/null
+++ b/target/fsm9900/tools/mkheader.c
@@ -0,0 +1,344 @@
+/*
+ * Copyright (c) 2007, Google Inc.
+ * All rights reserved.
+ *
+ * Copyright (c) 2009-2011, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Google, Inc. nor the names of its contributors
+ * may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <string.h>
+
+#include <sys/stat.h>
+
+int print_usage()
+{
+ fprintf(stderr, "usage: mkheader <bin> <hdr> <none|unified-boot>\n");
+ fprintf(stderr, " mkheader <bin> <hdr> <unsecure-boot>"
+ " <outbin>\n");
+ fprintf(stderr, " mkheader <bin> <hdr> <secure-boot> <outbin>"
+ " <maxsize>\n");
+ fprintf(stderr, " mkheader <bin> <hdr> <secure-boot> <outbin>"
+ " <maxsize> <certchain> <files...>\n\n");
+ fprintf(stderr, "bin: Input raw appsbl binary\n");
+ fprintf(stderr,
+ "hdr: Output of appsbl header location\n");
+ fprintf(stderr,
+ "outbin: Output of the signed or unsigned"
+ " apps boot location\n");
+ fprintf(stderr,
+ "maxsize: Maximum size for certificate" " chain\n");
+ fprintf(stderr,
+ "certchain: Output of the certchain location\n");
+ fprintf(stderr,
+ "files: Input format <bin signature>"
+ " <certifcate file(s) for certificate chain>...\n");
+ fprintf(stderr,
+ "certificate chain: Files will be concatenated in order"
+ " to create the certificate chain\n\n");
+ return -1;
+}
+
+int cat(FILE * in, FILE * out, unsigned size, unsigned buff_size)
+{
+ unsigned bytes_left = size;
+ char buf[buff_size];
+ int ret = 0;
+
+ while (bytes_left) {
+ fread(buf, sizeof(char), buff_size, in);
+ if (!feof(in)) {
+ bytes_left -= fwrite(buf, sizeof(char), buff_size, out);
+ } else
+ bytes_left = 0;
+ }
+ ret = ferror(in) | ferror(out);
+ if (ret)
+ fprintf(stderr, "ERROR: Occured during file concatenation\n");
+ return ret;
+}
+
+int main(int argc, char *argv[])
+{
+ struct stat s;
+ unsigned size, base;
+ int unified_boot = 0;
+ unsigned unified_boot_magic[20];
+ unsigned non_unified_boot_magic[10];
+ unsigned magic_len = 0;
+ unsigned *magic;
+ unsigned cert_chain_size = 0;
+ unsigned signature_size = 0;
+ int secure_boot = 0;
+ int fd;
+
+ if (argc < 3) {
+ return print_usage();
+ }
+
+ if (argc == 4) {
+ if (!strcmp("unified-boot", argv[3])) {
+ unified_boot = 1;
+ } else if (!strcmp("secure-boot", argv[3])) {
+ fprintf(stderr,
+ "ERROR: Missing arguments: [outbin maxsize] |"
+ " [outbin, maxsize, certchain,"
+ " signature + certifcate(s)]\n");
+ return print_usage();
+ } else if (!strcmp("unsecure-boot", argv[3])) {
+ fprintf(stderr, "ERROR: Missing arguments:"
+ " outbin directory\n");
+ return print_usage();
+ }
+ }
+
+ if (argc > 4) {
+ if (!strcmp("secure-boot", argv[3])) {
+ if (argc < 9 && argc != 6) {
+ fprintf(stderr,
+ "ERROR: Missing argument(s):"
+ " [outbin maxsize] | [outbin, maxsize,"
+ " certchain,"
+ " signature + certifcate(s)]\n");
+ return print_usage();
+ }
+ secure_boot = 1;
+ signature_size = 256; //Support SHA 256
+ cert_chain_size = atoi(argv[5]);
+ }
+ }
+
+ if (stat(argv[1], &s)) {
+ perror("cannot stat binary");
+ return -1;
+ }
+
+ if (unified_boot) {
+ magic = unified_boot_magic;
+ magic_len = sizeof(unified_boot_magic);
+ } else {
+ magic = non_unified_boot_magic;
+ magic_len = sizeof(non_unified_boot_magic);
+ }
+
+ size = s.st_size;
+#if MEMBASE
+ base = MEMBASE;
+#else
+ base = 0;
+#endif
+
+ printf("Image Destination Pointer: 0x%x\n", base);
+
+ magic[0] = 0x00000005; /* appsbl */
+ magic[1] = 0x00000003; //Flash_partition_version /* nand */
+ magic[2] = 0x00000000; //image source pointer
+ magic[3] = base; //image destination pointer
+ magic[4] = size + cert_chain_size + signature_size; //image size
+ magic[5] = size; //code size
+ magic[6] = base + size;
+ magic[7] = signature_size;
+ magic[8] = size + base + signature_size;
+ magic[9] = cert_chain_size;
+
+ if (unified_boot == 1) {
+ magic[10] = 0x33836685; /* cookie magic number */
+ magic[11] = 0x00000001; /* cookie version */
+ magic[12] = 0x00000002; /* file formats */
+ magic[13] = 0x00000000;
+ magic[14] = 0x00000000; /* not setting size for boot.img */
+ magic[15] = 0x00000000;
+ magic[16] = 0x00000000;
+ magic[17] = 0x00000000;
+ magic[18] = 0x00000000;
+ magic[19] = 0x00000000;
+ }
+
+ fd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, 0644);
+ if (fd < 0) {
+ perror("cannot open header for writing");
+ return -1;
+ }
+ if (write(fd, magic, magic_len) != magic_len) {
+ perror("cannot write header");
+ close(fd);
+ unlink(argv[2]);
+ return -1;
+ }
+ close(fd);
+
+ if (secure_boot && argc > 6) {
+ FILE *input_file;
+ FILE *output_file;
+ unsigned buff_size = 1;
+ char buf[buff_size];
+ unsigned bytes_left;
+ unsigned current_cert_chain_size = 0;
+ int padding_size = 0;
+ int i;
+
+ if ((output_file = fopen(argv[6], "wb")) == NULL) {
+ perror("ERROR: Occured during fopen");
+ return -1;
+ }
+ printf("Certificate Chain Output File: %s\n", argv[6]);
+
+ for (i = 8; i < argc; i++) {
+ if ((input_file = fopen(argv[i], "rb")) == NULL) {
+ perror("ERROR: Occured during fopen");
+ return -1;
+ }
+ stat(argv[i], &s);
+ bytes_left = s.st_size;
+ current_cert_chain_size += bytes_left;
+ if (cat(input_file, output_file, bytes_left, buff_size))
+ return -1;
+ fclose(input_file);
+ }
+
+ //Pad certifcate chain to the max expected size from input
+ memset(buf, 0xFF, sizeof(buf));
+ padding_size = cert_chain_size - current_cert_chain_size;
+
+ if (padding_size < 0) {
+ fprintf(stderr, "ERROR: Input certificate chain"
+ " (Size=%d) is larger than the maximum"
+ " specified (Size=%d)\n",
+ current_cert_chain_size, cert_chain_size);
+ return -1;
+ }
+
+ bytes_left = (padding_size > 0) ? padding_size : 0;
+ while (bytes_left) {
+ if (!ferror(output_file))
+ bytes_left -= fwrite(buf,
+ sizeof(buf),
+ buff_size, output_file);
+ else {
+ fprintf(stderr, "ERROR: Occured during"
+ " certifcate chain padding\n");
+ return -1;
+ }
+ }
+ fclose(output_file);
+
+ /* Concat and combine to signed image.
+ * Format [HDR][RAW APPSBOOT][PADDED CERT CHAIN]
+ */
+ if ((output_file = fopen(argv[4], "wb")) == NULL) {
+ perror("ERROR: Occured during fopen");
+ return -1;
+ }
+ printf("Image Output File: %s\n", argv[4]);
+
+ //Header
+ if ((input_file = fopen(argv[2], "rb")) == NULL) {
+ perror("ERROR: Occured during fopen");
+ return -1;
+ }
+ stat(argv[2], &s);
+ if (cat(input_file, output_file, s.st_size, buff_size))
+ return -1;
+ fclose(input_file);
+
+ //Raw Appsbl
+ if ((input_file = fopen(argv[1], "rb")) == NULL) {
+ perror("ERROR: Occured during fopen");
+ return -1;
+ }
+ stat(argv[1], &s);
+ if (cat(input_file, output_file, s.st_size, buff_size))
+ return -1;
+ fclose(input_file);
+
+ //Signature
+ if ((input_file = fopen(argv[7], "rb")) == NULL) {
+ perror("ERROR: Occured during fopen");
+ return -1;
+ }
+ stat(argv[7], &s);
+ if (cat(input_file, output_file, s.st_size, buff_size))
+ return -1;
+ fclose(input_file);
+
+ //Certifcate Chain
+ if ((input_file = fopen(argv[6], "rb")) == NULL) {
+ perror("ERROR: Occured during fopen");
+ return -1;
+ }
+ if (cat(input_file, output_file,
+ (current_cert_chain_size + padding_size), buff_size))
+ return -1;
+ fclose(input_file);
+
+ fclose(output_file);
+
+ } else if (argc == 5 || argc == 6) {
+ FILE *input_file;
+ FILE *output_file;
+ unsigned buff_size = 1;
+ char buf[buff_size];
+
+ /* Concat and combine to unsigned image.
+ * Format [HDR][RAW APPSBOOT]
+ */
+ if ((output_file = fopen(argv[4], "wb")) == NULL) {
+ perror("ERROR: Occured during fopen");
+ return -1;
+ }
+ printf("Image Output File: %s\n", argv[4]);
+
+ //Header
+ if ((input_file = fopen(argv[2], "rb")) == NULL) {
+ perror("ERROR: Occured during fopen");
+ return -1;
+ }
+ stat(argv[2], &s);
+ if (cat(input_file, output_file, s.st_size, buff_size))
+ return -1;
+ fclose(input_file);
+
+ //Raw Appsbl
+ if ((input_file = fopen(argv[1], "rb")) == NULL) {
+ perror("ERROR: Occured during fopen");
+ return -1;
+ }
+ stat(argv[1], &s);
+ if (cat(input_file, output_file, s.st_size, buff_size))
+ return -1;
+ fclose(input_file);
+ fclose(output_file);
+ }
+
+ printf("Done execution\n");
+
+ return 0;
+}
diff --git a/target/init.c b/target/init.c
index 8a9a9d0..a2c1d93 100644
--- a/target/init.c
+++ b/target/init.c
@@ -107,6 +107,18 @@
#endif
}
+__WEAK bool target_is_ssd_enabled(void)
+{
+#ifdef SSD_ENABLE
+ return 1;
+#else
+ return 0;
+#endif
+}
+
+__WEAK void target_load_ssd_keystore(void)
+{
+}
/* Default target does not support continuous splash screen feature. */
__WEAK int target_cont_splash_screen()
diff --git a/target/msm8226/init.c b/target/msm8226/init.c
index dbd12d3..7b31f43 100644
--- a/target/msm8226/init.c
+++ b/target/msm8226/init.c
@@ -35,6 +35,7 @@
#include <dload_util.h>
#include <uart_dm.h>
#include <mmc_sdhci.h>
+#include <platform/clock.h>
#include <platform/gpio.h>
#include <spmi.h>
#include <board.h>
@@ -44,6 +45,9 @@
#include <pm8x41.h>
#include <crypto5_wrapper.h>
#include <hsusb.h>
+#include <scm.h>
+#include <stdlib.h>
+#include <partition_parser.h>
extern bool target_use_signed_kernel(void);
static void set_sdc_power_ctrl(void);
@@ -62,10 +66,13 @@
#define TLMM_VOL_UP_BTN_GPIO 106
+#define SSD_CE_INSTANCE 1
+
enum target_subtype {
HW_PLATFORM_SUBTYPE_SKUAA = 1,
HW_PLATFORM_SUBTYPE_SKUF = 2,
HW_PLATFORM_SUBTYPE_SKUAB = 3,
+ HW_PLATFORM_SUBTYPE_SKUG = 5,
};
static uint32_t mmc_pwrctl_base[] =
@@ -79,6 +86,48 @@
struct mmc_device *dev;
+void target_load_ssd_keystore(void)
+{
+ uint64_t ptn;
+ int index;
+ uint64_t size;
+ uint32_t *buffer;
+
+ if (!target_is_ssd_enabled())
+ return;
+
+ index = partition_get_index("ssd");
+
+ ptn = partition_get_offset(index);
+ if (ptn == 0){
+ dprintf(CRITICAL, "Error: ssd partition not found\n");
+ return;
+ }
+
+ size = partition_get_size(index);
+ if (size == 0) {
+ dprintf(CRITICAL, "Error: invalid ssd partition size\n");
+ return;
+ }
+
+ buffer = memalign(CACHE_LINE, ROUNDUP(size, CACHE_LINE));
+ if (!buffer) {
+ dprintf(CRITICAL, "Error: allocating memory for ssd buffer\n");
+ return;
+ }
+
+ if (mmc_read(ptn, buffer, size)) {
+ dprintf(CRITICAL, "Error: cannot read data\n");
+ free(buffer);
+ return;
+ }
+
+ clock_ce_enable(SSD_CE_INSTANCE);
+ scm_protect_keystore(buffer, size);
+ clock_ce_disable(SSD_CE_INSTANCE);
+ free(buffer);
+}
+
void target_early_init(void)
{
#if WITH_DEBUG_UART
@@ -142,6 +191,8 @@
ce_params.read_fifo_size = CRYPTO_ENGINE_FIFO_SIZE;
ce_params.write_fifo_size = CRYPTO_ENGINE_FIFO_SIZE;
+ ce_params.do_bam_init = 0;
+
crypto_init_params(&ce_params);
}
@@ -212,6 +263,11 @@
{
/* Set the BOOT_DONE flag in PM8026 */
pm8x41_set_boot_done();
+
+ if (target_is_ssd_enabled()) {
+ clock_ce_enable(SSD_CE_INSTANCE);
+ target_load_ssd_keystore();
+ }
}
/* Detect the target type */
@@ -246,6 +302,8 @@
break;
case HW_PLATFORM_SUBTYPE_SKUAB:
break;
+ case HW_PLATFORM_SUBTYPE_SKUG:
+ break;
default:
dprintf(CRITICAL, "Platform Subtype : %u is not supported\n", platform_subtype);
ASSERT(0);
@@ -324,6 +382,9 @@
void target_uninit(void)
{
mmc_put_card_to_sleep(dev);
+
+ if (target_is_ssd_enabled())
+ clock_ce_disable(SSD_CE_INSTANCE);
}
void target_usb_init(void)
@@ -362,7 +423,6 @@
unsigned target_pause_for_battery_charge(void)
{
-#if 0
uint8_t pon_reason = pm8x41_get_pon_reason();
uint8_t is_cold_boot = pm8x41_get_is_cold_boot();
dprintf(INFO, "%s : pon_reason is %d cold_boot:%d\n", __func__,
@@ -378,7 +438,6 @@
((pon_reason & USB_CHG) || (pon_reason & DC_CHG)))
return 1;
else
-#endif
return 0;
}
diff --git a/target/msm8226/target_display.c b/target/msm8226/target_display.c
index 2da792e..5b719cc 100755
--- a/target/msm8226/target_display.c
+++ b/target/msm8226/target_display.c
@@ -42,13 +42,13 @@
#include "include/display_resource.h"
+#define HFPLL_LDO_ID 8
+
static struct pm8x41_wled_data wled_ctrl = {
- .mod_scheme = 0xC3,
+ .mod_scheme = 0x00,
.led1_brightness = (0x0F << 8) | 0xEF,
- .led2_brightness = (0x0F << 8) | 0xEF,
- .led3_brightness = (0x0F << 8) | 0xEF,
.max_duty_cycle = 0x01,
- .ovp = 0x2,
+ .ovp = 0x0,
.full_current_scale = 0x19
};
@@ -131,11 +131,16 @@
ldo_entry_array[ldocounter].ldo_id);
/* Set voltage during power on */
- if (enable == 1) {
+ if (enable) {
pm8x41_ldo_set_voltage(&ldo_entry,
ldo_entry_array[ldocounter].ldo_voltage);
+
+ pm8x41_ldo_control(&ldo_entry, enable);
+
+ } else if(!target_cont_splash_screen() &&
+ ldo_entry_array[ldocounter].ldo_id != HFPLL_LDO_ID) {
+ pm8x41_ldo_control(&ldo_entry, enable);
}
- pm8x41_ldo_control(&ldo_entry, enable);
ldocounter++;
}
diff --git a/target/msm8610/init.c b/target/msm8610/init.c
index 92c9855..b662767 100644
--- a/target/msm8610/init.c
+++ b/target/msm8610/init.c
@@ -165,6 +165,10 @@
target_sdc_init();
}
+void target_uninit(void)
+{
+ mmc_put_card_to_sleep(dev);
+}
/* Do any target specific intialization needed before entering fastboot mode */
void target_fastboot_init(void)
{
@@ -270,13 +274,15 @@
int target_cont_splash_screen()
{
int ret = 0;
+
switch(board_hardware_id())
{
- case HW_PLATFORM_MTP:
case HW_PLATFORM_QRD:
+ case HW_PLATFORM_MTP:
case HW_PLATFORM_SURF:
- dprintf(SPEW, "Target_cont_splash=0\n");
- ret = 0;
+ dprintf(SPEW, "Target_cont_splash=1\n");
+ ret = 1;
+ break;
default:
dprintf(SPEW, "Target_cont_splash=0\n");
ret = 0;
@@ -287,16 +293,21 @@
unsigned target_pause_for_battery_charge(void)
{
uint8_t pon_reason = pm8x41_get_pon_reason();
-
- /* This function will always return 0 to facilitate
- * automated testing/reboot with usb connected.
- * uncomment if this feature is needed.
+ uint8_t is_cold_boot = pm8x41_get_is_cold_boot();
+ dprintf(INFO, "%s : pon_reason is %d cold_boot:%d\n", __func__,
+ pon_reason, is_cold_boot);
+ /*In case of fastboot reboot, adb reboot or if we see the power key
+ * pressed we do not want go into charger mode.
+ * fastboot reboot is warm boot with PON hard reset bit not set
+ * adb reboot is a cold boot with PON hard reset bit set
*/
- /* if ((pon_reason == USB_CHG) || (pon_reason == DC_CHG))
- * return 1;
- */
-
- return 0;
+ if (is_cold_boot &&
+ (!(pon_reason & HARD_RST)) &&
+ (!(pon_reason & KPDPWR_N)) &&
+ ((pon_reason & USB_CHG) || (pon_reason & DC_CHG)))
+ return 1;
+ else
+ return 0;
}
void target_usb_stop(void)
diff --git a/target/msm8610/target_display.c b/target/msm8610/target_display.c
index 6316fa8..80d8316 100644
--- a/target/msm8610/target_display.c
+++ b/target/msm8610/target_display.c
@@ -166,11 +166,29 @@
void display_init(void)
{
uint32_t hw_id = board_hardware_id();
+ uint32_t platform_subtype = board_hardware_subtype();
dprintf(SPEW, "display_init(),target_id=%d.\n", hw_id);
+ dprintf(SPEW, "display_init(),platform_subtype=%d.\n",
+ platform_subtype);
switch (hw_id) {
case HW_PLATFORM_QRD:
+ if ((0 == platform_subtype) || (1 == platform_subtype))
+ mipi_hx8379a_video_wvga_init(&(panel.panel_info));
+ else if (3 == platform_subtype)
+ mipi_otm8018b_video_wvga_init(&(panel.panel_info));
+
+ panel.clk_func = msm8610_mdss_dsi_panel_clock;
+ panel.power_func = msm8610_mipi_panel_power;
+ panel.fb.base = MIPI_FB_ADDR;
+ panel.fb.width = panel.panel_info.xres;
+ panel.fb.height = panel.panel_info.yres;
+ panel.fb.stride = panel.panel_info.xres;
+ panel.fb.bpp = panel.panel_info.bpp;
+ panel.fb.format = FB_FORMAT_RGB888;
+ panel.mdp_rev = MDP_REV_304;
+ break;
case HW_PLATFORM_MTP:
case HW_PLATFORM_SURF:
mipi_truly_video_wvga_init(&(panel.panel_info));
diff --git a/target/msm8974/include/target/display.h b/target/msm8974/include/target/display.h
index 818011c..468b6d5 100644
--- a/target/msm8974/include/target/display.h
+++ b/target/msm8974/include/target/display.h
@@ -30,6 +30,7 @@
#define _TARGET_COPPER_DISPLAY_H
#define MIPI_FB_ADDR 0x0D200000
+#define EDP_FB_ADDR 0x7EF00000
#define MIPI_HSYNC_PULSE_WIDTH 12
#define MIPI_HSYNC_BACK_PORCH_DCLK 32
diff --git a/target/msm8974/init.c b/target/msm8974/init.c
index b5fbf82..6b1c61b 100644
--- a/target/msm8974/init.c
+++ b/target/msm8974/init.c
@@ -144,6 +144,9 @@
pm8x41_gpio_config(5, &gpio);
+ /* Wait for the pmic gpio config to take effect */
+ thread_sleep(1);
+
/* Get status of P_GPIO_5 */
pm8x41_gpio_get(5, &status);
@@ -613,6 +616,7 @@
case HW_PLATFORM_MTP:
case HW_PLATFORM_FLUID:
case HW_PLATFORM_DRAGON:
+ case HW_PLATFORM_LIQUID:
dprintf(SPEW, "Target_cont_splash=1\n");
return 1;
break;
diff --git a/target/msm8974/target_display.c b/target/msm8974/target_display.c
index d612015..10aefc7 100644
--- a/target/msm8974/target_display.c
+++ b/target/msm8974/target_display.c
@@ -46,9 +46,10 @@
extern int msm_display_off();
extern int mdss_dsi_uniphy_pll_config(uint32_t ctl_base);
extern int mdss_sharp_dsi_uniphy_pll_config(uint32_t ctl_base);
+extern void edp_auo_1080p_init(struct edp_panel_data *edp_panel);
static struct pm8x41_wled_data wled_ctrl = {
- .mod_scheme = 0xC3,
+ .mod_scheme = 0x00,
.led1_brightness = (0x0F << 8) | 0xEF,
.led2_brightness = (0x0F << 8) | 0xEF,
.led3_brightness = (0x0F << 8) | 0xEF,
@@ -200,6 +201,60 @@
return 0;
}
+static int msm8974_mdss_edp_panel_clock(int enable)
+{
+ if (enable) {
+ mdp_gdsc_ctrl(enable);
+ mdp_clock_init();
+ edp_clk_enable();
+ } else if (!target_cont_splash_screen()) {
+ /* Add here for continuous splash */
+ edp_clk_disable();
+ mdp_clock_disable();
+ mdp_gdsc_ctrl(enable);
+ }
+
+ return 0;
+}
+
+static int msm8974_edp_panel_power(int enable)
+{
+ struct pm8x41_gpio gpio36_param = {
+ .direction = PM_GPIO_DIR_OUT,
+ .output_buffer = PM_GPIO_OUT_CMOS,
+ .out_strength = PM_GPIO_OUT_DRIVE_MED,
+ };
+
+ struct pm8x41_ldo ldo12 = LDO(PM8x41_LDO12, PLDO_TYPE);
+
+ if (enable) {
+ /* Enable backlight */
+ dprintf(SPEW, "Enable Backlight\n");
+ pm8x41_gpio_config(36, &gpio36_param);
+ pm8x41_gpio_set(36, PM_GPIO_FUNC_HIGH);
+ dprintf(SPEW, "Enable Backlight Done\n");
+
+ /* Turn on LDO12 for edp vdda */
+ dprintf(SPEW, "Setting LDO12 n");
+ pm8x41_ldo_set_voltage(&ldo12, 1800000);
+ pm8x41_ldo_control(&ldo12, enable);
+ dprintf(SPEW, "Setting LDO12 Done\n");
+
+ /* Panel Enable */
+ dprintf(SPEW, "Panel Enable\n");
+ gpio_tlmm_config(58, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_8MA,
+ GPIO_DISABLE);
+ gpio_set(58, 2);
+ dprintf(SPEW, "Panel Enable Done\n");
+ } else {
+ /* Keep LDO12 on, otherwise kernel will not boot */
+ gpio_set(58, 0);
+ pm8x41_gpio_set(36, PM_GPIO_FUNC_LOW);
+ }
+
+ return 0;
+}
+
void display_init(void)
{
uint32_t hw_id = board_hardware_id();
@@ -224,8 +279,9 @@
break;
case HW_PLATFORM_DRAGON:
mipi_sharp_video_qhd_init(&(panel.panel_info));
- wled_ctrl.ovp = 0x1; /* 32V */
+ wled_ctrl.ovp = 0x0; /* 35V */
wled_ctrl.full_current_scale = 0x14; /* 20mA */
+ wled_ctrl.max_duty_cycle = 0; /* 26ns */
panel.clk_func = msm8974_mdss_sharp_dsi_panel_clock;
panel.power_func = msm8974_mipi_panel_power;
panel.fb.base = MIPI_FB_ADDR;
@@ -236,6 +292,14 @@
panel.fb.format = FB_FORMAT_RGB888;
panel.mdp_rev = MDP_REV_50;
break;
+ case HW_PLATFORM_LIQUID:
+ edp_panel_init(&(panel.panel_info));
+ panel.clk_func = msm8974_mdss_edp_panel_clock;
+ panel.power_func = msm8974_edp_panel_power;
+ panel.fb.base = (void *)EDP_FB_ADDR;
+ panel.fb.format = FB_FORMAT_RGB888;
+ panel.mdp_rev = MDP_REV_50;
+ break;
default:
return;
};