apq8084: enable usb30 support
Implements platform and target specific logic needed to enable
using dwc controller for usb30.
Change-Id: I33f049702f71acd68dfb1543e11dfd8bfcd300fd
diff --git a/platform/apq8084/acpuclock.c b/platform/apq8084/acpuclock.c
index 8c3f841..b785aa1 100644
--- a/platform/apq8084/acpuclock.c
+++ b/platform/apq8084/acpuclock.c
@@ -206,3 +206,36 @@
clock_ce_enable(instance);
}
+
+void clock_usb30_gdsc_enable(void)
+{
+ uint32_t reg = readl(GCC_USB30_GDSCR);
+
+ reg &= ~(0x1);
+
+ writel(reg, GCC_USB30_GDSCR);
+}
+
+/* enables usb30 interface and master clocks */
+void clock_usb30_init(void)
+{
+ int ret;
+
+ /* interface clock */
+ ret = clk_get_set_enable("usb30_iface_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_iface_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ clock_usb30_gdsc_enable();
+
+ /* master clock */
+ ret = clk_get_set_enable("usb30_master_clk", 125000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_master_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+}
diff --git a/platform/apq8084/apq8084-clock.c b/platform/apq8084/apq8084-clock.c
index c939bad..a353a15 100644
--- a/platform/apq8084/apq8084-clock.c
+++ b/platform/apq8084/apq8084-clock.c
@@ -281,6 +281,54 @@
},
};
+/* USB 3.0 Clocks */
+static struct clk_freq_tbl ftbl_gcc_usb30_master_clk[] =
+{
+ F(125000000, gpll0, 1, 5, 24),
+ F_END
+};
+
+static struct rcg_clk usb30_master_clk_src =
+{
+ .cmd_reg = (uint32_t *) GCC_USB30_MASTER_CMD_RCGR,
+ .cfg_reg = (uint32_t *) GCC_USB30_MASTER_CFG_RCGR,
+ .m_reg = (uint32_t *) GCC_USB30_MASTER_M,
+ .n_reg = (uint32_t *) GCC_USB30_MASTER_N,
+ .d_reg = (uint32_t *) GCC_USB30_MASTER_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_usb30_master_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "usb30_master_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+
+static struct branch_clk gcc_usb30_master_clk =
+{
+ .cbcr_reg = (uint32_t *) GCC_USB30_MASTER_CBCR,
+ .parent = &usb30_master_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_usb30_master_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_sys_noc_usb30_axi_clk =
+{
+ .cbcr_reg = (uint32_t *) SYS_NOC_USB3_AXI_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_sys_noc_usb3_axi_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
/* Clock lookup table */
static struct clk_lookup msm_clocks_8084[] =
{
@@ -292,6 +340,10 @@
CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c),
CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c),
+
+ /* USB 3.0 */
+ CLK_LOOKUP("usb30_iface_clk", gcc_sys_noc_usb30_axi_clk.c),
+ CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c),
};
void platform_clock_init(void)
diff --git a/platform/apq8084/include/platform/clock.h b/platform/apq8084/include/platform/clock.h
index bf63755..b620dd0 100644
--- a/platform/apq8084/include/platform/clock.h
+++ b/platform/apq8084/include/platform/clock.h
@@ -45,5 +45,6 @@
void mdp_clock_init(void);
void clock_ce_enable(uint8_t instance);
void clock_ce_disable(uint8_t instance);
+void clock_usb30_init(void);
#endif
diff --git a/platform/apq8084/include/platform/iomap.h b/platform/apq8084/include/platform/iomap.h
index d1ca7a9..7f47659 100644
--- a/platform/apq8084/include/platform/iomap.h
+++ b/platform/apq8084/include/platform/iomap.h
@@ -108,13 +108,36 @@
#define SDCC1_D (CLK_CTL_BASE + 0x4E0) /* d */
#define SDCC1_CDCCAL_SLEEP_CBCR (CLK_CTL_BASE + 0x4E4)
+/* USB 3.0 clocks */
+#define SYS_NOC_USB3_AXI_CBCR (CLK_CTL_BASE + 0x0108)
+
+#define GCC_USB_30_BCR (CLK_CTL_BASE + 0x03C0)
+#define GCC_USB_30_MISC (CLK_CTL_BASE + 0x03C4)
+
+#define GCC_USB30_MASTER_CBCR (CLK_CTL_BASE + 0x03C8)
+#define GCC_USB30_SLEEP_CBCR (CLK_CTL_BASE + 0x03CC)
+#define GCC_USB30_MOCK_UTMI_CBCR (CLK_CTL_BASE + 0x03D0)
+
+#define GCC_USB30_MASTER_CMD_RCGR (CLK_CTL_BASE + 0x03D4)
+#define GCC_USB30_MASTER_CFG_RCGR (CLK_CTL_BASE + 0x03D8)
+#define GCC_USB30_MASTER_M (CLK_CTL_BASE + 0x03DC)
+#define GCC_USB30_MASTER_N (CLK_CTL_BASE + 0x03E0)
+#define GCC_USB30_MASTER_D (CLK_CTL_BASE + 0x03E4)
+
+#define GCC_USB3_PHY_BCR (CLK_CTL_BASE + 0x03FC)
+#define GCC_USB30_GDSCR (CLK_CTL_BASE + 0x1E84)
+
+/* USB30 base */
+#define MSM_USB30_BASE 0xF9200000
+#define MSM_USB30_QSCRATCH_BASE 0xF92F8800
+
+
/* Addresses below this point needs to be verified.
* Included only for compilation purposes.
*/
#define MSM_USB_BASE (PERIPH_SS_BASE + 0x00255000)
#define CLK_CTL_BASE 0xFC400000
-
#define GCC_WDOG_DEBUG (CLK_CTL_BASE + 0x00001780)
#define USB_HS_BCR (CLK_CTL_BASE + 0x480)
@@ -128,6 +151,7 @@
#define MSM_CE2_BAM_BASE 0xFD444000
#define MSM_CE2_BASE 0xFD45A000
#define USB2_PHY_SEL 0xFD4AB000
+#define COPSS_USB_CONTROL_WITH_JDR 0xFD4AB204
#define TLMM_BASE_ADDR 0xFD510000
#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10)
diff --git a/platform/apq8084/include/platform/irqs.h b/platform/apq8084/include/platform/irqs.h
index 33e1a12..5a614d3 100644
--- a/platform/apq8084/include/platform/irqs.h
+++ b/platform/apq8084/include/platform/irqs.h
@@ -47,6 +47,7 @@
#define UFS_IRQ (GIC_SPI_START + 28)
+#define USB30_EE1_IRQ (GIC_SPI_START + 131)
#define USB1_HS_BAM_IRQ (GIC_SPI_START + 135)
#define USB1_HS_IRQ (GIC_SPI_START + 134)
#define USB2_IRQ (GIC_SPI_START + 141)