Merge "platform: msm_shared: Add support for socinfo v9"
diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
index 71c6128..7d774f4 100755
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -2,7 +2,7 @@
* Copyright (c) 2009, Google Inc.
* All rights reserved.
*
- * Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2009-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -65,7 +65,6 @@
#include "mmc.h"
#include "devinfo.h"
#include "board.h"
-
#include "scm.h"
extern bool target_use_signed_kernel(void);
@@ -95,7 +94,7 @@
/* make 4096 as default size to ensure EFS,EXT4's erasing */
#define DEFAULT_ERASE_SIZE 4096
-#define MAX_PANEL_BUF_SIZE 64
+#define MAX_PANEL_BUF_SIZE 128
static const char *emmc_cmdline = " androidboot.emmc=true";
static const char *usb_sn_cmdline = " androidboot.serialno=";
@@ -124,7 +123,7 @@
/* Assuming unauthorized kernel image by default */
static int auth_kernel_img = 0;
-static device_info device = {DEVICE_MAGIC, 0, 0, 0};
+static device_info device = {DEVICE_MAGIC, 0, 0, 0, 0};
struct atag_ptbl_entry
{
@@ -161,6 +160,7 @@
char charger_screen_enabled[MAX_RSP_SIZE];
char sn_buf[13];
char display_panel_buf[MAX_PANEL_BUF_SIZE];
+char panel_display_mode[MAX_RSP_SIZE];
extern int emmc_recovery_init(void);
@@ -521,6 +521,12 @@
/* Perform target specific cleanup */
target_uninit();
+ /* Turn off splash screen if enabled */
+#if DISPLAY_SPLASH_SCREEN
+ target_display_shutdown();
+#endif
+
+
dprintf(INFO, "booting linux @ %p, ramdisk @ %p (%d), tags/device tree @ %p\n",
entry, ramdisk, ramdisk_size, tags_phys);
@@ -1454,7 +1460,7 @@
check_aboot_addr_range_overlap(hdr->ramdisk_addr, ramdisk_actual))
{
dprintf(CRITICAL, "kernel/ramdisk addresses overlap with aboot addresses.\n");
- return -1;
+ return;
}
/* sz should have atleast raw boot image */
@@ -1472,7 +1478,7 @@
if (check_aboot_addr_range_overlap(hdr->tags_addr, MAX_TAGS_SIZE))
{
dprintf(CRITICAL, "Tags addresses overlap with aboot addresses.\n");
- return -1;
+ return;
}
#endif
@@ -1502,7 +1508,7 @@
if (check_aboot_addr_range_overlap(hdr->tags_addr, MAX_TAGS_SIZE))
{
dprintf(CRITICAL, "Tags addresses overlap with aboot addresses.\n");
- return -1;
+ return;
}
#endif
@@ -1914,6 +1920,16 @@
fastboot_okay("");
}
+void cmd_oem_select_display_panel(const char *arg, void *data, unsigned size)
+{
+ dprintf(INFO, "Selecting display panel %s\n", arg);
+ if (arg)
+ strlcpy(device.display_panel, arg,
+ sizeof(device.display_panel));
+ write_device_info(&device);
+ fastboot_okay("");
+}
+
void cmd_oem_unlock(const char *arg, void *data, unsigned sz)
{
if(!device.is_unlocked)
@@ -1926,13 +1942,15 @@
void cmd_oem_devinfo(const char *arg, void *data, unsigned sz)
{
- char response[64];
+ char response[128];
snprintf(response, sizeof(response), "\tDevice tampered: %s", (device.is_tampered ? "true" : "false"));
fastboot_info(response);
snprintf(response, sizeof(response), "\tDevice unlocked: %s", (device.is_unlocked ? "true" : "false"));
fastboot_info(response);
snprintf(response, sizeof(response), "\tCharger screen enabled: %s", (device.charger_screen_enabled ? "true" : "false"));
fastboot_info(response);
+ snprintf(response, sizeof(response), "\tDisplay panel: %s", (device.display_panel));
+ fastboot_info(response);
fastboot_okay("");
}
@@ -2145,6 +2163,8 @@
cmd_oem_enable_charger_screen);
fastboot_register("oem disable-charger-screen",
cmd_oem_disable_charger_screen);
+ fastboot_register("oem select-display-panel",
+ cmd_oem_select_display_panel);
/* publish variables and their values */
fastboot_publish("product", TARGET(BOARD));
fastboot_publish("kernel", "lk");
@@ -2168,6 +2188,10 @@
device.charger_screen_enabled);
fastboot_publish("charger-screen-enabled",
(const char *) charger_screen_enabled);
+ snprintf(panel_display_mode, MAX_RSP_SIZE, "%s",
+ device.display_panel);
+ fastboot_publish("display-panel",
+ (const char *) panel_display_mode);
}
void aboot_init(const struct app_descriptor *app)
@@ -2191,6 +2215,14 @@
read_device_info(&device);
+ /* Display splash screen if enabled */
+#if DISPLAY_SPLASH_SCREEN
+ dprintf(SPEW, "Display Init: Start\n");
+ target_display_init(device.display_panel);
+ dprintf(SPEW, "Display Init: Done\n");
+#endif
+
+
target_serialno((unsigned char *) sn_buf);
dprintf(SPEW,"serial number: %s\n",sn_buf);
diff --git a/app/aboot/devinfo.h b/app/aboot/devinfo.h
index 558aaf9..a0d8743 100644
--- a/app/aboot/devinfo.h
+++ b/app/aboot/devinfo.h
@@ -1,5 +1,5 @@
/*
- * * Copyright (c) 2011, The Linux Foundation. All rights reserved.
+ * * Copyright (c) 2011,2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -34,6 +34,7 @@
#define DEVICE_MAGIC "ANDROID-BOOT!"
#define DEVICE_MAGIC_SIZE 13
+#define MAX_PANEL_ID_LEN 64
struct device_info
{
@@ -41,6 +42,7 @@
bool is_unlocked;
bool is_tampered;
bool charger_screen_enabled;
+ char display_panel[MAX_PANEL_ID_LEN];
};
#endif
diff --git a/dev/gcdb/display/gcdb_display.c b/dev/gcdb/display/gcdb_display.c
index 6167d07..4a15406 100755
--- a/dev/gcdb/display/gcdb_display.c
+++ b/dev/gcdb/display/gcdb_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -59,17 +59,9 @@
extern int msm_display_init(struct msm_fb_panel_data *pdata);
extern int msm_display_off();
-/* TODO: add other backlight type support */
static uint32_t panel_backlight_ctrl(uint8_t enable)
{
- uint32_t ret = NO_ERROR;
-
- if (panelstruct.backlightinfo->bl_pmic_controltype != BL_DCS) {
- /* deal with non-dcs backlight */
- ret = target_backlight_ctrl(enable);
- }
-
- return ret;
+ return target_backlight_ctrl(panelstruct.backlightinfo, enable);
}
static uint32_t mdss_dsi_panel_reset(uint8_t enable)
@@ -135,6 +127,25 @@
return ret;
}
+static int mdss_dsi_panel_pre_init(void)
+{
+ int ret = NO_ERROR;
+
+ if (panelstruct.paneldata->panel_lp11_init) {
+ ret = mdss_dsi_panel_reset(1);
+ if (ret) {
+ dprintf(CRITICAL, "panel reset failed\n");
+ return ret;
+ }
+ }
+
+ if(panelstruct.paneldata->panel_init_delay)
+ udelay(panelstruct.paneldata->panel_init_delay);
+
+ dprintf(SPEW, "Panel pre init done\n");
+ return ret;
+}
+
static int mdss_dsi_bl_enable(uint8_t enable)
{
int ret = NO_ERROR;
@@ -150,14 +161,20 @@
{
char *dsi_id = NULL;
char *panel_node = NULL;
- uint16_t dsi_id_len = 0;
+ char *slave_panel_node = NULL;
+ uint16_t dsi_id_len = 0, panel_node_len = 0, slave_panel_node_len = 0;
+ uint32_t arg_size = 0;
bool ret = true;
char *default_str;
+ int panel_mode = SPLIT_DISPLAY_FLAG | DUAL_PIPE_FLAG;
if(panelstruct.paneldata)
{
dsi_id = panelstruct.paneldata->panel_controller;
panel_node = panelstruct.paneldata->panel_node_id;
+ panel_mode = panelstruct.paneldata->panel_operating_mode &
+ panel_mode;
+ slave_panel_node = panelstruct.paneldata->slave_panel_node_id;
}
else
{
@@ -173,32 +190,57 @@
return true;
}
- if (dsi_id == NULL || panel_node == NULL)
+ if (dsi_id == NULL || panel_node == NULL) {
+ dprintf(CRITICAL, "panel node or dsi ctrl not present\n");
return false;
+ }
+
+ if (panel_mode && slave_panel_node == NULL) {
+ dprintf(CRITICAL, "slave node not present in dual dsi case\n");
+ return false;
+ }
dsi_id_len = strlen(dsi_id);
+ panel_node_len = strlen(panel_node);
+ slave_panel_node_len = strlen(slave_panel_node);
- if (buf_size < (strlen(panel_node) + dsi_id_len +
- MAX_PANEL_FORMAT_STRING + 1) ||
- !strlen(panel_node) ||
- !strlen(dsi_id))
+ arg_size = dsi_id_len + panel_node_len + LK_OVERRIDE_PANEL_LEN + 1;
+
+ /* For dual pipe or split display */
+ if (panel_mode)
+ arg_size += DSI_1_STRING_LEN + slave_panel_node_len;
+
+ if (buf_size < arg_size)
{
+ dprintf(CRITICAL, "display command line buffer is small\n");
ret = false;
}
else
{
- pbuf[0] = '1'; // 1 indicates that LK is overriding the panel
- pbuf[1] = ':'; // seperator
- pbuf += MAX_PANEL_FORMAT_STRING;
- buf_size -= MAX_PANEL_FORMAT_STRING;
+ strlcpy(pbuf, LK_OVERRIDE_PANEL, buf_size);
+ pbuf += LK_OVERRIDE_PANEL_LEN;
+ buf_size -= LK_OVERRIDE_PANEL_LEN;
strlcpy(pbuf, dsi_id, buf_size);
pbuf += dsi_id_len;
buf_size -= dsi_id_len;
strlcpy(pbuf, panel_node, buf_size);
- ret = true;
+
+ /* Return string for single dsi */
+ if (!panel_mode)
+ goto end;
+
+ pbuf += panel_node_len;
+ buf_size -= panel_node_len;
+
+ strlcpy(pbuf, DSI_1_STRING, buf_size);
+ pbuf += DSI_1_STRING_LEN;
+ buf_size -= DSI_1_STRING_LEN;
+
+ strlcpy(pbuf, slave_panel_node, buf_size);
}
+end:
return ret;
}
@@ -215,11 +257,11 @@
memcpy(dsi_video_mode_phy_db.laneCfg, panel_lane_config, LANE_SIZE);
}
-int gcdb_display_init(uint32_t rev, void *base)
+int gcdb_display_init(const char *panel_name, uint32_t rev, void *base)
{
int ret = NO_ERROR;
- if (!oem_panel_select(&panelstruct, &(panel.panel_info),
+ if (!oem_panel_select(panel_name, &panelstruct, &(panel.panel_info),
&dsi_video_mode_phy_db)) {
dprintf(CRITICAL, "Target panel init not found!\n");
ret = ERR_NOT_SUPPORTED;
@@ -237,6 +279,7 @@
panel.pll_clk_func = mdss_dsi_panel_clock;
panel.power_func = mdss_dsi_panel_power;
+ panel.pre_init_func = mdss_dsi_panel_pre_init;
panel.bl_func = mdss_dsi_bl_enable;
panel.fb.base = base;
panel.fb.width = panel.panel_info.xres;
diff --git a/dev/gcdb/display/gcdb_display.h b/dev/gcdb/display/gcdb_display.h
index 4811015..b2fb974 100755
--- a/dev/gcdb/display/gcdb_display.h
+++ b/dev/gcdb/display/gcdb_display.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -43,19 +43,22 @@
#define BIST_SIZE 6
#define LANE_SIZE 45
-#define MAX_PANEL_FORMAT_STRING 2
+#define LK_OVERRIDE_PANEL "1:"
+#define LK_OVERRIDE_PANEL_LEN 2
+#define DSI_1_STRING ":1:"
+#define DSI_1_STRING_LEN 3
/*---------------------------------------------------------------------------*/
/* API */
/*---------------------------------------------------------------------------*/
-int target_backlight_ctrl(uint8_t enable);
+int target_backlight_ctrl(struct backlight *bl, uint8_t enable);
int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo);
int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
struct msm_panel_info *pinfo);
int target_ldo_ctrl(uint8_t enable);
-int gcdb_display_init(uint32_t rev, void *base);
+int gcdb_display_init(const char *panel_name, uint32_t rev, void *base);
void gcdb_display_shutdown();
#endif /*_GCDB_DISPLAY_H_ */
diff --git a/dev/gcdb/display/include/panel.h b/dev/gcdb/display/include/panel.h
index f7f1f7f..0350885 100755
--- a/dev/gcdb/display/include/panel.h
+++ b/dev/gcdb/display/include/panel.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -57,14 +57,15 @@
uint16_t panel_channelid;
uint16_t dsi_virtualchannel_id;
uint16_t panel_broadcast_mode;
- uint16_t dsi_lp11_atinit;
- uint16_t dsi_initmaster_time;
+ uint16_t panel_lp11_init;
+ uint16_t panel_init_delay;
uint16_t dsi_stream;
uint8_t interleave_mode;
uint32_t panel_bitclock_freq;
uint32_t panel_operating_mode;
uint32_t panel_with_enable_gpio;
uint8_t mode_gpio_state;
+ char *slave_panel_node_id;
};
typedef struct panel_resolution{
@@ -150,7 +151,6 @@
BL_PWM = 0,
BL_WLED,
BL_DCS,
- BL_LPG,
};
typedef struct panel_reset_sequence {
diff --git a/dev/gcdb/display/include/panel_jdi_qhd_dualdsi_cmd.h b/dev/gcdb/display/include/panel_jdi_qhd_dualdsi_cmd.h
new file mode 100644
index 0000000..2f05288
--- /dev/null
+++ b/dev/gcdb/display/include/panel_jdi_qhd_dualdsi_cmd.h
@@ -0,0 +1,216 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PANEL_JDI_QHD_DUALDSI_CMD_H_
+#define _PANEL_JDI_QHD_DUALDSI_CMD_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+static struct panel_config jdi_qhd_dualdsi_cmd_panel_data = {
+ "qcom,mdss_dsi_jdi_qhd_dualmipi0_cmd", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 1, "DISPLAY_1", 0, 0, 60, 0, 0, 1, 0, 0, 0, 0, 0, 11, 0, 0,
+ "qcom,mdss_dsi_jdi_qhd_dualmipi1_cmd"
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution jdi_qhd_dualdsi_cmd_panel_res = {
+ 2560, 1440, 120, 44, 16, 0, 8, 4, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel color information */
+/*---------------------------------------------------------------------------*/
+static struct color_info jdi_qhd_dualdsi_cmd_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel on/off command information */
+/*---------------------------------------------------------------------------*/
+static char jdi_qhd_dualdsi_cmd_on_cmd0[] = {
+ 0x01, 0x00, 0x05, 0x80
+};
+
+static char jdi_qhd_dualdsi_cmd_on_cmd1[] = {
+ 0x3a, 0x77, 0x15, 0x80
+};
+
+static char jdi_qhd_dualdsi_cmd_on_cmd2[] = {
+ 0x05, 0x00, 0x39, 0xC0,
+ 0x2a, 0x00, 0x00, 0x04,
+ 0xff, 0xFF, 0xFF, 0xFF,
+};
+
+static char jdi_qhd_dualdsi_cmd_on_cmd3[] = {
+ 0x05, 0x00, 0x39, 0xC0,
+ 0x2b, 0x00, 0x00, 0x05,
+ 0x9f, 0xFF, 0xFF, 0xFF,
+};
+
+static char jdi_qhd_dualdsi_cmd_on_cmd4[] = {
+ 0x51, 0xff, 0x15, 0x80
+};
+
+static char jdi_qhd_dualdsi_cmd_on_cmd5[] = {
+ 0x11, 0x00, 0x05, 0x80
+};
+
+static char jdi_qhd_dualdsi_cmd_on_cmd6[] = {
+ 0xb0, 0x00, 0x23, 0x80
+};
+
+static char jdi_qhd_dualdsi_cmd_on_cmd7[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xb3, 0x0c, 0xFF, 0xFF,
+};
+
+static char jdi_qhd_dualdsi_cmd_on_cmd8[] = {
+ 0x14, 0x00, 0x29, 0xC0,
+ 0xce, 0x7d, 0x40, 0x48,
+ 0x56, 0x67, 0x78, 0x88,
+ 0x98, 0xa7, 0xb5, 0xc3,
+ 0xd1, 0xde, 0xe9, 0xf2,
+ 0xfa, 0xff, 0x04, 0x00,
+};
+
+static char jdi_qhd_dualdsi_cmd_on_cmd9[] = {
+ 0xb0, 0x03, 0x23, 0x80
+};
+
+static char jdi_qhd_dualdsi_cmd_on_cmd10[] = {
+ 0x29, 0x00, 0x05, 0x80
+};
+
+static char jdi_qhd_dualdsi_cmd_on_cmd11[] = {
+ 0x35, 0x00, 0x15, 0x80
+};
+
+static char jdi_qhd_dualdsi_cmd_on_cmd12[] = {
+ 0x53, 0x24, 0x15, 0x80
+};
+
+static struct mipi_dsi_cmd jdi_qhd_dualdsi_cmd_on_command[] = {
+ {0x4, jdi_qhd_dualdsi_cmd_on_cmd0, 0x05},
+ {0x4, jdi_qhd_dualdsi_cmd_on_cmd1, 0x05},
+ {0xc, jdi_qhd_dualdsi_cmd_on_cmd2, 0x05},
+ {0xc, jdi_qhd_dualdsi_cmd_on_cmd3, 0x05},
+ {0x4, jdi_qhd_dualdsi_cmd_on_cmd4, 0x05},
+ {0x4, jdi_qhd_dualdsi_cmd_on_cmd5, 0x78},
+ {0x4, jdi_qhd_dualdsi_cmd_on_cmd6, 0x05},
+ {0x8, jdi_qhd_dualdsi_cmd_on_cmd7, 0x05},
+ {0x18, jdi_qhd_dualdsi_cmd_on_cmd8, 0x05},
+ {0x4, jdi_qhd_dualdsi_cmd_on_cmd9, 0x05},
+ {0x4, jdi_qhd_dualdsi_cmd_on_cmd10, 0x14},
+ {0x4, jdi_qhd_dualdsi_cmd_on_cmd11, 0x05},
+ {0x4, jdi_qhd_dualdsi_cmd_on_cmd12, 0x05},
+};
+
+#define JDI_QHD_DUALDSI_CMD_ON_COMMAND 13
+
+
+static char jdi_qhd_dualdsi_cmdoff_cmd0[] = {
+ 0x28, 0x00, 0x05, 0x80
+};
+
+static char jdi_qhd_dualdsi_cmdoff_cmd1[] = {
+ 0x10, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd jdi_qhd_dualdsi_cmd_off_command[] = {
+ {0x4, jdi_qhd_dualdsi_cmdoff_cmd0, 0x32},
+ {0x4, jdi_qhd_dualdsi_cmdoff_cmd1, 0x78}
+};
+
+#define JDI_QHD_DUALDSI_CMD_OFF_COMMAND 2
+
+
+static struct command_state jdi_qhd_dualdsi_cmd_state = {
+ 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct commandpanel_info jdi_qhd_dualdsi_cmd_command_panel = {
+ 1, 1, 1, 0, 0, 0x2c, 0, 0, 0, 1, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct videopanel_info jdi_qhd_dualdsi_cmd_video_panel = {
+ 0, 0, 0, 0, 1, 1, 1, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane configuration */
+/*---------------------------------------------------------------------------*/
+static struct lane_configuration jdi_qhd_dualdsi_cmd_lane_config = {
+ 4, 0, 1, 1, 1, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel timing */
+/*---------------------------------------------------------------------------*/
+static const uint32_t jdi_qhd_dualdsi_cmd_timings[] = {
+ 0xcd, 0x32, 0x22, 0x00, 0x60, 0x64, 0x26, 0x34, 0x29, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing jdi_qhd_dualdsi_cmd_timing_info = {
+ 0x0, 0x04, 0x03, 0x27
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel reset sequence */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence jdi_qhd_dualdsi_cmd_reset_seq = {
+ {1, 0, 1, }, {20, 200, 20, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight setting */
+/*---------------------------------------------------------------------------*/
+static struct backlight jdi_qhd_dualdsi_cmd_backlight = {
+ 0, 1, 4095, 100, 1, "PMIC_8941"
+};
+
+#endif /*_PANEL_JDI_QHD_DUALDSI_CMD_H_*/
diff --git a/dev/gcdb/display/include/panel_jdi_qhd_dualdsi_video.h b/dev/gcdb/display/include/panel_jdi_qhd_dualdsi_video.h
index cd0301c..cfdd490 100644
--- a/dev/gcdb/display/include/panel_jdi_qhd_dualdsi_video.h
+++ b/dev/gcdb/display/include/panel_jdi_qhd_dualdsi_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -44,8 +44,9 @@
/* Panel configuration */
/*---------------------------------------------------------------------------*/
static struct panel_config jdi_qhd_dualdsi_video_panel_data = {
- "", "", "qcom,mdss-dsi-panel",
- 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 1, 0, 0, 0, 0, 0, 11, 0
+ "qcom,dsi_jdi_qhd_video_0", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 1, 0, 0, 0, 0, 0, 11, 0, 0,
+ "qcom,dsi_jdi_qhd_video_1",
};
/*---------------------------------------------------------------------------*/
@@ -220,7 +221,7 @@
/* Backlight setting */
/*---------------------------------------------------------------------------*/
static struct backlight jdi_qhd_dualdsi_video_backlight = {
- 0, 1, 4095, 100, 0, 0
+ 0, 1, 4095, 100, 1, "PMIC_8941"
};
#endif /*_PANEL_JDI_QHD_DUALDSI_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_ssd2080m_720p_video.h b/dev/gcdb/display/include/panel_ssd2080m_720p_video.h
old mode 100755
new mode 100644
index 018afc3..8533821
--- a/dev/gcdb/display/include/panel_ssd2080m_720p_video.h
+++ b/dev/gcdb/display/include/panel_ssd2080m_720p_video.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -34,7 +34,6 @@
*---------------------------------------------------------------------------*/
#ifndef _PANEL_SSD2080M_720P_VIDEO_H_
-
#define _PANEL_SSD2080M_720P_VIDEO_H_
/*---------------------------------------------------------------------------*/
/* HEADER files */
@@ -44,449 +43,446 @@
/*---------------------------------------------------------------------------*/
/* Panel configuration */
/*---------------------------------------------------------------------------*/
-
static struct panel_config ssd2080m_720p_video_panel_data = {
- "qcom,mdss_dsi_ssd2080m_720p_video", "dsi:0:", "qcom,mdss-dsi-panel",
- 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+ "qcom,mdss_dsi_ssd2080m_720p_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 1, 50000, 0, 0, 0, 0, 0, 0
};
/*---------------------------------------------------------------------------*/
/* Panel resolution */
/*---------------------------------------------------------------------------*/
static struct panel_resolution ssd2080m_720p_video_panel_res = {
- 720, 1280, 80, 24, 14, 0, 11, 14, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0
+ 720, 1280, 80, 24, 14, 0, 25, 14, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0
};
/*---------------------------------------------------------------------------*/
-/* Panel Color Information */
+/* Panel color information */
/*---------------------------------------------------------------------------*/
static struct color_info ssd2080m_720p_video_color = {
- 24, 0, 0xff, 0, 0, 0
+ 24, 0, 0xff, 0, 0, 0
};
/*---------------------------------------------------------------------------*/
-/* Panel Command information */
+/* Panel on/off command information */
/*---------------------------------------------------------------------------*/
static char ssd2080m_720p_video_on_cmd0[] = {
-0xFF, 0x01, 0x15, 0x80 };
-
+ 0xFF, 0x01, 0x15, 0x80
+};
static char ssd2080m_720p_video_on_cmd1[] = {
-0x05, 0x00, 0x29, 0xC0,
-0xC6, 0x63, 0x00, 0x81,
-0x31, 0xFF, 0xFF, 0xFF, };
-
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x53, 0x00, 0xFF, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd2[] = {
-0x05, 0x00, 0x29, 0xC0,
-0xCB, 0xE7, 0x80, 0x73,
-0x33, 0xFF, 0xFF, 0xFF, };
-
+ 0x05, 0x00, 0x29, 0xC0,
+ 0xC6, 0x63, 0x00, 0x81,
+ 0x31, 0xFF, 0xFF, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd3[] = {
-0x02, 0x00, 0x29, 0xC0,
-0xEC, 0xD2, 0xFF, 0xFF, };
-
+ 0x05, 0x00, 0x29, 0xC0,
+ 0xCB, 0xE7, 0x80, 0x73,
+ 0x33, 0xFF, 0xFF, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd4[] = {
-0x03, 0x00, 0x29, 0xC0,
-0xB3, 0x04, 0x9F, 0xFF, };
-
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xEC, 0xD2, 0xFF, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd5[] = {
-0x04, 0x00, 0x29, 0xC0,
-0xB2, 0x16, 0x1E, 0x10,
- };
-
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB3, 0x04, 0x9F, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd6[] = {
-0x02, 0x00, 0x29, 0xC0,
-0xB4, 0x00, 0xFF, 0xFF, };
-
+ 0x04, 0x00, 0x29, 0xC0,
+ 0xB2, 0x16, 0x26, 0x10,
+};
static char ssd2080m_720p_video_on_cmd7[] = {
-0x02, 0x00, 0x29, 0xC0,
-0xC1, 0x04, 0xFF, 0xFF, };
-
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xB4, 0x00, 0xFF, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd8[] = {
-0x04, 0x00, 0x29, 0xC0,
-0xC2, 0xBE, 0x00, 0x58,
- };
-
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xC1, 0x04, 0xFF, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd9[] = {
-0x09, 0x00, 0x29, 0xC0,
-0xC3, 0x01, 0x22, 0x11,
-0x21, 0x0E, 0x80, 0x80,
-0x24, 0xFF, 0xFF, 0xFF, };
-
+ 0x04, 0x00, 0x29, 0xC0,
+ 0xC2, 0xBE, 0x00, 0x58,
+};
static char ssd2080m_720p_video_on_cmd10[] = {
-0x08, 0x00, 0x29, 0xC0,
-0xB6, 0x09, 0x16, 0x42,
-0x01, 0x13, 0x00, 0x00,
- };
-
+ 0x09, 0x00, 0x29, 0xC0,
+ 0xC3, 0x01, 0x22, 0x11,
+ 0x21, 0x0E, 0x80, 0x80,
+ 0x24, 0xFF, 0xFF, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd11[] = {
-0x04, 0x00, 0x29, 0xC0,
-0xB7, 0x24, 0x26, 0x43,
- };
-
+ 0x08, 0x00, 0x29, 0xC0,
+ 0xB6, 0x09, 0x16, 0x42,
+ 0x01, 0x13, 0x00, 0x00,
+};
static char ssd2080m_720p_video_on_cmd12[] = {
-0x06, 0x00, 0x29, 0xC0,
-0xB8, 0x16, 0x08, 0x25,
-0x44, 0x08, 0xFF, 0xFF, };
-
+ 0x04, 0x00, 0x29, 0xC0,
+ 0xB7, 0x24, 0x26, 0x43,
+};
static char ssd2080m_720p_video_on_cmd13[] = {
-0x09, 0x00, 0x29, 0xC0,
-0xB9, 0x06, 0x08, 0x07,
-0x09, 0x00, 0x00, 0x00,
-0x00, 0xFF, 0xFF, 0xFF, };
-
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xB8, 0x16, 0x08, 0x25,
+ 0x44, 0x08, 0xFF, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd14[] = {
-0x09, 0x00, 0x29, 0xC0,
-0xBA, 0x0E, 0x10, 0x0A,
-0x0C, 0x16, 0x05, 0x00,
-0x00, 0xFF, 0xFF, 0xFF, };
-
+ 0x09, 0x00, 0x29, 0xC0,
+ 0xB9, 0x06, 0x08, 0x07,
+ 0x09, 0x00, 0x00, 0x00,
+ 0x00, 0xFF, 0xFF, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd15[] = {
-0x09, 0x00, 0x29, 0xC0,
-0xBB, 0xA1, 0xA1, 0xA1,
-0xA1, 0x00, 0x00, 0x00,
-0x00, 0xFF, 0xFF, 0xFF, };
-
+ 0x09, 0x00, 0x29, 0xC0,
+ 0xBA, 0x0E, 0x10, 0x0A,
+ 0x0C, 0x16, 0x05, 0x00,
+ 0x00, 0xFF, 0xFF, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd16[] = {
-0x09, 0x00, 0x29, 0xC0,
-0xBC, 0x0F, 0x11, 0x0B,
-0x0D, 0x16, 0x05, 0x00,
-0x00, 0xFF, 0xFF, 0xFF, };
-
+ 0x09, 0x00, 0x29, 0xC0,
+ 0xBB, 0xA1, 0xA1, 0xA1,
+ 0xA1, 0x00, 0x00, 0x00,
+ 0x00, 0xFF, 0xFF, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd17[] = {
-0x09, 0x00, 0x29, 0xC0,
-0xBD, 0xA1, 0xA1, 0xA1,
-0xA1, 0x00, 0x00, 0x00,
-0x00, 0xFF, 0xFF, 0xFF, };
-
+ 0x09, 0x00, 0x29, 0xC0,
+ 0xBC, 0x0F, 0x11, 0x0B,
+ 0x0D, 0x16, 0x05, 0x00,
+ 0x00, 0xFF, 0xFF, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd18[] = {
-0x04, 0x00, 0x29, 0xC0,
-0xE6, 0xFF, 0xFF, 0x0F,
- };
-
+ 0x09, 0x00, 0x29, 0xC0,
+ 0xBD, 0xA1, 0xA1, 0xA1,
+ 0xA1, 0x00, 0x00, 0x00,
+ 0x00, 0xFF, 0xFF, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd19[] = {
-0x02, 0x00, 0x29, 0xC0,
-0xC7, 0x3F, 0xFF, 0xFF, };
-
+ 0x04, 0x00, 0x29, 0xC0,
+ 0xE6, 0xFF, 0xFF, 0x0F,
+};
static char ssd2080m_720p_video_on_cmd20[] = {
-0x07, 0x00, 0x29, 0xC0,
-0xB5, 0x47, 0x00, 0x00,
-0x08, 0x00, 0x01, 0xFF, };
-
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xC7, 0x3F, 0xFF, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd21[] = {
-0x08, 0x00, 0x29, 0xC0,
-0xC4, 0xDF, 0x72, 0x12,
-0x12, 0x66, 0xE3, 0x99,
- };
-
+ 0x07, 0x00, 0x29, 0xC0,
+ 0xB5, 0x47, 0x00, 0x00,
+ 0x08, 0x00, 0x01, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd22[] = {
-0x07, 0x00, 0x29, 0xC0,
-0xD0, 0x0A, 0x00, 0x0D,
-0x15, 0x1F, 0x2E, 0xFF, };
-
+ 0x08, 0x00, 0x29, 0xC0,
+ 0xC4, 0xDF, 0xC2, 0x0C,
+ 0x0C, 0x63, 0xE3, 0x99,
+};
static char ssd2080m_720p_video_on_cmd23[] = {
-0x06, 0x00, 0x29, 0xC0,
-0xD1, 0x28, 0x27, 0x14,
-0x02, 0x01, 0xFF, 0xFF, };
-
+ 0x07, 0x00, 0x29, 0xC0,
+ 0xD0, 0x0A, 0x00, 0x06,
+ 0x09, 0x10, 0x20, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd24[] = {
-0x07, 0x00, 0x29, 0xC0,
-0xD2, 0x0A, 0x00, 0x0D,
-0x15, 0x1F, 0x2E, 0xFF, };
-
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xD1, 0x1D, 0x32, 0x1B,
+ 0x00, 0x00, 0xFF, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd25[] = {
-0x06, 0x00, 0x29, 0xC0,
-0xD3, 0x28, 0x27, 0x14,
-0x02, 0x01, 0xFF, 0xFF, };
-
+ 0x07, 0x00, 0x29, 0xC0,
+ 0xD2, 0x0A, 0x00, 0x06,
+ 0x09, 0x10, 0x20, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd26[] = {
-0x07, 0x00, 0x29, 0xC0,
-0xD4, 0x0A, 0x00, 0x0D,
-0x15, 0x1F, 0x2E, 0xFF, };
-
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xD3, 0x1D, 0x32, 0x1B,
+ 0x00, 0x00, 0xFF, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd27[] = {
-0x06, 0x00, 0x29, 0xC0,
-0xD5, 0x28, 0x27, 0x14,
-0x02, 0x01, 0xFF, 0xFF, };
-
+ 0x07, 0x00, 0x29, 0xC0,
+ 0xD4, 0x0A, 0x00, 0x06,
+ 0x09, 0x10, 0x20, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd28[] = {
-0x07, 0x00, 0x29, 0xC0,
-0xD6, 0x0A, 0x00, 0x0D,
-0x15, 0x1F, 0x2E, 0xFF, };
-
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xD5, 0x1D, 0x32, 0x1B,
+ 0x00, 0x00, 0xFF, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd29[] = {
-0x06, 0x00, 0x29, 0xC0,
-0xD7, 0x28, 0x27, 0x14,
-0x02, 0x01, 0xFF, 0xFF, };
-
+ 0x07, 0x00, 0x29, 0xC0,
+ 0xD6, 0x0A, 0x00, 0x06,
+ 0x09, 0x10, 0x20, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd30[] = {
-0x07, 0x00, 0x29, 0xC0,
-0xD8, 0x0A, 0x00, 0x0D,
-0x15, 0x1F, 0x2E, 0xFF, };
-
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xD7, 0x1D, 0x32, 0x1B,
+ 0x00, 0x00, 0xFF, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd31[] = {
-0x06, 0x00, 0x29, 0xC0,
-0xD9, 0x28, 0x27, 0x14,
-0x02, 0x01, 0xFF, 0xFF, };
-
+ 0x07, 0x00, 0x29, 0xC0,
+ 0xD8, 0x0A, 0x00, 0x06,
+ 0x09, 0x10, 0x20, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd32[] = {
-0x07, 0x00, 0x29, 0xC0,
-0xDA, 0x0A, 0x00, 0x0D,
-0x15, 0x1F, 0x2E, 0xFF, };
-
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xD9, 0x1D, 0x32, 0x1B,
+ 0x00, 0x00, 0xFF, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd33[] = {
-0x06, 0x00, 0x29, 0xC0,
-0xDB, 0x28, 0x27, 0x14,
-0x02, 0x01, 0xFF, 0xFF, };
-
+ 0x07, 0x00, 0x29, 0xC0,
+ 0xDA, 0x0A, 0x00, 0x06,
+ 0x09, 0x10, 0x20, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd34[] = {
-0x03, 0x00, 0x29, 0xC0,
-0xCC, 0x10, 0x00, 0xFF, };
-
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xDB, 0x1D, 0x32, 0x1B,
+ 0x00, 0x00, 0xFF, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd35[] = {
-0x04, 0x00, 0x29, 0xC0,
-0xCE, 0x4E, 0x55, 0xA5,
- };
-
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xCC, 0x10, 0x00, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd36[] = {
-0x04, 0x00, 0x29, 0xC0,
-0xE0, 0x01, 0x02, 0x02,
- };
-
+ 0x04, 0x00, 0x29, 0xC0,
+ 0xCE, 0x4E, 0x55, 0xA5,
+};
static char ssd2080m_720p_video_on_cmd37[] = {
-0x05, 0x00, 0x29, 0xC0,
-0xF6, 0x00, 0x00, 0x00,
-0x00, 0xFF, 0xFF, 0xFF, };
-
+ 0x04, 0x00, 0x29, 0xC0,
+ 0xE0, 0x01, 0x02, 0x02,
+};
static char ssd2080m_720p_video_on_cmd38[] = {
-0x05, 0x00, 0x29, 0xC0,
-0xF7, 0x00, 0x00, 0x00,
-0x00, 0xFF, 0xFF, 0xFF, };
-
+ 0x05, 0x00, 0x29, 0xC0,
+ 0xF6, 0x00, 0x00, 0x00,
+ 0x00, 0xFF, 0xFF, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd39[] = {
-0x03, 0x00, 0x29, 0xC0,
-0xE1, 0x90, 0x00, 0xFF, };
-
+ 0x05, 0x00, 0x29, 0xC0,
+ 0xF7, 0x00, 0x00, 0x00,
+ 0x00, 0xFF, 0xFF, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd40[] = {
-0x03, 0x00, 0x29, 0xC0,
-0xDE, 0x95, 0xCF, 0xFF, };
-
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xE1, 0x90, 0x00, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd41[] = {
-0x02, 0x00, 0x29, 0xC0,
-0xCF, 0x46, 0xFF, 0xFF, };
-
+ 0x07, 0x00, 0x29, 0xC0,
+ 0xDE, 0x95, 0xCF, 0xE2,
+ 0xCE, 0x11, 0x15, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd42[] = {
-0x03, 0x00, 0x29, 0xC0,
-0xC5, 0x77, 0x47, 0xFF, };
-
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xCF, 0x46, 0xFF, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd43[] = {
-0x03, 0x00, 0x29, 0xC0,
-0xED, 0x00, 0x20, 0xFF, };
-
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xC5, 0x66, 0xFF, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd44[] = {
-0x11, 0x00, 0x05, 0x80 };
-
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xED, 0x00, 0x20, 0xFF,
+};
static char ssd2080m_720p_video_on_cmd45[] = {
-0x29, 0x00, 0x05, 0x80 };
-
+ 0x53, 0x2c, 0x15, 0x80
+};
static char ssd2080m_720p_video_on_cmd46[] = {
-0x53, 0x2c, 0x15, 0x80 };
+ 0x11, 0x00, 0x05, 0x80
+};
-
-
+static char ssd2080m_720p_video_on_cmd47[] = {
+ 0x29, 0x00, 0x05, 0x80
+};
static struct mipi_dsi_cmd ssd2080m_720p_video_on_command[] = {
-{ 0x4 , ssd2080m_720p_video_on_cmd0},
-{ 0xc , ssd2080m_720p_video_on_cmd1},
-{ 0xc , ssd2080m_720p_video_on_cmd2},
-{ 0x8 , ssd2080m_720p_video_on_cmd3},
-{ 0x8 , ssd2080m_720p_video_on_cmd4},
-{ 0x8 , ssd2080m_720p_video_on_cmd5},
-{ 0x8 , ssd2080m_720p_video_on_cmd6},
-{ 0x8 , ssd2080m_720p_video_on_cmd7},
-{ 0x8 , ssd2080m_720p_video_on_cmd8},
-{ 0x10 , ssd2080m_720p_video_on_cmd9},
-{ 0xc , ssd2080m_720p_video_on_cmd10},
-{ 0x8 , ssd2080m_720p_video_on_cmd11},
-{ 0xc , ssd2080m_720p_video_on_cmd12},
-{ 0x10 , ssd2080m_720p_video_on_cmd13},
-{ 0x10 , ssd2080m_720p_video_on_cmd14},
-{ 0x10 , ssd2080m_720p_video_on_cmd15},
-{ 0x10 , ssd2080m_720p_video_on_cmd16},
-{ 0x10 , ssd2080m_720p_video_on_cmd17},
-{ 0x8 , ssd2080m_720p_video_on_cmd18},
-{ 0x8 , ssd2080m_720p_video_on_cmd19},
-{ 0xc , ssd2080m_720p_video_on_cmd20},
-{ 0xc , ssd2080m_720p_video_on_cmd21},
-{ 0xc , ssd2080m_720p_video_on_cmd22},
-{ 0xc , ssd2080m_720p_video_on_cmd23},
-{ 0xc , ssd2080m_720p_video_on_cmd24},
-{ 0xc , ssd2080m_720p_video_on_cmd25},
-{ 0xc , ssd2080m_720p_video_on_cmd26},
-{ 0xc , ssd2080m_720p_video_on_cmd27},
-{ 0xc , ssd2080m_720p_video_on_cmd28},
-{ 0xc , ssd2080m_720p_video_on_cmd29},
-{ 0xc , ssd2080m_720p_video_on_cmd30},
-{ 0xc , ssd2080m_720p_video_on_cmd31},
-{ 0xc , ssd2080m_720p_video_on_cmd32},
-{ 0xc , ssd2080m_720p_video_on_cmd33},
-{ 0x8 , ssd2080m_720p_video_on_cmd34},
-{ 0x8 , ssd2080m_720p_video_on_cmd35},
-{ 0x8 , ssd2080m_720p_video_on_cmd36},
-{ 0xc , ssd2080m_720p_video_on_cmd37},
-{ 0xc , ssd2080m_720p_video_on_cmd38},
-{ 0x8 , ssd2080m_720p_video_on_cmd39},
-{ 0x8 , ssd2080m_720p_video_on_cmd40},
-{ 0x8 , ssd2080m_720p_video_on_cmd41},
-{ 0x8 , ssd2080m_720p_video_on_cmd42},
-{ 0x8 , ssd2080m_720p_video_on_cmd43},
-{ 0x4 , ssd2080m_720p_video_on_cmd44},
-{ 0x4 , ssd2080m_720p_video_on_cmd45},
-{ 0x4 , ssd2080m_720p_video_on_cmd46}
+ {0x4, ssd2080m_720p_video_on_cmd0, 0x00},
+ {0x8, ssd2080m_720p_video_on_cmd1, 0x00},
+ {0xc, ssd2080m_720p_video_on_cmd2, 0x00},
+ {0xc, ssd2080m_720p_video_on_cmd3, 0x00},
+ {0x8, ssd2080m_720p_video_on_cmd4, 0x00},
+ {0x8, ssd2080m_720p_video_on_cmd5, 0x00},
+ {0x8, ssd2080m_720p_video_on_cmd6, 0x00},
+ {0x8, ssd2080m_720p_video_on_cmd7, 0x00},
+ {0x8, ssd2080m_720p_video_on_cmd8, 0x00},
+ {0x8, ssd2080m_720p_video_on_cmd9, 0x00},
+ {0x10, ssd2080m_720p_video_on_cmd10, 0x00},
+ {0xc, ssd2080m_720p_video_on_cmd11, 0x00},
+ {0x8, ssd2080m_720p_video_on_cmd12, 0x00},
+ {0xc, ssd2080m_720p_video_on_cmd13, 0x00},
+ {0x10, ssd2080m_720p_video_on_cmd14, 0x00},
+ {0x10, ssd2080m_720p_video_on_cmd15, 0x00},
+ {0x10, ssd2080m_720p_video_on_cmd16, 0x00},
+ {0x10, ssd2080m_720p_video_on_cmd17, 0x00},
+ {0x10, ssd2080m_720p_video_on_cmd18, 0x00},
+ {0x8, ssd2080m_720p_video_on_cmd19, 0x00},
+ {0x8, ssd2080m_720p_video_on_cmd20, 0x00},
+ {0xc, ssd2080m_720p_video_on_cmd21, 0x00},
+ {0xc, ssd2080m_720p_video_on_cmd22, 0x00},
+ {0xc, ssd2080m_720p_video_on_cmd23, 0x00},
+ {0xc, ssd2080m_720p_video_on_cmd24, 0x00},
+ {0xc, ssd2080m_720p_video_on_cmd25, 0x00},
+ {0xc, ssd2080m_720p_video_on_cmd26, 0x00},
+ {0xc, ssd2080m_720p_video_on_cmd27, 0x00},
+ {0xc, ssd2080m_720p_video_on_cmd28, 0x00},
+ {0xc, ssd2080m_720p_video_on_cmd29, 0x00},
+ {0xc, ssd2080m_720p_video_on_cmd30, 0x00},
+ {0xc, ssd2080m_720p_video_on_cmd31, 0x00},
+ {0xc, ssd2080m_720p_video_on_cmd32, 0x00},
+ {0xc, ssd2080m_720p_video_on_cmd33, 0x00},
+ {0xc, ssd2080m_720p_video_on_cmd34, 0x00},
+ {0x8, ssd2080m_720p_video_on_cmd35, 0x00},
+ {0x8, ssd2080m_720p_video_on_cmd36, 0x00},
+ {0x8, ssd2080m_720p_video_on_cmd37, 0x00},
+ {0xc, ssd2080m_720p_video_on_cmd38, 0x00},
+ {0xc, ssd2080m_720p_video_on_cmd39, 0x00},
+ {0x8, ssd2080m_720p_video_on_cmd40, 0x00},
+ {0xc, ssd2080m_720p_video_on_cmd41, 0x00},
+ {0x8, ssd2080m_720p_video_on_cmd42, 0x00},
+ {0x8, ssd2080m_720p_video_on_cmd43, 0x00},
+ {0x8, ssd2080m_720p_video_on_cmd44, 0x00},
+ {0x4, ssd2080m_720p_video_on_cmd45, 0x00},
+ {0x4, ssd2080m_720p_video_on_cmd46, 0x20},
+ {0x4, ssd2080m_720p_video_on_cmd47, 0x20}
};
-#define SSD2080M_720P_VIDEO_ON_COMMAND 47
+
+#define SSD2080M_720P_VIDEO_ON_COMMAND 48
static char ssd2080m_720p_videooff_cmd0[] = {
-0x10, 0x00, 0x05, 0x80 };
-
+ 0x10, 0x00, 0x05, 0x80
+};
static char ssd2080m_720p_videooff_cmd1[] = {
-0x53, 0x00, 0x05, 0x80 };
-
+ 0x02, 0x00, 0x39, 0xC0,
+ 0x53, 0x00, 0xFF, 0xFF,
+};
static char ssd2080m_720p_videooff_cmd2[] = {
-0xc2, 0x00, 0x05, 0x80 };
-
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xc2, 0x00, 0xFF, 0xFF,
+};
static char ssd2080m_720p_videooff_cmd3[] = {
-0x02, 0x00, 0x39, 0xC0,
-0xcf, 0x40, 0xFF, 0xFF, };
-
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xcf, 0x40, 0xFF, 0xFF,
+};
static char ssd2080m_720p_videooff_cmd4[] = {
-0xde, 0x84, 0x00, 0x05, 0x80 };
-
+ 0x03, 0x00, 0x39, 0xC0,
+ 0xde, 0x84, 0x00, 0xFF,
+};
static char ssd2080m_720p_videooff_cmd5[] = {
-0x02, 0x00, 0x39, 0xC0,
-0xcb, 0x22, 0xFF, 0xFF, };
-
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xcb, 0x22, 0xFF, 0xFF,
+};
static char ssd2080m_720p_videooff_cmd6[] = {
-0xc3, 0x00, 0x05, 0x80 };
-
-
-
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xc3, 0x00, 0xFF, 0xFF,
+};
static struct mipi_dsi_cmd ssd2080m_720p_video_off_command[] = {
-{ 0x4 , ssd2080m_720p_videooff_cmd0},
-{ 0x4 , ssd2080m_720p_videooff_cmd1},
-{ 0x4 , ssd2080m_720p_videooff_cmd2},
-{ 0x8 , ssd2080m_720p_videooff_cmd3},
-{ 0x4 , ssd2080m_720p_videooff_cmd4},
-{ 0x8 , ssd2080m_720p_videooff_cmd5},
-{ 0x4 , ssd2080m_720p_videooff_cmd6}
+ {0x4, ssd2080m_720p_videooff_cmd0, 0x32},
+ {0x8, ssd2080m_720p_videooff_cmd1, 0x20},
+ {0x8, ssd2080m_720p_videooff_cmd2, 0x20},
+ {0x8, ssd2080m_720p_videooff_cmd3, 0x00},
+ {0x8, ssd2080m_720p_videooff_cmd4, 0x20},
+ {0x8, ssd2080m_720p_videooff_cmd5, 0x00},
+ {0x8, ssd2080m_720p_videooff_cmd6, 0x00}
};
+
#define SSD2080M_720P_VIDEO_OFF_COMMAND 7
static struct command_state ssd2080m_720p_video_state = {
- 0, 1
+ 0, 1
};
/*---------------------------------------------------------------------------*/
/* Command mode panel information */
/*---------------------------------------------------------------------------*/
-
static struct commandpanel_info ssd2080m_720p_video_command_panel = {
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
};
/*---------------------------------------------------------------------------*/
/* Video mode panel information */
/*---------------------------------------------------------------------------*/
-
static struct videopanel_info ssd2080m_720p_video_video_panel = {
- 1, 0, 0, 0, 1, 0, 2, 0, 0x8
+ 1, 0, 0, 0, 1, 0, 2, 0, 0x8
};
/*---------------------------------------------------------------------------*/
-/* Lane Configuration */
+/* Lane configuration */
/*---------------------------------------------------------------------------*/
-
static struct lane_configuration ssd2080m_720p_video_lane_config = {
- 4, 0, 1, 1, 1, 1
+ 4, 0, 1, 1, 1, 1
};
-
/*---------------------------------------------------------------------------*/
-/* Panel Timing */
+/* Panel timing */
/*---------------------------------------------------------------------------*/
static const uint32_t ssd2080m_720p_video_timings[] = {
- 0xA8, 0x1F, 0x17, 0x00, 0x2F, 0x2D, 0x1C, 0x21, 0x29, 0x03, 0x04, 0x00
+ 0x68, 0x1d, 0x15, 0x00, 0x2e, 0x2d, 0x19, 0x1f, 0x24, 0x03, 0x04, 0x00
};
static struct panel_timing ssd2080m_720p_video_timing_info = {
- 0, 4, 0x20, 0x2F
+ 0, 4, 0x20, 0x2f
};
+/*---------------------------------------------------------------------------*/
+/* Panel reset sequence */
+/*---------------------------------------------------------------------------*/
static struct panel_reset_sequence ssd2080m_720p_video_panel_reset_seq = {
-{ 1, 0, 1, }, { 20, 20, 20, }, 2
+ {1, 0, 1, }, {20, 2, 20, }, 2
};
/*---------------------------------------------------------------------------*/
-/* Backlight Settings */
+/* Backlight setting */
/*---------------------------------------------------------------------------*/
-
static struct backlight ssd2080m_720p_video_backlight = {
- 1, 1, 4095, 100, 1, "bl_ctrl_wled"
+ 1, 1, 4095, 100, 1, "PMIC_8941"
};
-
#endif /*_PANEL_SSD2080M_720P_VIDEO_H_*/
diff --git a/dev/gcdb/display/panel_display.c b/dev/gcdb/display/panel_display.c
index 8503760..e34d966 100644
--- a/dev/gcdb/display/panel_display.c
+++ b/dev/gcdb/display/panel_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -38,6 +38,7 @@
#include <err.h>
#include <reg.h>
#include <mdp5.h>
+#include <string.h>
/*---------------------------------------------------------------------------*/
@@ -108,7 +109,6 @@
pinfo->rotation = pstruct->paneldata->panel_orientation;
pinfo->mipi.interleave_mode = pstruct->paneldata->interleave_mode;
pinfo->mipi.broadcast = pstruct->paneldata->panel_broadcast_mode;
- pinfo->lowpowerstop = pstruct->paneldata->dsi_lp11_atinit;
pinfo->mipi.vc = pstruct->paneldata->dsi_virtualchannel_id;
pinfo->mipi.frame_rate = pstruct->paneldata->panel_framerate;
pinfo->mipi.stream = pstruct->paneldata->dsi_stream;
@@ -235,7 +235,7 @@
pinfo->mipi.dst_format,
pinfo->mipi.traffic_mode,
lane_enable,
- pinfo->lowpowerstop,
+ pinfo->mipi.hsa_power_stop,
pinfo->mipi.eof_bllp_power,
pinfo->mipi.interleave_mode,
MIPI_DSI0_BASE);
@@ -255,7 +255,7 @@
pinfo->mipi.dst_format,
pinfo->mipi.traffic_mode,
lane_enable,
- pinfo->lowpowerstop,
+ pinfo->mipi.hsa_power_stop,
pinfo->mipi.eof_bllp_power,
pinfo->mipi.interleave_mode,
MIPI_DSI1_BASE);
@@ -269,6 +269,10 @@
int ret = NO_ERROR;
uint8_t lane_en = 0;
uint8_t ystride = pinfo->bpp / 8;
+ uint32_t panel_width = pinfo->xres;
+
+ if (pinfo->mipi.dual_dsi)
+ panel_width = panel_width / 2;
if (pinfo->mipi.data_lane0)
lane_en |= (1 << 0);
@@ -279,12 +283,22 @@
if (pinfo->mipi.data_lane3)
lane_en |= (1 << 3);
- ret = mdss_dsi_cmd_mode_config((pinfo->xres + plcdc->xres_pad),
+ ret = mdss_dsi_cmd_mode_config((panel_width + plcdc->xres_pad),
(pinfo->yres + plcdc->yres_pad),
- (pinfo->xres), (pinfo->yres),
+ panel_width, (pinfo->yres),
pinfo->mipi.dst_format,
ystride, lane_en,
- pinfo->mipi.interleave_mode);
+ pinfo->mipi.interleave_mode,
+ MIPI_DSI0_BASE);
+
+ if (pinfo->mipi.dual_dsi)
+ ret = mdss_dsi_cmd_mode_config((panel_width + plcdc->xres_pad),
+ (pinfo->yres + plcdc->yres_pad),
+ panel_width, (pinfo->yres),
+ pinfo->mipi.dst_format,
+ ystride, lane_en,
+ pinfo->mipi.interleave_mode,
+ MIPI_DSI1_BASE);
return ret;
}
@@ -312,3 +326,28 @@
return ret;
}
+
+int32_t panel_name_to_id(struct panel_list supp_panels[],
+ uint32_t supp_panels_size,
+ const char *panel_name)
+{
+ uint32_t i;
+ int32_t panel_id = ERR_NOT_FOUND;
+
+ if (!panel_name) {
+ dprintf(CRITICAL, "Invalid panel name\n");
+ return panel_id;
+ }
+
+ /* Remove any leading whitespaces */
+ panel_name += strspn(panel_name, " ");
+ for (i = 0; i < supp_panels_size; i++) {
+ if (!strncmp(panel_name, supp_panels[i].name,
+ MAX_PANEL_ID_LEN)) {
+ panel_id = supp_panels[i].id;
+ break;
+ }
+ }
+
+ return panel_id;
+}
diff --git a/dev/gcdb/display/panel_display.h b/dev/gcdb/display/panel_display.h
index d805715..676bd69 100755
--- a/dev/gcdb/display/panel_display.h
+++ b/dev/gcdb/display/panel_display.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -44,6 +44,8 @@
#define DUAL_PIPE_FLAG 0x2
#define PIPE_SWAP_FLAG 0x4
#define SPLIT_DISPLAY_FLAG 0x8
+
+#define MAX_PANEL_ID_LEN 64
/*---------------------------------------------------------------------------*/
/* struct definition */
/*---------------------------------------------------------------------------*/
@@ -60,6 +62,10 @@
struct backlight *backlightinfo;
};
+struct panel_list {
+ char name[MAX_PANEL_ID_LEN];
+ uint32_t id;
+};
/*---------------------------------------------------------------------------*/
/* API */
@@ -79,4 +85,7 @@
int oem_panel_on();
int oem_panel_off();
+/* OEM support API */
+int32_t panel_name_to_id(struct panel_list supp_panels[],
+ uint32_t supp_panels_size, const char *panel_name);
#endif /*_PLATFORM_DISPLAY_H_ */
diff --git a/dev/pmic/pm8x41/include/pm8x41.h b/dev/pmic/pm8x41/include/pm8x41.h
index 82d3c1d..8a5eaff 100644
--- a/dev/pmic/pm8x41/include/pm8x41.h
+++ b/dev/pmic/pm8x41/include/pm8x41.h
@@ -201,6 +201,7 @@
int pm8x41_ldo_control(struct pm8x41_ldo *ldo, uint8_t enable);
uint8_t pm8x41_get_pmic_rev();
uint8_t pm8x41_get_pon_reason();
+uint32_t pm8x41_get_pwrkey_is_pressed();
void pm8x41_config_output_mpp(struct pm8x41_mpp *mpp);
void pm8x41_enable_mpp(struct pm8x41_mpp *mpp, enum mpp_en_ctl enable);
uint8_t pm8x41_get_is_cold_boot();
diff --git a/dev/pmic/pm8x41/include/pm8x41_hw.h b/dev/pmic/pm8x41/include/pm8x41_hw.h
index 7664f37..672514a 100644
--- a/dev/pmic/pm8x41/include/pm8x41_hw.h
+++ b/dev/pmic/pm8x41/include/pm8x41_hw.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -81,6 +81,7 @@
/* PON Peripheral register bit values */
#define RESIN_ON_INT_BIT 1
+#define KPDPWR_ON_INT_BIT 0
#define RESIN_BARK_INT_BIT 4
#define S2_RESET_EN_BIT 7
diff --git a/dev/pmic/pm8x41/include/pm8x41_wled.h b/dev/pmic/pm8x41/include/pm8x41_wled.h
index 92632ca..8ad7370 100644
--- a/dev/pmic/pm8x41/include/pm8x41_wled.h
+++ b/dev/pmic/pm8x41/include/pm8x41_wled.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -32,7 +32,7 @@
#define PM_WLED_BASE 0x0D800
#define PM_WLED_CTNL_REG(n) (PM_WLED_BASE + n)
-#define PM_WLED_LED_CTNL_REG(n) (PM_WLED_BASE + 0x60 + (n-1)*10)
+#define PM_WLED_LED_CTNL_REG(n) (PM_WLED_BASE + 0x60 + (n-1)*0x10)
#define PM_WLED_LED1_BRIGHTNESS_LSB PM_WLED_CTNL_REG(0x40)
#define PM_WLED_LED1_BRIGHTNESS_MSB PM_WLED_CTNL_REG(0x41)
diff --git a/dev/pmic/pm8x41/include/pm_vib.h b/dev/pmic/pm8x41/include/pm_vib.h
new file mode 100644
index 0000000..9b10327
--- /dev/null
+++ b/dev/pmic/pm8x41/include/pm_vib.h
@@ -0,0 +1,38 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __DEV_PMIC_VIB_VIBRATOR_H
+#define __DEV_PMIC_VIB_VIBRATOR_H
+
+#define QPNP_VIB_EN_CTL 0x1c046
+#define QPNP_VIB_VTG_CTL 0x1c041
+#define QPNP_VIB_VTG_SET_MASK 0x1F
+#define QPNP_VIB_DEFAULT_VTG_LVL 22
+
+void pm_vib_turn_on(void);
+void pm_vib_turn_off(void);
+#endif/* __DEV_PMIC_VIB_VIBRATOR_H */
diff --git a/dev/pmic/pm8x41/pm8x41.c b/dev/pmic/pm8x41/pm8x41.c
index 4ea7643..2c14d3b 100644
--- a/dev/pmic/pm8x41/pm8x41.c
+++ b/dev/pmic/pm8x41/pm8x41.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -219,6 +219,19 @@
return (rt_sts & BIT(RESIN_ON_INT_BIT));
}
+/* Return 1 if power key is pressed */
+uint32_t pm8x41_get_pwrkey_is_pressed()
+{
+ uint8_t pwr_sts = 0;
+
+ pwr_sts = REG_READ(PON_INT_RT_STS);
+
+ if (pwr_sts & BIT(KPDPWR_ON_INT_BIT))
+ return 1;
+ else
+ return 0;
+}
+
void pm8x41_v2_reset_configure(uint8_t reset_type)
{
uint8_t val;
diff --git a/dev/pmic/pm8x41/pm8x41_vib.c b/dev/pmic/pm8x41/pm8x41_vib.c
new file mode 100644
index 0000000..7dbba77
--- /dev/null
+++ b/dev/pmic/pm8x41/pm8x41_vib.c
@@ -0,0 +1,60 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <bits.h>
+#include <debug.h>
+#include <reg.h>
+#include <pm8x41.h>
+#include <pm_vib.h>
+
+#define QPNP_VIB_EN BIT(7)
+
+/* Turn on vibrator */
+void pm_vib_turn_on(void)
+{
+ uint8_t val;
+
+ val = pm8x41_reg_read(QPNP_VIB_VTG_CTL);
+ val &= ~QPNP_VIB_VTG_SET_MASK;
+ val |= (QPNP_VIB_DEFAULT_VTG_LVL & QPNP_VIB_VTG_SET_MASK);
+ pm8x41_reg_write(QPNP_VIB_VTG_CTL, val);
+
+ val = pm8x41_reg_read(QPNP_VIB_EN_CTL);
+ val |= QPNP_VIB_EN;
+ pm8x41_reg_write(QPNP_VIB_EN_CTL, val);
+}
+
+/* Turn off vibrator */
+void pm_vib_turn_off(void)
+{
+ uint8_t val;
+
+ val = pm8x41_reg_read(QPNP_VIB_EN_CTL);
+ val &= ~QPNP_VIB_EN;
+ pm8x41_reg_write(QPNP_VIB_EN_CTL, val);
+}
diff --git a/dev/pmic/pm8x41/rules.mk b/dev/pmic/pm8x41/rules.mk
index 1cecf27..3713a4e 100644
--- a/dev/pmic/pm8x41/rules.mk
+++ b/dev/pmic/pm8x41/rules.mk
@@ -6,3 +6,8 @@
$(LOCAL_DIR)/pm8x41.o \
$(LOCAL_DIR)/pm8x41_adc.o \
$(LOCAL_DIR)/pm8x41_wled.o
+
+ifeq ($(ENABLE_PON_VIB_SUPPORT),true)
+OBJS += \
+ $(LOCAL_DIR)/pm8x41_vib.o
+endif
diff --git a/dev/vib/include/vibrator.h b/dev/vib/include/vibrator.h
new file mode 100644
index 0000000..d6fb8bf
--- /dev/null
+++ b/dev/vib/include/vibrator.h
@@ -0,0 +1,37 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __DEV_VIB_VIBRATOR_H
+#define __DEV_VIB_VIBRATOR_H
+
+#define VIB_TIMER_DEFAULT_TIMEOUT 250
+
+void vib_turn_on(void);
+void vib_turn_off(void);
+void vib_timed_turn_on(const uint32_t);
+void wait_vib_timeout(void);
+#endif /* __DEV_VIB_VIBRATOR_H */
diff --git a/dev/vib/rules.mk b/dev/vib/rules.mk
new file mode 100644
index 0000000..e9e1d10
--- /dev/null
+++ b/dev/vib/rules.mk
@@ -0,0 +1,6 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+INCLUDES += -I$(LOCAL_DIR)/include
+
+OBJS += \
+ $(LOCAL_DIR)/vibrator.o
diff --git a/dev/vib/vibrator.c b/dev/vib/vibrator.c
new file mode 100644
index 0000000..e8cb8c7
--- /dev/null
+++ b/dev/vib/vibrator.c
@@ -0,0 +1,83 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <reg.h>
+#include <stdlib.h>
+#include <kernel/timer.h>
+#include <platform/timer.h>
+#include <vibrator.h>
+#include <pm_vib.h>
+
+#define CHECK_VIB_TIMER_FREQUENCY 50
+
+static struct timer vib_timer;
+static uint32_t vib_timeout;
+
+/* Function to turn on vibrator */
+void vib_turn_on()
+{
+ pm_vib_turn_on();
+}
+
+/* Function to turn off vibrator */
+void vib_turn_off()
+{
+ pm_vib_turn_off();
+}
+
+/* Function to turn off vibrator when the vib_timer is expired. */
+static enum handler_return vib_timer_func(struct timer *v_timer, void *arg)
+{
+ timer_cancel(&vib_timer);
+ vib_turn_off();
+ vib_timeout=1;
+
+ return INT_RESCHEDULE;
+}
+
+/*
+ * Function to turn on vibrator.
+ * vibrate_time - the time of phone vibrate.
+ */
+void vib_timed_turn_on(const uint32_t vibrate_time)
+{
+ vib_turn_on();
+ vib_timeout=0;
+ timer_initialize(&vib_timer);
+ timer_set_oneshot(&vib_timer, vibrate_time, vib_timer_func, NULL);
+}
+
+/* Wait for vibrator timer expired */
+void wait_vib_timeout(void)
+{
+ while (!vib_timeout) {
+ /* every 50ms to check if the vibrator timer is timeout*/
+ thread_sleep(CHECK_VIB_TIMER_FREQUENCY);
+ }
+}
diff --git a/include/target.h b/include/target.h
index 45f1605..dfd5521 100644
--- a/include/target.h
+++ b/include/target.h
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2008 Travis Geiselbrecht
*
- * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
@@ -51,5 +51,6 @@
struct mmc_device *target_mmc_device();
bool target_display_panel_node(char *pbuf, uint16_t buf_size);
-
+void target_display_init(const char *panel_name);
+void target_display_shutdown(void);
#endif
diff --git a/platform/apq8084/include/platform/iomap.h b/platform/apq8084/include/platform/iomap.h
index 09485e0..b7e3eda 100644
--- a/platform/apq8084/include/platform/iomap.h
+++ b/platform/apq8084/include/platform/iomap.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -154,6 +154,12 @@
#define TRIG_CTRL 0x084
#define CTRL 0x004
#define COMMAND_MODE_DMA_CTRL 0x03C
+#define COMMAND_MODE_MDP_CTRL 0x040
+#define COMMAND_MODE_MDP_DCS_CMD_CTRL 0x044
+#define COMMAND_MODE_MDP_STREAM0_CTRL 0x058
+#define COMMAND_MODE_MDP_STREAM0_TOTAL 0x05C
+#define COMMAND_MODE_MDP_STREAM1_CTRL 0x060
+#define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064
#define ERR_INT_MASK0 0x10C
#define LANE_SWAP_CTL 0x0B0
@@ -178,6 +184,7 @@
#define CMD_MODE_DMA_SW_TRIGGER 0x090
#define EOT_PACKET_CTRL 0x0C8
+#define MISR_CMD_CTRL 0x0A0
#define MISR_VIDEO_CTRL 0x0A4
#define VIDEO_MODE_CTRL 0x010
#define HS_TIMER_CTRL 0x0BC
diff --git a/platform/init.c b/platform/init.c
index a809501..5001373 100644
--- a/platform/init.c
+++ b/platform/init.c
@@ -101,3 +101,7 @@
{
return 0;
}
+
+__WEAK void clock_config_cdc(uint8_t slot)
+{
+}
diff --git a/platform/msm8226/include/platform/iomap.h b/platform/msm8226/include/platform/iomap.h
index 5418229..1f1b335 100644
--- a/platform/msm8226/include/platform/iomap.h
+++ b/platform/msm8226/include/platform/iomap.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -178,6 +178,12 @@
#define TRIG_CTRL 0x084
#define CTRL 0x004
#define COMMAND_MODE_DMA_CTRL 0x03C
+#define COMMAND_MODE_MDP_CTRL 0x040
+#define COMMAND_MODE_MDP_DCS_CMD_CTRL 0x044
+#define COMMAND_MODE_MDP_STREAM0_CTRL 0x058
+#define COMMAND_MODE_MDP_STREAM0_TOTAL 0x05C
+#define COMMAND_MODE_MDP_STREAM1_CTRL 0x060
+#define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064
#define ERR_INT_MASK0 0x10C
#define LANE_SWAP_CTL 0x0B0
@@ -197,6 +203,7 @@
#define CMD_MODE_DMA_SW_TRIGGER 0x090
#define EOT_PACKET_CTRL 0x0C8
+#define MISR_CMD_CTRL 0x0A0
#define MISR_VIDEO_CTRL 0x0A4
#define VIDEO_MODE_CTRL 0x010
#define HS_TIMER_CTRL 0x0BC
diff --git a/platform/msm8610/include/platform/iomap.h b/platform/msm8610/include/platform/iomap.h
index 7999453..20ae908 100644
--- a/platform/msm8610/include/platform/iomap.h
+++ b/platform/msm8610/include/platform/iomap.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Copyright (c) 2008, Google Inc.
* All rights reserved.
@@ -168,6 +168,12 @@
#define TRIG_CTRL 0x080
#define CTRL 0x000
#define COMMAND_MODE_DMA_CTRL 0x038
+#define COMMAND_MODE_MDP_CTRL 0x03C
+#define COMMAND_MODE_MDP_DCS_CMD_CTRL 0x040
+#define COMMAND_MODE_MDP_STREAM0_CTRL 0x054
+#define COMMAND_MODE_MDP_STREAM0_TOTAL 0x058
+#define COMMAND_MODE_MDP_STREAM1_CTRL 0x05C
+#define COMMAND_MODE_MDP_STREAM1_TOTAL 0x060
#define ERR_INT_MASK0 0x108
#define LANE_SWAP_CTL 0x0AC
@@ -187,6 +193,7 @@
#define CMD_MODE_DMA_SW_TRIGGER 0x08C
#define EOT_PACKET_CTRL 0x0C8
+#define MISR_CMD_CTRL 0x09C
#define MISR_VIDEO_CTRL 0x0A0
#define VIDEO_MODE_CTRL 0x00C
#define HS_TIMER_CTRL 0x0B8
diff --git a/platform/msm8974/acpuclock.c b/platform/msm8974/acpuclock.c
index e66208c..da1b024 100644
--- a/platform/msm8974/acpuclock.c
+++ b/platform/msm8974/acpuclock.c
@@ -128,6 +128,10 @@
{
ret = clk_get_set_enable(clk_name, 400000, 1);
}
+ else if(freq == MMC_CLK_25MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 25000000, 1);
+ }
else if(freq == MMC_CLK_50MHZ)
{
ret = clk_get_set_enable(clk_name, 50000000, 1);
@@ -136,10 +140,18 @@
{
ret = clk_get_set_enable(clk_name, 100000000, 1);
}
+ else if(freq == MMC_CLK_192MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 192000000, 1);
+ }
else if(freq == MMC_CLK_200MHZ)
{
ret = clk_get_set_enable(clk_name, 200000000, 1);
}
+ else if(freq == MMC_CLK_400MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 384000000, 1);
+ }
else
{
dprintf(CRITICAL, "sdc frequency (%u) is not supported\n", freq);
@@ -159,6 +171,29 @@
#endif
}
+/* Configure clocks needed for CDCLP533 circuit */
+void clock_config_cdc(uint32_t interface)
+{
+ int ret = 0;
+ char clk_name[64];
+
+ snprintf(clk_name, sizeof(clk_name), "gcc_sdcc%u_cdccal_sleep_clk", interface);
+ ret = clk_get_set_enable(clk_name, 0 , 1);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to enable clock: %s\n", clk_name);
+ ASSERT(0);
+ }
+
+ snprintf(clk_name, sizeof(clk_name), "gcc_sdcc%u_cdccal_ff_clk", interface);
+ ret = clk_get_set_enable(clk_name, 0 , 1);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to enable clock: %s\n", clk_name);
+ ASSERT(0);
+ }
+}
+
/* Configure UART clock based on the UART block id*/
void clock_config_uart_dm(uint8_t id)
{
diff --git a/platform/msm8974/include/platform/iomap.h b/platform/msm8974/include/platform/iomap.h
index 42a436f..5c9d7dc 100644
--- a/platform/msm8974/include/platform/iomap.h
+++ b/platform/msm8974/include/platform/iomap.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -150,6 +150,9 @@
#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x1480)
#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x1484)
+/* GPLL4 */
+#define GPLL4_STATUS (CLK_CTL_BASE + 0x1DDC)
+
/* SDCC */
#define SDCC1_BCR (CLK_CTL_BASE + 0x4C0) /* block reset */
#define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x4C4) /* branch control */
@@ -161,6 +164,10 @@
#define SDCC1_N (CLK_CTL_BASE + 0x4DC) /* n */
#define SDCC1_D (CLK_CTL_BASE + 0x4E0) /* d */
+/* SDCC clocks for CDC calibration*/
+#define SDCC1_CDCCAL_SLEEP_CBCR (CLK_CTL_BASE + 0x04E4)
+#define SDCC1_CDCCAL_FF_CBCR (CLK_CTL_BASE + 0x04E8)
+
/* SDCC2 */
#define SDCC2_BCR (CLK_CTL_BASE + 0x500) /* block reset */
#define SDCC2_APPS_CBCR (CLK_CTL_BASE + 0x504) /* branch control */
@@ -225,6 +232,12 @@
#define TRIG_CTRL 0x084
#define CTRL 0x004
#define COMMAND_MODE_DMA_CTRL 0x03C
+#define COMMAND_MODE_MDP_CTRL 0x040
+#define COMMAND_MODE_MDP_DCS_CMD_CTRL 0x044
+#define COMMAND_MODE_MDP_STREAM0_CTRL 0x058
+#define COMMAND_MODE_MDP_STREAM0_TOTAL 0x05C
+#define COMMAND_MODE_MDP_STREAM1_CTRL 0x060
+#define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064
#define ERR_INT_MASK0 0x10C
#define LANE_SWAP_CTL 0x0B0
@@ -244,6 +257,7 @@
#define CMD_MODE_DMA_SW_TRIGGER 0x090
#define EOT_PACKET_CTRL 0x0C8
+#define MISR_CMD_CTRL 0x0A0
#define MISR_VIDEO_CTRL 0x0A4
#define VIDEO_MODE_CTRL 0x010
#define HS_TIMER_CTRL 0x0BC
diff --git a/platform/msm8974/msm8974-clock.c b/platform/msm8974/msm8974-clock.c
index 68000d5..e2209c2 100644
--- a/platform/msm8974/msm8974-clock.c
+++ b/platform/msm8974/msm8974-clock.c
@@ -39,6 +39,7 @@
/* Mux source select values */
#define cxo_source_val 0
#define gpll0_source_val 1
+#define gpll4_source_val 5
#define cxo_mm_source_val 0
#define mmpll0_mm_source_val 1
#define mmpll1_mm_source_val 2
@@ -115,8 +116,41 @@
},
};
+static struct pll_vote_clk gpll4_clk_src =
+{
+ .en_reg = (void *) APCS_GPLL_ENA_VOTE,
+ .en_mask = BIT(4),
+ .status_reg = (void *) GPLL4_STATUS,
+ .status_mask = BIT(17),
+ .parent = &cxo_clk_src.c,
+
+ .c = {
+ .rate = 768000000,
+ .dbg_name = "gpll4_clk_src",
+ .ops = &clk_ops_pll_vote,
+ },
+};
+
/* SDCC Clocks */
-static struct clk_freq_tbl ftbl_gcc_sdcc1_2_apps_clk[] =
+/* This table is for sdc1 apps clk only for MSM8974 PRO AC */
+static struct clk_freq_tbl ftbl_gcc_sdcc1_apps_clk_ac[] =
+{
+ F( 144000, cxo, 16, 3, 25),
+ F( 400000, cxo, 12, 1, 4),
+ F( 20000000, gpll0, 15, 1, 2),
+ F( 25000000, gpll0, 12, 1, 2),
+ F( 50000000, gpll0, 12, 0, 0),
+ F(100000000, gpll0, 6, 0, 0),
+ F(192000000, gpll4, 4, 0, 0),
+ F(384000000, gpll4, 2, 0, 0),
+ F_END
+};
+
+/* This table is for
+ * sdc[1-4] for all MSM8974 excluding MSM8974PROAC
+ * sdc[2-4] for MSM8974PRO AC
+ */
+static struct clk_freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] =
{
F( 144000, cxo, 16, 3, 25),
F( 400000, cxo, 12, 1, 4),
@@ -137,7 +171,7 @@
.d_reg = (uint32_t *) SDCC1_D,
.set_rate = clock_lib2_rcg_set_rate_mnd,
- .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk,
+ .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
.current_freq = &rcg_dummy_freq,
.c = {
@@ -168,6 +202,28 @@
},
};
+static struct branch_clk gcc_sdcc1_cdccal_sleep_clk =
+{
+ .cbcr_reg = SDCC1_CDCCAL_SLEEP_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_sdcc1_cdccal_sleep_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_sdcc1_cdccal_ff_clk =
+{
+ .cbcr_reg = SDCC1_CDCCAL_FF_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_sdcc1_cdccal_ff_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
static struct rcg_clk sdcc2_apps_clk_src =
{
.cmd_reg = (uint32_t *) SDCC2_CMD_RCGR,
@@ -177,7 +233,7 @@
.d_reg = (uint32_t *) SDCC2_D,
.set_rate = clock_lib2_rcg_set_rate_mnd,
- .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk,
+ .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
.current_freq = &rcg_dummy_freq,
.c = {
@@ -761,6 +817,9 @@
CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c),
+ CLK_LOOKUP("gcc_sdcc1_cdccal_sleep_clk", gcc_sdcc1_cdccal_sleep_clk.c),
+ CLK_LOOKUP("gcc_sdcc1_cdccal_ff_clk", gcc_sdcc1_cdccal_ff_clk.c),
+
CLK_LOOKUP("sdc2_iface_clk", gcc_sdcc2_ahb_clk.c),
CLK_LOOKUP("sdc2_core_clk", gcc_sdcc2_apps_clk.c),
@@ -804,8 +863,14 @@
CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c),
};
+void msm8974_ac_clock_override()
+{
+ sdcc1_apps_clk_src.freq_tbl = ftbl_gcc_sdcc1_apps_clk_ac;
+}
void platform_clock_init(void)
{
+ if (platform_is_8974ac())
+ msm8974_ac_clock_override();
clk_init(msm_clocks_8974, ARRAY_SIZE(msm_clocks_8974));
}
diff --git a/platform/msm8974/platform.c b/platform/msm8974/platform.c
index be35f84..460317c 100644
--- a/platform/msm8974/platform.c
+++ b/platform/msm8974/platform.c
@@ -87,6 +87,81 @@
return readl(MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL);
}
+/* Check for 8974 chip */
+int platform_is_8974()
+{
+ uint32_t platform = board_platform_id();
+ int ret = 0;
+
+ switch(platform)
+ {
+ case APQ8074:
+ case MSM8274:
+ case MSM8674:
+ case MSM8974:
+ ret = 1;
+ break;
+ default:
+ ret = 0;
+ };
+
+ return ret;
+}
+
+/* Check for 8974 PRO chip */
+int platform_is_8974Pro()
+{
+ uint32_t platform = board_platform_id();
+ int ret = 0;
+
+ switch(platform)
+ {
+ case MSM8974AC:
+ case MSM8674AC:
+ case MSM8274AC:
+ case APQ8074AC:
+ ret = 1;
+ break;
+ default:
+ ret = 0;
+ };
+
+ return ret;
+}
+
+/* Check for 8974PRO AC chip */
+int platform_is_8974ac()
+{
+ uint32_t platform = board_platform_id();
+ int ret = 0;
+
+ switch(platform)
+ {
+ case APQ8074AA:
+ case APQ8074AB:
+ case APQ8074AC:
+
+ case MSM8274AA:
+ case MSM8274AB:
+ case MSM8274AC:
+
+ case MSM8674AA:
+ case MSM8674AB:
+ case MSM8674AC:
+
+ case MSM8974AA:
+ case MSM8974AB:
+ case MSM8974AC:
+
+ ret = 1;
+ break;
+ default:
+ ret = 0;
+ };
+
+ return ret;
+}
+
addr_t get_bs_info_addr()
{
uint32_t soc_ver = board_soc_version();
diff --git a/platform/msm_shared/clock_lib2.c b/platform/msm_shared/clock_lib2.c
index 218b585..6f778b1 100644
--- a/platform/msm_shared/clock_lib2.c
+++ b/platform/msm_shared/clock_lib2.c
@@ -129,7 +129,14 @@
return rc;
/* First enable the source clock for this freq. */
- clk_enable(nf->src_clk);
+ rc = clk_enable(nf->src_clk);
+
+ if(rc)
+ {
+ dprintf(CRITICAL, "clock_lib2_rcg_set_rate: failed to enable clk %s ret %d\n",
+ nf->src_clk->dbg_name, rc);
+ ASSERT(0);
+ }
/* Perform clock-specific frequency switch operations. */
ASSERT(rclk->set_rate);
diff --git a/platform/msm_shared/debug.c b/platform/msm_shared/debug.c
index 3349db7..28c053e 100644
--- a/platform/msm_shared/debug.c
+++ b/platform/msm_shared/debug.c
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2009, Google Inc.
* All rights reserved.
- * Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2009-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -39,6 +39,10 @@
#include <platform/timer.h>
#include <platform.h>
+#if PON_VIB_SUPPORT
+#include <vibrator.h>
+#endif
+
static void write_dcc(char c)
{
uint32_t timeout = 10;
@@ -134,6 +138,9 @@
void platform_halt(void)
{
+#if PON_VIB_SUPPORT
+ vib_turn_off();
+#endif
if (set_download_mode(NORMAL_DLOAD) == 0)
{
dprintf(CRITICAL, "HALT: reboot into dload mode...\n");
diff --git a/platform/msm_shared/include/clock-local.h b/platform/msm_shared/include/clock-local.h
index a9f1151..7a7d9fd 100644
--- a/platform/msm_shared/include/clock-local.h
+++ b/platform/msm_shared/include/clock-local.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -130,7 +130,7 @@
struct bank_masks *const bank_masks;
void (*set_rate)(struct rcg_clk *, struct clk_freq_tbl *);
- struct clk_freq_tbl *const freq_tbl;
+ struct clk_freq_tbl *freq_tbl;
struct clk_freq_tbl *current_freq;
struct clk *depends;
diff --git a/platform/msm_shared/include/clock_lib2.h b/platform/msm_shared/include/clock_lib2.h
index 7998a89..e808c87 100644
--- a/platform/msm_shared/include/clock_lib2.h
+++ b/platform/msm_shared/include/clock_lib2.h
@@ -156,7 +156,7 @@
void (*set_rate)(struct rcg_clk *, struct clk_freq_tbl *);
/* freq table */
- struct clk_freq_tbl *const freq_tbl;
+ struct clk_freq_tbl *freq_tbl;
struct clk_freq_tbl *current_freq;
struct clk c;
diff --git a/platform/msm_shared/include/gpio.h b/platform/msm_shared/include/gpio.h
index 2a95eda..56b9c82 100644
--- a/platform/msm_shared/include/gpio.h
+++ b/platform/msm_shared/include/gpio.h
@@ -34,12 +34,19 @@
/* Current values for tlmm pins */
enum {
- TLMM_CUR_VAL_16MA = 0x7,
- TLMM_CUR_VAL_10MA = 0x4,
+ TLMM_CUR_VAL_2MA = 0x0,
+ TLMM_CUR_VAL_4MA,
+ TLMM_CUR_VAL_6MA,
+ TLMM_CUR_VAL_8MA,
+ TLMM_CUR_VAL_10MA,
+ TLMM_CUR_VAL_12MA,
+ TLMM_CUR_VAL_14MA,
+ TLMM_CUR_VAL_16MA,
} tlmm_drive_config;
enum {
TLMM_PULL_UP = 0x3,
+ TLMM_PULL_DOWN = 0x1,
TLMM_NO_PULL = 0x0,
} tlmm_pull_values;
@@ -51,6 +58,7 @@
SDC1_DATA_PULL_CTL_OFF = 9,
SDC1_CMD_PULL_CTL_OFF = 11,
SDC1_CLK_PULL_CTL_OFF = 13,
+ SDC1_RCLK_PULL_CTL_OFF = 15,
} tlmm_drv_ctrl;
/* Input for the tlmm config function */
diff --git a/platform/msm_shared/include/mdp5.h b/platform/msm_shared/include/mdp5.h
index 1970cbb..149162f 100644
--- a/platform/msm_shared/include/mdp5.h
+++ b/platform/msm_shared/include/mdp5.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -64,10 +64,27 @@
#define LAYER_3_BLEND_OP 0xB0
#define LAYER_3_BLEND0_FG_ALPHA 0xB4
+/* HW Revisions for different MDSS targets */
+#define MDSS_GET_MAJOR(rev) ((rev) >> 28)
+#define MDSS_GET_MINOR(rev) (((rev) >> 16) & 0xFFF)
+#define MDSS_GET_STEP(rev) ((rev) & 0xFFFF)
+#define MDSS_GET_MAJOR_MINOR(rev) ((rev) >> 16)
-#define MDSS_MDP_HW_REV_100 0x10000000
-#define MDSS_MDP_HW_REV_101 0x10010000
-#define MDSS_MDP_HW_REV_102 0x10020000
+#define MDSS_IS_MAJOR_MINOR_MATCHING(a, b) \
+ (MDSS_GET_MAJOR_MINOR((a)) == MDSS_GET_MAJOR_MINOR((b)))
+
+#define MDSS_MDP_REV(major, minor, step) \
+ ((((major) & 0x000F) << 28) | \
+ (((minor) & 0x0FFF) << 16) | \
+ ((step) & 0xFFFF))
+
+#define MDSS_MDP_HW_REV_100 MDSS_MDP_REV(1, 0, 0) /* 8974 v1.0 */
+#define MDSS_MDP_HW_REV_101 MDSS_MDP_REV(1, 1, 0) /* 8x26 v1.0 */
+#define MDSS_MDP_HW_REV_101_1 MDSS_MDP_REV(1, 1, 1) /* 8x26 v2.0, 8926 v1.0 */
+#define MDSS_MDP_HW_REV_102 MDSS_MDP_REV(1, 2, 0) /* 8974 v2.0 */
+#define MDSS_MDP_HW_REV_102_1 MDSS_MDP_REV(1, 2, 1) /* 8974 v3.0 (Pro) */
+#define MDSS_MDP_HW_REV_103 MDSS_MDP_REV(1, 3, 0) /* 8084 v1.0 */
+#define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) /* 8092 v1.0 */
#define MDP_HW_REV REG_MDP(0x0100)
#define MDP_INTR_EN REG_MDP(0x0110)
@@ -91,9 +108,9 @@
#define CTL_FLUSH 0x18
#define CTL_START 0x1C
-#define MDP_TG_SINK REG_MDP(0x4F0)
#define MDP_REG_SPLIT_DISPLAY_EN REG_MDP(0x3F4)
#define MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL REG_MDP(0x3F8)
+#define MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL REG_MDP(0x4F0)
#define MDP_INTF_0_BASE REG_MDP(0x12500)
#define MDP_INTF_1_BASE REG_MDP(0x12700)
diff --git a/platform/msm_shared/include/mmc.h b/platform/msm_shared/include/mmc.h
index abdd31f..33ad2bf 100644
--- a/platform/msm_shared/include/mmc.h
+++ b/platform/msm_shared/include/mmc.h
@@ -397,6 +397,7 @@
/* EXT_CSD */
#define MMC_BOOT_ACCESS_WRITE 0x3
+#define MMC_BOOT_SET_BIT 0x1
#define MMC_BOOT_EXT_USER_WP 171
#define MMC_BOOT_EXT_ERASE_GROUP_DEF 175
diff --git a/platform/msm_shared/include/mmc_sdhci.h b/platform/msm_shared/include/mmc_sdhci.h
index b6a2ca6..1eb9745 100644
--- a/platform/msm_shared/include/mmc_sdhci.h
+++ b/platform/msm_shared/include/mmc_sdhci.h
@@ -49,6 +49,7 @@
#define CMD16_SET_BLOCKLEN 16
#define CMD17_READ_SINGLE_BLOCK 17
#define CMD18_READ_MULTIPLE_BLOCK 18
+#define CMD21_SEND_TUNING_BLOCK 21
#define CMD23_SET_BLOCK_COUNT 23
#define CMD24_WRITE_SINGLE_BLOCK 24
#define CMD25_WRITE_MULTIPLE_BLOCK 25
@@ -101,10 +102,12 @@
/* Values for ext csd fields */
#define MMC_HS_TIMING 0x1
#define MMC_HS200_TIMING 0x2
+#define MMC_HS400_TIMING 0x3
#define MMC_ACCESS_WRITE 0x3
#define MMC_SET_BIT 0x1
#define MMC_HS_DDR_MODE (BIT(2) | BIT(3))
#define MMC_HS_HS200_MODE (BIT(4) | BIT(5))
+#define MMC_HS_HS400_MODE (BIT(6) | BIT(7))
#define MMC_SEC_COUNT4_SHIFT 24
#define MMC_SEC_COUNT3_SHIFT 16
#define MMC_SEC_COUNT2_SHIFT 8
@@ -140,6 +143,8 @@
#define MMC_CLK_50MHZ 49152000
#define MMC_CLK_96MHZ 96000000
#define MMC_CLK_200MHZ 200000000
+#define MMC_CLK_192MHZ 192000000
+#define MMC_CLK_400MHZ 400000000
#define MMC_ADDR_OUT_OF_RANGE(resp) ((resp >> 31) & 0x01)
@@ -181,6 +186,8 @@
#define ACMD51_READ_CARD_SCR 51
#define CMD55_APP_CMD 55
+#define MMC_SAVE_TIMING(host, TIMING) host->timing = TIMING
+
/* Can be used to unpack array of upto 32 bits data */
#define UNPACK_BITS(array, start, len, size_of) \
({ \
diff --git a/platform/msm_shared/include/msm_panel.h b/platform/msm_shared/include/msm_panel.h
index 1cddbd2..1d8ebad 100755
--- a/platform/msm_shared/include/msm_panel.h
+++ b/platform/msm_shared/include/msm_panel.h
@@ -219,6 +219,7 @@
int (*clk_func) (int enable);
int (*bl_func) (int enable);
int (*pll_clk_func) (int enable, struct msm_panel_info *);
+ int (*pre_init_func)(void);
};
#endif
diff --git a/platform/msm_shared/include/scm.h b/platform/msm_shared/include/scm.h
index b2ae7a9..6b9efb5 100644
--- a/platform/msm_shared/include/scm.h
+++ b/platform/msm_shared/include/scm.h
@@ -174,6 +174,9 @@
#define SCM_SVC_ES 0x10
#define SCM_SAVE_PARTITION_HASH_ID 0x01
+#define SCM_SVC_PWR 0x9
+#define SCM_IO_DISABLE_PMIC_ARBITER 0x1
+
enum ap_ce_channel_type {
AP_CE_REGISTER_USE = 0,
AP_CE_ADM_USE = 1
@@ -187,6 +190,8 @@
void set_tamper_fuse_cmd();
+int scm_halt_pmic_arbiter();
+
/**
* struct scm_command - one SCM command buffer
* @len: total available memory for command and response
diff --git a/platform/msm_shared/include/sdhci.h b/platform/msm_shared/include/sdhci.h
index 976b5e3..a14b3b5 100644
--- a/platform/msm_shared/include/sdhci.h
+++ b/platform/msm_shared/include/sdhci.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -47,6 +47,8 @@
uint8_t sdr_support; /* Single Data rate */
uint8_t ddr_support; /* Dual Data rate */
uint8_t sdr50_support; /* UHS mode, with 100 MHZ clock */
+ uint8_t sdr104_support; /* UHS mode, with 200 MHZ clock */
+ uint8_t hs400_support; /* Hs400 mode, with 400 MHZ clock */
};
/*
@@ -54,10 +56,13 @@
* controller parameters
*/
struct sdhci_host {
- uint32_t base; /* Base address for the host */
- uint32_t cur_clk_rate; /* Running clock rate */
- event_t* sdhc_event; /* Event for power control irqs */
- struct host_caps caps; /* Host capabilities */
+ uint32_t base; /* Base address for the host */
+ uint32_t cur_clk_rate; /* Running clock rate */
+ uint32_t timing; /* current timing for the host */
+ bool tuning_in_progress; /* Tuning is being executed */
+ event_t* sdhc_event; /* Event for power control irqs */
+ struct host_caps caps; /* Host capabilities */
+ struct sdhci_msm_data *msm_host; /* MSM specific host info */
};
/*
@@ -123,6 +128,7 @@
#define REG_READ32(host, a) readl(host->base + a)
#define REG_WRITE32(host, v, a) writel(v, (host->base + a))
+#define REG_RMW32(host, a, s, w, v) RMWREG32((host->base + a), s, w, v)
#define REG_READ16(host, a) readhw(host->base + a)
#define REG_WRITE16(host, v, a) writehw(v, (host->base + a))
@@ -269,7 +275,7 @@
#define SDHCI_SWITCH_CMD 6
#define SDHCI_CMD_TIMEOUT 0xF
#define SDHCI_MAX_CMD_RETRY 10000
-#define SDHCI_MAX_TRANS_RETRY 100000
+#define SDHCI_MAX_TRANS_RETRY 10000
#define SDHCI_PREP_CMD(c, f) ((((c) & 0xff) << 8) | ((f) & 0xff))
@@ -309,15 +315,30 @@
#define SDHCI_CLK_50MHZ 50000000
#define SDHCI_CLK_100MHZ 100000000
#define SDHCI_CLK_200MHZ 200000000
+#define SDHCI_CLK_400MHZ 400000000
+
+/* UHS macros */
+#define SDHCI_UHS_MODE_MASK 0x0007
/* DDR mode related macros */
-#define SDHCI_DDR_MODE_EN 0x0004
-#define SDHCI_DDR_MODE_MASK BIT(2)
+#define SDHCI_DDR50_MODE_EN 0x0004
+#define SDHCI_DDR50_MODE_MASK BIT(2)
/* HS200/SDR50 mode related macros */
+#define SDHCI_SDR25_MODE_EN 0x0001
+#define SDHCI_SDR12_MODE_EN 0x0000
#define SDHCI_SDR50_MODE_MASK BIT(0)
#define SDHCI_SDR50_MODE_EN 0x0002
+#define SDHCI_SDR104_MODE_MASK BIT(1)
+#define SDHCI_SDR104_MODE_EN 0x0003
+
+#define SDHCI_SDR104_MODE 0x3
+#define SDHCI_SDR50_MODE 0x2
+#define SDHCI_DDR50_MODE 0x4
+#define SDHCI_SDR25_MODE 0x1
+#define SDHCI_SDR12_MODE 0x0
+
/*
* APIs and macros exposed for mmc/sd drivers
*/
@@ -338,8 +359,8 @@
uint8_t sdhci_set_bus_width(struct sdhci_host *, uint16_t);
/* API: Clock supply for the controller */
uint32_t sdhci_clk_supply(struct sdhci_host *, uint32_t);
-/* API: Enable DDR mode */
-void sdhci_set_ddr_mode(struct sdhci_host *);
-/* API: To enable SDR mode */
-void sdhci_set_sdr_mode(struct sdhci_host *);
+/* API: To enable SDR/DDR mode */
+void sdhci_set_uhs_mode(struct sdhci_host *, uint32_t);
+/* API: Soft reset for the controller */
+void sdhci_reset(struct sdhci_host *host, uint8_t mask);
#endif
diff --git a/platform/msm_shared/include/sdhci_msm.h b/platform/msm_shared/include/sdhci_msm.h
index 1d77823..a075460 100644
--- a/platform/msm_shared/include/sdhci_msm.h
+++ b/platform/msm_shared/include/sdhci_msm.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -31,13 +31,89 @@
#include <kernel/event.h>
+#define SDHCI_HC_START_BIT 0x0
+#define SDHCI_HC_WIDTH 0x1
+
+#define SDCC_MCI_POWER 0x0
+#define CORE_SW_RST_START 0x7
+#define CORE_SW_RST_WIDTH 0x1
+
+/* DLL & CDC registers
+ * DLL: Delay Line
+ * CDC: Calibrated Delay Circuit
+ */
+#define SDCC_DLL_CONFIG_REG 0x100
+#define SDCC_VENDOR_SPECIFIC_FUNC 0x10C
+#define SDCC_REG_DLL_STATUS 0x108
+#define SDCC_CDC_DDR200_CFG 0x184
+#define SDCC_VENDOR_SPEC_CSR_CDC_CFG 0x178
+#define SDCC_CSR_CDC_CTRL_CFG0 0x130
+#define SDCC_CSR_CDC_CTRL_CFG1 0x134
+#define SDCC_CSR_CDC_CAL_TIMER_CFG0 0x138
+#define SDCC_CSR_CDC_CAL_TIMER_CFG1 0x13C
+#define SDCC_CSR_CDC_REFCOUNT_CFG 0x140
+#define SDCC_CSR_CDC_COARSE_CAL_CFG 0x144
+#define SDCC_CSR_CDC_DELAY_CFG 0x150
+#define SDCC_CDC_OFFSET_CFG 0x14C
+#define SDCC_CDC_SLAVE_DDA_CFG 0x160
+#define SDCC_CSR_CDC_STATUS0 0x164
+
+/* DLL & CDC helper macros */
+#define SDCC_DLL_PWR_SAVE_EN BIT(1)
+#define SDCC_DLL_LOCK_STAT BIT(7)
+#define SDCC_DLL_EN BIT(16)
+#define SDCC_DLL_CDR_EN BIT(17)
+#define SDCC_DLL_CLK_OUT_EN BIT(18)
+#define SDCC_DLL_CDR_EXT_EN BIT(19)
+#define SDCC_DLL_PDN_EN BIT(29)
+#define SDCC_DLL_RESET_EN BIT(30)
+#define SDCC_DLL_CONFIG_MCLK_START 0x18
+#define SDCC_DLL_CONFIG_MCLK_WIDTH 0x3
+#define SDCC_DLL_GRAY_CODE_START 0x14
+#define SDCC_DLL_GRAY_CODE_WIDTH 0x4
+#define CMD_DAT_TRACK_SEL BIT(0)
+#define CDC_T4_DLY_SEL BIT(0)
+#define CDC_SWITCH_BYPASS_OFF BIT(0)
+#define CDC_SWITCH_RC_EN BIT(1)
+#define START_CDC_TRAFFIC BIT(6)
+#define FW_CLK_SW_RST_DIS BIT(13)
+#define CDC_SW_TRIGGER_FULL_CALIB BIT(16)
+#define CDC_HW_AUTO_CAL_EN BIT(17)
+#define CDC_TIMER_EN BIT(16)
+#define CSR_CDC_ERROR_MASK 0x7000000
+
+/* SDCC macros for HS400 */
+#define SDCC_HC_MCLK_SEL_HS400 0x3
+#define SDCC_HC_MCLK_HS400_START 0x8
+#define SDCC_HC_MCLK_HS400_WIDTH 0x2
+#define SDCC_HC_MCLK_SEL_IN_HS400 0x6
+#define SDCC_HC_MCLK_SEL_IN_DFLT 0x2
+#define SDCC_HC_MCLK_SEL_IN_UHS 0x4
+#define SDCC_HC_MCLK_SEL_IN_START 0x13
+#define SDCC_HC_MCLK_SEL_IN_WIDTH 0x3
+#define SDCC_HC_MCLK_SEL_IN_EN 0x1
+#define SDCC_HC_MCLK_SEL_IN_EN_START 0x12
+#define SDCC_HC_MCLK_SEL_IN_EN_WIDTH 0x1
+
+#define MAX_PHASES 16
+
+/* SDCC version macros */
+#define MCI_VERSION 0x50
+#define CORE_VERSION_MAJOR_MASK 0xF0000000
+#define CORE_VERSION_MAJOR_SHIFT 0x1C
+
struct sdhci_msm_data
{
uint32_t pwrctl_base;
uint32_t pwr_irq;
+ uint8_t tuning_done;
+ uint8_t calibration_done;
+ uint8_t saved_phase;
+ uint8_t slot;
event_t* sdhc_event;
};
-void sdhci_msm_init(struct sdhci_msm_data *data);
-
+void sdhci_msm_init(struct sdhci_host *host, struct sdhci_msm_data *data);
+uint32_t sdhci_msm_execute_tuning(struct sdhci_host *host, uint32_t bus_width);
+void sdhci_mode_disable(struct sdhci_host *host);
#endif
diff --git a/platform/msm_shared/include/shutdown_detect.h b/platform/msm_shared/include/shutdown_detect.h
new file mode 100644
index 0000000..23690c9
--- /dev/null
+++ b/platform/msm_shared/include/shutdown_detect.h
@@ -0,0 +1,33 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __PLATFORM_MSM_SHARED_SHUTDOWN_DETECT_H
+#define __PLATFORM_MSM_SHARED_SHUTDOWN_DETECT_H
+
+void shutdown_detect(void);
+#endif /* __PLATFORM_MSM_SHARED_SHUTDOWN_DETECT_H */
diff --git a/platform/msm_shared/mdp5.c b/platform/msm_shared/mdp5.c
index e1b3f77..2cbf408 100644
--- a/platform/msm_shared/mdp5.c
+++ b/platform/msm_shared/mdp5.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -124,12 +124,17 @@
* successfully unlocked. Ignore TZ return value till it's fixed */
if (!access_secure || 1) {
dprintf(SPEW, "MDSS VBIF registers unlocked by TZ.\n");
- /* Force VBIF Clocks on */
- writel(0x1, VBIF_VBIF_DDR_FORCE_CLK_ON);
- if (mdp_hw_rev == MDSS_MDP_HW_REV_100
- || mdp_hw_rev >= MDSS_MDP_HW_REV_102) {
- /* Configure DDR burst length */
+ /* Force VBIF Clocks on */
+ if (mdp_hw_rev < MDSS_MDP_HW_REV_103)
+ writel(0x1, VBIF_VBIF_DDR_FORCE_CLK_ON);
+
+ /*
+ * Following configuration is needed because on some versions,
+ * recommended reset values are not stored.
+ */
+ if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
+ MDSS_MDP_HW_REV_100)) {
writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST);
writel(0x00000030, VBIF_VBIF_DDR_ARB_CTRL );
writel(0x00000001, VBIF_VBIF_DDR_RND_RBN_QOS_ARB);
@@ -137,7 +142,8 @@
writel(0x0FFF0FFF, VBIF_VBIF_DDR_OUT_AX_AOOO);
writel(0x22222222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0);
writel(0x00002222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1);
- } else if (mdp_hw_rev >= MDSS_MDP_HW_REV_101) {
+ } else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
+ MDSS_MDP_HW_REV_101)) {
writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST);
writel(0x00000003, VBIF_VBIF_DDR_ARB_CTRL);
}
@@ -225,7 +231,7 @@
if (pinfo->lcdc.split_display) {
adjust_xres /= 2;
if (intf_base == MDP_INTF_1_BASE) {
- writel(BIT(8), MDP_TG_SINK);
+ writel(BIT(8), MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL);
writel(0x0, MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL);
writel(0x1, MDP_REG_SPLIT_DISPLAY_EN);
}
@@ -337,6 +343,27 @@
}
}
+void mdss_qos_remapper_setup(void)
+{
+ uint32_t mdp_hw_rev = readl(MDP_HW_REV);
+ uint32_t map;
+
+ if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_100) ||
+ MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
+ MDSS_MDP_HW_REV_102))
+ map = 0xE9;
+ else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
+ MDSS_MDP_HW_REV_101))
+ map = 0xA5;
+ else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
+ MDSS_MDP_HW_REV_103))
+ map = 0xFA;
+ else
+ return;
+
+ writel(map, MDP_QOS_REMAPPER_CLASS_0);
+}
+
int mdp_dsi_video_config(struct msm_panel_info *pinfo,
struct fbcon_config *fb)
{
@@ -354,7 +381,7 @@
mdss_vbif_setup();
mdss_smp_setup(pinfo);
- writel(0x0E9, MDP_QOS_REMAPPER_CLASS_0);
+ mdss_qos_remapper_setup();
mdss_rgb_pipe_config(fb, pinfo, MDP_VP_0_RGB_0_BASE);
if (pinfo->lcdc.dual_pipe)
@@ -390,7 +417,7 @@
mdss_vbif_setup();
mdss_smp_setup(pinfo);
- writel(0x0E9, MDP_QOS_REMAPPER_CLASS_0);
+ mdss_qos_remapper_setup();
mdss_rgb_pipe_config(fb, pinfo, MDP_VP_0_RGB_0_BASE);
if (pinfo->lcdc.dual_pipe)
@@ -416,6 +443,7 @@
int mdp_dsi_cmd_config(struct msm_panel_info *pinfo,
struct fbcon_config *fb)
{
+ uint32_t intf_sel = BIT(8);
int ret = NO_ERROR;
struct lcdc_panel_info *lcdc = NULL;
@@ -428,21 +456,38 @@
if (lcdc == NULL)
return ERR_INVALID_ARGS;
+ if (pinfo->lcdc.split_display) {
+ writel(0x102, MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL);
+ writel(0x2, MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL);
+ writel(0x1, MDP_REG_SPLIT_DISPLAY_EN);
+ }
+
mdss_mdp_intf_off = mdss_mdp_intf_offset();
mdp_clk_gating_ctrl();
- writel(0x0100, MDP_DISP_INTF_SEL);
+ if (pinfo->mipi.dual_dsi)
+ intf_sel |= BIT(16); /* INTF 2 enable */
+
+ writel(intf_sel, MDP_DISP_INTF_SEL);
mdss_vbif_setup();
mdss_smp_setup(pinfo);
+ mdss_qos_remapper_setup();
+
mdss_rgb_pipe_config(fb, pinfo, MDP_VP_0_RGB_0_BASE);
+ if (pinfo->lcdc.dual_pipe)
+ mdss_rgb_pipe_config(fb, pinfo, MDP_VP_0_RGB_1_BASE);
mdss_layer_mixer_setup(fb, pinfo);
writel(0x213F, MDP_INTF_1_BASE + MDP_PANEL_FORMAT + mdss_mdp_intf_off);
+ writel(0x21f20, MDP_CTL_0_BASE + CTL_TOP);
- writel(0x20020, MDP_CTL_0_BASE + CTL_TOP);
+ if (pinfo->mipi.dual_dsi) {
+ writel(0x213F, MDP_INTF_2_BASE + MDP_PANEL_FORMAT + mdss_mdp_intf_off);
+ writel(0x21F30, MDP_CTL_1_BASE + CTL_TOP);
+ }
return ret;
}
@@ -489,6 +534,7 @@
int mdp_dma_on(void)
{
writel(0x32048, MDP_CTL_0_BASE + CTL_FLUSH);
+ writel(0x32090, MDP_CTL_1_BASE + CTL_FLUSH);
writel(0x01, MDP_CTL_0_BASE + CTL_START);
return NO_ERROR;
}
diff --git a/platform/msm_shared/mipi_dsi.c b/platform/msm_shared/mipi_dsi.c
index 1962081..4b86359 100644
--- a/platform/msm_shared/mipi_dsi.c
+++ b/platform/msm_shared/mipi_dsi.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -415,7 +415,7 @@
return data;
}
-int mdss_dsi_panel_initialize(struct mipi_dsi_panel_config *pinfo, uint32_t
+int mdss_dsi_host_init(struct mipi_dsi_panel_config *pinfo, uint32_t
broadcast)
{
uint8_t DMA_STREAM1 = 0; // for mdp display processor path
@@ -425,7 +425,6 @@
uint8_t VC1 = 0;
uint8_t DT1 = 0; // non embedded mode
uint8_t WC1 = 0; // for non embedded mode only
- int status = 0;
uint8_t DLNx_EN;
uint8_t lane_swap = 0;
uint32_t timing_ctl = 0;
@@ -484,7 +483,17 @@
writel(lane_swap, MIPI_DSI0_BASE + LANE_SWAP_CTL);
writel(timing_ctl, MIPI_DSI0_BASE + TIMING_CTL);
+#endif
+ return 0;
+}
+
+int mdss_dsi_panel_initialize(struct mipi_dsi_panel_config *pinfo, uint32_t
+ broadcast)
+{
+ int status = 0;
+
+#if (DISPLAY_TYPE_MDSS == 1)
if (pinfo->panel_cmds) {
if (broadcast) {
@@ -1020,12 +1029,31 @@
if (pinfo->mipi.dual_dsi)
mdss_dsi_phy_init(&mipi_pinfo, MIPI_DSI1_BASE);
- ret += mdss_dsi_panel_initialize(&mipi_pinfo, pinfo->mipi.broadcast);
+ ret = mdss_dsi_host_init(&mipi_pinfo, pinfo->mipi.broadcast);
+ if (ret) {
+ dprintf(CRITICAL, "dsi host init error\n");
+ goto error;
+ }
+
+ if (panel->pre_init_func) {
+ ret = panel->pre_init_func();
+ if (ret) {
+ dprintf(CRITICAL, "pre_init_func error\n");
+ goto error;
+ }
+ }
+
+ ret = mdss_dsi_panel_initialize(&mipi_pinfo, pinfo->mipi.broadcast);
+ if (ret) {
+ dprintf(CRITICAL, "dsi panel init error\n");
+ goto error;
+ }
if (pinfo->rotate && panel->rotate)
pinfo->rotate();
#endif
+error:
return ret;
}
@@ -1129,7 +1157,8 @@
uint16_t dst_format,
uint8_t ystride,
uint8_t lane_en,
- uint8_t interleav)
+ uint8_t interleav,
+ uint32_t ctl_base)
{
uint16_t dst_fmt = 0;
@@ -1150,36 +1179,36 @@
}
#if (DISPLAY_TYPE_MDSS == 1)
- writel(0x00000000, DSI_CLK_CTRL);
- writel(0x00000000, DSI_CLK_CTRL);
- writel(0x00000000, DSI_CLK_CTRL);
- writel(0x00000000, DSI_CLK_CTRL);
- writel(0x00000002, DSI_CLK_CTRL);
- writel(0x00000006, DSI_CLK_CTRL);
- writel(0x0000000e, DSI_CLK_CTRL);
- writel(0x0000001e, DSI_CLK_CTRL);
- writel(0x0000023f, DSI_CLK_CTRL);
+ writel(0x00000000, ctl_base + CLK_CTRL);
+ writel(0x00000000, ctl_base + CLK_CTRL);
+ writel(0x00000000, ctl_base + CLK_CTRL);
+ writel(0x00000000, ctl_base + CLK_CTRL);
+ writel(0x00000002, ctl_base + CLK_CTRL);
+ writel(0x00000006, ctl_base + CLK_CTRL);
+ writel(0x0000000e, ctl_base + CLK_CTRL);
+ writel(0x0000001e, ctl_base + CLK_CTRL);
+ writel(0x0000023f, ctl_base + CLK_CTRL);
- writel(0, DSI_CTRL);
+ writel(0, ctl_base + CTRL);
- writel(0, DSI_ERR_INT_MASK0);
+ writel(0, ctl_base + ERR_INT_MASK0);
- writel(0x02020202, DSI_INT_CTRL);
+ writel(0x02020202, ctl_base + INT_CTRL);
- writel(dst_fmt, DSI_COMMAND_MODE_MDP_CTRL);
+ writel(dst_fmt, ctl_base + COMMAND_MODE_MDP_CTRL);
writel((img_width * ystride + 1) << 16 | 0x0039,
- DSI_COMMAND_MODE_MDP_STREAM0_CTRL);
+ ctl_base + COMMAND_MODE_MDP_STREAM0_CTRL);
writel((img_width * ystride + 1) << 16 | 0x0039,
- DSI_COMMAND_MODE_MDP_STREAM1_CTRL);
+ ctl_base + COMMAND_MODE_MDP_STREAM1_CTRL);
writel(img_height << 16 | img_width,
- DSI_COMMAND_MODE_MDP_STREAM0_TOTAL);
+ ctl_base + COMMAND_MODE_MDP_STREAM0_TOTAL);
writel(img_height << 16 | img_width,
- DSI_COMMAND_MODE_MDP_STREAM1_TOTAL);
- writel(0x13c2c, DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL);
+ ctl_base + COMMAND_MODE_MDP_STREAM1_TOTAL);
+ writel(0x13c2c, ctl_base + COMMAND_MODE_MDP_DCS_CMD_CTRL);
writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4 | 0x105,
- DSI_CTRL);
- writel(0x10000000, DSI_COMMAND_MODE_DMA_CTRL);
- writel(0x10000000, DSI_MISR_CMD_CTRL);
+ ctl_base + CTRL);
+ writel(0x10000000, ctl_base + COMMAND_MODE_DMA_CTRL);
+ writel(0x10000000, ctl_base + MISR_CMD_CTRL);
#endif
return 0;
diff --git a/platform/msm_shared/mmc.c b/platform/msm_shared/mmc.c
index 25d619c..f62d407 100644
--- a/platform/msm_shared/mmc.c
+++ b/platform/msm_shared/mmc.c
@@ -2554,7 +2554,7 @@
sizeof(struct mmc_boot_command));
/* Disabling PERM_WP for USER AREA (CMD6) */
- mmc_ret = mmc_boot_switch_cmd(card, MMC_BOOT_ACCESS_WRITE,
+ mmc_ret = mmc_boot_switch_cmd(card, MMC_BOOT_SET_BIT,
MMC_BOOT_EXT_USER_WP,
MMC_BOOT_US_PERM_WP_DIS);
@@ -2601,8 +2601,7 @@
}
/* Setting POWER_ON_WP for USER AREA (CMD6) */
-
- mmc_ret = mmc_boot_switch_cmd(card, MMC_BOOT_ACCESS_WRITE,
+ mmc_ret = mmc_boot_switch_cmd(card, MMC_BOOT_SET_BIT,
MMC_BOOT_EXT_USER_WP,
MMC_BOOT_US_PWR_WP_EN);
@@ -2685,13 +2684,29 @@
unsigned int rc = MMC_BOOT_E_SUCCESS;
/* Checking whether group write protection feature is available */
- if (mmc_card.csd.wp_grp_enable) {
+ if (mmc_card.csd.wp_grp_enable)
+ {
rc = mmc_boot_get_wp_status(&mmc_card, sector);
+ if (rc != MMC_BOOT_E_SUCCESS)
+ {
+ dprintf(CRITICAL, "Failure in getting wp_status (%u):%s:%u\n", rc, __FILE__, __LINE__);
+ return rc;
+ }
rc = mmc_boot_set_clr_power_on_wp_user(&mmc_card, sector, size,
set_clear_wp);
+ if (rc != MMC_BOOT_E_SUCCESS)
+ {
+ dprintf(CRITICAL, "Failure in setting power on wp user (%u):%s:%u\n", rc, __FILE__, __LINE__);
+ return rc;
+ }
rc = mmc_boot_get_wp_status(&mmc_card, sector);
- return rc;
- } else
+ if (rc != MMC_BOOT_E_SUCCESS)
+ {
+ dprintf(CRITICAL, "Failure in getting wp_status (%u)%s:%u\n", rc, __FILE__, __LINE__);
+ return rc;
+ }
+ }
+ else
return MMC_BOOT_E_FAILURE;
}
diff --git a/platform/msm_shared/mmc_sdhci.c b/platform/msm_shared/mmc_sdhci.c
index de3db2b..0883c53 100644
--- a/platform/msm_shared/mmc_sdhci.c
+++ b/platform/msm_shared/mmc_sdhci.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -768,9 +768,23 @@
/*
- * Function: mmc card supports ddr mode
+ * Function: mmc card supports hs400 mode
* Arg : None
- * Return : 1 if DDR mode is supported, 0 otherwise
+ * Return : 1 if hs400 mode is supported, 0 otherwise
+ * Flow : Check the ext csd attributes of the card
+ */
+static uint8_t mmc_card_supports_hs400_mode(struct mmc_card *card)
+{
+ if (card->ext_csd[MMC_DEVICE_TYPE] & MMC_HS_HS400_MODE)
+ return 1;
+ else
+ return 0;
+}
+
+/*
+ * Function: mmc card supports hs200 mode
+ * Arg : None
+ * Return : 1 if HS200 mode is supported, 0 otherwise
* Flow : Check the ext csd attributes of the card
*/
static uint8_t mmc_card_supports_hs200_mode(struct mmc_card *card)
@@ -824,8 +838,25 @@
return mmc_ret;
}
- /* Enable hs200 mode in controller */
- sdhci_set_sdr_mode(host);
+ /* Enable SDR104 mode in controller */
+ sdhci_set_uhs_mode(host, SDHCI_SDR104_MODE);
+
+ /* Run the clock @ 400 Mhz */
+ if (host->caps.hs400_support && mmc_card_supports_hs400_mode(card))
+ {
+ clock_config_mmc(host->msm_host->slot, SDHCI_CLK_400MHZ);
+ /* Save the timing value, before changing the clock */
+ MMC_SAVE_TIMING(host, MMC_HS400_TIMING);
+ }
+ else
+ {
+ /* Save the timing value, before changing the clock */
+ MMC_SAVE_TIMING(host, MMC_HS200_TIMING);
+ }
+
+ /* Execute Tuning for hs200 mode */
+ if ((mmc_ret = sdhci_msm_execute_tuning(host, width)))
+ dprintf(CRITICAL, "Tuning for hs200 failed\n");
return mmc_ret;
}
@@ -849,7 +880,11 @@
return mmc_ret;
}
- sdhci_set_ddr_mode(host);
+ /* Save the timing value, before changing the clock */
+ MMC_SAVE_TIMING(host, SDHCI_DDR50_MODE);
+
+ /* Set the DDR mode in controller */
+ sdhci_set_uhs_mode(host, SDHCI_DDR50_MODE);
return 0;
}
@@ -875,10 +910,98 @@
return mmc_ret;
}
+ /* Save the timing value, before changing the clock */
+ MMC_SAVE_TIMING(host, SDHCI_SDR25_MODE);
+
+ /* Set the SDR25 mode in controller */
+ sdhci_set_uhs_mode(host, SDHCI_SDR25_MODE);
+
return 0;
}
/*
+ * Function : Enable HS400 mode
+ * Arg : Host, card structure and bus width
+ * Return : 0 on Success, 1 on Failure
+ * Flow :
+ * - Set the bus width to 8 bit DDR
+ * - Set the HS_TIMING on ext_csd 185 for the card
+ */
+uint32_t mmc_set_hs400_mode(struct sdhci_host *host,
+ struct mmc_card *card, uint32_t width)
+{
+ uint32_t mmc_ret = 0;
+
+ /*
+ * Emmc 5.0 spec does not allow changing to hs400 mode directly
+ * Need to follow the sequence to change to hs400 mode
+ * 1. Enable HS200 mode, perform tuning
+ * 2. Change to high speed mode
+ * 3. Enable DDR mode
+ * 4. Enable HS400 mode & execute tuning
+ */
+
+ /* HS400 mode is supported only in DDR 8-bit */
+ if (width != DATA_BUS_WIDTH_8BIT)
+ {
+ dprintf(CRITICAL, "Bus width is not 8-bit, cannot switch to hs400: %u\n", width);
+ return 1;
+ }
+
+ /* 1.Enable HS200 mode */
+ mmc_ret = mmc_set_hs200_mode(host, card, width);
+
+ if (mmc_ret)
+ {
+ dprintf(CRITICAL, "Failure Setting HS200 mode %s\t%d\n",__func__, __LINE__);
+ return mmc_ret;
+ }
+
+ /* 2. Enable High speed mode */
+ /* This is needed to set the clock to a low value &
+ * so that we can switch to hs_timing --> 0x1 */
+ /* Save the timing value, before changing the clock */
+ MMC_SAVE_TIMING(host, SDHCI_SDR12_MODE);
+ sdhci_set_uhs_mode(host, SDHCI_SDR12_MODE);
+
+ /* 3. Set HS_TIMING to 0x1 */
+ mmc_ret = mmc_set_hs_interface(host, card);
+ if (mmc_ret)
+ {
+ dprintf(CRITICAL, "Error adjusting interface speed!:%s\t%d\n", __func__, __LINE__);
+ return mmc_ret;
+ }
+
+ /*4. Enable DDR mode */
+ mmc_ret = mmc_set_ddr_mode(host, card);
+ if (mmc_ret)
+ {
+ dprintf(CRITICAL, "Failure setting DDR mode:%s\t%d\n", __func__, __LINE__);
+ return mmc_ret;
+ }
+
+ /*5. Set hs400 timing */
+ mmc_ret = mmc_switch_cmd(host, card, MMC_ACCESS_WRITE, MMC_EXT_MMC_HS_TIMING, MMC_HS400_TIMING);
+
+ if (mmc_ret)
+ {
+ dprintf(CRITICAL, "Switch cmd returned failure %s\t%d\n",__func__, __LINE__);
+ return mmc_ret;
+ }
+
+ /* 6. Enable SDR104 mode in controller */
+ /* Save the timing value, before changing the clock */
+ MMC_SAVE_TIMING(host, MMC_HS400_TIMING);
+ sdhci_set_uhs_mode(host, SDHCI_SDR104_MODE);
+
+ /* 7. Execute Tuning for hs400 mode */
+ if ((mmc_ret = sdhci_msm_execute_tuning(host, width)))
+ dprintf(CRITICAL, "Tuning for hs400 failed\n");
+
+ return mmc_ret;
+}
+
+/*
* Function: mmc_host_init
* Arg : mmc device structure
* Return : 0 on success, 1 on Failure
@@ -891,7 +1014,7 @@
struct sdhci_host *host;
struct mmc_config_data *cfg;
- struct sdhci_msm_data data;
+ struct sdhci_msm_data *data;
event_t sdhc_event;
@@ -903,9 +1026,15 @@
host->base = cfg->sdhc_base;
host->sdhc_event = &sdhc_event;
- data.sdhc_event = &sdhc_event;
- data.pwrctl_base = cfg->pwrctl_base;
- data.pwr_irq = cfg->pwr_irq;
+ data = (struct sdhci_msm_data *) malloc(sizeof(struct sdhci_msm_data));
+ ASSERT(data);
+
+ data->sdhc_event = &sdhc_event;
+ data->pwrctl_base = cfg->pwrctl_base;
+ data->pwr_irq = cfg->pwr_irq;
+ data->slot = cfg->slot;
+
+ host->msm_host = data;
/* Initialize any clocks needed for SDC controller */
clock_init_mmc(cfg->slot);
@@ -915,7 +1044,7 @@
/*
* MSM specific sdhc init
*/
- sdhci_msm_init(&data);
+ sdhci_msm_init(host, data);
/*
* Initialize the controller, read the host capabilities
@@ -1261,6 +1390,9 @@
if (sdhci_send_command(host, &cmd))
return 1;
+ /* Set the SDR25 mode in controller*/
+ sdhci_set_uhs_mode(host, SDHCI_SDR25_MODE);
+
return 0;
}
@@ -1330,9 +1462,6 @@
}
}
- /* Set the sdcc clock to 50 MHZ */
- sdhci_clk_supply(host, SDHCI_CLK_50MHZ);
-
/* Now get the extended CSD for the card */
if (MMC_CARD_MMC(card))
{
@@ -1391,11 +1520,23 @@
}
/* Enable high speed mode in the follwing order:
+ * 1. HS400 mode if supported by host & card
* 1. HS200 mode if supported by host & card
* 2. DDR mode host, if supported by host & card
* 3. Use normal speed mode with supported bus width
*/
- if (mmc_card_supports_hs200_mode(card) && host->caps.sdr50_support) {
+ if (host->caps.hs400_support && mmc_card_supports_hs400_mode(card))
+ {
+ mmc_return = mmc_set_hs400_mode(host, card, bus_width);
+ if (mmc_return)
+ {
+ dprintf(CRITICAL, "Failure to set HS400 mode for Card(RCA:%x)\n",
+ card->rca);
+ return mmc_return;
+ }
+ }
+ else if (host->caps.sdr104_support && mmc_card_supports_hs200_mode(card))
+ {
mmc_return = mmc_set_hs200_mode(host, card, bus_width);
if (mmc_return) {
@@ -1403,7 +1544,7 @@
card->rca);
return mmc_return;
}
- } else if (mmc_card_supports_ddr_mode(card) && host->caps.ddr_support) {
+ } else if (host->caps.ddr_support && mmc_card_supports_ddr_mode(card)) {
mmc_return = mmc_set_ddr_mode(host, card);
if (mmc_return) {
@@ -1537,6 +1678,7 @@
{
uint32_t mmc_ret = 0;
struct mmc_command cmd;
+ struct mmc_card *card = &dev->card;
memset((struct mmc_command *)&cmd, 0, sizeof(struct mmc_command));
@@ -1553,8 +1695,19 @@
cmd.resp_type = SDHCI_CMD_RESP_R1;
cmd.trans_mode = SDHCI_MMC_READ;
cmd.data_present = 0x1;
- /* Use CMD23 If card supports cMD23 */
- cmd.cmd23_support = dev->card.scr.cmd23_support;
+
+ /* Use CMD23 If card supports CMD23:
+ * For SD card use the value read from SCR register
+ * For emmc by default use CMD23.
+ * Also as per SDCC spec always use CMD23 to stop
+ * multiblock read/write if UHS (Ultra High Speed) is
+ * enabled
+ */
+ if (MMC_CARD_SD(card))
+ cmd.cmd23_support = dev->card.scr.cmd23_support;
+ else
+ cmd.cmd23_support = 0x1;
+
cmd.data.data_ptr = dest;
cmd.data.num_blocks = num_blocks;
@@ -1596,6 +1749,7 @@
{
uint32_t mmc_ret = 0;
struct mmc_command cmd;
+ struct mmc_card *card = &dev->card;
memset((struct mmc_command *)&cmd, 0, sizeof(struct mmc_command));
@@ -1612,8 +1766,19 @@
cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL;
cmd.resp_type = SDHCI_CMD_RESP_R1;
cmd.trans_mode = SDHCI_MMC_WRITE;
- /* Use CMD23 If card supports cMD23 */
- cmd.cmd23_support = dev->card.scr.cmd23_support;
+
+ /* Use CMD23 If card supports CMD23:
+ * For SD card use the value read from SCR register
+ * For emmc by default use CMD23.
+ * Also as per SDCC spec always use CMD23 to stop
+ * multiblock read/write if UHS (Ultra High Speed) is
+ * enabled
+ */
+ if (MMC_CARD_SD(card))
+ cmd.cmd23_support = dev->card.scr.cmd23_support;
+ else
+ cmd.cmd23_support = 0x1;
+
cmd.data_present = 0x1;
cmd.data.data_ptr = src;
cmd.data.num_blocks = num_blocks;
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index 7f48e01..632de53 100755
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -132,7 +132,8 @@
$(LOCAL_DIR)/crypto5_wrapper.o \
$(LOCAL_DIR)/dev_tree.o \
$(LOCAL_DIR)/gpio.o \
- $(LOCAL_DIR)/dload_util.o
+ $(LOCAL_DIR)/dload_util.o \
+ $(LOCAL_DIR)/shutdown_detect.o
endif
ifeq ($(PLATFORM),mpq8092)
diff --git a/platform/msm_shared/scm.c b/platform/msm_shared/scm.c
index 8adc0d2..5592f20 100644
--- a/platform/msm_shared/scm.c
+++ b/platform/msm_shared/scm.c
@@ -29,6 +29,8 @@
#include <stdlib.h>
#include <string.h>
#include <err.h>
+#include <asm.h>
+#include <bits.h>
#include <arch/ops.h>
#include "scm.h"
@@ -41,6 +43,14 @@
# define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
#endif
+#define SCM_CLASS_REGISTER (0x2 << 8)
+#define SCM_MASK_IRQS BIT(5)
+#define SCM_ATOMIC(svc, cmd, n) ((((((svc) & 0x3f) << 10)|((cmd) & 0x3ff)) << 12) | \
+ SCM_CLASS_REGISTER | \
+ SCM_MASK_IRQS | \
+ ((n) & 0xf))
+
+
/**
* alloc_scm_command() - Allocate an SCM command
* @cmd_size: size of the command buffer
@@ -122,6 +132,32 @@
}
/**
+* scm_call_automic: Make scm call with one or no argument
+* @svc: service id
+* @cmd: command id
+* @ arg1: argument
+*/
+
+static int scm_call_atomic(uint32_t svc, uint32_t cmd, uint32_t arg1)
+{
+ uint32_t context_id;
+ register uint32_t r0 __asm__("r0") = SCM_ATOMIC(svc, cmd, 1);
+ register uint32_t r1 __asm__("r1") = &context_id;
+ register uint32_t r2 __asm__("r2") = arg1;
+
+ __asm__ volatile(
+ __asmeq("%0", "r0")
+ __asmeq("%1", "r0")
+ __asmeq("%2", "r1")
+ __asmeq("%3", "r2")
+ "smc #0 @ switch to secure world\n"
+ : "=r" (r0)
+ : "r" (r0), "r" (r1), "r" (r2)
+ : "r3");
+ return r0;
+}
+
+/**
* scm_call() - Send an SCM command
* @svc_id: service identifier
* @cmd_id: command identifier
@@ -561,3 +597,11 @@
return resp_buf;
}
+int scm_halt_pmic_arbiter()
+{
+ int ret = 0;
+
+ ret = scm_call_atomic(SCM_SVC_PWR, SCM_IO_DISABLE_PMIC_ARBITER, 0);
+
+ return ret;
+}
diff --git a/platform/msm_shared/sdhci.c b/platform/msm_shared/sdhci.c
index 4399c60..547f4ec 100644
--- a/platform/msm_shared/sdhci.c
+++ b/platform/msm_shared/sdhci.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -37,7 +37,7 @@
#include <bits.h>
#include <debug.h>
#include <sdhci.h>
-
+#include <sdhci_msm.h>
/*
* Function: sdhci reset
@@ -45,7 +45,7 @@
* Return : None
* Flow: : Reset the host controller
*/
-static void sdhci_reset(struct sdhci_host *host, uint8_t mask)
+void sdhci_reset(struct sdhci_host *host, uint8_t mask)
{
uint32_t reg;
uint32_t timeout = SDHCI_RESET_MAX_TIMEOUT;
@@ -102,12 +102,7 @@
uint32_t freq = 0;
uint16_t clk_val = 0;
- if (clk > host->caps.base_clk_rate) {
- dprintf(CRITICAL, "Error: Requested clk freq is more than supported\n");
- return 1;
- }
-
- if (clk == host->caps.base_clk_rate)
+ if (clk >= host->caps.base_clk_rate)
goto clk_ctrl;
/* As per the sd spec div should be a multiplier of 2 */
@@ -141,7 +136,7 @@
clk_val |= SDHCI_CLK_EN;
REG_WRITE16(host, clk_val, SDHCI_CLK_CTRL_REG);
- host->cur_clk_rate = freq;
+ host->cur_clk_rate = clk;
return 0;
}
@@ -212,58 +207,23 @@
}
+
/*
* Function: sdhci set SDR mode
- * Arg : Host structure
+ * Arg : Host structure, UHS mode
* Return : None
* Flow: : 1. Disable the clock
- * 2. Enable sdr mode
+ * 2. Enable UHS mode
* 3. Enable the clock
* Details : SDR50/SDR104 mode is nothing but HS200
* mode SDCC spec refers to it as SDR mode
* & emmc spec refers as HS200 mode.
*/
-void sdhci_set_sdr_mode(struct sdhci_host *host)
+void sdhci_set_uhs_mode(struct sdhci_host *host, uint32_t mode)
{
uint16_t clk;
uint16_t ctrl = 0;
-
- /* Disable the clock */
- clk = REG_READ16(host, SDHCI_CLK_CTRL_REG);
- clk &= ~SDHCI_CLK_EN;
- REG_WRITE16(host, clk, SDHCI_CLK_CTRL_REG);
-
- /* Enable SDR50 mode:
- * Right now we support only SDR50 mode which runs at
- * 100 MHZ sdcc clock, we dont need tuning with SDR50
- * mode
- */
- ctrl = REG_READ16(host, SDHCI_HOST_CTRL2_REG);
-
- /* Enable SDR50/SDR104 mode based on the controller
- * capabilities.
- */
- if (host->caps.sdr50_support)
- ctrl |= SDHCI_SDR50_MODE_EN;
-
- REG_WRITE16(host, ctrl, SDHCI_HOST_CTRL2_REG);
-
- /* Run the clock back */
- sdhci_clk_supply(host, SDHCI_CLK_100MHZ);
-}
-
-/*
- * Function: sdhci set ddr mode
- * Arg : Host structure
- * Return : None
- * Flow: : 1. Disable the clock
- * 2. Enable DDR mode
- * 3. Enable the clock
- */
-void sdhci_set_ddr_mode(struct sdhci_host *host)
-{
- uint16_t clk;
- uint16_t ctrl = 0;
+ uint32_t clk_val = 0;
/* Disable the clock */
clk = REG_READ16(host, SDHCI_CLK_CTRL_REG);
@@ -271,13 +231,48 @@
REG_WRITE16(host, clk, SDHCI_CLK_CTRL_REG);
ctrl = REG_READ16(host, SDHCI_HOST_CTRL2_REG);
- ctrl |= SDHCI_DDR_MODE_EN;
- /* Enalbe DDR mode */
+ ctrl &= ~SDHCI_UHS_MODE_MASK;
+
+ /* Enable SDR50/SDR104/DDR50 mode */
+ switch (mode)
+ {
+ case SDHCI_SDR104_MODE:
+ ctrl |= SDHCI_SDR104_MODE_EN;
+ clk_val = SDHCI_CLK_200MHZ;
+ break;
+ case SDHCI_SDR50_MODE:
+ ctrl |= SDHCI_SDR50_MODE_EN;
+ clk_val = SDHCI_CLK_100MHZ;
+ break;
+ case SDHCI_DDR50_MODE:
+ ctrl |= SDHCI_DDR50_MODE_EN;
+ clk_val = SDHCI_CLK_50MHZ;
+ break;
+ case SDHCI_SDR25_MODE:
+ ctrl |= SDHCI_SDR25_MODE_EN;
+ clk_val = SDHCI_CLK_50MHZ;
+ break;
+ case SDHCI_SDR12_MODE_EN:
+ ctrl |= SDHCI_SDR12_MODE_EN;
+ clk_val = SDHCI_CLK_25MHZ;
+ break;
+ default:
+ dprintf(CRITICAL, "Error: Invalid UHS mode: %x\n", mode);
+ ASSERT(0);
+ };
+
REG_WRITE16(host, ctrl, SDHCI_HOST_CTRL2_REG);
+ /*
+ * SDHC spec does not have matching UHS mode
+ * So we use Vendor specific registers to enable
+ * HS400 mode
+ */
+ sdhci_msm_set_mci_clk(host);
+
/* Run the clock back */
- sdhci_clk_supply(host, host->cur_clk_rate);
+ sdhci_clk_supply(host, clk_val);
}
/*
@@ -388,6 +383,7 @@
uint32_t retry = 0;
uint32_t int_status;
uint32_t trans_complete = 0;
+ uint32_t err_status;
do {
int_status = REG_READ16(host, SDHCI_NRML_INT_STS_REG);
@@ -444,6 +440,20 @@
break;
}
+ /*
+ * If we are in tuning then we need to wait until Data timeout , Data end
+ * or Data CRC error
+ */
+ if (host->tuning_in_progress)
+ {
+ err_status = REG_READ16(host, SDHCI_ERR_INT_STS_REG);
+ if ((err_status & SDHCI_DAT_TIMEOUT_MASK) || (err_status & SDHCI_DAT_CRC_MASK))
+ {
+ sdhci_reset(host, (SOFT_RESET_CMD | SOFT_RESET_DATA));
+ return 0;
+ }
+ }
+
retry++;
udelay(1000);
if (retry == SDHCI_MAX_TRANS_RETRY) {
@@ -789,11 +799,7 @@
void sdhci_init(struct sdhci_host *host)
{
uint32_t caps[2];
-
- /*
- * Reset the controller
- */
- sdhci_reset(host, SDHCI_SOFT_RESET);
+ uint8_t sdcc_version = 0;
/* Read the capabilities register & store the info */
caps[0] = REG_READ32(host, SDHCI_CAPS_REG1);
@@ -822,11 +828,22 @@
host->caps.voltage = SDHCI_VOL_1_8;
/* DDR mode support */
- host->caps.ddr_support = (caps[1] & SDHCI_DDR_MODE_MASK) ? 1 : 0;
+ host->caps.ddr_support = (caps[1] & SDHCI_DDR50_MODE_MASK) ? 1 : 0;
/* SDR50 mode support */
host->caps.sdr50_support = (caps[1] & SDHCI_SDR50_MODE_MASK) ? 1 : 0;
+ /* SDR104 mode support */
+ host->caps.sdr104_support = (caps[1] & SDHCI_SDR104_MODE_MASK) ? 1 : 0;
+
+ /* HS400 mode support:
+ * The last four bits of MCI_VERSION indicate the SDCC major version
+ * Version 0 --> SDCC4 core
+ * Version >= 1 --> SDCC5 or above core
+ */
+ sdcc_version = ((readl(host->msm_host->pwrctl_base + MCI_VERSION)) & CORE_VERSION_MAJOR_MASK) >> CORE_VERSION_MAJOR_SHIFT;
+ host->caps.hs400_support = (sdcc_version >= 1) ? 1 : 0;
+
/* Set bus power on */
sdhci_set_bus_power_on(host);
diff --git a/platform/msm_shared/sdhci_msm.c b/platform/msm_shared/sdhci_msm.c
index 1b6c8b0..8677dbe 100644
--- a/platform/msm_shared/sdhci_msm.c
+++ b/platform/msm_shared/sdhci_msm.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -30,14 +30,38 @@
#include <platform/irqs.h>
#include <platform/interrupts.h>
#include <platform/timer.h>
+#include <sys/types.h>
#include <target.h>
#include <string.h>
#include <stdlib.h>
#include <bits.h>
#include <debug.h>
+#include <mmc.h>
#include <sdhci.h>
#include <sdhci_msm.h>
+/* Known data stored in the card & read during tuning
+ * process. 64 bytes for 4bit bus width & 128 bytes
+ * of data for 8 bit bus width.
+ * These values are derived from HPG
+ */
+static const uint32_t tuning_block_64[] = {
+ 0x00FF0FFF, 0xCCC3CCFF, 0xFFCC3CC3, 0xEFFEFFFE,
+ 0xDDFFDFFF, 0xFBFFFBFF, 0xFF7FFFBF, 0xEFBDF777,
+ 0xF0FFF0FF, 0x3CCCFC0F, 0xCFCC33CC, 0xEEFFEFFF,
+ 0xFDFFFDFF, 0xFFBFFFDF, 0xFFF7FFBB, 0xDE7B7FF7
+};
+
+static const uint32_t tuning_block_128[] = {
+ 0xFF00FFFF, 0x0000FFFF, 0xCCCCFFFF, 0xCCCC33CC,
+ 0xCC3333CC, 0xFFFFCCCC, 0xFFFFEEFF, 0xFFEEEEFF,
+ 0xFFDDFFFF, 0xDDDDFFFF, 0xBBFFFFFF, 0xBBFFFFFF,
+ 0xFFFFFFBB, 0xFFFFFF77, 0x77FF7777, 0xFFEEDDBB,
+ 0x00FFFFFF, 0x00FFFFFF, 0xCCFFFF00, 0xCC33CCCC,
+ 0x3333CCCC, 0xFFCCCCCC, 0xFFEEFFFF, 0xEEEEFFFF,
+ 0xDDFFFFFF, 0xDDFFFFFF, 0xFFFFFFDD, 0xFFFFFFBB,
+ 0xFFFFBBBB, 0xFFFF77FF, 0xFF7777FF, 0xEEDDBB77
+};
/*
* Function: sdhci int handler
@@ -113,12 +137,26 @@
* Return : None
* Flow: : Enable sdhci mode & do msm specific init
*/
-void sdhci_msm_init(struct sdhci_msm_data *config)
+void sdhci_msm_init(struct sdhci_host *host, struct sdhci_msm_data *config)
{
+ /* Disable HC mode */
+ RMWREG32((config->pwrctl_base + SDCC_MCI_HC_MODE), SDHCI_HC_START_BIT, SDHCI_HC_WIDTH, 0);
+
+ /* Core power reset */
+ RMWREG32((config->pwrctl_base + SDCC_MCI_POWER), CORE_SW_RST_START, CORE_SW_RST_WIDTH, 1);
+
+ /* Wait for the core power reset to complete*/
+ mdelay(1);
+
/* Enable sdhc mode */
writel(SDHCI_HC_MODE_EN, (config->pwrctl_base + SDCC_MCI_HC_MODE));
/*
+ * Reset the controller
+ */
+ sdhci_reset(host, SDHCI_SOFT_RESET);
+
+ /*
* CORE_SW_RST may trigger power irq if previous status of PWRCTL
* was either BUS_ON or IO_HIGH. So before we enable the power irq
* interrupt in GIC (by registering the interrupt handler), we need to
@@ -136,4 +174,462 @@
/* Enable pwr control interrupt */
writel(SDCC_HC_PWR_CTRL_INT, (config->pwrctl_base + SDCC_HC_PWRCTL_MASK_REG));
+
+ config->tuning_done = false;
+ config->calibration_done = false;
+ host->tuning_in_progress = false;
}
+
+/*
+ * Function: sdhci msm set mci clk
+ * Arg : Host structure
+ * Return : None
+ * Flow: : Set HC_SELECT & HC_SELECT_EN for hs400
+ */
+void sdhci_msm_set_mci_clk(struct sdhci_host *host)
+{
+ struct sdhci_msm_data *msm_host;
+
+ msm_host = host->msm_host;
+
+ if (host->timing == MMC_HS400_TIMING)
+ {
+ /*
+ * If the current tuning mode is HS400 then we should set the MCLK to run
+ * the clock @ MCLK/2. Also set HS400 mode in SELECT_IN of vendor specific
+ * register
+ */
+ REG_RMW32(host, SDCC_VENDOR_SPECIFIC_FUNC, SDCC_HC_MCLK_HS400_START, SDCC_HC_MCLK_HS400_WIDTH, SDCC_HC_MCLK_SEL_HS400);
+
+ /* Enable HS400 mode from HC_SELECT_IN bit of VENDOR_SPEC register
+ * As the SDCC spec does not have matching mode for HS400
+ */
+ if (msm_host->tuning_done && !msm_host->calibration_done)
+ {
+ REG_RMW32(host, SDCC_VENDOR_SPECIFIC_FUNC, SDCC_HC_MCLK_SEL_IN_START, SDCC_HC_MCLK_SEL_IN_WIDTH, SDCC_HC_MCLK_SEL_IN_HS400);
+ REG_RMW32(host, SDCC_VENDOR_SPECIFIC_FUNC, SDCC_HC_MCLK_SEL_IN_EN_START, SDCC_HC_MCLK_SEL_IN_EN_WIDTH, SDCC_HC_MCLK_SEL_IN_EN);
+ }
+ }
+ else
+ {
+ /*
+ * Set 0x0 mode in SELECT_IN of vendor specific register so that the
+ * host control2 register settings from sdhc spec are used for
+ * speed mode
+ */
+ REG_RMW32(host, SDCC_VENDOR_SPECIFIC_FUNC, SDCC_HC_MCLK_SEL_IN_START, SDCC_HC_MCLK_SEL_IN_WIDTH, 0x0);
+ REG_RMW32(host, SDCC_VENDOR_SPECIFIC_FUNC, SDCC_HC_MCLK_SEL_IN_EN_START, SDCC_HC_MCLK_SEL_IN_EN_WIDTH, 0x0);
+ }
+}
+
+/*
+ * Set the value based on sdcc clock frequency
+ */
+static void msm_set_dll_freq(struct sdhci_host *host)
+{
+ uint32_t reg_val = 0;
+
+ /* Set clock freq value based on clock range */
+ if (host->cur_clk_rate <= 112000000)
+ reg_val = 0x0;
+ else if (host->cur_clk_rate <= 125000000)
+ reg_val = 0x1;
+ else if (host->cur_clk_rate <= 137000000)
+ reg_val = 0x2;
+ else if (host->cur_clk_rate <= 150000000)
+ reg_val = 0x3;
+ else if (host->cur_clk_rate <= 162000000)
+ reg_val = 0x4;
+ else if (host->cur_clk_rate <= 175000000)
+ reg_val = 0x5;
+ else if (host->cur_clk_rate <= 187000000)
+ reg_val = 0x6;
+ else if (host->cur_clk_rate <= 200000000)
+ reg_val = 0x7;
+
+ REG_RMW32(host, SDCC_DLL_CONFIG_REG, SDCC_DLL_CONFIG_MCLK_START, SDCC_DLL_CONFIG_MCLK_WIDTH, reg_val);
+}
+
+/* Initialize DLL (Programmable Delay Line) */
+static void sdhci_msm_init_dll(struct sdhci_host *host)
+{
+ uint32_t pwr_save = 0;
+
+ pwr_save = REG_READ32(host, SDCC_VENDOR_SPECIFIC_FUNC) & SDCC_DLL_PWR_SAVE_EN;
+
+ /* PWR SAVE to 0 */
+ if (pwr_save)
+ REG_WRITE32(host, (REG_READ32(host, SDCC_VENDOR_SPECIFIC_FUNC) & ~SDCC_DLL_PWR_SAVE_EN), SDCC_VENDOR_SPECIFIC_FUNC);
+ /* Set DLL_RST to 1 */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) | SDCC_DLL_RESET_EN), SDCC_DLL_CONFIG_REG);
+ /* Set DLL_PDN to 1 */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) | SDCC_DLL_PDN_EN), SDCC_DLL_CONFIG_REG);
+
+ /* Set frequency field in DLL_CONFIG */
+ msm_set_dll_freq(host);
+
+ /* Write 0 to DLL_RST */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) & ~SDCC_DLL_RESET_EN), SDCC_DLL_CONFIG_REG);
+ /* Write 0 to DLL_PDN */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) & ~SDCC_DLL_PDN_EN), SDCC_DLL_CONFIG_REG);
+ /* Write 1 to DLL_EN */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) | SDCC_DLL_EN), SDCC_DLL_CONFIG_REG);
+ /* Write 1 to CLK_OUT_EN */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) | SDCC_DLL_CLK_OUT_EN), SDCC_DLL_CONFIG_REG);
+ /* Wait for DLL_LOCK in DLL_STATUS register */
+ while(!((REG_READ32(host, SDCC_REG_DLL_STATUS)) & SDCC_DLL_LOCK_STAT));
+ /* Set the powersave back on */
+ if (pwr_save)
+ REG_WRITE32(host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) | SDCC_DLL_PWR_SAVE_EN), SDCC_VENDOR_SPECIFIC_FUNC);
+}
+
+/* Configure DLL with delay value based on 'phase' */
+static void sdhci_msm_config_dll(struct sdhci_host *host, uint32_t phase)
+{
+ uint32_t core_cfg = 0;
+ /* Gray code values from SWI */
+ uint32_t gray_code [] = { 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4, 0xC, 0xD, 0xF, 0xE, 0xA, 0xB, 0x9, 0x8 };
+
+ /* set CDR_EN & CLK_OUT_EN to 0 and
+ * CDR_EXT_EN & DLL_EN to 1*/
+ core_cfg = REG_READ32(host, SDCC_DLL_CONFIG_REG);
+ core_cfg &= ~(SDCC_DLL_CDR_EN | SDCC_DLL_CLK_OUT_EN);
+ core_cfg |= (SDCC_DLL_CDR_EXT_EN | SDCC_DLL_EN);
+ REG_WRITE32(host, core_cfg, SDCC_DLL_CONFIG_REG);
+
+ /* Wait until CLK_OUT_EN is 0 */
+ while(REG_READ32(host, SDCC_DLL_CONFIG_REG) & SDCC_DLL_CLK_OUT_EN);
+
+ REG_RMW32(host, SDCC_DLL_CONFIG_REG, SDCC_DLL_GRAY_CODE_START, SDCC_DLL_GRAY_CODE_WIDTH, gray_code[phase]);
+
+ REG_WRITE32(host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) | SDCC_DLL_CLK_OUT_EN), SDCC_DLL_CONFIG_REG);
+
+ /* Wait until CLK_OUT_EN is 1 */
+ while(!(REG_READ32(host, SDCC_DLL_CONFIG_REG) & SDCC_DLL_CLK_OUT_EN));
+
+ core_cfg = REG_READ32(host, SDCC_DLL_CONFIG_REG);
+
+ core_cfg |= SDCC_DLL_CDR_EN;
+ core_cfg &= ~SDCC_DLL_CDR_EXT_EN;
+
+ REG_WRITE32(host, core_cfg, SDCC_DLL_CONFIG_REG);
+
+ return;
+}
+
+/*
+ * Find the right tuning delay, this function finds the largest
+ * consecutive sequence of phases & then selects the 3/4 th of
+ * the range which has max entries
+ * For eg: If we get the following sequence in phase_table[]
+ * (A) phase_table[] = 0x1, 0x2, 0x3, 0x4 , 0x5
+ * (B) phase_table[] = 0xA, 0xB, 0xC
+ * In the above case the (A) has maximum consecutive entries with '5' entries
+ * So delay would be phase_table[(0x5 * 3) / 4] = 0x3
+ */
+static int sdhci_msm_find_appropriate_phase(struct sdhci_host *host,
+ uint32_t *phase_table,
+ uint32_t total_phases)
+{
+ int sub_phases[MAX_PHASES][MAX_PHASES]={{0}};
+ int phases_per_row[MAX_PHASES] = {0};
+ uint32_t i,j;
+ int selected_phase = 0;
+ uint32_t row_index = 0;
+ uint32_t col_index = 0;
+ uint32_t phase_15_row_idx = 0;
+ uint32_t phases_0_row_idx = 0;
+ uint32_t max_phases_3_4_idx = 0;
+ uint32_t max_phases = 0;
+ uint32_t max_phases_row = 0;
+ bool found_loop = false;
+
+ if (!phase_table[0] && phase_table[total_phases - 1] == (MAX_PHASES - 1))
+ found_loop = true;
+
+ for (i = 0; i < total_phases; i++)
+ {
+ /* Break the phase table entries into different sub arrays based
+ * on the consecutive entries. Each row will have one sub array
+ * of consecutive entries.
+ * for eg: phase_table [] = { 0x0, 0x1, 0x2, 0xA, 0xB}
+ * sub_phases [0][] = { 0x0, 0x1, 0x2}
+ * sub_phases [1][] = { 0xA, 0xB}
+ */
+ sub_phases[row_index][col_index] = phase_table[i];
+ phases_per_row[row_index]++;
+ col_index++;
+
+ /* If we are at the last phase no need to check further */
+ if ((i + 1) == total_phases)
+ break;
+
+ /* If phase_table does not have consecutive entries, move to next entry */
+ if (phase_table[i]+1 != phase_table[i+1])
+ {
+ row_index++;
+ col_index = 0;
+ }
+ }
+
+ if (found_loop && total_phases < MAX_PHASES)
+ {
+ /* For consecutive entries we need to consider loops.
+ * If the phase_table contains 0x0 & 0xF then we have
+ * a loop, the number after 0xF in the sequence would be
+ * 0x0.
+ * for eg:
+ * phase_table = { 0x0, 0x1, 0x2, 0xD, 0xE, 0xF }
+ * then
+ * sub_phase [0][] = { 0x0, 0x1, 0x2 }
+ * sub_phase [1][] = { 0xD, 0xE, 0xF }
+ * Since we have a loop here, we need to merge the sub arrays as:
+ * sub_phase [1][] = { 0xD, 0xE, 0xF, 0x0, 0x1, 0x2 }
+ */
+
+ /* The entry 0xF will always be in the last row
+ * and entry 0x0 will always be in the first row
+ */
+ phase_15_row_idx = row_index;
+ j = 0;
+ for (i = phases_per_row[phase_15_row_idx] ; i < MAX_PHASES ; i++)
+ {
+ sub_phases[phase_15_row_idx][i] = sub_phases[phases_0_row_idx][j];
+ if (++j >= phases_per_row[phases_0_row_idx])
+ break;
+ }
+
+ /* Update the number of entries for the sub_phase after the merger */
+ phases_per_row[phase_15_row_idx] = phases_per_row[phase_15_row_idx] + phases_per_row[phases_0_row_idx];
+ phases_per_row[phases_0_row_idx] = 0;
+ }
+
+ for (i = 0 ; i <= row_index; i++)
+ {
+ if (phases_per_row[i] > max_phases)
+ {
+ max_phases = phases_per_row[i];
+ max_phases_row = i;
+ }
+ }
+
+ max_phases_3_4_idx = (max_phases * 3) / 4;
+ if (max_phases_3_4_idx)
+ max_phases_3_4_idx--;
+
+ selected_phase = sub_phases[max_phases_row][max_phases_3_4_idx];
+
+ return selected_phase;
+}
+
+static uint32_t sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
+{
+ uint32_t timeout;
+ uint32_t cdc_err;
+
+ /* Reset & Initialize the DLL block */
+ sdhci_msm_init_dll(host);
+
+ /* Write the save phase */
+ sdhci_msm_config_dll(host, host->msm_host->saved_phase);
+
+ /* Configure the clocks needed for CDC */
+ clock_config_cdc(host->msm_host->slot);
+
+ /* Set the FF_CLK_SW_RST_DIS to 1 */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_MCI_HC_MODE) | FW_CLK_SW_RST_DIS), SDCC_MCI_HC_MODE);
+
+ /* Write 1 to CMD_DAT_TRACK_SEL field in DLL_CONFIG */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) | CMD_DAT_TRACK_SEL), SDCC_DLL_CONFIG_REG);
+
+ /* Write 0 to CDC_T4_DLY_SEL field in VENDOR_SPEC_DDR200_CFG */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_CDC_DDR200_CFG) & ~CDC_T4_DLY_SEL), SDCC_CDC_DDR200_CFG);
+
+ /* Write 0 to START_CDC_TRAFFIC field in CORE_DDR200_CFG */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_CDC_DDR200_CFG) & ~START_CDC_TRAFFIC), SDCC_CDC_DDR200_CFG);
+
+ /* Write 0 to CDC_SWITCH_BYPASS_OFF field in CSR_CDC_GEN_CFG */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_VENDOR_SPEC_CSR_CDC_CFG) & ~CDC_SWITCH_BYPASS_OFF), SDCC_VENDOR_SPEC_CSR_CDC_CFG);
+
+ /* Write 1 to CDC_SWITCH_RC_EN field in CSR_CDC_GEN_CFG */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_VENDOR_SPEC_CSR_CDC_CFG) | CDC_SWITCH_RC_EN), SDCC_VENDOR_SPEC_CSR_CDC_CFG);
+
+ /* Write 0 to START_CDC_TRAFFIC field in CORE_DDR200_CFG */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_CDC_DDR200_CFG) & ~START_CDC_TRAFFIC), SDCC_CDC_DDR200_CFG);
+
+ /* Perform CDCLP533 initialization sequence
+ * SDCC_CSR_CDC_CTRL_CFG0 --> 0x11800EC
+ * SDCC_CSR_CDC_CTRL_CFG1 --> 0x3011111
+ * SDCC_CSR_CDC_CAL_TIMER_CFG0 --> 0x1201000
+ * SDCC_CSR_CDC_CAL_TIMER_CFG1 --> 0x4
+ * SDCC_CSR_CDC_REFCOUNT_CFG --> 0xCB732020
+ * SDCC_CSR_CDC_COARSE_CAL_CFG --> 0xB19
+ * SDCC_CSR_CDC_DELAY_CFG --> 0x3AC
+ * SDCC_CDC_OFFSET_CFG --> 0x0
+ * SDCC_CDC_SLAVE_DDA_CFG --> 0x16334
+ */
+
+ REG_WRITE32(host, 0x11800EC, SDCC_CSR_CDC_CTRL_CFG0);
+ REG_WRITE32(host, 0x3011111, SDCC_CSR_CDC_CTRL_CFG1);
+ REG_WRITE32(host, 0x1201000, SDCC_CSR_CDC_CAL_TIMER_CFG0);
+ REG_WRITE32(host, 0x4, SDCC_CSR_CDC_CAL_TIMER_CFG1);
+ REG_WRITE32(host, 0xCB732020, SDCC_CSR_CDC_REFCOUNT_CFG);
+ REG_WRITE32(host, 0xB19, SDCC_CSR_CDC_COARSE_CAL_CFG);
+ REG_WRITE32(host, 0x3AC, SDCC_CSR_CDC_DELAY_CFG);
+ REG_WRITE32(host, 0x0, SDCC_CDC_OFFSET_CFG);
+ REG_WRITE32(host, 0x16334, SDCC_CDC_SLAVE_DDA_CFG);
+
+ /* Write 1 to SW_TRIGGER_FULL_CALIB */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_CSR_CDC_CTRL_CFG0) | CDC_SW_TRIGGER_FULL_CALIB), SDCC_CSR_CDC_CTRL_CFG0);
+
+ /* Write 0 to SW_TRIGGER_FULL_CALIB */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_CSR_CDC_CTRL_CFG0) & ~CDC_SW_TRIGGER_FULL_CALIB), SDCC_CSR_CDC_CTRL_CFG0);
+
+ /* Write 1 to HW_AUTO_CAL_EN */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_CSR_CDC_CTRL_CFG0) | CDC_HW_AUTO_CAL_EN), SDCC_CSR_CDC_CTRL_CFG0);
+
+ /* Write 1 to TIMER_ENA */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_CSR_CDC_CAL_TIMER_CFG0) | CDC_TIMER_EN), SDCC_CSR_CDC_CAL_TIMER_CFG0);
+
+ /* Wait for CALIBRATION_DONE in CDC_STATUS */
+ timeout = 50;
+ while (!(REG_READ32(host, SDCC_CSR_CDC_STATUS0) & BIT(0)))
+ {
+ timeout--;
+ mdelay(1);
+ if (!timeout)
+ {
+ dprintf(CRITICAL, "Error: Calibration done in CDC status not set\n");
+ return 1;
+ }
+ }
+
+ cdc_err = REG_READ32(host, SDCC_CSR_CDC_STATUS0) & CSR_CDC_ERROR_MASK;
+ if (cdc_err)
+ {
+ dprintf(CRITICAL, "CDC error set during calibration: %x\n", cdc_err);
+ return 1;
+ }
+ /* Write 1 to START_CDC_TRAFFIC field in CORE_DDR200_CFG */
+ REG_WRITE32(host, (REG_READ32(host, SDCC_CDC_DDR200_CFG) | START_CDC_TRAFFIC), SDCC_CDC_DDR200_CFG);
+
+ return 0;
+}
+
+/*
+ * Function: sdhci msm execute tuning
+ * Arg : Host structure & bus width
+ * Return : 0 on Success, 1 on Failure
+ * Flow: : Execute Tuning sequence for HS200
+ */
+uint32_t sdhci_msm_execute_tuning(struct sdhci_host *host, uint32_t bus_width)
+{
+ uint32_t *tuning_block;
+ uint32_t *tuning_data;
+ uint32_t tuned_phases[MAX_PHASES] = {{0}};
+ uint32_t size;
+ uint32_t phase = 0;
+ uint32_t tuned_phase_cnt = 0;
+ int ret = 0;
+ struct sdhci_msm_data *msm_host;
+
+ msm_host = host->msm_host;
+
+ /* In Tuning mode */
+ host->tuning_in_progress = true;
+
+ /* Calibration for CDCLP533 needed for HS400 mode */
+ if (msm_host->tuning_done && !msm_host->calibration_done && host->timing == MMC_HS400_TIMING)
+ {
+ ret = sdhci_msm_cdclp533_calibration(host);
+ if (!ret)
+ msm_host->calibration_done = true;
+ goto out;
+ }
+
+ if (bus_width == DATA_BUS_WIDTH_8BIT)
+ {
+ tuning_block = tuning_block_128;
+ size = sizeof(tuning_block_128);
+ }
+ else
+ {
+ tuning_block = tuning_block_64;
+ size = sizeof(tuning_block_64);
+ }
+
+ tuning_data = (uint32_t *) memalign(CACHE_LINE, ROUNDUP(size, CACHE_LINE));
+
+ ASSERT(tuning_data);
+
+ /* Reset & Initialize the DLL block */
+ sdhci_msm_init_dll(host);
+
+ while (phase < MAX_PHASES)
+ {
+ struct mmc_command cmd = {0};
+
+ /* configure dll to set phase delay */
+ sdhci_msm_config_dll(host, phase);
+
+ cmd.cmd_index = CMD21_SEND_TUNING_BLOCK;
+ cmd.argument = 0x0;
+ cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL;
+ cmd.resp_type = SDHCI_CMD_RESP_R1;
+ cmd.trans_mode = SDHCI_MMC_READ;
+ cmd.data_present = 0x1;
+ cmd.data.data_ptr = tuning_data;
+ cmd.data.blk_sz = size;
+ cmd.data.num_blocks = 0x1;
+
+ /* send command */
+ if (!sdhci_send_command(host, &cmd) && !memcmp(tuning_data, tuning_block, size))
+ tuned_phases[tuned_phase_cnt++] = phase;
+
+ phase++;
+ }
+
+ /* Find the appropriate tuned phase */
+ if (tuned_phase_cnt)
+ {
+ ret = sdhci_msm_find_appropriate_phase(host, tuned_phases, tuned_phase_cnt);
+
+ if (ret < 0)
+ {
+ dprintf(CRITICAL, "Failed in selecting the tuning phase\n");
+ ret = 1;
+ goto free;
+ }
+
+ phase = (uint32_t) ret;
+ ret = 0;
+
+ sdhci_msm_config_dll(host, phase);
+
+ /* Save the tuned phase */
+ host->msm_host->saved_phase = phase;
+ }
+ else
+ {
+ dprintf(CRITICAL, "Failed to get tuned phase\n");
+ ret = 1;
+ }
+
+free:
+ free(tuning_data);
+out:
+ /* Tuning done */
+ host->tuning_in_progress = false;
+ host->msm_host->tuning_done = true;
+ return ret;
+}
+
+/*
+ * API to disable HC mode
+ */
+void sdhci_mode_disable(struct sdhci_host *host)
+{
+ /* Disable HC mode */
+ RMWREG32((host->msm_host->pwrctl_base + SDCC_MCI_HC_MODE), SDHCI_HC_START_BIT, SDHCI_HC_WIDTH, 0);
+}
+
diff --git a/platform/msm_shared/shutdown_detect.c b/platform/msm_shared/shutdown_detect.c
new file mode 100644
index 0000000..a51c9ae
--- /dev/null
+++ b/platform/msm_shared/shutdown_detect.c
@@ -0,0 +1,160 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <reg.h>
+#include <stdlib.h>
+#include <pm8x41.h>
+#include <pm8x41_hw.h>
+#include <kernel/timer.h>
+#include <platform/timer.h>
+#include <shutdown_detect.h>
+
+/* sleep clock is 32.768 khz, 0x8000 count per second */
+#define MPM_SLEEP_TIMETICK_COUNT 0x8000
+#define PWRKEY_LONG_PRESS_COUNT 0xC000
+#define QPNP_DEFAULT_TIMEOUT 250
+#define PWRKEY_DETECT_FREQUENCY 50
+
+static struct timer pon_timer;
+static uint32_t pon_timer_complete = 0;
+
+/*
+ * Function to check if the the power key is pressed long enough.
+ * Return 0 if boot time more than PWRKEY_LONG_PRESS_COUNT.
+ * Return 1 if boot time less than PWRKEY_LONG_PRESS_COUNT.
+ */
+static uint32_t is_pwrkey_time_expired()
+{
+ /* power on button tied in with PMIC KPDPWR. */
+ uint32_t sclk_count = platform_get_sclk_count();
+
+ /* Here check if the long press power-key lasts for 1.5s */
+ if (sclk_count > PWRKEY_LONG_PRESS_COUNT)
+ return 0;
+ else
+ return 1;
+}
+
+/*
+ * Function to check if the power on reason is power key triggered.
+ * Return 1 if it is triggered by power key.
+ * Return 0 if it is not triggered by power key.
+ */
+static uint32_t is_pwrkey_pon_reason()
+{
+ uint8_t pon_reason = pm8x41_get_pon_reason();
+
+ if (pm8x41_get_is_cold_boot() && (pon_reason == KPDPWR_N))
+ return 1;
+ else
+ return 0;
+}
+
+/*
+ * Main timer handle: check every PWRKEY_DETECT_FREQUENCY to see
+ * if power key is pressed.
+ * Shutdown the device if power key is release before
+ * (PWRKEY_LONG_PRESS_COUNT/MPM_SLEEP_TIMETICK_COUNT) seconds.
+ */
+static enum handler_return long_press_pwrkey_timer_func(struct timer *p_timer,
+ void *arg)
+{
+ uint32_t sclk_count = platform_get_sclk_count();
+
+ /*
+ * The following condition is treated as the power key
+ * is pressed long enough.
+ * 1. if the power key is pressed last for PWRKEY_LONG_PRESS_COUNT.
+ */
+ if (sclk_count > PWRKEY_LONG_PRESS_COUNT) {
+ timer_cancel(p_timer);
+ pon_timer_complete = 1;
+ } else {
+ if (pm8x41_get_pwrkey_is_pressed()) {
+ /*
+ * For normal man response is > 0.1 secs, so we use 0.05 secs default
+ * for software to be safely detect if there is a key release action.
+ */
+ timer_set_oneshot(p_timer, PWRKEY_DETECT_FREQUENCY,
+ long_press_pwrkey_timer_func, NULL);
+ } else {
+ shutdown_device();
+ }
+ }
+
+ return INT_RESCHEDULE;
+}
+
+/*
+ * Function to wait until the power key is pressed long enough
+ */
+static void wait_for_long_pwrkey_pressed()
+{
+ uint32_t sclk_count = 0;
+
+ while (!pon_timer_complete) {
+ sclk_count = platform_get_sclk_count();
+ if (sclk_count > PWRKEY_LONG_PRESS_COUNT) {
+ timer_cancel(&pon_timer);
+ break;
+ }
+ }
+}
+
+/*
+ * Function to support for shutdown detection
+ * If below condition is met, the function will shut down
+ * the device. Otherwise it will do nothing and return to
+ * normal boot.
+ * condition:
+ * 1. it is triggered by power key &&
+ * 2. the power key is released before
+ * (PWRKEY_LONG_PRESS_COUNT/MPM_SLEEP_TIMETICK_COUNT) seconds.
+ */
+void shutdown_detect()
+{
+ /*
+ * If it is booted by power key tirigger.
+ * Initialize pon_timer and call long_press_pwrkey_timer_func
+ * function to check if the power key is last press long enough.
+ */
+ if (is_pwrkey_pon_reason() && is_pwrkey_time_expired()) {
+ timer_initialize(&pon_timer);
+ timer_set_oneshot(&pon_timer, 0, long_press_pwrkey_timer_func, NULL);
+
+ /*
+ * Wait until long press power key timeout
+ *
+ * It will be confused to end users if we shutdown the device
+ * after the splash screen displayed. But it can be moved the
+ * wait here if the boot time is much more considered.
+ */
+ wait_for_long_pwrkey_pressed();
+ }
+}
diff --git a/project/msm8226.mk b/project/msm8226.mk
index 1e94e03..2c97294 100644
--- a/project/msm8226.mk
+++ b/project/msm8226.mk
@@ -10,6 +10,9 @@
EMMC_BOOT := 1
ENABLE_SDHCI_SUPPORT := 1
+#enable power on vibrator feature
+ENABLE_PON_VIB_SUPPORT := true
+
#DEFINES += WITH_DEBUG_DCC=1
DEFINES += WITH_DEBUG_UART=1
DEFINES += WITH_DEBUG_LOG_BUF=1
@@ -26,6 +29,10 @@
#Disable thumb mode
ENABLE_THUMB := false
+ifeq ($(ENABLE_PON_VIB_SUPPORT),true)
+DEFINES += PON_VIB_SUPPORT=1
+endif
+
ifeq ($(ENABLE_SDHCI_SUPPORT),1)
DEFINES += MMC_SDHCI_SUPPORT=1
endif
diff --git a/target/apq8084/include/target/display.h b/target/apq8084/include/target/display.h
index 5861791..728d7bf 100644
--- a/target/apq8084/include/target/display.h
+++ b/target/apq8084/include/target/display.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -104,4 +104,6 @@
#define MIPI_VSYNC_BACK_PORCH_LINES 3
#define MIPI_VSYNC_FRONT_PORCH_LINES 9
+#define PWM_BL_LPG_CHAN_ID 3
+
#endif
diff --git a/target/apq8084/oem_panel.c b/target/apq8084/oem_panel.c
index dd86314..3b487c6 100644
--- a/target/apq8084/oem_panel.c
+++ b/target/apq8084/oem_panel.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -42,6 +42,7 @@
/*---------------------------------------------------------------------------*/
#include "include/panel_jdi_1080p_video.h"
#include "include/panel_jdi_qhd_dualdsi_video.h"
+#include "include/panel_jdi_qhd_dualdsi_cmd.h"
/*---------------------------------------------------------------------------*/
/* static panel selection variable */
@@ -49,6 +50,7 @@
enum {
JDI_1080P_VIDEO_PANEL,
JDI_QHD_DUALDSI_VIDEO_PANEL,
+JDI_QHD_DUALDSI_CMD_PANEL,
UNKNOWN_PANEL
};
@@ -123,6 +125,26 @@
memcpy(phy_db->timing,
jdi_qhd_dualdsi_video_timings, TIMING_SIZE);
break;
+ case JDI_QHD_DUALDSI_CMD_PANEL:
+ panelstruct->paneldata = &jdi_qhd_dualdsi_cmd_panel_data;
+ panelstruct->panelres = &jdi_qhd_dualdsi_cmd_panel_res;
+ panelstruct->color = &jdi_qhd_dualdsi_cmd_color;
+ panelstruct->videopanel = &jdi_qhd_dualdsi_cmd_video_panel;
+ panelstruct->commandpanel = &jdi_qhd_dualdsi_cmd_command_panel;
+ panelstruct->state = &jdi_qhd_dualdsi_cmd_state;
+ panelstruct->laneconfig = &jdi_qhd_dualdsi_cmd_lane_config;
+ panelstruct->paneltiminginfo
+ = &jdi_qhd_dualdsi_cmd_timing_info;
+ panelstruct->panelresetseq
+ = &jdi_qhd_dualdsi_cmd_reset_seq;
+ panelstruct->backlightinfo = &jdi_qhd_dualdsi_cmd_backlight;
+ pinfo->mipi.panel_cmds
+ = jdi_qhd_dualdsi_cmd_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = JDI_QHD_DUALDSI_CMD_ON_COMMAND;
+ memcpy(phy_db->timing,
+ jdi_qhd_dualdsi_cmd_timings, TIMING_SIZE);
+ break;
default:
case UNKNOWN_PANEL:
ret = false;
@@ -131,7 +153,7 @@
return ret;
}
-bool oem_panel_select(struct panel_struct *panelstruct,
+bool oem_panel_select(const char *panel_name, struct panel_struct *panelstruct,
struct msm_panel_info *pinfo,
struct mdss_dsi_phy_ctrl *phy_db)
{
diff --git a/target/apq8084/target_display.c b/target/apq8084/target_display.c
old mode 100644
new mode 100755
index 54589dc..fd6f766
--- a/target/apq8084/target_display.c
+++ b/target/apq8084/target_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -86,7 +86,7 @@
return rc;
}
-int target_backlight_ctrl(uint8_t enable)
+int target_backlight_ctrl(struct backlight *bl, uint8_t enable)
{
struct pm8x41_gpio pwmgpio_param = {
.direction = PM_GPIO_DIR_OUT,
@@ -96,18 +96,19 @@
.output_buffer = PM_GPIO_OUT_CMOS,
.out_strength = 0x03,
};
+
if (enable) {
- pm8x41_gpio_config(7, &pwmgpio_param);
+ pm8x41_gpio_config(pwm_gpio.pin_id, &pwmgpio_param);
/* lpg channel 2 */
- pm8x41_lpg_write(3, 0x41, 0x33); /* LPG_PWM_SIZE_CLK, */
- pm8x41_lpg_write(3, 0x42, 0x01); /* LPG_PWM_FREQ_PREDIV */
- pm8x41_lpg_write(3, 0x43, 0x20); /* LPG_PWM_TYPE_CONFIG */
- pm8x41_lpg_write(3, 0x44, 0xcc); /* LPG_VALUE_LSB */
- pm8x41_lpg_write(3, 0x45, 0x00); /* LPG_VALUE_MSB */
- pm8x41_lpg_write(3, 0x46, 0xe4); /* LPG_ENABLE_CONTROL */
+ pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x41, 0x33); /* LPG_PWM_SIZE_CLK, */
+ pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x42, 0x01); /* LPG_PWM_FREQ_PREDIV */
+ pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x43, 0x20); /* LPG_PWM_TYPE_CONFIG */
+ pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x44, 0xcc); /* LPG_VALUE_LSB */
+ pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x45, 0x00); /* LPG_VALUE_MSB */
+ pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x46, 0xe4); /* LPG_ENABLE_CONTROL */
} else {
- pm8x41_lpg_write(3, 0x46, 0x0); /* LPG_ENABLE_CONTROL */
+ pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x46, 0x0); /* LPG_ENABLE_CONTROL */
}
return NO_ERROR;
@@ -241,16 +242,16 @@
return NO_ERROR;
}
-void display_init(void)
+void target_display_init(const char *panel_name)
{
uint32_t ret = 0;
- ret = gcdb_display_init(MDP_REV_50, MIPI_FB_ADDR);
+ ret = gcdb_display_init(panel_name, MDP_REV_50, MIPI_FB_ADDR);
if (ret) {
msm_display_off();
}
}
-void display_shutdown(void)
+void target_display_shutdown(void)
{
gcdb_display_shutdown();
}
diff --git a/target/init.c b/target/init.c
index 7875a4f..8eeb906 100644
--- a/target/init.c
+++ b/target/init.c
@@ -146,6 +146,14 @@
return false;
}
+__WEAK void target_display_init(const char *panel_name)
+{
+}
+
+__WEAK void target_display_shutdown(void)
+{
+}
+
__WEAK uint8_t target_panel_auto_detect_enabled()
{
return 0;
diff --git a/target/msm7627a/init.c b/target/msm7627a/init.c
index 502cb54..41c9611 100644
--- a/target/msm7627a/init.c
+++ b/target/msm7627a/init.c
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2009, Google Inc.
* All rights reserved.
- * Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2009-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -186,12 +186,6 @@
keypad_init();
#endif
- /* Display splash screen if enabled */
-#if DISPLAY_SPLASH_SCREEN
- display_init();
- dprintf(SPEW, "Diplay initialized\n");
-#endif
-
if (target_is_emmc_boot()) {
/* Must wait for modem-up before we can intialize MMC.
*/
diff --git a/target/msm7627a/target_display.c b/target/msm7627a/target_display.c
old mode 100644
new mode 100755
index 0c4d073..94270b5
--- a/target/msm7627a/target_display.c
+++ b/target/msm7627a/target_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012, 2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -69,7 +69,7 @@
}
return ret;
}
-void display_init(void)
+void target_display_init(const char *panel_name)
{
unsigned mach_type;
mach_type = board_machtype();
@@ -155,7 +155,7 @@
display_enabled = 1;
}
-void display_shutdown(void)
+void target_display_shutdown(void)
{
dprintf(SPEW, "display_shutdown()\n");
if (display_enabled)
diff --git a/target/msm8226/init.c b/target/msm8226/init.c
index 4067a8c..286ef41 100644
--- a/target/msm8226/init.c
+++ b/target/msm8226/init.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -48,6 +48,8 @@
#include <scm.h>
#include <stdlib.h>
#include <partition_parser.h>
+#include <shutdown_detect.h>
+#include <vibrator.h>
extern bool target_use_signed_kernel(void);
static void set_sdc_power_ctrl(void);
@@ -65,6 +67,7 @@
#define CRYPTO_ENGINE_CMD_ARRAY_SIZE 20
#define TLMM_VOL_UP_BTN_GPIO 106
+#define VIBRATE_TIME 250
#define SSD_CE_INSTANCE 1
@@ -247,12 +250,10 @@
target_sdc_init();
- /* Display splash screen if enabled */
-#if DISPLAY_SPLASH_SCREEN
- dprintf(SPEW, "Display Init: Start\n");
- display_init();
- dprintf(SPEW, "Display Init: Done\n");
-#endif
+ shutdown_detect();
+
+ /* turn on vibrator to indicate that phone is booting up to end user */
+ vib_timed_turn_on(VIBRATE_TIME);
if (target_use_signed_kernel())
target_crypto_init_params();
@@ -369,6 +370,24 @@
dprintf(CRITICAL, "Rebooting failed\n");
}
+/* Configure PMIC and Drop PS_HOLD for shutdown */
+void shutdown_device()
+{
+ dprintf(CRITICAL, "Going down for shutdown.\n");
+
+ /* Configure PMIC for shutdown */
+ pm8x41_reset_configure(PON_PSHOLD_SHUTDOWN);
+
+ /* Drop PS_HOLD for MSM */
+ writel(0x00, MPM2_MPM_PS_HOLD);
+
+ mdelay(5000);
+
+ dprintf(CRITICAL, "shutdown failed\n");
+
+ ASSERT(0);
+}
+
crypto_engine_type board_ce_type(void)
{
return CRYPTO_ENGINE_TYPE_HW;
@@ -387,6 +406,9 @@
void target_uninit(void)
{
+ /* wait for the vibrator timer is expried */
+ wait_vib_timeout();
+
mmc_put_card_to_sleep(dev);
if (target_is_ssd_enabled())
@@ -413,15 +435,19 @@
uint8_t target_panel_auto_detect_enabled()
{
uint8_t ret = 0;
+ uint32_t hw_subtype = board_hardware_subtype();
switch(board_hardware_id())
{
case HW_PLATFORM_QRD:
- /* Enable auto detect for DVT boards only */
- if (((board_target_id() >> 16) & 0xFF) == 0x2)
- ret = 1;
- else
- ret = 0;
+ if (hw_subtype != HW_PLATFORM_SUBTYPE_SKUF
+ && hw_subtype != HW_PLATFORM_SUBTYPE_SKUG) {
+ /* Enable autodetect for 8x26 DVT boards only */
+ if (((board_target_id() >> 16) & 0xFF) == 0x2)
+ ret = 1;
+ else
+ ret = 0;
+ }
break;
case HW_PLATFORM_SURF:
case HW_PLATFORM_MTP:
@@ -501,9 +527,9 @@
/* Drive strength configs for sdc pins */
struct tlmm_cfgs sdc1_hdrv_cfg[] =
{
- { SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
+ { SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK },
{ SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
- { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
+ { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_6MA, TLMM_HDRV_MASK },
};
/* Pull configs for sdc pins */
diff --git a/target/msm8226/oem_panel.c b/target/msm8226/oem_panel.c
index 9f3127b..258f77c 100755
--- a/target/msm8226/oem_panel.c
+++ b/target/msm8226/oem_panel.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -51,6 +51,9 @@
#define DISPLAY_MAX_PANEL_DETECTION 2
+#define SSD2080M_720P_VIDEO_PANEL_ON_DELAY 200
+#define MAX_PANEL_ID_LEN 64
+
/*---------------------------------------------------------------------------*/
/* static panel selection variable */
/*---------------------------------------------------------------------------*/
@@ -72,9 +75,25 @@
HW_PLATFORM_SUBTYPE_SKUF = 2,
HW_PLATFORM_SUBTYPE_1080P = 2,
HW_PLATFORM_SUBTYPE_SKUAB = 3,
+ HW_PLATFORM_SUBTYPE_1080P_EXT_BUCK = 3,
HW_PLATFORM_SUBTYPE_SKUG = 5,
};
+/*
+ * The list of panels that are supported on this target.
+ * Any panel in this list can be selected using fastboot oem command.
+ */
+static struct panel_list supp_panels[] = {
+ {"toshiba_720p_video", TOSHIBA_720P_VIDEO_PANEL},
+ {"nt35590_720p_cmd", NT35590_720P_CMD_PANEL},
+ {"nt35590_720p_video", NT35590_720P_VIDEO_PANEL},
+ {"nt35596_1080p_video", NT35596_1080P_VIDEO_PANEL},
+ {"hx8394a_720p_video", HX8394A_720P_VIDEO_PANEL},
+ {"nt35521_720p_video", NT35521_720P_VIDEO_PANEL},
+ {"ssd2080m_720p_video", SSD2080M_720P_VIDEO_PANEL},
+ {"jdi_1080p_video", JDI_1080P_VIDEO_PANEL},
+};
+
static uint32_t panel_id;
int oem_panel_rotation()
@@ -98,11 +117,14 @@
return ret;
}
-
int oem_panel_on()
{
/* OEM can keep there panel spefic on instructions in this
function */
+ if (panel_id == SSD2080M_720P_VIDEO_PANEL) {
+ /* SSD2080M needs extra delay to avoid unexpected artifacts */
+ mdelay(SSD2080M_720P_VIDEO_PANEL_ON_DELAY);
+ }
return NO_ERROR;
}
@@ -300,7 +322,7 @@
static uint32_t auto_pan_loop = 0;
-bool oem_panel_select(struct panel_struct *panelstruct,
+bool oem_panel_select(const char *panel_name, struct panel_struct *panelstruct,
struct msm_panel_info *pinfo,
struct mdss_dsi_phy_ctrl *phy_db)
{
@@ -309,10 +331,24 @@
uint32_t nt35590_panel_id = NT35590_720P_VIDEO_PANEL;
uint32_t hw_subtype = board_hardware_subtype();
bool ret = true;
+ int32_t panel_override_id;
-#if DISPLAY_TYPE_CMD_MODE
- nt35590_panel_id = NT35590_720P_CMD_PANEL;
-#endif
+ if (panel_name) {
+ panel_override_id = panel_name_to_id(supp_panels,
+ ARRAY_SIZE(supp_panels), panel_name);
+
+ if (panel_override_id < 0) {
+ dprintf(CRITICAL, "Not able to search the panel:%s\n",
+ panel_name + strspn(panel_name, " "));
+ } else if (panel_override_id < UNKNOWN_PANEL) {
+ /* panel override using fastboot oem command */
+ panel_id = panel_override_id;
+
+ dprintf(INFO, "OEM panel override:%s\n",
+ panel_name + strspn(panel_name, " "));
+ goto panel_init;
+ }
+ }
switch (hw_id) {
case HW_PLATFORM_QRD:
@@ -349,11 +385,11 @@
break;
case HW_PLATFORM_MTP:
case HW_PLATFORM_SURF:
- if (hw_subtype == HW_PLATFORM_SUBTYPE_1080P) {
+ if ((hw_subtype == HW_PLATFORM_SUBTYPE_1080P) ||
+ (hw_subtype == HW_PLATFORM_SUBTYPE_1080P_EXT_BUCK))
panel_id = JDI_1080P_VIDEO_PANEL;
- } else {
+ else
panel_id = nt35590_panel_id;
- }
break;
default:
dprintf(CRITICAL, "Display not enabled for %d HW type\n"
@@ -361,6 +397,7 @@
return false;
}
+panel_init:
init_panel_data(panelstruct, pinfo, phy_db);
return ret;
diff --git a/target/msm8226/rules.mk b/target/msm8226/rules.mk
index f5c9596..d31f2bc 100755
--- a/target/msm8226/rules.mk
+++ b/target/msm8226/rules.mk
@@ -18,7 +18,6 @@
DEFINES += DISPLAY_SPLASH_SCREEN=1
DEFINES += DISPLAY_TYPE_MIPI=1
DEFINES += DISPLAY_TYPE_DSI6G=1
-DEFINES += DISPLAY_TYPE_CMD_MODE=0
MODULES += \
dev/keys \
@@ -26,6 +25,7 @@
dev/pmic/pm8x41 \
dev/panel/msm \
dev/gcdb/display \
+ dev/vib \
lib/libfdt
DEFINES += \
diff --git a/target/msm8226/target_display.c b/target/msm8226/target_display.c
index 8ddfa89..2e608c8 100755
--- a/target/msm8226/target_display.c
+++ b/target/msm8226/target_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -198,10 +198,21 @@
return pll_locked;
}
-int target_backlight_ctrl(uint8_t enable)
+int target_backlight_ctrl(struct backlight *bl, uint8_t enable)
{
dprintf(SPEW, "target_backlight_ctrl\n");
+ if (!bl) {
+ dprintf(CRITICAL, "backlight structure is not available\n");
+ return ERR_INVALID_ARGS;
+ }
+
+ if (bl->bl_interface_type != BL_WLED) {
+ dprintf(CRITICAL, "backlight type:%d not supported\n",
+ bl->bl_interface_type);
+ return ERR_NOT_SUPPORTED;
+ }
+
if (enable) {
pm8x41_wled_config(&wled_ctrl);
pm8x41_wled_sink_control(enable);
@@ -330,13 +341,13 @@
return ret;
}
-void display_init(void)
+void target_display_init(const char *panel_name)
{
uint32_t panel_loop = 0;
uint32_t ret = 0;
do {
- ret = gcdb_display_init(MDP_REV_50, MIPI_FB_ADDR);
+ ret = gcdb_display_init(panel_name, MDP_REV_50, MIPI_FB_ADDR);
if (!ret || ret == ERR_NOT_SUPPORTED) {
break;
} else {
@@ -348,7 +359,7 @@
}
-void display_shutdown(void)
+void target_display_shutdown(void)
{
gcdb_display_shutdown();
}
diff --git a/target/msm8610/init.c b/target/msm8610/init.c
index b4f78d3..fb6d24c 100644
--- a/target/msm8610/init.c
+++ b/target/msm8610/init.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -163,11 +163,6 @@
target_keystatus();
target_sdc_init();
-
- /* Display splash screen if enabled */
- dprintf(SPEW, "Display Init: Start\n");
- display_init();
- dprintf(SPEW, "Display Init: Done\n");
}
void target_uninit(void)
@@ -316,11 +311,17 @@
void reboot_device(unsigned reboot_reason)
{
+ int ret = 0;
+
writel(reboot_reason, RESTART_REASON_ADDR);
/* Configure PMIC for warm reset */
pm8x41_reset_configure(PON_PSHOLD_WARM_RESET);
+ ret = scm_halt_pmic_arbiter();
+ if (ret)
+ dprintf(CRITICAL , "Failed to halt pmic arbiter: %d\n", ret);
+
/* Drop PS_HOLD for MSM */
writel(0x00, MPM2_MPM_PS_HOLD);
@@ -404,7 +405,7 @@
{
{ SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK },
{ SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
- { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
+ { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_6MA, TLMM_HDRV_MASK },
};
/* Pull configs for sdc pins */
diff --git a/target/msm8610/oem_panel.c b/target/msm8610/oem_panel.c
index 8ea0a5e..e1fad7c 100644
--- a/target/msm8610/oem_panel.c
+++ b/target/msm8610/oem_panel.c
@@ -221,7 +221,7 @@
return true;
}
-bool oem_panel_select(struct panel_struct *panelstruct,
+bool oem_panel_select(const char *panel_name, struct panel_struct *panelstruct,
struct msm_panel_info *pinfo,
struct mdss_dsi_phy_ctrl *phy_db)
{
diff --git a/target/msm8610/target_display.c b/target/msm8610/target_display.c
old mode 100644
new mode 100755
index e352c46..4b963b8
--- a/target/msm8610/target_display.c
+++ b/target/msm8610/target_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -53,7 +53,7 @@
#define PWM_DUTY_US 13
#define PWM_PERIOD_US 27
-int target_backlight_ctrl(uint8_t enable)
+int target_backlight_ctrl(struct backlight *bl, uint8_t enable)
{
struct pm8x41_mpp mpp;
int rc;
@@ -162,12 +162,12 @@
return 0;
}
-void display_init(void)
+void target_display_init(const char *panel_name)
{
- gcdb_display_init(MDP_REV_304, MIPI_FB_ADDR);
+ gcdb_display_init(panel_name, MDP_REV_304, MIPI_FB_ADDR);
}
-void display_shutdown(void)
+void target_display_shutdown(void)
{
gcdb_display_shutdown();
}
diff --git a/target/msm8960/init.c b/target/msm8960/init.c
index 72d9463..dcee3b4 100755
--- a/target/msm8960/init.c
+++ b/target/msm8960/init.c
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2009, Google Inc.
* All rights reserved.
- * Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2009-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -142,12 +142,6 @@
dprintf(CRITICAL,"Keyboard is not supported for platform: %d\n",platform_id);
};
- /* Display splash screen if enabled */
-#if DISPLAY_SPLASH_SCREEN
- display_init();
- dprintf(SPEW, "Diplay initialized\n");
-#endif
-
if ((platform_id == MSM8960) || (platform_id == MSM8960AB) ||
(platform_id == APQ8060AB) || (platform_id == MSM8260AB) ||
(platform_id == MSM8660AB) || (platform_id == MSM8660A) ||
diff --git a/target/msm8960/target_display.c b/target/msm8960/target_display.c
old mode 100644
new mode 100755
index 39a3aeb..2eec1ea
--- a/target/msm8960/target_display.c
+++ b/target/msm8960/target_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -255,7 +255,7 @@
return 0;
}
-void display_init(void)
+void target_display_init(const char *panel_name)
{
int target_id = board_target_id();
@@ -345,7 +345,7 @@
display_enable = 1;
}
-void display_shutdown(void)
+void target_display_shutdown(void)
{
if (display_enable) {
msm_display_off();
diff --git a/target/msm8974/include/target/display.h b/target/msm8974/include/target/display.h
index 8897239..b827cf6 100644
--- a/target/msm8974/include/target/display.h
+++ b/target/msm8974/include/target/display.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -45,6 +45,9 @@
"msmgpio", 58, 3, 1, 0, 1
};
+static struct gpio_pin pwm_gpio = {
+ "pm8941_gpios", 36, 3, 1, 0, 1
+};
/*---------------------------------------------------------------------------*/
/* LDO configuration */
@@ -100,6 +103,8 @@
#define MIPI_VSYNC_BACK_PORCH_LINES 3
#define MIPI_VSYNC_FRONT_PORCH_LINES 9
+#define PWM_BL_LPG_CHAN_ID 8
+
extern int mdss_dsi_phy_init(struct mipi_dsi_panel_config *, uint32_t ctl_base);
#endif
diff --git a/target/msm8974/init.c b/target/msm8974/init.c
index 1ee89bf..20d3b02 100644
--- a/target/msm8974/init.c
+++ b/target/msm8974/init.c
@@ -239,10 +239,19 @@
config.bus_width = DATA_BUS_WIDTH_8BIT;
};
- config.max_clk_rate = MMC_CLK_200MHZ;
-
/* Trying Slot 1*/
config.slot = 1;
+ /*
+ * For 8974 AC platform the software clock
+ * plan recommends to use the following frequencies:
+ * 200 MHz --> 192 MHZ
+ * 400 MHZ --> 384 MHZ
+ * only for emmc slot
+ */
+ if (platform_is_8974ac())
+ config.max_clk_rate = MMC_CLK_192MHZ;
+ else
+ config.max_clk_rate = MMC_CLK_200MHZ;
config.sdhc_base = mmc_sdhci_base[config.slot - 1];
config.pwrctl_base = mmc_sdc_base[config.slot - 1];
config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
@@ -250,6 +259,7 @@
if (!(dev = mmc_init(&config))) {
/* Trying Slot 2 next */
config.slot = 2;
+ config.max_clk_rate = MMC_CLK_200MHZ;
config.sdhc_base = mmc_sdhci_base[config.slot - 1];
config.pwrctl_base = mmc_sdc_base[config.slot - 1];
config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
@@ -341,15 +351,6 @@
if (target_use_signed_kernel())
target_crypto_init_params();
- /* Display splash screen if enabled */
-#if DISPLAY_SPLASH_SCREEN
- dprintf(INFO, "Display Init: Start\n");
- if (board_hardware_subtype() != HW_PLATFORM_SUBTYPE_CDP_INTERPOSER)
- {
- display_init();
- }
- dprintf(INFO, "Display Init: Done\n");
-#endif
/*
* Set drive strength & pull ctrl for
@@ -685,6 +686,9 @@
#ifdef SSD_ENABLE
clock_ce_disable(SSD_CE_INSTANCE_1);
#endif
+
+ /* Disable HC mode before jumping to kernel */
+ sdhci_mode_disable(&dev->host);
}
void shutdown_device()
@@ -745,9 +749,20 @@
{ SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
};
+ struct tlmm_cfgs sdc1_rclk_cfg[] =
+ {
+ { SDC1_RCLK_PULL_CTL_OFF, TLMM_PULL_DOWN, TLMM_PULL_MASK },
+ };
+
/* Set the drive strength & pull control values */
tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg));
tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg));
+
+ /* RCLK is supported only with 8974 pro, set rclk to pull down
+ * only for 8974 pro targets
+ */
+ if (!platform_is_8974())
+ tlmm_set_pull_ctrl(sdc1_rclk_cfg, ARRAY_SIZE(sdc1_rclk_cfg));
}
int emmc_recovery_init(void)
diff --git a/target/msm8974/oem_panel.c b/target/msm8974/oem_panel.c
index c9b87c2..1634cd4 100755
--- a/target/msm8974/oem_panel.c
+++ b/target/msm8974/oem_panel.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -44,6 +44,8 @@
#include "include/panel_sharp_qhd_video.h"
#include "include/panel_jdi_1080p_video.h"
#include "include/panel_generic_720p_cmd.h"
+#include "include/panel_jdi_qhd_dualdsi_video.h"
+#include "include/panel_jdi_qhd_dualdsi_cmd.h"
#define DISPLAY_MAX_PANEL_DETECTION 3
@@ -55,6 +57,8 @@
TOSHIBA_720P_VIDEO_PANEL,
SHARP_QHD_VIDEO_PANEL,
GENERIC_720P_CMD_PANEL,
+JDI_QHD_DUALDSI_VIDEO_PANEL,
+JDI_QHD_DUALDSI_CMD_PANEL,
UNKNOWN_PANEL
};
@@ -170,6 +174,46 @@
generic_720p_cmd_timings, TIMING_SIZE);
pinfo->mipi.signature = GENERIC_720P_CMD_SIGNATURE;
break;
+ case JDI_QHD_DUALDSI_VIDEO_PANEL:
+ panelstruct->paneldata = &jdi_qhd_dualdsi_video_panel_data;
+ panelstruct->panelres = &jdi_qhd_dualdsi_video_panel_res;
+ panelstruct->color = &jdi_qhd_dualdsi_video_color;
+ panelstruct->videopanel = &jdi_qhd_dualdsi_video_video_panel;
+ panelstruct->commandpanel = &jdi_qhd_dualdsi_video_command_panel;
+ panelstruct->state = &jdi_qhd_dualdsi_video_state;
+ panelstruct->laneconfig = &jdi_qhd_dualdsi_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &jdi_qhd_dualdsi_video_timing_info;
+ panelstruct->panelresetseq
+ = &jdi_qhd_dualdsi_video_reset_seq;
+ panelstruct->backlightinfo = &jdi_qhd_dualdsi_video_backlight;
+ pinfo->mipi.panel_cmds
+ = jdi_qhd_dualdsi_video_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = JDI_QHD_DUALDSI_VIDEO_ON_COMMAND;
+ memcpy(phy_db->timing,
+ jdi_qhd_dualdsi_video_timings, TIMING_SIZE);
+ break;
+ case JDI_QHD_DUALDSI_CMD_PANEL:
+ panelstruct->paneldata = &jdi_qhd_dualdsi_cmd_panel_data;
+ panelstruct->panelres = &jdi_qhd_dualdsi_cmd_panel_res;
+ panelstruct->color = &jdi_qhd_dualdsi_cmd_color;
+ panelstruct->videopanel = &jdi_qhd_dualdsi_cmd_video_panel;
+ panelstruct->commandpanel = &jdi_qhd_dualdsi_cmd_command_panel;
+ panelstruct->state = &jdi_qhd_dualdsi_cmd_state;
+ panelstruct->laneconfig = &jdi_qhd_dualdsi_cmd_lane_config;
+ panelstruct->paneltiminginfo
+ = &jdi_qhd_dualdsi_cmd_timing_info;
+ panelstruct->panelresetseq
+ = &jdi_qhd_dualdsi_cmd_reset_seq;
+ panelstruct->backlightinfo = &jdi_qhd_dualdsi_cmd_backlight;
+ pinfo->mipi.panel_cmds
+ = jdi_qhd_dualdsi_cmd_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = JDI_QHD_DUALDSI_CMD_ON_COMMAND;
+ memcpy(phy_db->timing,
+ jdi_qhd_dualdsi_cmd_timings, TIMING_SIZE);
+ break;
case UNKNOWN_PANEL:
memset(panelstruct, 0, sizeof(struct panel_struct));
memset(pinfo->mipi.panel_cmds, 0, sizeof(struct mipi_dsi_cmd));
@@ -188,7 +232,7 @@
static uint32_t auto_pan_loop = 0;
-bool oem_panel_select(struct panel_struct *panelstruct,
+bool oem_panel_select(const char *panel_name, struct panel_struct *panelstruct,
struct msm_panel_info *pinfo,
struct mdss_dsi_phy_ctrl *phy_db)
{
diff --git a/target/msm8974/target_display.c b/target/msm8974/target_display.c
old mode 100644
new mode 100755
index ddee155..270a300
--- a/target/msm8974/target_display.c
+++ b/target/msm8974/target_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -94,7 +94,7 @@
return rc;
}
-int target_backlight_ctrl(uint8_t enable)
+static int msm8974_wled_backlight_ctrl(uint8_t enable)
{
uint32_t platform_id = board_platform_id();
uint32_t hardware_id = board_hardware_id();
@@ -117,6 +117,62 @@
return NO_ERROR;
}
+static int msm8974_pwm_backlight_ctrl(int gpio_num, int lpg_chan, int enable)
+{
+ struct pm8x41_gpio gpio_param = {
+ .direction = PM_GPIO_DIR_OUT,
+ .function = PM_GPIO_FUNC_2,
+ .vin_sel = 2, /* VIN_2 */
+ .pull = PM_GPIO_PULL_UP_1_5 | PM_GPIO_PULLDOWN_10,
+ .output_buffer = PM_GPIO_OUT_CMOS,
+ .out_strength = PM_GPIO_OUT_DRIVE_HIGH,
+ };
+
+ dprintf(SPEW, "%s: gpio=%d lpg=%d enable=%d\n", __func__,
+ gpio_num, lpg_chan, enable);
+
+ if (enable) {
+ pm8x41_gpio_config(gpio_num, &gpio_param);
+ pm8x41_lpg_write(lpg_chan, 0x41, 0x33); /* LPG_PWM_SIZE_CLK, */
+ pm8x41_lpg_write(lpg_chan, 0x42, 0x01); /* LPG_PWM_FREQ_PREDIV */
+ pm8x41_lpg_write(lpg_chan, 0x43, 0x20); /* LPG_PWM_TYPE_CONFIG */
+ pm8x41_lpg_write(lpg_chan, 0x44, 0xb2); /* LPG_VALUE_LSB */
+ pm8x41_lpg_write(lpg_chan, 0x45, 0x01); /* LPG_VALUE_MSB */
+ pm8x41_lpg_write(lpg_chan, 0x46, 0xe4); /* LPG_ENABLE_CONTROL */
+ } else {
+ pm8x41_lpg_write(lpg_chan, 0x46, 0x00);
+ }
+
+ return NO_ERROR;
+}
+
+int target_backlight_ctrl(struct backlight *bl, uint8_t enable)
+{
+ uint32_t ret = NO_ERROR;
+
+ if (!bl) {
+ dprintf(CRITICAL, "backlight structure is not available\n");
+ return ERR_INVALID_ARGS;
+ }
+
+ switch (bl->bl_interface_type) {
+ case BL_WLED:
+ ret = msm8974_wled_backlight_ctrl(enable);
+ break;
+ case BL_PWM:
+ ret = msm8974_pwm_backlight_ctrl(pwm_gpio.pin_id,
+ PWM_BL_LPG_CHAN_ID,
+ enable);
+ break;
+ default:
+ dprintf(CRITICAL, "backlight type:%d not supported\n",
+ bl->bl_interface_type);
+ return ERR_NOT_SUPPORTED;
+ }
+
+ return ret;
+}
+
int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
{
struct mdss_dsi_pll_config *pll_data;
@@ -234,22 +290,6 @@
return 0;
}
-static void msm8974_lpg_backlight_enable(void)
-{
- /* lpg channel 8 */
- pm8x41_lpg_write(8, 0x41, 0x33); /* LPG_PWM_SIZE_CLK, */
- pm8x41_lpg_write(8, 0x42, 0x01); /* LPG_PWM_FREQ_PREDIV */
- pm8x41_lpg_write(8, 0x43, 0x20); /* LPG_PWM_TYPE_CONFIG */
- pm8x41_lpg_write(8, 0x44, 0xb2); /* LPG_VALUE_LSB */
- pm8x41_lpg_write(8, 0x45, 0x01); /* LPG_VALUE_MSB */
- pm8x41_lpg_write(8, 0x46, 0xe4); /* LPG_ENABLE_CONTROL */
-}
-
-static void msm8974_lpg_backlight_disable(void)
-{
- pm8x41_lpg_write(8, 0x46, 0x00); /* LPG_ENABLE_CONTROL */
-}
-
static int msm8974_edp_panel_power(int enable)
{
struct pm8x41_gpio gpio36_param = {
@@ -266,8 +306,7 @@
if (enable) {
/* Enable backlight */
dprintf(SPEW, "Enable Backlight\n");
- pm8x41_gpio_config(36, &gpio36_param);
- msm8974_lpg_backlight_enable();
+ msm8974_pwm_backlight_ctrl(36, 8, 1);
dprintf(SPEW, "Enable Backlight Done\n");
/* Turn on LDO12 for edp vdda */
@@ -285,13 +324,13 @@
} else {
/* Keep LDO12 on, otherwise kernel will not boot */
gpio_set(58, 0);
- msm8974_lpg_backlight_disable();
+ msm8974_pwm_backlight_ctrl(36, 8, 0);
}
return 0;
}
-void display_init(void)
+void target_display_init(const char *panel_name)
{
uint32_t hw_id = board_hardware_id();
uint32_t panel_loop = 0;
@@ -314,7 +353,8 @@
break;
default:
do {
- ret = gcdb_display_init(MDP_REV_50, MIPI_FB_ADDR);
+ ret = gcdb_display_init(panel_name, MDP_REV_50,
+ MIPI_FB_ADDR);
if (!ret || ret == ERR_NOT_SUPPORTED) {
break;
} else {
@@ -327,7 +367,7 @@
}
}
-void display_shutdown(void)
+void target_display_shutdown(void)
{
uint32_t hw_id = board_hardware_id();
switch (hw_id) {