target: msm8226: update dsi pll lock sequence
This change updates dsi pll lock sequence for 8226
platform as recommended by HW team.
Change-Id: Ie8669bd6f7a8ee4d92fd21aa568528faebe3612a
diff --git a/platform/msm_shared/mipi_dsi_autopll.c b/platform/msm_shared/mipi_dsi_autopll.c
index 72f2f94..d21e8d7 100755
--- a/platform/msm_shared/mipi_dsi_autopll.c
+++ b/platform/msm_shared/mipi_dsi_autopll.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013, 2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -149,9 +149,14 @@
cal_cfg11 = gen_vco_clk / 256000000;
cal_cfg10 = (gen_vco_clk % 256000000) / 1000000;
- writel(sdm_cfg1 , ctl_base + 0x023c); /* SDM CFG1 */
- writel(sdm_cfg2 , ctl_base + 0x0240); /* SDM CFG2 */
- writel(sdm_cfg3 , ctl_base + 0x0244); /* SDM CFG3 */
+ writel(0x02, ctl_base + 0x0208); /* PUMP CFG */
+ writel(0x2b, ctl_base + 0x0278); /* CAL CFG3 */
+ writel(0x66, ctl_base + 0x027c); /* CAL CFG4 */
+ writel(0x0d, ctl_base + 0x0264); /* LKDetect CFG2 */
+
+ writel(sdm_cfg1 & 0xff , ctl_base + 0x023c); /* SDM CFG1 */
+ writel(sdm_cfg2 & 0xff , ctl_base + 0x0240); /* SDM CFG2 */
+ writel(sdm_cfg3 & 0xff, ctl_base + 0x0244); /* SDM CFG3 */
writel(0x00, ctl_base + 0x0248); /* SDM CFG4 */
udelay(10);
@@ -162,7 +167,7 @@
writel(pd->directpath, ctl_base + 0x0210); /* VREG CFG */
writel(sdm_cfg0, ctl_base + 0x0238); /* SDM CFG0 */
- writel(0x0a, ctl_base + 0x026c); /* CAL CFG0 */
+ writel(0x12, ctl_base + 0x026c); /* CAL CFG0 */
writel(0x30, ctl_base + 0x0284); /* CAL CFG6 */
writel(0x00, ctl_base + 0x0288); /* CAL CFG7 */
writel(0x60, ctl_base + 0x028c); /* CAL CFG8 */
diff --git a/platform/msm_shared/mipi_dsi_phy.c b/platform/msm_shared/mipi_dsi_phy.c
index 367ed01..6449e02 100644
--- a/platform/msm_shared/mipi_dsi_phy.c
+++ b/platform/msm_shared/mipi_dsi_phy.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -199,10 +199,10 @@
void mdss_dsi_uniphy_pll_lock_detect_setting(uint32_t ctl_base)
{
- writel(0x0c, ctl_base + 0x0264); /* LKDetect CFG2 */
- udelay(100);
writel(0x0d, ctl_base + 0x0264); /* LKDetect CFG2 */
- mdelay(1);
+ writel(0x0c, ctl_base + 0x0264); /* LKDetect CFG2 */
+ udelay(1);
+ writel(0x0d, ctl_base + 0x0264); /* LKDetect CFG2 */
}
void mdss_dsi_uniphy_pll_sw_reset(uint32_t ctl_base)
diff --git a/target/msm8226/target_display.c b/target/msm8226/target_display.c
index d36ac56..a176b58 100755
--- a/target/msm8226/target_display.c
+++ b/target/msm8226/target_display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -45,6 +45,7 @@
#include "include/display_resource.h"
#define HFPLL_LDO_ID 8
+#define MAX_M_SEQ_COUNTER 7
static struct pm8x41_wled_data wled_ctrl = {
.mod_scheme = 0x00,
@@ -67,22 +68,23 @@
* the updates to take effect. These delays are necessary for the
* PLL to successfully lock
*/
+ writel(0x34, ctl_base + 0x00270); /* CAL CFG1*/
writel(0x01, ctl_base + 0x0220); /* GLB CFG */
udelay(200);
writel(0x05, ctl_base + 0x0220); /* GLB CFG */
udelay(200);
writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
- udelay(1000);
+ udelay(600);
mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
pll_locked = readl(ctl_base + 0x02c0) & 0x01;
- for (i = 0; (i < 4) && !pll_locked; i++) {
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
- if (i != 0)
- writel(0x34, ctl_base + 0x00270); /* CAL CFG1*/
- udelay(1);
+ for (i = 0; (i < MAX_M_SEQ_COUNTER) && !pll_locked; i++) {
+ writel(0x00, ctl_base + 0x0214); /* PWRGEN CFG */
+ udelay(50);
+ writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ udelay(100);
writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
- udelay(1000);
+ udelay(600);
mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
pll_locked = readl(ctl_base + 0x02c0) & 0x01;
}
@@ -101,6 +103,8 @@
* the updates to take effect. These delays are necessary for the
* PLL to successfully lock
*/
+ writel(0x00, ctl_base + 0x0214); /* PWRGEN CFG */
+ udelay(50);
writel(0x01, ctl_base + 0x0220); /* GLB CFG */
udelay(200);
writel(0x05, ctl_base + 0x0220); /* GLB CFG */
@@ -112,7 +116,7 @@
writel(0x07, ctl_base + 0x0220); /* GLB CFG */
udelay(200);
writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
- udelay(1000);
+ udelay(600);
mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
pll_locked = readl(ctl_base + 0x02c0) & 0x01;
@@ -131,6 +135,8 @@
* the updates to take effect. These delays are necessary for the
* PLL to successfully lock
*/
+ writel(0x00, ctl_base + 0x0214); /* PWRGEN CFG */
+ udelay(50);
writel(0x01, ctl_base + 0x0220); /* GLB CFG */
udelay(200);
writel(0x05, ctl_base + 0x0220); /* GLB CFG */
@@ -140,7 +146,7 @@
writel(0x0d, ctl_base + 0x0220); /* GLB CFG */
udelay(200);
writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
- udelay(1000);
+ udelay(600);
mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
pll_locked = readl(ctl_base + 0x02c0) & 0x01;
@@ -159,12 +165,14 @@
* the updates to take effect. These delays are necessary for the
* PLL to successfully lock
*/
+ writel(0x00, ctl_base + 0x0214); /* PWRGEN CFG */
+ udelay(50);
writel(0x01, ctl_base + 0x0220); /* GLB CFG */
udelay(200);
writel(0x05, ctl_base + 0x0220); /* GLB CFG */
udelay(200);
writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
- udelay(1000);
+ udelay(600);
mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
pll_locked = readl(ctl_base + 0x02c0) & 0x01;
@@ -183,6 +191,8 @@
* the updates to take effect. These delays are necessary for the
* PLL to successfully lock
*/
+ writel(0x00, ctl_base + 0x0214); /* PWRGEN CFG */
+ udelay(50);
writel(0x01, ctl_base + 0x0220); /* GLB CFG */
udelay(200);
writel(0x05, ctl_base + 0x0220); /* GLB CFG */
@@ -190,7 +200,7 @@
writel(0x0d, ctl_base + 0x0220); /* GLB CFG */
udelay(1);
writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
- udelay(1000);
+ udelay(600);
mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
pll_locked = readl(ctl_base + 0x02c0) & 0x01;
@@ -273,6 +283,7 @@
static void dsi_pll_enable_seq(uint32_t ctl_base)
{
if (dsi_pll_enable_seq_m(ctl_base)) {
+ } else if (dsi_pll_enable_seq_m(ctl_base)) {
} else if (dsi_pll_enable_seq_d(ctl_base)) {
} else if (dsi_pll_enable_seq_d(ctl_base)) {
} else if (dsi_pll_enable_seq_f1(ctl_base)) {