Merge "platform/target: msm8909: Change debug UART to UART0"
diff --git a/dev/gcdb/display/gcdb_autopll.c b/dev/gcdb/display/gcdb_autopll.c
index 38ba3b4..e2e497f 100755
--- a/dev/gcdb/display/gcdb_autopll.c
+++ b/dev/gcdb/display/gcdb_autopll.c
@@ -43,7 +43,10 @@
uint32_t width = pinfo->xres;
if (pinfo->mipi.dual_dsi)
- width = pinfo->xres / 2;
+ width /= 2;
+
+ if (pinfo->fbc.enabled && pinfo->fbc.comp_ratio)
+ width /= pinfo->fbc.comp_ratio;
h_period = width + pinfo->lcdc.h_back_porch +
pinfo->lcdc.h_front_porch + pinfo->lcdc.h_pulse_width +
diff --git a/dev/gcdb/display/include/panel.h b/dev/gcdb/display/include/panel.h
index 1a328f5..c21383e 100755
--- a/dev/gcdb/display/include/panel.h
+++ b/dev/gcdb/display/include/panel.h
@@ -178,4 +178,24 @@
char *bl_pmic_model;
};
+typedef struct fb_compression {
+ uint32_t enabled;
+ uint32_t comp_ratio;
+ uint32_t comp_mode;
+ uint32_t qerr_enable;
+ uint32_t cd_bias;
+ uint32_t pat_enable;
+ uint32_t vlc_enable;
+ uint32_t bflc_enable;
+
+ uint32_t line_x_budget;
+ uint32_t block_x_budget;
+ uint32_t block_budget;
+
+ uint32_t lossless_mode_thd;
+ uint32_t lossy_mode_thd;
+ uint32_t lossy_rgb_thd;
+ uint32_t lossy_mode_idx;
+};
+
#endif /*_PANEL_H_ */
diff --git a/dev/gcdb/display/include/panel_nt35521_wxga_video.h b/dev/gcdb/display/include/panel_nt35521_wxga_video.h
new file mode 100644
index 0000000..bdac711
--- /dev/null
+++ b/dev/gcdb/display/include/panel_nt35521_wxga_video.h
@@ -0,0 +1,1033 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PANEL_NT35521_WXGA_VIDEO_H_
+#define _PANEL_NT35521_WXGA_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+static struct panel_config nt35521_wxga_video_panel_data = {
+ "qcom,mdss_dsi_nt35521_wxga_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution nt35521_wxga_video_panel_res = {
+ 800, 1280, 44, 55, 11, 0, 14, 15, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel color information */
+/*---------------------------------------------------------------------------*/
+static struct color_info nt35521_wxga_video_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel on/off command information */
+/*---------------------------------------------------------------------------*/
+static char nt35521_wxga_video_on_cmd0[] = {
+ 0x05, 0x00, 0x29, 0xC0,
+ 0xFF, 0xAA, 0x55, 0xA5,
+ 0x80, 0xFF, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd1[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0x6F, 0x11, 0x00, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd2[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xF7, 0x20, 0x00, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd3[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x6F, 0x06, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd4[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xF7, 0xA0, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd5[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x6F, 0x19, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd6[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xF7, 0x12, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd7[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x6F, 0x08, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd8[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xFA, 0x40, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd9[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x6F, 0x11, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd10[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xF3, 0x01, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd11[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xF0, 0x55, 0xAA, 0x52,
+ 0x08, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd12[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xC8, 0x80, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd13[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB1, 0x6C, 0x01, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd14[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xB6, 0x08, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd15[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x6F, 0x02, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd16[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xB8, 0x08, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd17[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xBB, 0x74, 0x44, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd18[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xBC, 0x00, 0x00, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd19[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xBD, 0x02, 0xB0, 0x0C,
+ 0x0A, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd20[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xF0, 0x55, 0xAA, 0x52,
+ 0x08, 0x01, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd21[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB0, 0x05, 0x05, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd22[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB1, 0x05, 0x05, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd23[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xBC, 0x90, 0x01, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd24[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xBD, 0x90, 0x01, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd25[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xCA, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd26[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xC0, 0x04, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd27[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xB2, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd28[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xBE, 0x29, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd29[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB3, 0x37, 0x37, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd30[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB4, 0x19, 0x19, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd31[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB9, 0x44, 0x44, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd32[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xBA, 0x24, 0x24, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd33[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xF0, 0x55, 0xAA, 0x52,
+ 0x08, 0x02, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd34[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xEE, 0x01, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd35[] = {
+ 0x05, 0x00, 0x29, 0xC0,
+ 0xEF, 0x09, 0x06, 0x15,
+ 0x18, 0xFF, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd36[] = {
+ 0x07, 0x00, 0x29, 0xC0,
+ 0xB0, 0x00, 0x00, 0x00,
+ 0x25, 0x00, 0x43, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd37[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x6F, 0x06, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd38[] = {
+ 0x07, 0x00, 0x29, 0xC0,
+ 0xB0, 0x00, 0x54, 0x00,
+ 0x68, 0x00, 0xA0, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd39[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x6F, 0x0C, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd40[] = {
+ 0x05, 0x00, 0x29, 0xC0,
+ 0xB0, 0x00, 0xC0, 0x01,
+ 0x00, 0xFF, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd41[] = {
+ 0x07, 0x00, 0x29, 0xC0,
+ 0xB1, 0x01, 0x30, 0x01,
+ 0x78, 0x01, 0xAE, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd42[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x6F, 0x06, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd43[] = {
+ 0x07, 0x00, 0x29, 0xC0,
+ 0xB1, 0x02, 0x08, 0x02,
+ 0x52, 0x02, 0x54, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd44[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x6F, 0x0C, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd45[] = {
+ 0x05, 0x00, 0x29, 0xC0,
+ 0xB1, 0x02, 0x99, 0x02,
+ 0xF0, 0xFF, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd46[] = {
+ 0x07, 0x00, 0x29, 0xC0,
+ 0xB2, 0x03, 0x20, 0x03,
+ 0x56, 0x03, 0x76, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd47[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x6F, 0x06, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd48[] = {
+ 0x07, 0x00, 0x29, 0xC0,
+ 0xB2, 0x03, 0x93, 0x03,
+ 0xA4, 0x03, 0xB9, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd49[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x6F, 0x0C, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd50[] = {
+ 0x05, 0x00, 0x29, 0xC0,
+ 0xB2, 0x03, 0xC9, 0x03,
+ 0xE3, 0xFF, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd51[] = {
+ 0x05, 0x00, 0x29, 0xC0,
+ 0xB3, 0x03, 0xFC, 0x03,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd52[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xF0, 0x55, 0xAA, 0x52,
+ 0x08, 0x06, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd53[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB0, 0x00, 0x10, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd54[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB1, 0x12, 0x14, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd55[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB2, 0x16, 0x18, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd56[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB3, 0x1A, 0x29, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd57[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB4, 0x2A, 0x08, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd58[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB5, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd59[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB6, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd60[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB7, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd61[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB8, 0x31, 0x0A, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd62[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB9, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd63[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xBA, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd64[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xBB, 0x0B, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd65[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xBC, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd66[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xBD, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd67[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xBE, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd68[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xBF, 0x09, 0x2A, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd69[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xC0, 0x29, 0x1B, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd70[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xC1, 0x19, 0x17, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd71[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xC2, 0x15, 0x13, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd72[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xC3, 0x11, 0x01, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd73[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xE5, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd74[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xC4, 0x09, 0x1B, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd75[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xC5, 0x19, 0x17, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd76[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xC6, 0x15, 0x13, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd77[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xC7, 0x11, 0x29, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd78[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xC8, 0x2A, 0x01, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd79[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xC9, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd80[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xCA, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd81[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xCB, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd82[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xCC, 0x31, 0x0B, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd83[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xCD, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd84[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xCE, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd85[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xCF, 0x0A, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd86[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xD0, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd87[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xD1, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd88[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xD2, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd89[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xD3, 0x00, 0x2A, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd90[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xD4, 0x29, 0x10, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd91[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xD5, 0x12, 0x14, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd92[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xD6, 0x16, 0x18, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd93[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xD7, 0x1A, 0x08, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd94[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xE6, 0x31, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd95[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xD8, 0x00, 0x00, 0x00,
+ 0x54, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd96[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xD9, 0x00, 0x15, 0x00,
+ 0x00, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd97[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xE7, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd98[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xF0, 0x55, 0xAA, 0x52,
+ 0x08, 0x03, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd99[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB0, 0x20, 0x00, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd100[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB1, 0x20, 0x00, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd101[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xB2, 0x05, 0x00, 0x00,
+ 0x00, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd102[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xB6, 0x05, 0x00, 0x00,
+ 0x00, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd103[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xB7, 0x05, 0x00, 0x00,
+ 0x00, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd104[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xBA, 0x57, 0x00, 0x00,
+ 0x00, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd105[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xBB, 0x57, 0x00, 0x00,
+ 0x00, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd106[] = {
+ 0x05, 0x00, 0x29, 0xC0,
+ 0xC0, 0x00, 0x00, 0x00,
+ 0x00, 0xFF, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd107[] = {
+ 0x05, 0x00, 0x29, 0xC0,
+ 0xC1, 0x00, 0x00, 0x00,
+ 0x00, 0xFF, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd108[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xC4, 0x60, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd109[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xC5, 0x40, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd110[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xF0, 0x55, 0xAA, 0x52,
+ 0x08, 0x05, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd111[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xBD, 0x03, 0x01, 0x03,
+ 0x03, 0x03, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd112[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB0, 0x17, 0x06, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd113[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB1, 0x17, 0x06, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd114[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB2, 0x17, 0x06, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd115[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB3, 0x17, 0x06, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd116[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB4, 0x17, 0x06, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd117[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xB5, 0x17, 0x06, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd118[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xB8, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd119[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xB9, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd120[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xBA, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd121[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xBB, 0x02, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd122[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xBC, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd123[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xC0, 0x07, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd124[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xC4, 0x80, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd125[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xC5, 0xA4, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd126[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xC8, 0x05, 0x30, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd127[] = {
+ 0x03, 0x00, 0x29, 0xC0,
+ 0xC9, 0x01, 0x31, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd128[] = {
+ 0x04, 0x00, 0x29, 0xC0,
+ 0xCC, 0x00, 0x00, 0x3C,
+};
+
+static char nt35521_wxga_video_on_cmd129[] = {
+ 0x04, 0x00, 0x29, 0xC0,
+ 0xCD, 0x00, 0x00, 0x3C,
+};
+
+static char nt35521_wxga_video_on_cmd130[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xD1, 0x00, 0x04, 0xFD,
+ 0x07, 0x10, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd131[] = {
+ 0x06, 0x00, 0x29, 0xC0,
+ 0xD2, 0x00, 0x05, 0x02,
+ 0x07, 0x10, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd132[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xE5, 0x06, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd133[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xE6, 0x06, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd134[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xE7, 0x06, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd135[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xE8, 0x06, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd136[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xE9, 0x06, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd137[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xEA, 0x06, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd138[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xED, 0x30, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd139[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x6F, 0x11, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd140[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0xF3, 0x01, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd141[] = {
+ 0x02, 0x00, 0x29, 0xC0,
+ 0x35, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35521_wxga_video_on_cmd142[] = {
+ 0x11, 0x00, 0x05, 0x80
+};
+
+static char nt35521_wxga_video_on_cmd143[] = {
+ 0x29, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd nt35521_wxga_video_on_command[] = {
+ {0xc, nt35521_wxga_video_on_cmd0, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd1, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd2, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd3, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd4, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd5, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd6, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd7, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd8, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd9, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd10, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd11, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd12, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd13, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd14, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd15, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd16, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd17, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd18, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd19, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd20, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd21, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd22, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd23, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd24, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd25, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd26, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd27, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd28, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd29, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd30, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd31, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd32, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd33, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd34, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd35, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd36, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd37, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd38, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd39, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd40, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd41, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd42, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd43, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd44, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd45, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd46, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd47, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd48, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd49, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd50, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd51, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd52, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd53, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd54, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd55, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd56, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd57, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd58, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd59, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd60, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd61, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd62, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd63, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd64, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd65, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd66, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd67, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd68, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd69, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd70, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd71, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd72, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd73, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd74, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd75, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd76, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd77, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd78, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd79, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd80, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd81, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd82, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd83, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd84, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd85, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd86, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd87, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd88, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd89, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd90, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd91, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd92, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd93, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd94, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd95, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd96, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd97, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd98, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd99, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd100, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd101, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd102, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd103, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd104, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd105, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd106, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd107, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd108, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd109, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd110, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd111, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd112, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd113, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd114, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd115, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd116, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd117, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd118, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd119, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd120, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd121, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd122, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd123, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd124, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd125, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd126, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd127, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd128, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd129, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd130, 0x00},
+ {0xc, nt35521_wxga_video_on_cmd131, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd132, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd133, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd134, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd135, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd136, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd137, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd138, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd139, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd140, 0x00},
+ {0x8, nt35521_wxga_video_on_cmd141, 0x00},
+ {0x4, nt35521_wxga_video_on_cmd142, 0x00},
+ {0x4, nt35521_wxga_video_on_cmd143, 0x00}
+};
+
+#define NT35521_WXGA_VIDEO_ON_COMMAND 144
+
+
+static char nt35521_wxga_videooff_cmd0[] = {
+ 0x28, 0x00, 0x05, 0x80
+};
+
+static char nt35521_wxga_videooff_cmd1[] = {
+ 0x10, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd nt35521_wxga_video_off_command[] = {
+ {0x4, nt35521_wxga_videooff_cmd0, 0x32},
+ {0x4, nt35521_wxga_videooff_cmd1, 0x78}
+};
+
+#define NT35521_WXGA_VIDEO_OFF_COMMAND 2
+
+
+static struct command_state nt35521_wxga_video_state = {
+ 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct commandpanel_info nt35521_wxga_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct videopanel_info nt35521_wxga_video_video_panel = {
+ 1, 0, 0, 0, 1, 1, 2, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane configuration */
+/*---------------------------------------------------------------------------*/
+static struct lane_configuration nt35521_wxga_video_lane_config = {
+ 4, 0, 1, 1, 1, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel timing */
+/*---------------------------------------------------------------------------*/
+static const uint32_t nt35521_wxga_video_timings[] = {
+ 0x93, 0x1F, 0x17, 0x00, 0x2F, 0x2E, 0x1C, 0x21, 0x26, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing nt35521_wxga_video_timing_info = {
+ 0, 4, 0x20, 0x2D
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel reset sequence */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence nt35521_wxga_video_reset_seq = {
+ {1, 0, 1, }, {20, 1, 20, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight setting */
+/*---------------------------------------------------------------------------*/
+static struct backlight nt35521_wxga_video_backlight = {
+ 0, 1, 255, 2, 0, "PMIC_8941"
+};
+
+#endif /*_PANEL_NT35521_WXGA_VIDEO_H_*/
diff --git a/dev/gcdb/display/panel_display.c b/dev/gcdb/display/panel_display.c
old mode 100644
new mode 100755
index 427a548..9734574
--- a/dev/gcdb/display/panel_display.c
+++ b/dev/gcdb/display/panel_display.c
@@ -153,6 +153,27 @@
pinfo->mipi.mdp_trigger = pstruct->paneltiminginfo->dsi_mdp_trigger;
pinfo->mipi.dma_trigger = pstruct->paneltiminginfo->dsi_dma_trigger;
+ pinfo->fbc.enabled = pstruct->fbcinfo.enabled;
+ if (pinfo->fbc.enabled) {
+ pinfo->fbc.enabled = pstruct->fbcinfo.enabled;
+ pinfo->fbc.comp_ratio= pstruct->fbcinfo.comp_ratio;
+ pinfo->fbc.comp_mode = pstruct->fbcinfo.comp_mode;
+ pinfo->fbc.qerr_enable = pstruct->fbcinfo.qerr_enable;
+ pinfo->fbc.cd_bias = pstruct->fbcinfo.cd_bias;
+ pinfo->fbc.pat_enable = pstruct->fbcinfo.pat_enable;
+ pinfo->fbc.vlc_enable = pstruct->fbcinfo.vlc_enable;
+ pinfo->fbc.bflc_enable = pstruct->fbcinfo.bflc_enable;
+ pinfo->fbc.line_x_budget = pstruct->fbcinfo.line_x_budget;
+ pinfo->fbc.block_x_budget = pstruct->fbcinfo.block_x_budget;
+ pinfo->fbc.block_budget = pstruct->fbcinfo.block_budget;
+ pinfo->fbc.lossless_mode_thd = pstruct->fbcinfo.lossless_mode_thd;
+ pinfo->fbc.lossy_mode_thd = pstruct->fbcinfo.lossy_mode_thd;
+ pinfo->fbc.lossy_rgb_thd = pstruct->fbcinfo.lossy_rgb_thd;
+ pinfo->fbc.lossy_mode_idx = pstruct->fbcinfo.lossy_mode_idx;
+ } else {
+ pinfo->fbc.comp_ratio = 1;
+ }
+
pinfo->pre_on = dsi_panel_pre_on;
pinfo->pre_off = dsi_panel_pre_off;
pinfo->on = dsi_panel_post_on;
@@ -211,6 +232,9 @@
int ret = NO_ERROR;
uint8_t lane_enable = 0;
uint32_t panel_width = pinfo->xres;
+ uint32_t final_xres, final_yres, final_width;
+ uint32_t final_height, final_hbp, final_hfp,final_vbp;
+ uint32_t final_vfp, final_hpw, final_vpw;
if (pinfo->mipi.dual_dsi)
panel_width = panel_width / 2;
@@ -224,16 +248,29 @@
if (pinfo->mipi.data_lane3)
lane_enable |= (1 << 3);
- ret = mdss_dsi_video_mode_config((panel_width + plcdc->xres_pad),
- (pinfo->yres + plcdc->yres_pad),
- (panel_width),
- (pinfo->yres),
- (plcdc->h_front_porch),
- (plcdc->h_back_porch + plcdc->h_pulse_width),
- (plcdc->v_front_porch),
- (plcdc->v_back_porch + plcdc->v_pulse_width),
- (plcdc->h_pulse_width),
- (plcdc->v_pulse_width),
+ final_xres = panel_width;
+ final_width = panel_width + pinfo->lcdc.xres_pad;
+
+ if (pinfo->fbc.enabled && pinfo->fbc.comp_ratio) {
+ final_xres /= pinfo->fbc.comp_ratio;
+ final_width /= pinfo->fbc.comp_ratio;
+ dprintf(SPEW, "DSI xres =%d final_width=%d\n", final_xres,
+ final_width);
+ }
+ final_yres = pinfo->yres;
+ final_height = pinfo->yres + pinfo->lcdc.yres_pad;
+ final_hbp = pinfo->lcdc.h_back_porch;
+ final_hfp = pinfo->lcdc.h_front_porch;
+ final_vbp = pinfo->lcdc.v_back_porch;
+ final_vfp = pinfo->lcdc.v_front_porch;
+ final_hpw = pinfo->lcdc.h_pulse_width;
+ final_vpw = pinfo->lcdc.v_pulse_width;
+
+ ret = mdss_dsi_video_mode_config(final_width, final_height,
+ final_xres, final_yres,
+ final_hfp, final_hbp + final_hpw,
+ final_vfp, final_vbp + final_vpw,
+ final_hpw, final_vpw,
pinfo->mipi.dst_format,
pinfo->mipi.traffic_mode,
lane_enable,
@@ -243,24 +280,18 @@
MIPI_DSI0_BASE);
if (pinfo->mipi.dual_dsi)
- ret = mdss_dsi_video_mode_config(
- (panel_width + plcdc->xres_pad),
- (pinfo->yres + plcdc->yres_pad),
- (panel_width),
- (pinfo->yres),
- (plcdc->h_front_porch),
- (plcdc->h_back_porch + plcdc->h_pulse_width),
- (plcdc->v_front_porch),
- (plcdc->v_back_porch + plcdc->v_pulse_width),
- (plcdc->h_pulse_width),
- (plcdc->v_pulse_width),
- pinfo->mipi.dst_format,
- pinfo->mipi.traffic_mode,
- lane_enable,
- pinfo->mipi.hsa_power_stop,
- pinfo->mipi.eof_bllp_power,
- pinfo->mipi.interleave_mode,
- MIPI_DSI1_BASE);
+ ret = mdss_dsi_video_mode_config(final_width, final_height,
+ final_xres, final_yres,
+ final_hfp, final_hbp + final_hpw,
+ final_vfp, final_vbp + final_vpw,
+ final_hpw, final_vpw,
+ pinfo->mipi.dst_format,
+ pinfo->mipi.traffic_mode,
+ lane_enable,
+ pinfo->mipi.hsa_power_stop,
+ pinfo->mipi.eof_bllp_power,
+ pinfo->mipi.interleave_mode,
+ MIPI_DSI1_BASE);
return ret;
}
diff --git a/dev/gcdb/display/panel_display.h b/dev/gcdb/display/panel_display.h
index a6843ce..dcc5631 100755
--- a/dev/gcdb/display/panel_display.h
+++ b/dev/gcdb/display/panel_display.h
@@ -47,6 +47,7 @@
#define DST_SPLIT_FLAG 0x10
#define MAX_PANEL_ID_LEN 64
+#include "panel.h"
/*---------------------------------------------------------------------------*/
/* struct definition */
/*---------------------------------------------------------------------------*/
@@ -61,6 +62,7 @@
struct panel_timing *paneltiminginfo;
struct panel_reset_sequence *panelresetseq;
struct backlight *backlightinfo;
+ struct fb_compression fbcinfo;
};
struct panel_list {
diff --git a/include/target.h b/include/target.h
index ba95cbb..16a4268 100644
--- a/include/target.h
+++ b/include/target.h
@@ -75,4 +75,5 @@
bool target_is_cdp_qvga();
uint32_t target_hw_interposer();
uint32_t target_override_pll();
+uint32_t target_ddr_cfg_val();
#endif
diff --git a/platform/apq8084/include/platform/iomap.h b/platform/apq8084/include/platform/iomap.h
index c8a7991..67a6f5b 100644
--- a/platform/apq8084/include/platform/iomap.h
+++ b/platform/apq8084/include/platform/iomap.h
@@ -259,6 +259,16 @@
#define MDP_VP_0_MIXER_0_BASE REG_MDP(0x3A00)
#define MDP_VP_0_MIXER_1_BASE REG_MDP(0x3E00)
+#ifdef MDP_PP_0_BASE
+#undef MDP_PP_0_BASE
+#endif
+#define MDP_PP_0_BASE REG_MDP(0x12F00)
+
+#ifdef MDP_PP_1_BASE
+#undef MDP_PP_1_BASE
+#endif
+#define MDP_PP_1_BASE REG_MDP(0x13000)
+
#define DMA_CMD_OFFSET 0x048
#define DMA_CMD_LENGTH 0x04C
diff --git a/platform/msm8916/platform.c b/platform/msm8916/platform.c
index beab585..7e583c6 100644
--- a/platform/msm8916/platform.c
+++ b/platform/msm8916/platform.c
@@ -52,7 +52,7 @@
MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
/* IMEM memory - cacheable, write through */
-#define IMEM_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+#define COMMON_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
static mmu_section_t mmu_section_table[] = {
@@ -60,7 +60,10 @@
{ MEMBASE, MEMBASE, (MEMSIZE / MB), LK_MEMORY},
{ MSM_IOMAP_BASE, MSM_IOMAP_BASE, MSM_IOMAP_SIZE, IOMAP_MEMORY},
{ A53_SS_BASE, A53_SS_BASE, A53_SS_SIZE, IOMAP_MEMORY},
- { SYSTEM_IMEM_BASE, SYSTEM_IMEM_BASE, 1, IMEM_MEMORY},
+ { SYSTEM_IMEM_BASE, SYSTEM_IMEM_BASE, 1, COMMON_MEMORY},
+ { MSM_SHARED_BASE, MSM_SHARED_BASE, 1, COMMON_MEMORY},
+ { BASE_ADDR, BASE_ADDR, 90, COMMON_MEMORY},
+ { SCRATCH_ADDR, SCRATCH_ADDR, 256, COMMON_MEMORY},
};
static struct smem_ram_ptable ram_ptable;
@@ -114,39 +117,6 @@
uint32_t i;
uint32_t sections;
uint32_t table_size = ARRAY_SIZE(mmu_section_table);
- ram_partition ptn_entry;
- uint32_t len = 0;
-
- ASSERT(smem_ram_ptable_init_v1());
-
- len = smem_get_ram_ptable_len();
-
- /* Configure the MMU page entries for SDRAM and IMEM memory read
- from the smem ram table*/
- for(i = 0; i < len; i++)
- {
- smem_get_ram_ptable_entry(&ptn_entry, i);
- if(ptn_entry.type == SYS_MEMORY)
- {
- if((ptn_entry.category == SDRAM) ||
- (ptn_entry.category == IMEM))
- {
- /* Check to ensure that start address is 1MB aligned */
- ASSERT((ptn_entry.start & (MB-1)) == 0);
-
- sections = (ptn_entry.size) / MB;
- while(sections--)
- {
- arm_mmu_map_section(ptn_entry.start +
- sections * MB,
- ptn_entry.start +
- sections * MB,
- (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
- MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN));
- }
- }
- }
- }
/* Configure the MMU page entries for memory read from the
mmu_section_table */
diff --git a/platform/msm8994/include/platform/iomap.h b/platform/msm8994/include/platform/iomap.h
index c0b2880..341c0a6 100644
--- a/platform/msm8994/include/platform/iomap.h
+++ b/platform/msm8994/include/platform/iomap.h
@@ -243,6 +243,17 @@
#define MDP_BASE (0xfd900000)
+
+#ifdef MDP_PP_0_BASE
+#undef MDP_PP_0_BASE
+#endif
+#define MDP_PP_0_BASE REG_MDP(0x71000)
+
+#ifdef MDP_PP_1_BASE
+#undef MDP_PP_1_BASE
+#endif
+#define MDP_PP_1_BASE REG_MDP(0x71800)
+
#define REG_MDP(off) (MDP_BASE + (off))
#define MDP_HW_REV REG_MDP(0x1000)
#define MDP_INTR_EN REG_MDP(0x1010)
diff --git a/platform/msm_shared/include/mdp5.h b/platform/msm_shared/include/mdp5.h
index dd5132f..8e17def 100644
--- a/platform/msm_shared/include/mdp5.h
+++ b/platform/msm_shared/include/mdp5.h
@@ -103,6 +103,9 @@
#define MDP_CTL_0_BASE REG_MDP(0x600)
#define MDP_CTL_1_BASE REG_MDP(0x700)
+#define MDP_PP_0_BASE REG_MDP(0x12D00)
+#define MDP_PP_1_BASE REG_MDP(0x12E00)
+
#define CTL_LAYER_0 0x00
#define CTL_LAYER_1 0x04
#define CTL_TOP 0x14
@@ -181,6 +184,10 @@
#define VBIF_VBIF_ABIT_SHORT_CONF REG_MDP(0x24074)
#define VBIF_VBIF_GATE_OFF_WRREQ_EN REG_MDP(0x240A8)
+#define MDSS_MDP_REG_PP_FBC_MODE 0x034
+#define MDSS_MDP_REG_PP_FBC_BUDGET_CTL 0x038
+#define MDSS_MDP_REG_PP_FBC_LOSSY_MODE 0x03C
+
void mdp_set_revision(int rev);
int mdp_get_revision();
int mdp_dsi_video_config(struct msm_panel_info *pinfo, struct fbcon_config *fb);
diff --git a/platform/msm_shared/include/msm_panel.h b/platform/msm_shared/include/msm_panel.h
index c3497a8..651cc53 100755
--- a/platform/msm_shared/include/msm_panel.h
+++ b/platform/msm_shared/include/msm_panel.h
@@ -114,6 +114,45 @@
uint8_t dst_split;
};
+struct fbc_panel_info {
+ uint32_t enabled;
+ uint32_t comp_ratio;
+ uint32_t comp_mode;
+ uint32_t qerr_enable;
+ uint32_t cd_bias;
+ uint32_t pat_enable;
+ uint32_t vlc_enable;
+ uint32_t bflc_enable;
+
+ uint32_t line_x_budget;
+ uint32_t block_x_budget;
+ uint32_t block_budget;
+
+ uint32_t lossless_mode_thd;
+ uint32_t lossy_mode_thd;
+ uint32_t lossy_rgb_thd;
+ uint32_t lossy_mode_idx;
+};
+
+/* intf timing settings */
+struct intf_timing_params {
+ uint32_t width;
+ uint32_t height;
+ uint32_t xres;
+ uint32_t yres;
+
+ uint32_t h_back_porch;
+ uint32_t h_front_porch;
+ uint32_t v_back_porch;
+ uint32_t v_front_porch;
+ uint32_t hsync_pulse_width;
+ uint32_t vsync_pulse_width;
+
+ uint32_t border_clr;
+ uint32_t underflow_clr;
+ uint32_t hsync_skew;
+};
+
struct mipi_panel_info {
char mode; /* video/cmd */
char interleave_mode;
@@ -204,6 +243,7 @@
struct lcd_panel_info lcd;
struct lcdc_panel_info lcdc;
+ struct fbc_panel_info fbc;
struct mipi_panel_info mipi;
struct lvds_panel_info lvds;
struct hdmi_panel_info hdmi;
diff --git a/platform/msm_shared/mdp5.c b/platform/msm_shared/mdp5.c
old mode 100644
new mode 100755
index dd32038..08ebafb
--- a/platform/msm_shared/mdp5.c
+++ b/platform/msm_shared/mdp5.c
@@ -363,11 +363,12 @@
{
uint32_t hsync_period, vsync_period;
uint32_t hsync_start_x, hsync_end_x;
- uint32_t display_hctl, active_hctl, hsync_ctl, display_vstart, display_vend;
+ uint32_t display_hctl, hsync_ctl, display_vstart, display_vend;
uint32_t mdss_mdp_intf_off;
uint32_t adjust_xres = 0;
struct lcdc_panel_info *lcdc = NULL;
+ struct intf_timing_params itp = {0};
if (pinfo == NULL)
return ERR_INVALID_ARGS;
@@ -391,41 +392,58 @@
writel(BIT(5), MDP_REG_PPB0_CNTL);
}
+ if (!pinfo->fbc.enabled || !pinfo->fbc.comp_ratio)
+ pinfo->fbc.comp_ratio = 1;
+
+ itp.xres = (adjust_xres / pinfo->fbc.comp_ratio);
+ itp.yres = pinfo->yres;
+ itp.width =((adjust_xres + pinfo->lcdc.xres_pad) / pinfo->fbc.comp_ratio);
+ itp.height = pinfo->yres + pinfo->lcdc.yres_pad;
+ itp.h_back_porch = pinfo->lcdc.h_back_porch;
+ itp.h_front_porch = pinfo->lcdc.h_front_porch;
+ itp.v_back_porch = pinfo->lcdc.v_back_porch;
+ itp.v_front_porch = pinfo->lcdc.v_front_porch;
+ itp.hsync_pulse_width = pinfo->lcdc.h_pulse_width;
+ itp.vsync_pulse_width = pinfo->lcdc.v_pulse_width;
+
+ itp.border_clr = pinfo->lcdc.border_clr;
+ itp.underflow_clr = pinfo->lcdc.underflow_clr;
+ itp.hsync_skew = pinfo->lcdc.hsync_skew;
+
+
mdss_mdp_intf_off = intf_base + mdss_mdp_intf_offset();
- hsync_period = lcdc->h_pulse_width +
- lcdc->h_back_porch +
- adjust_xres + lcdc->xres_pad + lcdc->h_front_porch;
- vsync_period = (lcdc->v_pulse_width +
- lcdc->v_back_porch +
- pinfo->yres + lcdc->yres_pad +
- lcdc->v_front_porch);
+ hsync_period = itp.hsync_pulse_width + itp.h_back_porch +
+ itp.width + itp.h_front_porch;
+
+ vsync_period = itp.vsync_pulse_width + itp.v_back_porch +
+ itp.height + itp.v_front_porch;
hsync_start_x =
- lcdc->h_pulse_width +
- lcdc->h_back_porch;
+ itp.hsync_pulse_width +
+ itp.h_back_porch;
hsync_end_x =
- hsync_period - lcdc->h_front_porch - 1;
+ hsync_period - itp.h_front_porch - 1;
- display_vstart = (lcdc->v_pulse_width +
- lcdc->v_back_porch)
- * hsync_period + lcdc->hsync_skew;
- display_vend = ((vsync_period - lcdc->v_front_porch) * hsync_period)
- +lcdc->hsync_skew - 1;
+ display_vstart = (itp.vsync_pulse_width +
+ itp.v_back_porch)
+ * hsync_period + itp.hsync_skew;
+ display_vend = ((vsync_period - itp.v_front_porch) * hsync_period)
+ + itp.hsync_skew - 1;
if (intf_base == MDP_INTF_0_BASE) { /* eDP */
- display_vstart += lcdc->h_pulse_width + lcdc->h_back_porch;
- display_vend -= lcdc->h_front_porch;
+ display_vstart += itp.hsync_pulse_width + itp.h_back_porch;
+ display_vend -= itp.h_front_porch;
}
- hsync_ctl = (hsync_period << 16) | lcdc->h_pulse_width;
+ hsync_ctl = (hsync_period << 16) | itp.hsync_pulse_width;
display_hctl = (hsync_end_x << 16) | hsync_start_x;
writel(hsync_ctl, MDP_HSYNC_CTL + mdss_mdp_intf_off);
writel(vsync_period*hsync_period, MDP_VSYNC_PERIOD_F0 +
mdss_mdp_intf_off);
writel(0x00, MDP_VSYNC_PERIOD_F1 + mdss_mdp_intf_off);
- writel(lcdc->v_pulse_width*hsync_period,
+ writel(itp.vsync_pulse_width*hsync_period,
MDP_VSYNC_PULSE_WIDTH_F0 +
mdss_mdp_intf_off);
writel(0x00, MDP_VSYNC_PULSE_WIDTH_F1 + mdss_mdp_intf_off);
@@ -571,6 +589,57 @@
}
}
+void mdss_fbc_cfg(struct msm_panel_info *pinfo)
+{
+ uint32_t mode = 0;
+ uint32_t budget_ctl = 0;
+ uint32_t lossy_mode = 0;
+ uint32_t xres;
+ struct fbc_panel_info *fbc;
+ uint32_t enc_mode;
+
+ fbc = &pinfo->fbc;
+ xres = pinfo->xres;
+
+ if (!pinfo->fbc.enabled)
+ return;
+
+ if (pinfo->mipi.dual_dsi)
+ xres /= 2;
+
+ /* enc_mode defines FBC version. 0 = FBC 1.0 and 1 = FBC 2.0 */
+ enc_mode = (fbc->comp_ratio == 2) ? 0 : 1;
+
+ mode = ((xres) << 16) | (enc_mode) << 9 | ((fbc->comp_mode) << 8) |
+ ((fbc->qerr_enable) << 7) | ((fbc->cd_bias) << 4) |
+ ((fbc->pat_enable) << 3) | ((fbc->vlc_enable) << 2) |
+ ((fbc->bflc_enable) << 1) | 1;
+
+ dprintf(SPEW, "xres = %d, comp_mode %d, qerr_enable = %d, cd_bias = %d\n",
+ xres, fbc->comp_mode, fbc->qerr_enable, fbc->cd_bias);
+ dprintf(SPEW, "pat_enable %d, vlc_enable = %d, bflc_enable\n",
+ fbc->pat_enable, fbc->vlc_enable, fbc->bflc_enable);
+
+ budget_ctl = ((fbc->line_x_budget) << 12) |
+ ((fbc->block_x_budget) << 8) | fbc->block_budget;
+
+ lossy_mode = ((fbc->lossless_mode_thd) << 16) |
+ ((fbc->lossy_mode_thd) << 8) |
+ ((fbc->lossy_rgb_thd) << 4) | fbc->lossy_mode_idx;
+
+ writel(mode, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_MODE);
+ writel(budget_ctl, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_BUDGET_CTL);
+ writel(lossy_mode, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_LOSSY_MODE);
+
+ if (pinfo->mipi.dual_dsi) {
+ writel(mode, MDP_PP_1_BASE + MDSS_MDP_REG_PP_FBC_MODE);
+ writel(budget_ctl, MDP_PP_1_BASE +
+ MDSS_MDP_REG_PP_FBC_BUDGET_CTL);
+ writel(lossy_mode, MDP_PP_1_BASE +
+ MDSS_MDP_REG_PP_FBC_LOSSY_MODE);
+ }
+}
+
void mdss_qos_remapper_setup(void)
{
uint32_t mdp_hw_rev = readl(MDP_HW_REV);
@@ -698,6 +767,8 @@
/*If dst_split is enabled only intf 2 needs to be enabled.
CTL_1 path should not be set since CTL_0 itself is going
to split after DSPP block*/
+ if (pinfo->fbc.enabled)
+ mdss_fbc_cfg(pinfo);
if (pinfo->mipi.dual_dsi) {
if (!pinfo->lcdc.dst_split) {
@@ -842,6 +913,9 @@
reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 1);
writel(reg, MDP_CTL_0_BASE + CTL_TOP);
+ if (pinfo->fbc.enabled)
+ mdss_fbc_cfg(pinfo);
+
if (pinfo->mipi.dual_dsi) {
writel(0x213F, MDP_INTF_2_BASE + MDP_PANEL_FORMAT + mdss_mdp_intf_off);
reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 0);
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index 81e3f70..9d9196c 100755
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -471,7 +471,7 @@
$(LOCAL_DIR)/shutdown_detect.o \
$(LOCAL_DIR)/certificate.o \
$(LOCAL_DIR)/image_verify.o \
- $(LOCAL_DIR)/i2c_qup.o
+ $(LOCAL_DIR)/i2c_qup.o \
$(LOCAL_DIR)/mdp3.o \
$(LOCAL_DIR)/display.o \
$(LOCAL_DIR)/mipi_dsi.o \
diff --git a/platform/msm_shared/sdhci_msm.c b/platform/msm_shared/sdhci_msm.c
index 5a7795f..a54752b 100644
--- a/platform/msm_shared/sdhci_msm.c
+++ b/platform/msm_shared/sdhci_msm.c
@@ -478,8 +478,8 @@
DBG("\n CM_DLL_SDC4 Calibration Start\n");
- /*1.Write the default value to SDCC_HC_REG_DDR_CONFIG register*/
- REG_WRITE32(host, DDR_CONFIG_VAL, SDCC_HC_REG_DDR_CONFIG);
+ /*1.Write the DDR config value to SDCC_HC_REG_DDR_CONFIG register*/
+ REG_WRITE32(host, target_ddr_cfg_val(), SDCC_HC_REG_DDR_CONFIG);
/*2. Write DDR_CAL_EN to '1' */
REG_WRITE32(host, (REG_READ32(host, SDCC_HC_REG_DLL_CONFIG_2) | DDR_CAL_EN), SDCC_HC_REG_DLL_CONFIG_2);
diff --git a/platform/msm_shared/usb30_dwc.c b/platform/msm_shared/usb30_dwc.c
index ccaa3b5..d8858b9 100644
--- a/platform/msm_shared/usb30_dwc.c
+++ b/platform/msm_shared/usb30_dwc.c
@@ -456,6 +456,7 @@
for (uint8_t ep_index = 2; ep_index < DWC_MAX_NUM_OF_EP; ep_index++)
{
dwc_ep_t *ep = &dev->ep[ep_index];
+ ASSERT(ep != NULL);
DBG("\n RESET on EP = %d while state = %s", ep_index,
ep_state_lookup[ep->state]);
@@ -489,7 +490,7 @@
uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
uint16_t event_param = DWC_EVENT_EP_EVENT_PARAM(*event);
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -573,7 +574,11 @@
uint8_t status = 0;
uint8_t trb_updated = 0;
uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
+
+ ASSERT(index < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[index];
+ ASSERT(ep != NULL);
+
dwc_trb_t *trb = ep->trb;
uint32_t num_of_trb = ep->trb_queued;
uint32_t bytes_remaining = 0;
@@ -641,7 +646,7 @@
dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -756,7 +761,7 @@
uint8_t event_ctrl_stage = DWC_EVENT_EP_EVENT_CTRL_STAGE(*event);
uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -930,6 +935,8 @@
uint8_t ep_phy_num = DWC_EVENT_EP_EVENT_EP_NUM(*event);
dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
uint8_t event_ctrl_stage = DWC_EVENT_EP_EVENT_CTRL_STAGE(*event);
+
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -1011,7 +1018,7 @@
dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -1085,7 +1092,7 @@
dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -1164,7 +1171,7 @@
uint8_t ep_phy_num = DWC_EVENT_EP_EVENT_EP_NUM(*event);
dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -1239,7 +1246,7 @@
dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
uint8_t event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -1289,7 +1296,7 @@
uint8_t ep_phy_num = DWC_EVENT_EP_EVENT_EP_NUM(*event);
dwc_event_ep_event_id_t event_id = DWC_EVENT_EP_EVENT_ID(*event);
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -1373,7 +1380,7 @@
uint16_t event_param = DWC_EVENT_EP_EVENT_PARAM(*event);
#endif
- ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
ASSERT(ep != NULL);
@@ -1433,6 +1440,7 @@
*/
static void dwc_ep_config_init_enable(dwc_dev_t *dev, uint8_t index)
{
+ ASSERT(index < DWC_MAX_NUM_OF_EP);
uint8_t ep_phy_num = dev->ep[index].phy_num;
dwc_ep_cmd_set_config(dev, index, SET_CONFIG_ACTION_INIT);
@@ -1455,6 +1463,7 @@
/* Control OUT */
index = DWC_EP_INDEX(0, DWC_EP_DIRECTION_OUT);
+ ASSERT(index < DWC_MAX_NUM_OF_EP);
dev->ep[index].number = 0;
dev->ep[index].dir = DWC_EP_DIRECTION_OUT;
@@ -1525,7 +1534,9 @@
/* entry function into inactive state for data transfer fsm */
static void dwc_ep_bulk_state_inactive_enter(dwc_dev_t *dev, uint8_t ep_phy_num)
{
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
+ ASSERT(ep != NULL);
/* queue request to receive the first setup pkt from host */
ep->req.data = NULL;
@@ -1605,7 +1616,9 @@
{
uint8_t index = DWC_EP_INDEX(new_ep->number, new_ep->dir);
+ ASSERT(index < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[index];
+ ASSERT(ep != NULL);
memset(ep, 0, sizeof(ep));
@@ -1691,7 +1704,9 @@
uint8_t ep_phy_num,
dwc_request_t *req)
{
+ ASSERT(DWC_EP_PHY_TO_INDEX(ep_phy_num) < DWC_MAX_NUM_OF_EP);
dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
+ ASSERT(ep != NULL);
dwc_trb_t *trb = ep->trb;
uint8_t *data_ptr = req->data;
diff --git a/target/init.c b/target/init.c
index 78feeea..79e0466 100644
--- a/target/init.c
+++ b/target/init.c
@@ -25,6 +25,7 @@
#include <target.h>
#include <compiler.h>
#include <dload_util.h>
+#include <sdhci_msm.h>
#define EXPAND(NAME) #NAME
#define TARGET(NAME) EXPAND(NAME)
@@ -197,3 +198,9 @@
__WEAK void target_crypto_init_params()
{
}
+
+/* Default CFG delay value */
+__WEAK uint32_t target_ddr_cfg_val()
+{
+ return DDR_CONFIG_VAL;
+}
diff --git a/target/msm8916/include/target/display.h b/target/msm8916/include/target/display.h
old mode 100644
new mode 100755
index 0faf033..d904966
--- a/target/msm8916/include/target/display.h
+++ b/target/msm8916/include/target/display.h
@@ -77,6 +77,10 @@
"msmgpio", 98, 3, 1, 0, 1
};
+static struct gpio_pin enable_gpio_skut1 = {
+ "msmgpio", 8, 3, 1, 0, 1
+};
+
/*---------------------------------------------------------------------------*/
/* Target Physical configuration */
/*---------------------------------------------------------------------------*/
@@ -126,6 +130,7 @@
HW_PLATFORM_SUBTYPE_SKUH = 4,
HW_PLATFORM_SUBTYPE_SKUI = 5, /* msm8916 */
HW_PLATFORM_SUBTYPE_SKUK = 5, /* msm8939 */
+ HW_PLATFORM_SUBTYPE_SKUT1 = 0x40, /* msm8916 */
};
#endif
diff --git a/target/msm8916/oem_panel.c b/target/msm8916/oem_panel.c
old mode 100644
new mode 100755
index 33a11f2..82bcdad
--- a/target/msm8916/oem_panel.c
+++ b/target/msm8916/oem_panel.c
@@ -52,6 +52,7 @@
#include "include/panel_jdi_fhd_video.h"
#include "include/panel_hx8379a_fwvga_video.h"
#include "include/panel_hx8394d_720p_video.h"
+#include "include/panel_nt35521_wxga_video.h"
#define DISPLAY_MAX_PANEL_DETECTION 2
#define OTM8019A_FWVGA_VIDEO_PANEL_ON_DELAY 50
@@ -74,6 +75,7 @@
JDI_FHD_VIDEO_PANEL,
HX8379A_FWVGA_VIDEO_PANEL,
HX8394D_720P_VIDEO_PANEL,
+NT35521_WXGA_VIDEO_PANEL,
UNKNOWN_PANEL
};
@@ -92,7 +94,8 @@
{"sharp_wqxga_dualdsi_video",SHARP_WQXGA_DUALDSI_VIDEO_PANEL},
{"jdi_fhd_video", JDI_FHD_VIDEO_PANEL},
{"hx8379a_wvga_video", HX8379A_FWVGA_VIDEO_PANEL},
- {"hx8394d_720p_video", HX8394D_720P_VIDEO_PANEL}
+ {"hx8394d_720p_video", HX8394D_720P_VIDEO_PANEL},
+ {"nt35521_wxga_video", NT35521_WXGA_VIDEO_PANEL}
};
static uint32_t panel_id;
@@ -359,6 +362,26 @@
hx8394d_720p_video_timings, TIMING_SIZE);
pinfo->mipi.signature = HX8394D_720P_VIDEO_SIGNATURE;
break;
+ case NT35521_WXGA_VIDEO_PANEL:
+ panelstruct->paneldata = &nt35521_wxga_video_panel_data;
+ panelstruct->panelres = &nt35521_wxga_video_panel_res;
+ panelstruct->color = &nt35521_wxga_video_color;
+ panelstruct->videopanel = &nt35521_wxga_video_video_panel;
+ panelstruct->commandpanel = &nt35521_wxga_video_command_panel;
+ panelstruct->state = &nt35521_wxga_video_state;
+ panelstruct->laneconfig = &nt35521_wxga_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &nt35521_wxga_video_timing_info;
+ panelstruct->panelresetseq
+ = &nt35521_wxga_video_reset_seq;
+ panelstruct->backlightinfo = &nt35521_wxga_video_backlight;
+ pinfo->mipi.panel_cmds
+ = nt35521_wxga_video_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = NT35521_WXGA_VIDEO_ON_COMMAND;
+ memcpy(phy_db->timing,
+ nt35521_wxga_video_timings, TIMING_SIZE);
+ break;
case UNKNOWN_PANEL:
default:
memset(panelstruct, 0, sizeof(struct panel_struct));
@@ -453,6 +476,10 @@
else
panel_id = HX8379A_FWVGA_VIDEO_PANEL;
break;
+ case HW_PLATFORM_SUBTYPE_SKUT1:
+ /* qrd SKUT1 */
+ panel_id = NT35521_WXGA_VIDEO_PANEL;
+ break;
default:
dprintf(CRITICAL, "Invalid subtype id %d for QRD HW\n",
hw_subtype);
diff --git a/target/msm8916/target_display.c b/target/msm8916/target_display.c
old mode 100644
new mode 100755
index 0cd12df..b47f1e0
--- a/target/msm8916/target_display.c
+++ b/target/msm8916/target_display.c
@@ -293,6 +293,10 @@
if (enable) {
if (pinfo->mipi.use_enable_gpio) {
+ /* set enable gpio pin for SKUT1 */
+ if ((hw_id == HW_PLATFORM_QRD) &&
+ (hw_subtype == HW_PLATFORM_SUBTYPE_SKUT1))
+ enable_gpio = enable_gpio_skut1;
gpio_tlmm_config(enable_gpio.pin_id, 0,
enable_gpio.pin_direction, enable_gpio.pin_pull,
enable_gpio.pin_strength,
diff --git a/target/msm8994/init.c b/target/msm8994/init.c
index 0780268..18c6ab9 100644
--- a/target/msm8994/init.c
+++ b/target/msm8994/init.c
@@ -76,6 +76,7 @@
#define FASTBOOT_MODE 0x77665500
#define PMIC_WLED_SLAVE_ID 3
+#define DDR_CFG_DLY_VAL 0x80040870
static void set_sdc_power_ctrl(uint8_t slot);
static uint32_t mmc_pwrctl_base[] =
@@ -182,6 +183,26 @@
{
}
+unsigned target_pause_for_battery_charge(void)
+{
+ uint8_t pon_reason = pm8x41_get_pon_reason();
+ uint8_t is_cold_boot = pm8x41_get_is_cold_boot();
+ dprintf(INFO, "%s : pon_reason is %d cold_boot:%d\n", __func__,
+ pon_reason, is_cold_boot);
+ /* In case of fastboot reboot,adb reboot or if we see the power key
+ * pressed we do not want go into charger mode.
+ * fastboot reboot is warm boot with PON hard reset bit not set
+ * adb reboot is a cold boot with PON hard reset bit set
+ */
+ if (is_cold_boot &&
+ (!(pon_reason & HARD_RST)) &&
+ (!(pon_reason & KPDPWR_N)) &&
+ ((pon_reason & USB_CHG) || (pon_reason & DC_CHG)))
+ return 1;
+ else
+ return 0;
+}
+
static void set_sdc_power_ctrl(uint8_t slot)
{
uint32_t reg = 0;
@@ -539,3 +560,8 @@
/* We are entering fastboot mode, so read partition table */
mmc_read_partition_table(1);
}
+
+uint32_t target_ddr_cfg_val()
+{
+ return DDR_CFG_DLY_VAL;
+}
diff --git a/target/msmzirc/keypad.c b/target/msmzirc/keypad.c
index 569ea66..11ba6e8 100644
--- a/target/msmzirc/keypad.c
+++ b/target/msmzirc/keypad.c
@@ -33,7 +33,7 @@
/* GPIO that controls the button
* for FASTBOOT.
*/
-#define FASTBOOT_KEY_GPIO_ID 17
+#define FASTBOOT_KEY_GPIO_ID 92
/*
* Returns fastboot button state.
diff --git a/target/msmzirc/rules.mk b/target/msmzirc/rules.mk
index 7acd1db..7a19970 100644
--- a/target/msmzirc/rules.mk
+++ b/target/msmzirc/rules.mk
@@ -4,16 +4,16 @@
PLATFORM := msmzirc
-MEMBASE := 0x87C00000
+MEMBASE := 0x81200000
MEMSIZE := 0x00100000 # 1MB
BASE_ADDR := 0x80000000
SCRATCH_ADDR := 0x80000000
-SCRATCH_REGION1 := 0x81C00000
-SCRATCH_REGION1_SIZE := 0x06000000 # 97MB
+SCRATCH_REGION1 := 0x81300000
+SCRATCH_REGION1_SIZE := 0x06900000 # 105MB
SCRATCH_REGION2 := 0x88000000
SCRATCH_REGION2_SIZE := 0x08000000 # 128MB
KERNEL_REGION := 0x80000000
-KERNEL_REGION_SIZE := 0x01C00000 # 28MB
+KERNEL_REGION_SIZE := 0x01200000 # 18MB
DEFINES += NO_KEYPAD_DRIVER=1