platform: dsi: Remove dead DSI code
There is no longer the need to manually setup the dsi pll clocks
since the auto pll feature is now enabled. Removing unused code.
Change-Id: Ia482c9a26d40b6caf19649b996d1c5060ae14359
diff --git a/platform/msm_shared/mipi_dsi_phy.c b/platform/msm_shared/mipi_dsi_phy.c
index e3a4527..90e541a 100644
--- a/platform/msm_shared/mipi_dsi_phy.c
+++ b/platform/msm_shared/mipi_dsi_phy.c
@@ -213,154 +213,6 @@
udelay(1);
}
-int mdss_dsi_uniphy_pll_config(uint32_t ctl_base)
-{
- mdss_dsi_phy_sw_reset(ctl_base);
-
- /* Configuring the Pll Vco clk to 424 Mhz */
-
- /* Loop filter resistance value */
- writel(0x08, ctl_base + 0x022c);
- /* Loop filter capacitance values : c1 and c2 */
- writel(0x70, ctl_base + 0x0230);
- writel(0x15, ctl_base + 0x0234);
-
- writel(0x02, ctl_base + 0x0208); /* ChgPump */
- writel(0x00, ctl_base + 0x0204); /* postDiv1 */
- writel(0x03, ctl_base + 0x0224); /* postDiv2 */
- writel(0x05, ctl_base + 0x0228); /* postDiv3 */
-
- writel(0x2b, ctl_base + 0x0278); /* Cal CFG3 */
- writel(0x66, ctl_base + 0x027c); /* Cal CFG4 */
- writel(0x05, ctl_base + 0x0264); /* LKDetect CFG2 */
-
- writel(0x0a, ctl_base + 0x023c); /* SDM CFG1 */
- writel(0xab, ctl_base + 0x0240); /* SDM CFG2 */
- writel(0x0a, ctl_base + 0x0244); /* SDM CFG3 */
- writel(0x00, ctl_base + 0x0248); /* SDM CFG4 */
-
- udelay(10);
-
- writel(0x01, ctl_base + 0x0200); /* REFCLK CFG */
- writel(0x00, ctl_base + 0x0214); /* PWRGEN CFG */
- writel(0x71, ctl_base + 0x020c); /* VCOLPF CFG */
- writel(0x02, ctl_base + 0x0210); /* VREG CFG */
- writel(0x00, ctl_base + 0x0238); /* SDM CFG0 */
-
- writel(0x5f, ctl_base + 0x028c); /* CAL CFG8 */
- writel(0xa8, ctl_base + 0x0294); /* CAL CFG10 */
- writel(0x01, ctl_base + 0x0298); /* CAL CFG11 */
- writel(0x0a, ctl_base + 0x026c); /* CAL CFG0 */
- writel(0x30, ctl_base + 0x0284); /* CAL CFG6 */
- writel(0x00, ctl_base + 0x0288); /* CAL CFG7 */
- writel(0x00, ctl_base + 0x0290); /* CAL CFG9 */
- writel(0x20, ctl_base + 0x029c); /* EFUSE CFG */
-
- mdss_dsi_uniphy_pll_sw_reset(ctl_base);
- writel(0x01, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
-
- mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
-
- while (!(readl(ctl_base + 0x02c0) & 0x01)) {
- mdss_dsi_uniphy_pll_sw_reset(ctl_base);
- writel(0x01, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
- mdelay(2);
- mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
- }
-
-}
-
-int mdss_sharp_dsi_uniphy_pll_config(uint32_t ctl_base)
-{
- mdss_dsi_phy_sw_reset(ctl_base);
-
- /* Configuring the Pll Vco clk to 500 Mhz */
-
- /* Loop filter resistance value */
- writel(0x08, ctl_base + 0x022c);
- /* Loop filter capacitance values : c1 and c2 */
- writel(0x70, ctl_base + 0x0230);
- writel(0x15, ctl_base + 0x0234);
-
- writel(0x02, ctl_base + 0x0208); /* ChgPump */
- writel(0x00, ctl_base + 0x0204); /* postDiv1 */
- writel(0x03, ctl_base + 0x0224); /* postDiv2 */
- writel(0x0b, ctl_base + 0x0228); /* postDiv3 */
-
- writel(0x2b, ctl_base + 0x0278); /* Cal CFG3 */
- writel(0x66, ctl_base + 0x027c); /* Cal CFG4 */
- writel(0x05, ctl_base + 0x0264); /* LKDetect CFG2 */
-
- writel(0x0c, ctl_base + 0x023c); /* SDM CFG1 */
- writel(0x55, ctl_base + 0x0240); /* SDM CFG2 */
- writel(0x05, ctl_base + 0x0244); /* SDM CFG3 */
- writel(0x00, ctl_base + 0x0248); /* SDM CFG4 */
-
- udelay(10);
-
- writel(0x01, ctl_base + 0x0200); /* REFCLK CFG */
- writel(0x00, ctl_base + 0x0214); /* PWRGEN CFG */
- writel(0x01, ctl_base + 0x020c); /* VCOLPF CFG */
- writel(0x02, ctl_base + 0x0210); /* VREG CFG */
- writel(0x00, ctl_base + 0x0238); /* SDM CFG0 */
-
- writel(0x60, ctl_base + 0x028c); /* CAL CFG8 */
- writel(0xf4, ctl_base + 0x0294); /* CAL CFG10 */
- writel(0x01, ctl_base + 0x0298); /* CAL CFG11 */
- writel(0x0a, ctl_base + 0x026c); /* CAL CFG0 */
- writel(0x30, ctl_base + 0x0284); /* CAL CFG6 */
- writel(0x00, ctl_base + 0x0288); /* CAL CFG7 */
- writel(0x00, ctl_base + 0x0290); /* CAL CFG9 */
- writel(0x20, ctl_base + 0x029c); /* EFUSE CFG */
-
- mdss_dsi_uniphy_pll_sw_reset(ctl_base);
- writel(0x01, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
-
- mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
-
- while (!(readl(ctl_base + 0x02c0) & 0x01)) {
- mdss_dsi_uniphy_pll_sw_reset(ctl_base);
- writel(0x01, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
- mdelay(2);
- mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
- }
-
-}
-
int mdss_dsi_phy_regulator_init(struct mdss_dsi_phy_ctrl *pd)
{
/* DSI0 and DSI1 have a common regulator */
diff --git a/target/msm8226/include/target/display.h b/target/msm8226/include/target/display.h
index 49aa5f7..62f0eac 100755
--- a/target/msm8226/include/target/display.h
+++ b/target/msm8226/include/target/display.h
@@ -109,5 +109,4 @@
#define MIPI_VSYNC_FRONT_PORCH_LINES 9
extern int mdss_dsi_phy_init(struct mipi_dsi_panel_config *, uint32_t ctl_base);
-extern int mdss_dsi_uniphy_pll_config(uint32_t ctl_base);
#endif
diff --git a/target/msm8974/include/target/display.h b/target/msm8974/include/target/display.h
index 237bfdd..8897239 100644
--- a/target/msm8974/include/target/display.h
+++ b/target/msm8974/include/target/display.h
@@ -101,6 +101,5 @@
#define MIPI_VSYNC_FRONT_PORCH_LINES 9
extern int mdss_dsi_phy_init(struct mipi_dsi_panel_config *, uint32_t ctl_base);
-extern int mdss_dsi_uniphy_pll_config(uint32_t ctl_base);
#endif