msm8994: Add support for QUSB2PHY for dragonboard
In dragonboard, Port 1 will be used for fastboot use cases and
Port 1 uses QUSB2 PHY. We need to configure the PHY for
successful USB enumeration on Port 1.
CRs-Fixed: 665264
Change-Id: Ie2dc5470dd27436b1a9293635b8d0def8f0bb94a
diff --git a/platform/msm8994/include/platform/iomap.h b/platform/msm8994/include/platform/iomap.h
index 592a369..2472fce 100644
--- a/platform/msm8994/include/platform/iomap.h
+++ b/platform/msm8994/include/platform/iomap.h
@@ -75,6 +75,12 @@
#define BLSP2_UART1_BASE (PERIPH_SS_BASE + 0x0015E000)
#define MSM_USB_BASE (PERIPH_SS_BASE + 0x00255000)
+#define USB2_PHY_SEL 0xFD4AB000
+
+/* QUSB2 PHY */
+#define QUSB2_PHY_BASE (PERIPH_SS_BASE + 0x00339000)
+
+#define QUSB2PHY_PORT_POWERDOWN (QUSB2_PHY_BASE + 0x000000B4)
#define MSM_USB30_BASE 0xF9200000
#define MSM_USB30_QSCRATCH_BASE 0xF92F8800
@@ -137,6 +143,7 @@
#define USB30_PHY_BCR (CLK_CTL_BASE + 0x1400)
#define USB30PHY_PHY_BCR (CLK_CTL_BASE + 0x1404)
#define GCC_USB30_GDSCR (CLK_CTL_BASE + 0x03C4)
+#define GCC_QUSB2_PHY_BCR (CLK_CTL_BASE + 0x04B8)
/* SDCC */
#define SDCC1_BCR (CLK_CTL_BASE + 0x4C0) /* block reset */
diff --git a/target/msm8994/init.c b/target/msm8994/init.c
index 71ee5d2..3ca3549 100644
--- a/target/msm8994/init.c
+++ b/target/msm8994/init.c
@@ -135,6 +135,26 @@
{
uint32_t val;
+ if(board_hardware_id() == HW_PLATFORM_DRAGON)
+ {
+ /* Select the QUSB2 PHY */
+ writel(0x1, USB2_PHY_SEL);
+
+ /* Block Reset */
+ val = readl(GCC_QUSB2_PHY_BCR) | BIT(0);
+ writel(val, GCC_QUSB2_PHY_BCR);
+ udelay(10);
+ writel(val & ~BIT(0), GCC_QUSB2_PHY_BCR);
+
+ /* Deassert POWERDOWN by clearing bit 0 to enable the PHY */
+ val = readl(QUSB2PHY_PORT_POWERDOWN);
+ writel(val & ~BIT(0), QUSB2PHY_PORT_POWERDOWN);
+ udelay(10);
+
+ /* set CLAMP_N_EN and FREEZIO_N */
+ writel(0x22, QUSB2PHY_PORT_POWERDOWN);
+ }
+
/* Select and enable external configuration with USB PHY */
ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_SET);