commit 0ebf2fc460c014d51913dfbae80c76dac7a40af4
author Sundarajan Srinivasan <sundaraj@codeaurora.org> Wed Apr 23 16:45:18 2014 -0700
committer Sundarajan Srinivasan <sundaraj@codeaurora.org> Thu May 15 16:47:48 2014 -0700
tree 18f24463980cfbb996c8022118711bf4198ccb2a
parent 4c4a3bf940879f21cf9cc0b4881c610f60a3fd81

msm8994: Add support for QUSB2PHY for dragonboard

In dragonboard, Port 1 will be used for fastboot use cases and
Port 1 uses QUSB2 PHY. We need to configure the PHY for
successful USB enumeration on Port 1.

CRs-Fixed: 665264
Change-Id: Ie2dc5470dd27436b1a9293635b8d0def8f0bb94a

platform/msm8994/include/platform/iomap.h

diff --git a/platform/msm8994/include/platform/iomap.h b/platform/msm8994/include/platform/iomap.h
index 592a369..2472fce 100644
--- a/platform/msm8994/include/platform/iomap.h
+++ b/platform/msm8994/include/platform/iomap.h
@@ -75,6 +75,12 @@
 #define BLSP2_UART1_BASE            (PERIPH_SS_BASE + 0x0015E000)
 
 #define MSM_USB_BASE                (PERIPH_SS_BASE + 0x00255000)
+#define USB2_PHY_SEL                0xFD4AB000
+
+/* QUSB2 PHY */
+#define QUSB2_PHY_BASE              (PERIPH_SS_BASE + 0x00339000)
+
+#define QUSB2PHY_PORT_POWERDOWN     (QUSB2_PHY_BASE + 0x000000B4)
 
 #define MSM_USB30_BASE              0xF9200000
 #define MSM_USB30_QSCRATCH_BASE     0xF92F8800
@@ -137,6 +143,7 @@
 #define USB30_PHY_BCR               (CLK_CTL_BASE + 0x1400)
 #define USB30PHY_PHY_BCR            (CLK_CTL_BASE + 0x1404)
 #define GCC_USB30_GDSCR             (CLK_CTL_BASE + 0x03C4)
+#define GCC_QUSB2_PHY_BCR           (CLK_CTL_BASE + 0x04B8)
 
 /* SDCC */
 #define SDCC1_BCR                   (CLK_CTL_BASE + 0x4C0) /* block reset */