Merge "platform: msm_shared: Add support for mdm boot config"
diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
index c7522d6..b9d89f4 100644
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -98,6 +98,7 @@
#define RECOVERY_MODE 0x77665502
#define FASTBOOT_MODE 0x77665500
+#define ALARM_BOOT 0x77665503
/* make 4096 as default size to ensure EFS,EXT4's erasing */
#define DEFAULT_ERASE_SIZE 4096
@@ -119,6 +120,7 @@
#endif
static const char *usb_sn_cmdline = " androidboot.serialno=";
static const char *androidboot_mode = " androidboot.mode=";
+static const char *alarmboot_cmdline = " androidboot.alarmboot=true";
static const char *loglevel = " quiet";
static const char *battchg_pause = " androidboot.mode=charger";
static const char *auth_kernel = " androidboot.authorized_kernel=true";
@@ -141,6 +143,7 @@
static char ffbm_mode_string[FFBM_MODE_BUF_SIZE];
static bool boot_into_ffbm;
static char target_boot_params[64];
+static bool boot_reason_alarm;
/* Assuming unauthorized kernel image by default */
static int auth_kernel_img = 0;
@@ -252,6 +255,8 @@
cmdline_len += strlen(ffbm_mode_string);
/* reduce kernel console messages to speed-up boot */
cmdline_len += strlen(loglevel);
+ } else if (boot_reason_alarm) {
+ cmdline_len += strlen(alarmboot_cmdline);
} else if (device.charger_screen_enabled &&
target_pause_for_battery_charge()) {
pause_at_bootup = 1;
@@ -383,6 +388,10 @@
src = loglevel;
if (have_cmdline) --dst;
while ((*dst++ = *src++));
+ } else if (boot_reason_alarm) {
+ src = alarmboot_cmdline;
+ if (have_cmdline) --dst;
+ while ((*dst++ = *src++));
} else if (pause_at_bootup) {
src = battchg_pause;
if (have_cmdline) --dst;
@@ -2669,6 +2678,8 @@
boot_into_recovery = 1;
} else if(reboot_mode == FASTBOOT_MODE) {
boot_into_fastboot = true;
+ } else if(reboot_mode == ALARM_BOOT) {
+ boot_reason_alarm = true;
}
normal_boot:
diff --git a/platform/msm8916/rules.mk b/platform/msm8916/rules.mk
index 1b737e7..b0a2070 100644
--- a/platform/msm8916/rules.mk
+++ b/platform/msm8916/rules.mk
@@ -13,8 +13,6 @@
DEFINES += WITH_CPU_EARLY_INIT=0 WITH_CPU_WARM_BOOT=0 \
MMC_SLOT=$(MMC_SLOT) SSD_ENABLE
-DEFINES += TZ_SAVE_KERNEL_HASH
-
INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared/include
DEVS += fbcon
diff --git a/platform/msm8994/acpuclock.c b/platform/msm8994/acpuclock.c
index ba316fa..46129d8 100644
--- a/platform/msm8994/acpuclock.c
+++ b/platform/msm8994/acpuclock.c
@@ -328,7 +328,7 @@
ASSERT(0);
}
- ret = clk_get_set_enable("mdss_mdp_clk_src", 240000000, 1);
+ ret = clk_get_set_enable("mdss_mdp_clk_src", 300000000, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set mdp_clk_src ret = %d\n", ret);
@@ -371,7 +371,7 @@
{
int ret;
/* Configure MMSSNOC AXI clock */
- ret = clk_get_set_enable("mmss_mmssnoc_axi_clk", 100000000, 1);
+ ret = clk_get_set_enable("mmss_mmssnoc_axi_clk", 300000000, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set mmssnoc_axi_clk ret = %d\n", ret);
@@ -379,7 +379,7 @@
}
/* Configure S0 AXI clock */
- ret = clk_get_set_enable("mmss_s0_axi_clk", 100000000, 1);
+ ret = clk_get_set_enable("mmss_s0_axi_clk", 300000000, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set mmss_s0_axi_clk ret = %d\n", ret);
@@ -387,7 +387,7 @@
}
/* Configure AXI clock */
- ret = clk_get_set_enable("mdss_axi_clk", 100000000, 1);
+ ret = clk_get_set_enable("mdss_axi_clk", 300000000, 1);
if(ret)
{
dprintf(CRITICAL, "failed to set mdss_axi_clk ret = %d\n", ret);
diff --git a/platform/msm8994/msm8994-clock.c b/platform/msm8994/msm8994-clock.c
index a28291a..5ee2d5c 100644
--- a/platform/msm8994/msm8994-clock.c
+++ b/platform/msm8994/msm8994-clock.c
@@ -554,12 +554,14 @@
static struct clk_freq_tbl ftbl_mmss_axi_clk[] = {
F_MM(19200000, cxo, 1, 0, 0),
F_MM(100000000, gpll0, 6, 0, 0),
+ F_MM(300000000, gpll0, 2, 0, 0),
F_END
};
static struct clk_freq_tbl ftbl_mdp_clk[] = {
F_MM( 75000000, gpll0, 8, 0, 0),
F_MM( 240000000, gpll0, 2.5, 0, 0),
+ F_MM(300000000, gpll0, 2, 0, 0),
F_END
};
diff --git a/platform/msm_shared/include/qgic.h b/platform/msm_shared/include/qgic.h
index 45607ff..30abec5 100644
--- a/platform/msm_shared/include/qgic.h
+++ b/platform/msm_shared/include/qgic.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2011, 2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -56,11 +56,17 @@
#define GIC_DIST_CONFIG GIC_DIST_REG(0xc00)
#define GIC_DIST_SOFTINT GIC_DIST_REG(0xf00)
+#define INTERRUPT_LVL_N_TO_N 0x0
+#define INTERRUPT_LVL_1_TO_N 0x1
+#define INTERRUPT_EDGE_N_TO_N 0x2
+#define INTERRUPT_EDGE_1_TO_N 0x3
+
struct ihandler {
int_handler func;
void *arg;
};
void qgic_init(void);
+void qgic_change_interrupt_cfg(uint32_t spi_number, uint8_t type);
#endif
diff --git a/platform/msm_shared/mdp5.c b/platform/msm_shared/mdp5.c
index 08ebafb..ff0709e 100755
--- a/platform/msm_shared/mdp5.c
+++ b/platform/msm_shared/mdp5.c
@@ -887,6 +887,11 @@
writel(0x1, MDP_REG_SPLIT_DISPLAY_EN);
}
+ if (pinfo->lcdc.dst_split) {
+ writel(BIT(16), MDP_REG_PPB0_CONFIG);
+ writel(BIT(5), MDP_REG_PPB0_CNTL);
+ }
+
mdss_mdp_intf_off = mdss_mdp_intf_offset();
mdp_clk_gating_ctrl();
@@ -918,8 +923,10 @@
if (pinfo->mipi.dual_dsi) {
writel(0x213F, MDP_INTF_2_BASE + MDP_PANEL_FORMAT + mdss_mdp_intf_off);
- reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 0);
- writel(reg, MDP_CTL_1_BASE + CTL_TOP);
+ if (!pinfo->lcdc.dst_split) {
+ reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 0);
+ writel(reg, MDP_CTL_1_BASE + CTL_TOP);
+ }
}
return ret;
diff --git a/platform/msm_shared/qgic.c b/platform/msm_shared/qgic.c
index 48e846d..49299e7 100644
--- a/platform/msm_shared/qgic.c
+++ b/platform/msm_shared/qgic.c
@@ -32,6 +32,7 @@
*/
#include <reg.h>
+#include <bits.h>
#include <debug.h>
#include <arch/arm.h>
#include <kernel/thread.h>
@@ -179,3 +180,24 @@
handler[vector].arg = arg;
exit_critical_section();
}
+
+void qgic_change_interrupt_cfg(uint32_t spi_number, uint8_t type)
+{
+ uint32_t register_number, register_address, bit_number, value;
+ register_number = spi_number >> 4; // r = n DIV 16
+ bit_number = (spi_number % 16) << 1; // b = (n MOD 16) * 2
+ value = readl(GIC_DIST_CONFIG + (register_number << 2));
+ // there are two bits per register to indicate the level
+ if (type == INTERRUPT_LVL_N_TO_N)
+ value &= ~(BIT(bit_number)|BIT(bit_number+1)); // 0x0 0x0
+ else if (type == INTERRUPT_LVL_1_TO_N)
+ value = (value & ~BIT(bit_number+1)) | BIT(bit_number); // 0x0 0x1
+ else if (type == INTERRUPT_EDGE_N_TO_N)
+ value = BIT(bit_number+1) | (value & ~BIT(bit_number));// 0x1 0x0
+ else if (type == INTERRUPT_EDGE_1_TO_N)
+ value |= (BIT(bit_number)|BIT(bit_number+1)); // 0x1 0x1
+ else
+ dprintf(CRITICAL, "Invalid interrupt type change requested\n");
+ register_address = GIC_DIST_CONFIG + (register_number << 2);
+ writel(value, register_address);
+}
diff --git a/platform/msm_shared/ufs.c b/platform/msm_shared/ufs.c
index 1897735..1fd26b4 100644
--- a/platform/msm_shared/ufs.c
+++ b/platform/msm_shared/ufs.c
@@ -34,8 +34,10 @@
#include <uic.h>
#include <ucs.h>
#include <dme.h>
+#include <qgic.h>
#include <string.h>
#include <platform/iomap.h>
+#include <platform/irqs.h>
#include <kernel/mutex.h>
static int ufs_dev_init(struct ufs_dev *dev)
@@ -83,6 +85,8 @@
/* Enable the required irqs. */
val = UFS_IE_UEE | UFS_IE_UCCE ;
ufs_irq_enable(dev, val);
+ // Change UFS_IRQ to level based
+ qgic_change_interrupt_cfg(UFS_IRQ, INTERRUPT_LVL_N_TO_N);
}
int ufs_read(struct ufs_dev* dev, uint64_t start_lba, addr_t buffer, uint32_t num_blocks)