| /* |
| * Copyright (c) 2011, 2014, The Linux Foundation. All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions are |
| * met: |
| * * Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * * Redistributions in binary form must reproduce the above |
| * copyright notice, this list of conditions and the following |
| * disclaimer in the documentation and/or other materials provided |
| * with the distribution. |
| * * Neither the name of The Linux Foundation nor the names of its |
| * contributors may be used to endorse or promote products derived |
| * from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| |
| #ifndef __PLATFORM_MSM_SHARED_QGIC_H |
| #define __PLATFORM_MSM_SHARED_QGIC_H |
| |
| #include "qgic_common.h" |
| #include <platform/iomap.h> |
| #include <platform/interrupts.h> |
| #include <arch/arm.h> |
| |
| #define GIC_CPU_REG(off) (MSM_GIC_CPU_BASE + (off)) |
| |
| #define GIC_CPU_CTRL GIC_CPU_REG(0x00) |
| #define GIC_CPU_PRIMASK GIC_CPU_REG(0x04) |
| #define GIC_CPU_BINPOINT GIC_CPU_REG(0x08) |
| #define GIC_CPU_INTACK GIC_CPU_REG(0x0c) |
| #define GIC_CPU_EOI GIC_CPU_REG(0x10) |
| #define GIC_CPU_RUNNINGPRI GIC_CPU_REG(0x14) |
| #define GIC_CPU_HIGHPRI GIC_CPU_REG(0x18) |
| |
| #define INTERRUPT_LVL_N_TO_N 0x0 |
| #define INTERRUPT_LVL_1_TO_N 0x1 |
| #define INTERRUPT_EDGE_N_TO_N 0x2 |
| #define INTERRUPT_EDGE_1_TO_N 0x3 |
| |
| uint32_t qgic_read_iar(void); |
| void qgic_write_eoi(uint32_t); |
| |
| enum handler_return gic_platform_irq(struct arm_iframe *frame); |
| void gic_platform_fiq(struct arm_iframe *frame); |
| status_t gic_mask_interrupt(unsigned int vector); |
| status_t gic_unmask_interrupt(unsigned int vector); |
| void gic_register_int_handler(unsigned int vector, int_handler func, void *arg); |
| #endif |