msm8974: Configure the MMU for msm8974
Change-Id: Ife6a4e08113afaa316e9b8357a8e7062f234a047
diff --git a/arch/arm/arch.c b/arch/arm/arch.c
index f17fa09..dc171b4 100644
--- a/arch/arm/arch.c
+++ b/arch/arm/arch.c
@@ -47,7 +47,6 @@
#if ARM_WITH_MMU
arm_mmu_init();
- platform_init_mmu_mappings();
#endif
/* turn the cache back on */
diff --git a/arch/arm/mmu.c b/arch/arm/mmu.c
index 4b51d50..cc74534 100644
--- a/arch/arm/mmu.c
+++ b/arch/arm/mmu.c
@@ -78,6 +78,8 @@
MMU_MEMORY_AP_READ_WRITE);
}
+ platform_init_mmu_mappings();
+
/* set up the translation table base */
arm_write_ttbr((uint32_t)tt);
diff --git a/platform/copper/include/platform/iomap.h b/platform/copper/include/platform/iomap.h
index c498bdc..d48c7c9 100644
--- a/platform/copper/include/platform/iomap.h
+++ b/platform/copper/include/platform/iomap.h
@@ -29,6 +29,9 @@
#ifndef _PLATFORM_MSMCOPPER_IOMAP_H_
#define _PLATFORM_MSMCOPPER_IOMAP_H_
+#define MSM_IOMAP_BASE 0xF9000000
+#define MSM_IOMAP_END 0xFEFFFFFF
+
#define SDRAM_START_ADDR 0x00000000
#define SDRAM_SEC_BANK_START_ADDR 0x10000000
diff --git a/platform/copper/platform.c b/platform/copper/platform.c
index 397bb84..6ccfe2d 100644
--- a/platform/copper/platform.c
+++ b/platform/copper/platform.c
@@ -34,7 +34,27 @@
#include <qgic.h>
#include <qtimer.h>
#include <platform/clock.h>
+#include <mmu.h>
+#include <arch/arm/mmu.h>
+#include <smem.h>
+#define MB (1024*1024)
+
+#define MSM_IOMAP_SIZE ((MSM_IOMAP_END - MSM_IOMAP_BASE)/MB)
+
+/* LK memory - cacheable, write through */
+#define LK_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_WRITE)
+
+/* Peripherals - non-shared device */
+#define IOMAP_MEMORY (MMU_MEMORY_TYPE_DEVICE_SHARED | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
+mmu_section_t mmu_section_table[] = {
+/* Physical addr, Virtual addr, Size (in MB), Flags */
+ {MEMBASE, MEMBASE, (MEMSIZE / MB), LK_MEMORY},
+ {MSM_IOMAP_BASE, MSM_IOMAP_BASE, MSM_IOMAP_SIZE, IOMAP_MEMORY},
+};
void platform_early_init(void)
{
@@ -53,3 +73,48 @@
{
qtimer_uninit();
}
+
+/* Setup memory for this platform */
+void platform_init_mmu_mappings(void)
+{
+ struct smem_ram_ptable ram_ptable;
+ uint32_t i;
+ uint32_t sections;
+ uint32_t table_size = ARRAY_SIZE(mmu_section_table);
+
+ ASSERT(smem_ram_ptable_init(&ram_ptable));
+
+ /* Configure the MMU page entries for SDRAM and IMEM memory read
+ from the smem ram table*/
+ for(i = 0; i < ram_ptable.len; i++)
+ { if((ram_ptable.parts[i].category == SDRAM) ||
+ (ram_ptable.parts[i].category == IMEM))
+ {
+ /* Check to ensure that start address is 1MB aligned */
+ ASSERT((ram_ptable.parts[i].start & 0xFFFFF) == 0);
+
+ sections = (ram_ptable.parts[i].size) / MB;
+ while(sections--) {
+ arm_mmu_map_section(ram_ptable.parts[i].start +
+ sections * MB,
+ ram_ptable.parts[i].start +
+ sections * MB,
+ (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN));
+ }
+ }
+ }
+ /* Configure the MMU page entries for memory read from the
+ mmu_section_table */
+ for (i = 0; i < table_size; i++) {
+ sections = mmu_section_table[i].num_of_sections;
+
+ while (sections--) {
+ arm_mmu_map_section(mmu_section_table[i].paddress +
+ sections * MB,
+ mmu_section_table[i].vaddress +
+ sections * MB,
+ mmu_section_table[i].flags);
+ }
+ }
+}