Merge "platform: msm_shared: Fix MMC tuning in LK for re-tuning."
diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
index 504cb82..55b1181 100755
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -1032,6 +1032,7 @@
return ret;
}
buf = (char *) memalign(CACHE_LINE, ROUNDUP(page_size, CACHE_LINE));
+ mmc_set_lun(partition_get_lun(index));
ASSERT(buf);
if (mmc_read(offset, (uint32_t *)buf, page_size))
{
@@ -1968,6 +1969,9 @@
ptn_size = partition_get_size(index);
offset = ptn_size - blocksize;
+ /* Set Lun for partition */
+ mmc_set_lun(partition_get_lun(index));
+
if (mmc_read(ptn + offset, (void *)buf, blocksize))
{
dprintf(CRITICAL, "Reading MMC failed\n");
@@ -2002,6 +2006,7 @@
ptn = partition_get_offset(index);
ptn_size = partition_get_size(index);
offset = ptn_size - blocksize;
+ mmc_set_lun(partition_get_lun(index));
if (mmc_read(ptn + offset, (void *)buf, blocksize))
{
diff --git a/app/tests/kauth_test.c b/app/tests/kauth_test.c
index e92922e..a4c8d01 100644
--- a/app/tests/kauth_test.c
+++ b/app/tests/kauth_test.c
@@ -73,6 +73,7 @@
#if !VERIFIED_BOOT
index = partition_get_index("system");
ptn = partition_get_offset(index);
+ mmc_set_lun(partition_get_lun(index));
if(!ptn)
{
diff --git a/include/target.h b/include/target.h
index d0d830d..62369ed 100644
--- a/include/target.h
+++ b/include/target.h
@@ -93,6 +93,7 @@
struct qmp_reg *target_get_qmp_settings();
int target_get_qmp_regsize();
+uint32_t target_ddr_cfg_reg();
#if PON_VIB_SUPPORT
void get_vibration_type();
diff --git a/platform/msm_shared/mmc_sdhci.c b/platform/msm_shared/mmc_sdhci.c
index f73d10c..68ce54b 100644
--- a/platform/msm_shared/mmc_sdhci.c
+++ b/platform/msm_shared/mmc_sdhci.c
@@ -686,6 +686,9 @@
memset(card->ext_csd, 0, sizeof(card->ext_csd));
+ /* invalidate any cached buf data (controller updates main memory) */
+ arch_invalidate_cache_range((addr_t) card->ext_csd, 512);
+
memset((struct mmc_command *)&cmd, 0, sizeof(struct mmc_command));
/* CMD8 */
diff --git a/platform/msm_shared/scm.c b/platform/msm_shared/scm.c
index 403441c..b544201 100644
--- a/platform/msm_shared/scm.c
+++ b/platform/msm_shared/scm.c
@@ -55,6 +55,15 @@
SCM_MASK_IRQS | \
((n) & 0xf))
+#define SECBOOT_FUSE_BIT 0
+#define SECBOOT_FUSE_SHK_BIT 1
+#define SECBOOT_FUSE_DEBUG_DISABLED_BIT 2
+#define SECBOOT_FUSE_ANTI_ROLLBACK_BIT 3
+#define SECBOOT_FUSE_FEC_ENABLED_BIT 4
+#define SECBOOT_FUSE_RPMB_ENABLED_BIT 5
+#define SECBOOT_FUSE_DEBUG_RE_ENABLED_BIT 6
+#define CHECK_BIT(var, pos) ((var) & (1 << (pos)))
+
/* SCM interface as per ARM spec present? */
bool scm_arm_support;
static bool scm_initialized;
@@ -1244,7 +1253,7 @@
return 0;
}
-static bool secure_boot_enabled = true;
+static bool secure_boot_enabled = false;
static bool wdog_debug_fuse_disabled = true;
void scm_check_boot_fuses()
@@ -1265,14 +1274,16 @@
resp[0] = scm_ret.x1;
}
-
- /* Parse Bit 0 and Bit 2 of the response */
- if(!ret) {
- /* Bit 0 - SECBOOT_ENABLE_CHECK */
- if(resp[0] & 0x1)
- secure_boot_enabled = false;
+ if (!ret) {
+ /* Check for secure device: Bit#0 = 0, Bit#1 = 0 Bit#2 = 0 , Bit#5 = 0 , Bit#6 = 1 */
+ if (!CHECK_BIT(resp[0], SECBOOT_FUSE_BIT) && !CHECK_BIT(resp[0], SECBOOT_FUSE_SHK_BIT) &&
+ !CHECK_BIT(resp[0], SECBOOT_FUSE_DEBUG_DISABLED_BIT) &&
+ !CHECK_BIT(resp[0], SECBOOT_FUSE_RPMB_ENABLED_BIT) &&
+ CHECK_BIT(resp[0], SECBOOT_FUSE_DEBUG_RE_ENABLED_BIT)) {
+ secure_boot_enabled = true;
+ }
/* Bit 2 - DEBUG_DISABLE_CHECK */
- if(resp[0] & 0x4)
+ if (CHECK_BIT(resp[0], SECBOOT_FUSE_DEBUG_DISABLED_BIT))
wdog_debug_fuse_disabled = false;
} else
dprintf(CRITICAL, "scm call to check secure boot fuses failed\n");
diff --git a/platform/msm_shared/sdhci_msm.c b/platform/msm_shared/sdhci_msm.c
index 1063278..b34bfd5 100644
--- a/platform/msm_shared/sdhci_msm.c
+++ b/platform/msm_shared/sdhci_msm.c
@@ -556,7 +556,7 @@
DBG("\n CM_DLL_SDC4 Calibration Start\n");
/*1.Write the DDR config value to SDCC_HC_REG_DDR_CONFIG register*/
- REG_WRITE32(host, target_ddr_cfg_val(), SDCC_HC_REG_DDR_CONFIG);
+ REG_WRITE32(host, target_ddr_cfg_val(), target_ddr_cfg_reg());
/*2. Write DDR_CAL_EN to '1' */
REG_WRITE32(host, (REG_READ32(host, SDCC_HC_REG_DLL_CONFIG_2) | DDR_CAL_EN), SDCC_HC_REG_DLL_CONFIG_2);
diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h
index b32bda7..983cac7 100644
--- a/platform/msm_shared/smem.h
+++ b/platform/msm_shared/smem.h
@@ -494,6 +494,8 @@
HW_PLATFORM_SUBTYPE_CSFB = 1,
HW_PLATFORM_SUBTYPE_SVLTE1 = 2,
HW_PLATFORM_SUBTYPE_IOT = 2,
+ HW_PLATFORM_SUBTYPE_SNAP = 2,
+ HW_PLATFORM_SUBTYPE_SNAP_NOPMI = 3,
HW_PLATFORM_SUBTYPE_SVLTE2A = 3,
HW_PLATFORM_SUBTYPE_SGLTE = 6,
HW_PLATFORM_SUBTYPE_DSDA = 7,
diff --git a/target/init.c b/target/init.c
index d5cfa92..a0e0e10 100644
--- a/target/init.c
+++ b/target/init.c
@@ -248,6 +248,33 @@
return DDR_CONFIG_VAL;
}
+/* Default CFG register value */
+uint32_t target_ddr_cfg_reg()
+{
+ uint32_t platform = board_platform_id();
+ uint32_t ret = SDCC_HC_REG_DDR_CONFIG;
+
+ switch(platform)
+ {
+ case MSM8937:
+ case MSM8940:
+ case APQ8037:
+ case MSM8917:
+ case MSM8920:
+ case MSM8217:
+ case MSM8617:
+ case APQ8017:
+ case MSM8953:
+ case APQ8053:
+ /* SDCC HC DDR CONFIG has shifted by 4 bytes for these platform */
+ ret += 4;
+ break;
+ default:
+ break;
+ }
+ return ret;
+}
+
#if PON_VIB_SUPPORT
void get_vibration_type(struct qpnp_hap *config)
{