Merge "[msm8x60]: Enable fastboot reboot for 8660."
diff --git a/arch/arm/ops.S b/arch/arm/ops.S
index e2aa506..a858fa3 100644
--- a/arch/arm/ops.S
+++ b/arch/arm/ops.S
@@ -201,3 +201,13 @@
FUNCTION(arch_switch_stacks_and_call)
mov sp, r1
bx r0
+
+/*void dmb(void) */
+FUNCTION(dmb)
+#if ARM_CPU_CORTEX_A8
+ dmb sy
+#elif ARM_CPU_ARM1136
+ mov r0, #0
+ mcr p15, 0, r0, c7, c10, 5
+#endif
+ bx lr
diff --git a/platform/msm8x60/include/platform/iomap.h b/platform/msm8x60/include/platform/iomap.h
index ed64bd1..5f7bda8 100755
--- a/platform/msm8x60/include/platform/iomap.h
+++ b/platform/msm8x60/include/platform/iomap.h
@@ -43,15 +43,20 @@
#define MSM_ACC0_BASE 0x02041000
#define MSM_ACC1_BASE 0x02051000
+#define MSM_TCSR_BASE 0x16B00000
+#define TCSR_WDOG_CFG 0x30
+#define MSM_WDT0_RST (MSM_TMR_BASE + 0x38)
+#define MSM_WDT0_EN (MSM_TMR_BASE + 0x40)
+#define MSM_WDT0_BT (MSM_TMR_BASE + 0x4C)
#define MSM_GIC_CPU_BASE 0x02081000
#define MSM_GIC_DIST_BASE 0x02080000
#define MSM_SDC1_BASE 0x12400000
-#define MSM_SHARED_BASE 0x40000000
+#define MSM_SHARED_BASE 0x40000000
-#define SURF_DEBUG_LED_ADDR 0x1D000202
+#define SURF_DEBUG_LED_ADDR 0x1D000202
#define GPIO_CFG133_ADDR 0x00801850
#define GPIO_CFG135_ADDR 0x00801870
diff --git a/target/msm8660_surf/init.c b/target/msm8660_surf/init.c
index e91f125..f1e1b94 100755
--- a/target/msm8660_surf/init.c
+++ b/target/msm8660_surf/init.c
@@ -87,6 +87,19 @@
void reboot_device(unsigned reboot_reason)
{
+ /* Reset WDG0 counter */
+ writel(1,MSM_WDT0_RST);
+ /* Disable WDG0 */
+ writel(0,MSM_WDT0_EN);
+ /* Set WDG0 bark time */
+ writel(0x31F3,MSM_WDT0_BT);
+ /* Enable WDG0 */
+ writel(3,MSM_WDT0_EN);
+ dmb();
+ /* Enable WDG output */
+ writel(3,MSM_TCSR_BASE + TCSR_WDOG_CFG);
+ mdelay(10000);
+ dprintf (CRITICAL, "Rebooting failed\n");
return;
}