Merge "include: dev: Modify the flash_write api to use a flag for spare bytes."
diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
index ab52899..f700033 100755
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -585,6 +585,7 @@
{
/* Authorized kernel */
device.is_tampered = 0;
+ auth_kernel_img = 1;
}
#if USE_PCOM_SECBOOT
@@ -624,6 +625,7 @@
struct dt_entry dt_entry;
unsigned dt_table_offset;
uint32_t dt_actual;
+ uint32_t dt_hdr_size;
#endif
if (!boot_into_recovery) {
memset(ffbm_mode_string, '\0', sizeof(ffbm_mode_string));
@@ -773,15 +775,14 @@
#if DEVICE_TREE
if(hdr->dt_size) {
- table = (struct dt_table*) dt_buf;
dt_table_offset = ((uint32_t)image_addr + page_size + kernel_actual + ramdisk_actual + second_actual);
+ table = (struct dt_table*) dt_table_offset;
- memmove((void *) dt_buf, (char *)dt_table_offset, page_size);
-
- if (dev_tree_validate(table, hdr->page_size) != 0) {
+ if (dev_tree_validate(table, hdr->page_size, &dt_hdr_size) != 0) {
dprintf(CRITICAL, "ERROR: Cannot validate Device Tree Table \n");
return -1;
}
+
/* Find index of device tree within device tree table */
if(dev_tree_get_entry_info(table, &dt_entry) != 0){
dprintf(CRITICAL, "ERROR: Device Tree Blob cannot be found\n");
@@ -852,18 +853,28 @@
#if DEVICE_TREE
if(hdr->dt_size != 0) {
- /* Read the device tree table into buffer */
+ /* Read the first page of device tree table into buffer */
if(mmc_read(ptn + offset,(unsigned int *) dt_buf, page_size)) {
dprintf(CRITICAL, "ERROR: Cannot read the Device Tree Table\n");
return -1;
}
table = (struct dt_table*) dt_buf;
- if (dev_tree_validate(table, hdr->page_size) != 0) {
+ if (dev_tree_validate(table, hdr->page_size, &dt_hdr_size) != 0) {
dprintf(CRITICAL, "ERROR: Cannot validate Device Tree Table \n");
return -1;
}
+ table = (struct dt_table*) memalign(CACHE_LINE, dt_hdr_size);
+ if (!table)
+ return -1;
+
+ /* Read the entire device tree table into buffer */
+ if(mmc_read(ptn + offset,(unsigned int *) table, dt_hdr_size)) {
+ dprintf(CRITICAL, "ERROR: Cannot read the Device Tree Table\n");
+ return -1;
+ }
+
/* Find index of device tree within device tree table */
if(dev_tree_get_entry_info(table, &dt_entry) != 0){
dprintf(CRITICAL, "ERROR: Getting device tree address failed\n");
@@ -935,6 +946,7 @@
struct dt_table *table;
struct dt_entry dt_entry;
uint32_t dt_actual;
+ uint32_t dt_hdr_size;
#endif
if (target_is_emmc_boot()) {
@@ -1126,11 +1138,22 @@
table = (struct dt_table*) dt_buf;
- if (dev_tree_validate(table, hdr->page_size) != 0) {
+ if (dev_tree_validate(table, hdr->page_size, &dt_hdr_size) != 0) {
dprintf(CRITICAL, "ERROR: Cannot validate Device Tree Table \n");
return -1;
}
+ table = (struct dt_table*) memalign(CACHE_LINE, dt_hdr_size);
+ if (!table)
+ return -1;
+
+ /* Read the entire device tree table into buffer */
+ if(flash_read(ptn, offset, (void *)table, dt_hdr_size)) {
+ dprintf(CRITICAL, "ERROR: Cannot read the Device Tree Table\n");
+ return -1;
+ }
+
+
/* Find index of device tree within device tree table */
if(dev_tree_get_entry_info(table, &dt_entry) != 0){
dprintf(CRITICAL, "ERROR: Getting device tree address failed\n");
@@ -1335,6 +1358,7 @@
uint32_t n;
struct dt_table *table;
struct dt_entry dt_entry;
+ uint32_t dt_hdr_size;
struct boot_img_hdr *hdr = (struct boot_img_hdr *) (boot_image_start);
@@ -1358,7 +1382,7 @@
/* offset now point to start of dt.img */
table = (struct dt_table*)(boot_image_start + dt_image_offset);
- if (dev_tree_validate(table, hdr->page_size) != 0) {
+ if (dev_tree_validate(table, hdr->page_size, &dt_hdr_size) != 0) {
dprintf(CRITICAL, "ERROR: Cannot validate Device Tree Table \n");
return -1;
}
@@ -1593,12 +1617,16 @@
{
unsigned int chunk;
unsigned int chunk_data_sz;
+ uint32_t *fill_buf = NULL;
+ uint32_t fill_val;
+ uint32_t chunk_blk_cnt = 0;
sparse_header_t *sparse_header;
chunk_header_t *chunk_header;
uint32_t total_blocks = 0;
unsigned long long ptn = 0;
unsigned long long size = 0;
int index = INVALID_PTN;
+ int i;
index = partition_get_index(arg);
ptn = partition_get_offset(index);
@@ -1681,6 +1709,47 @@
data += chunk_data_sz;
break;
+ case CHUNK_TYPE_FILL:
+ if(chunk_header->total_sz != (sparse_header->chunk_hdr_sz +
+ sizeof(uint32_t)))
+ {
+ fastboot_fail("Bogus chunk size for chunk type FILL");
+ return;
+ }
+
+ fill_buf = (uint32_t *)memalign(CACHE_LINE, ROUNDUP(sparse_header->blk_sz, CACHE_LINE));
+ if (!fill_buf)
+ {
+ fastboot_fail("Malloc failed for: CHUNK_TYPE_FILL");
+ return;
+ }
+
+ fill_val = *(uint32_t *)data;
+ data = (char *) data + sizeof(uint32_t);
+ chunk_blk_cnt = chunk_data_sz / sparse_header->blk_sz;
+
+ for (i = 0; i < (sparse_header->blk_sz / sizeof(fill_val)); i++)
+ {
+ fill_buf[i] = fill_val;
+ }
+
+ for (i = 0; i < chunk_blk_cnt; i++)
+ {
+ if(mmc_write(ptn + ((uint64_t)total_blocks*sparse_header->blk_sz),
+ sparse_header->blk_sz,
+ fill_buf))
+ {
+ fastboot_fail("flash write failure");
+ free(fill_buf);
+ return;
+ }
+
+ total_blocks++;
+ }
+
+ free(fill_buf);
+ break;
+
case CHUNK_TYPE_DONT_CARE:
total_blocks += chunk_header->chunk_sz;
break;
@@ -1696,6 +1765,7 @@
break;
default:
+ dprintf(CRITICAL, "Unkown chunk type: %x\n",chunk_header->chunk_type);
fastboot_fail("Unknown chunk type");
return;
}
@@ -1910,33 +1980,123 @@
fastboot_okay("");
}
-void splash_screen ()
+static struct fbimage logo_header = {0};
+struct fbimage* splash_screen_flash();
+
+int splash_screen_check_header(struct fbimage *logo)
+{
+ if (memcmp(logo->header.magic, LOGO_IMG_MAGIC, 8))
+ return -1;
+ if (logo->header.width == 0 || logo->header.height == 0)
+ return -1;
+ return 0;
+}
+
+struct fbimage* splash_screen_flash()
{
struct ptentry *ptn;
struct ptable *ptable;
struct fbcon_config *fb_display = NULL;
+ struct fbimage *logo = &logo_header;
- if (!target_is_emmc_boot())
- {
- ptable = flash_get_ptable();
- if (ptable == NULL) {
- dprintf(CRITICAL, "ERROR: Partition table not found\n");
- return;
+
+ ptable = flash_get_ptable();
+ if (ptable == NULL) {
+ dprintf(CRITICAL, "ERROR: Partition table not found\n");
+ return NULL;
+ }
+ ptn = ptable_find(ptable, "splash");
+ if (ptn == NULL) {
+ dprintf(CRITICAL, "ERROR: splash Partition not found\n");
+ return NULL;
+ }
+
+ if (flash_read(ptn, 0,(unsigned int *) logo, sizeof(logo->header))) {
+ dprintf(CRITICAL, "ERROR: Cannot read boot image header\n");
+ return NULL;
+ }
+
+ if (splash_screen_check_header(logo)) {
+ dprintf(CRITICAL, "ERROR: Boot image header invalid\n");
+ return NULL;
+ }
+
+ fb_display = fbcon_display();
+ if (fb_display) {
+ uint8_t *base = (uint8_t *) fb_display->base;
+ if (logo->header.width != fb_display->width || logo->header.height != fb_display->height) {
+ base += LOGO_IMG_OFFSET;
}
- ptn = ptable_find(ptable, "splash");
- if (ptn == NULL) {
- dprintf(CRITICAL, "ERROR: No splash partition found\n");
- } else {
- fb_display = fbcon_display();
- if (fb_display) {
- if (flash_read(ptn, 0, fb_display->base,
- (fb_display->width * fb_display->height * fb_display->bpp/8))) {
- fbcon_clear();
- dprintf(CRITICAL, "ERROR: Cannot read splash image\n");
- }
- }
+ if (flash_read(ptn + sizeof(logo->header), 0,
+ base,
+ ((((logo->header.width * logo->header.height * fb_display->bpp/8) + 511) >> 9) << 9))) {
+ fbcon_clear();
+ dprintf(CRITICAL, "ERROR: Cannot read splash image\n");
+ return NULL;
}
+ logo->image = base;
+ }
+
+ return logo;
+}
+
+struct fbimage* splash_screen_mmc()
+{
+ int index = INVALID_PTN;
+ unsigned long long ptn = 0;
+ struct fbcon_config *fb_display = NULL;
+ struct fbimage *logo = &logo_header;
+
+ index = partition_get_index("splash");
+ if (index == 0) {
+ dprintf(CRITICAL, "ERROR: splash Partition table not found\n");
+ return NULL;
+ }
+
+ ptn = partition_get_offset(index);
+ if (ptn == 0) {
+ dprintf(CRITICAL, "ERROR: splash Partition invalid\n");
+ return NULL;
+ }
+
+ if (mmc_read(ptn, (unsigned int *) logo, sizeof(logo->header))) {
+ dprintf(CRITICAL, "ERROR: Cannot read splash image header\n");
+ return NULL;
+ }
+
+ if (splash_screen_check_header(logo)) {
+ dprintf(CRITICAL, "ERROR: Splash image header invalid\n");
+ return NULL;
+ }
+
+ fb_display = fbcon_display();
+ if (fb_display) {
+ uint8_t *base = (uint8_t *) fb_display->base;
+ if (logo->header.width != fb_display->width || logo->header.height != fb_display->height)
+ base += LOGO_IMG_OFFSET;
+
+ if (mmc_read(ptn + sizeof(logo->header),
+ base,
+ ((((logo->header.width * logo->header.height * fb_display->bpp/8) + 511) >> 9) << 9))) {
+ fbcon_clear();
+ dprintf(CRITICAL, "ERROR: Cannot read splash image\n");
+ return NULL;
+ }
+
+ logo->image = base;
+ }
+
+ return logo;
+}
+
+
+struct fbimage* fetch_image_from_partition()
+{
+ if (target_is_emmc_boot()) {
+ return splash_screen_mmc();
+ } else {
+ return splash_screen_flash();
}
}
diff --git a/dev/fbcon/fbcon.c b/dev/fbcon/fbcon.c
index 608f4c0..1fa8bd5 100644
--- a/dev/fbcon/fbcon.c
+++ b/dev/fbcon/fbcon.c
@@ -2,7 +2,7 @@
* Copyright (c) 2008, Google Inc.
* All rights reserved.
*
- * Copyright (c) 2009-2011, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -208,52 +208,110 @@
return config;
}
-void display_image_on_screen(void)
+
+extern struct fbimage* fetch_image_from_partition();
+void fbcon_putImage(struct fbimage *fbimg, bool flag);
+
+void display_image_on_screen()
+{
+ struct fbimage default_fbimg, *fbimg;
+ bool flag = true;
+
+ fbcon_clear();
+ fbimg = fetch_image_from_partition();
+
+ if(!fbimg) {
+ flag = false;
+ fbimg = &default_fbimg;
+ fbimg->header.width = SPLASH_IMAGE_HEIGHT;
+ fbimg->header.height = SPLASH_IMAGE_WIDTH;
+#if DISPLAY_TYPE_MIPI
+ fbimg->image = (unsigned char *)imageBuffer_rgb888;
+#else
+ fbimg->image = (unsigned char *)imageBuffer;
+#endif
+ }
+
+ fbcon_putImage(fbimg, flag);
+}
+
+void fbcon_putImage(struct fbimage *fbimg, bool flag)
{
unsigned i = 0;
unsigned total_x;
unsigned total_y;
unsigned bytes_per_bpp;
unsigned image_base;
+ unsigned width, pitch, height;
+ unsigned char *logo_base;
+ struct logo_img_header *header;
- if (!config) {
- dprintf(CRITICAL,"NULL configuration, image cannot be displayed\n");
- return;
- }
- fbcon_clear();
+ if (!config) {
+ dprintf(CRITICAL,"NULL configuration, image cannot be displayed\n");
+ return;
+ }
- total_x = config->width;
- total_y = config->height;
- bytes_per_bpp = ((config->bpp) / 8);
- image_base = ((((total_y/2) - (SPLASH_IMAGE_WIDTH / 2) - 1) *
- (config->width)) + (total_x/2 - (SPLASH_IMAGE_HEIGHT / 2)));
+ if(fbimg) {
+ header = &fbimg->header;
+ width = pitch = header->width;
+ height = header->height;
+ logo_base = (unsigned char *)fbimg->image;
+ }
+
+ total_x = config->width;
+ total_y = config->height;
+ bytes_per_bpp = ((config->bpp) / 8);
#if DISPLAY_TYPE_MIPI
- if (bytes_per_bpp == 3)
- {
- for (i = 0; i < SPLASH_IMAGE_WIDTH; i++)
- {
- memcpy (config->base + ((image_base + (i * (config->width))) * bytes_per_bpp),
- imageBuffer_rgb888 + (i * SPLASH_IMAGE_HEIGHT * bytes_per_bpp),
- SPLASH_IMAGE_HEIGHT * bytes_per_bpp);
+ if (bytes_per_bpp == 3)
+ {
+ if(flag) {
+ if (header->width == config->width && header->height == config->height)
+ return;
+ else {
+ logo_base = (unsigned char *)config->base + LOGO_IMG_OFFSET;
+ if (header->width > config->width) {
+ width = config->width;
+ pitch = header->width;
+ logo_base += (header->width - config->width) / 2 * bytes_per_bpp;
+ } else {
+ width = pitch = header->width;
+ }
+
+ if (header->height > config->height) {
+ height = config->height;
+ logo_base += (header->height - config->height) / 2 * pitch * bytes_per_bpp;
+ } else {
+ height = header->height;
+ }
+ }
+ }
+
+ image_base = ((((total_y/2) - (height / 2) ) *
+ (config->width)) + (total_x/2 - (width / 2)));
+ for (i = 0; i < height; i++) {
+ memcpy (config->base + ((image_base + (i * (config->width))) * bytes_per_bpp),
+ logo_base + (i * pitch * bytes_per_bpp), width * bytes_per_bpp);
+ }
}
- }
- fbcon_flush();
+
+ fbcon_flush();
+
#if DISPLAY_MIPI_PANEL_NOVATEK_BLUE
- if(is_cmd_mode_enabled())
+ if(is_cmd_mode_enabled())
mipi_dsi_cmd_mode_trigger();
#endif
#else
if (bytes_per_bpp == 2)
{
- for (i = 0; i < SPLASH_IMAGE_WIDTH; i++)
+ for (i = 0; i < header->width; i++)
{
memcpy (config->base + ((image_base + (i * (config->width))) * bytes_per_bpp),
- imageBuffer + (i * SPLASH_IMAGE_HEIGHT * bytes_per_bpp),
- SPLASH_IMAGE_HEIGHT * bytes_per_bpp);
- }
+ fbimg->image + (i * header->height * bytes_per_bpp),
+ header->height * bytes_per_bpp);
+ }
}
fbcon_flush();
#endif
diff --git a/dev/gcdb/display/gcdb_display.c b/dev/gcdb/display/gcdb_display.c
index e9872df..d4d1cb0 100755
--- a/dev/gcdb/display/gcdb_display.c
+++ b/dev/gcdb/display/gcdb_display.c
@@ -76,8 +76,8 @@
{
uint32_t ret = NO_ERROR;
- ret = target_panel_reset(enable, &reset_gpio,
- &enable_gpio, &reset_sequence);
+ ret = target_panel_reset(enable, panelstruct.panelresetseq,
+ &panel.panel_info);
return ret;
}
@@ -110,8 +110,7 @@
dprintf(CRITICAL, "Backlight enable failed \n");
return ret;
}
- ret = target_ldo_ctrl(enable, ldo_entry_array,
- TOTAL_LDO_DEFINED);
+ ret = target_ldo_ctrl(enable);
if (ret) {
dprintf(CRITICAL, "LDO control enable failed \n");
return ret;
@@ -138,8 +137,7 @@
return ret;
}
- ret = target_ldo_ctrl(enable, ldo_entry_array,
- TOTAL_LDO_DEFINED);
+ ret = target_ldo_ctrl(enable);
if (ret) {
dprintf(CRITICAL, "ldo control disable failed \n");
return ret;
@@ -154,9 +152,15 @@
{
char *dsi_id = panelstruct.paneldata->panel_controller;
char *panel_node = panelstruct.paneldata->panel_node_id;
+ uint16_t dsi_id_len = 0;
bool ret = true;
- if (buf_size < (strlen(panel_node) + MAX_DSI_STREAM_LEN +
+ if (dsi_id == NULL || panel_node == NULL)
+ return false;
+
+ dsi_id_len = strlen(dsi_id);
+
+ if (buf_size < (strlen(panel_node) + dsi_id_len +
MAX_PANEL_FORMAT_STRING + 1) ||
!strlen(panel_node) ||
!strlen(dsi_id))
@@ -171,8 +175,8 @@
buf_size -= MAX_PANEL_FORMAT_STRING;
strlcpy(pbuf, dsi_id, buf_size);
- pbuf += MAX_DSI_STREAM_LEN;
- buf_size -= MAX_DSI_STREAM_LEN;
+ pbuf += dsi_id_len;
+ buf_size -= dsi_id_len;
strlcpy(pbuf, panel_node, buf_size);
}
diff --git a/dev/gcdb/display/gcdb_display.h b/dev/gcdb/display/gcdb_display.h
index 6d647b2..16dd2c0 100755
--- a/dev/gcdb/display/gcdb_display.h
+++ b/dev/gcdb/display/gcdb_display.h
@@ -43,8 +43,6 @@
#define BIST_SIZE 6
#define LANE_SIZE 45
-#define MAX_DSI_STREAM_LEN 6
-
#define MAX_PANEL_FORMAT_STRING 2
/*---------------------------------------------------------------------------*/
@@ -53,12 +51,9 @@
int target_backlight_ctrl(uint8_t enable);
int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo);
-int target_panel_reset(uint8_t enable,
- struct gpio_pin *resetgpio,
- struct gpio_pin *enablegpio,
- struct panel_reset_sequence *resetseq);
-int target_ldo_ctrl(uint8_t enable, struct ldo_entry ldo_entry_array[],
- uint8_t totalldo);
+int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
+ struct msm_panel_info *pinfo);
+int target_ldo_ctrl(uint8_t enable);
void gcdb_display_init(unsigned int rev, void *base);
void gcdb_display_shutdown();
diff --git a/dev/gcdb/display/include/display_resource.h b/dev/gcdb/display/include/display_resource.h
index 24a375d..c469ec8 100755
--- a/dev/gcdb/display/include/display_resource.h
+++ b/dev/gcdb/display/include/display_resource.h
@@ -37,8 +37,6 @@
#include <smem.h>
#include <board.h>
-#define TOTAL_RESET_GPIO_CTRL 5
-
#define TOTAL_LDO_CTRL 5
/*---------------------------------------------------------------------------*/
@@ -56,13 +54,6 @@
uint32_t pin_state;
};
-typedef struct panel_reset_sequence {
-
- uint8_t pin_state[TOTAL_RESET_GPIO_CTRL];
- uint32_t sleep[TOTAL_RESET_GPIO_CTRL];
- uint8_t pin_direction;
-};
-
/*LDO entry structure for different LDO entries. */
typedef struct ldo_entry{
char *ldo_name;
diff --git a/dev/gcdb/display/include/panel.h b/dev/gcdb/display/include/panel.h
index c32c7e7..f7f1f7f 100755
--- a/dev/gcdb/display/include/panel.h
+++ b/dev/gcdb/display/include/panel.h
@@ -36,6 +36,8 @@
#include <debug.h>
#include <smem.h>
+#define TOTAL_RESET_GPIO_CTRL 5
+
/*---------------------------------------------------------------------------*/
/* Structure definition */
/*---------------------------------------------------------------------------*/
@@ -62,6 +64,7 @@
uint32_t panel_bitclock_freq;
uint32_t panel_operating_mode;
uint32_t panel_with_enable_gpio;
+ uint8_t mode_gpio_state;
};
typedef struct panel_resolution{
@@ -150,6 +153,12 @@
BL_LPG,
};
+typedef struct panel_reset_sequence {
+ uint8_t pin_state[TOTAL_RESET_GPIO_CTRL];
+ uint32_t sleep[TOTAL_RESET_GPIO_CTRL];
+ uint8_t pin_direction;
+};
+
typedef struct backlight {
uint16_t bl_interface_type;
uint16_t bl_min_level;
diff --git a/dev/gcdb/display/include/panel_hx8379a_wvga_video.h b/dev/gcdb/display/include/panel_hx8379a_wvga_video.h
new file mode 100644
index 0000000..acda031
--- /dev/null
+++ b/dev/gcdb/display/include/panel_hx8379a_wvga_video.h
@@ -0,0 +1,252 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PANEL_HX8379A_WVGA_VIDEO_H_
+
+#define _PANEL_HX8379A_WVGA_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct panel_config hx8379a_wvga_video_panel_data = {
+ "qcom,mdss_dsi_hx8379a_wvga_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution hx8379a_wvga_video_panel_res = {
+ 480, 800, 94, 100, 40, 0, 6, 6, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Color Information */
+/*---------------------------------------------------------------------------*/
+static struct color_info hx8379a_wvga_video_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Command information */
+/*---------------------------------------------------------------------------*/
+static char hx8379a_wvga_video_on_cmd0[] = {
+0x04, 0x00, 0x39, 0xC0,
+0xB9, 0xFF, 0x83, 0x79,
+ };
+
+
+static char hx8379a_wvga_video_on_cmd1[] = {
+0x03, 0x00, 0x39, 0xC0,
+0xBA, 0x51, 0x93, 0xFF, };
+
+
+static char hx8379a_wvga_video_on_cmd2[] = {
+0x14, 0x00, 0x39, 0xC0,
+0xB1, 0x00, 0x50, 0x44,
+0xEA, 0x8D, 0x08, 0x11,
+0x11, 0x11, 0x27, 0x2F,
+0x9A, 0x1A, 0x42, 0x0B,
+0x6E, 0xF1, 0x00, 0xE6,
+ };
+
+
+static char hx8379a_wvga_video_on_cmd3[] = {
+0x0E, 0x00, 0x39, 0xC0,
+0xB2, 0x00, 0x00, 0x3C,
+0x08, 0x04, 0x19, 0x22,
+0x00, 0xFF, 0x08, 0x04,
+0x19, 0x20, 0xFF, 0xFF, };
+
+
+static char hx8379a_wvga_video_on_cmd4[] = {
+0x20, 0x00, 0x39, 0xC0,
+0xB4, 0x80, 0x08, 0x00,
+0x32, 0x10, 0x03, 0x32,
+0x13, 0x70, 0x32, 0x10,
+0x08, 0x37, 0x01, 0x28,
+0x07, 0x37, 0x08, 0x35,
+0x08, 0x3D, 0x44, 0x08,
+0x00, 0x40, 0x08, 0x28,
+0x08, 0x30, 0x30, 0x04,
+ };
+
+
+static char hx8379a_wvga_video_on_cmd5[] = {
+0x30, 0x00, 0x39, 0xC0,
+0xD5, 0x00, 0x00, 0x0A,
+0x00, 0x01, 0x05, 0x00,
+0x03, 0x00, 0x88, 0x88,
+0x88, 0x88, 0x23, 0x01,
+0x67, 0x45, 0x02, 0x13,
+0x88, 0x88, 0x88, 0x88,
+0x88, 0x88, 0x88, 0x88,
+0x88, 0x88, 0x54, 0x76,
+0x10, 0x32, 0x31, 0x20,
+0x88, 0x88, 0x88, 0x88,
+0x88, 0x88, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00,
+ };
+
+
+static char hx8379a_wvga_video_on_cmd6[] = {
+0x24, 0x00, 0x39, 0xC0,
+0xE0, 0x79, 0x05, 0x0F,
+0x14, 0x26, 0x20, 0x3F,
+0x2A, 0x43, 0x04, 0x0C,
+0x11, 0x15, 0x17, 0x15,
+0x15, 0x10, 0x13, 0x05,
+0x0F, 0x14, 0x26, 0x20,
+0x3F, 0x2A, 0x43, 0x04,
+0x0C, 0x11, 0x15, 0x17,
+0x15, 0x15, 0x10, 0x13,
+ };
+
+
+static char hx8379a_wvga_video_on_cmd7[] = {
+0xcc, 0x02, 0x23, 0x80 };
+
+
+static char hx8379a_wvga_video_on_cmd8[] = {
+0x05, 0x00, 0x39, 0xC0,
+0xB6, 0x00, 0x9C, 0x00,
+0x9C, 0xFF, 0xFF, 0xFF, };
+
+
+static char hx8379a_wvga_video_on_cmd9[] = {
+0x11, 0x00, 0x05, 0x80 };
+
+
+static char hx8379a_wvga_video_on_cmd10[] = {
+0x29, 0x00, 0x05, 0x80 };
+
+
+
+
+static struct mipi_dsi_cmd hx8379a_wvga_video_on_command[] = {
+{ 0x8 , hx8379a_wvga_video_on_cmd0},
+{ 0x8 , hx8379a_wvga_video_on_cmd1},
+{ 0x18 , hx8379a_wvga_video_on_cmd2},
+{ 0x14 , hx8379a_wvga_video_on_cmd3},
+{ 0x24 , hx8379a_wvga_video_on_cmd4},
+{ 0x34 , hx8379a_wvga_video_on_cmd5},
+{ 0x28 , hx8379a_wvga_video_on_cmd6},
+{ 0x4 , hx8379a_wvga_video_on_cmd7},
+{ 0xc , hx8379a_wvga_video_on_cmd8},
+{ 0x4 , hx8379a_wvga_video_on_cmd9},
+{ 0x4 , hx8379a_wvga_video_on_cmd10}
+};
+#define HX8379A_WVGA_VIDEO_ON_COMMAND 11
+
+
+static char hx8379a_wvga_videooff_cmd0[] = {
+0x28, 0x00, 0x05, 0x80 };
+
+
+static char hx8379a_wvga_videooff_cmd1[] = {
+0x10, 0x00, 0x05, 0x80 };
+
+
+
+
+static struct mipi_dsi_cmd hx8379a_wvga_video_off_command[] = {
+{ 0x4 , hx8379a_wvga_videooff_cmd0},
+{ 0x4 , hx8379a_wvga_videooff_cmd1}
+};
+#define HX8379A_WVGA_VIDEO_OFF_COMMAND 2
+
+
+static struct command_state hx8379a_wvga_video_state = {
+ 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct commandpanel_info hx8379a_wvga_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct videopanel_info hx8379a_wvga_video_video_panel = {
+ 1, 0, 0, 0, 1, 1, 2, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane Configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct lane_configuration hx8379a_wvga_video_lane_config = {
+ 2, 1, 1, 1, 0, 0
+};
+
+
+/*---------------------------------------------------------------------------*/
+/* Panel Timing */
+/*---------------------------------------------------------------------------*/
+static const uint32_t hx8379a_wvga_video_timings[] = {
+ 0x78, 0x1B, 0x11, 0x00, 0x3E, 0x43, 0x16, 0x1E, 0x1D, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing hx8379a_wvga_video_timing_info = {
+ 0, 4, 0x04, 0x1b
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Reset Sequence */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence hx8379a_wvga_video_reset_seq = {
+ { 2, 0, 2, }, { 20, 2, 20, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight Settings */
+/*---------------------------------------------------------------------------*/
+
+static struct backlight hx8379a_wvga_video_backlight = {
+ 0, 1, 255, 0, 1, 0
+};
+
+
+#endif /*_PANEL_HX8379A_WVGA_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_hx8394a_720p_video.h b/dev/gcdb/display/include/panel_hx8394a_720p_video.h
index d50b5be..75b8493 100644
--- a/dev/gcdb/display/include/panel_hx8394a_720p_video.h
+++ b/dev/gcdb/display/include/panel_hx8394a_720p_video.h
@@ -148,13 +148,13 @@
static char hx8394a_720p_video_on_cmd11[] = {
0x23, 0x00, 0x39, 0xC0,
-0xe0, 0x01, 0x05, 0x07,
-0x25, 0x35, 0x3f, 0x0b,
-0x32, 0x04, 0x09, 0x0e,
+0xe0, 0x01, 0x0b, 0x10,
+0x25, 0x35, 0x3f, 0x15,
+0x36, 0x04, 0x09, 0x0e,
0x10, 0x13, 0x10, 0x14,
-0x16, 0x1b, 0x01, 0x05,
-0x07, 0x25, 0x35, 0x3f,
-0x0b, 0x32, 0x04, 0x09,
+0x16, 0x1b, 0x01, 0x0b,
+0x10, 0x25, 0x35, 0x3f,
+0x15, 0x36, 0x04, 0x09,
0x0e, 0x10, 0x13, 0x10,
0x14, 0x16, 0x1b, 0xFF, };
@@ -265,6 +265,10 @@
0, 4, 0x1f, 0x2d
};
+static struct panel_reset_sequence hx8394a_720p_video_panel_reset_seq = {
+{ 1, 0, 1, }, { 20, 20, 20, }, 2
+};
+
/*---------------------------------------------------------------------------*/
/* Backlight Settings */
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_nt35521_720p_video.h b/dev/gcdb/display/include/panel_nt35521_720p_video.h
index 6eb316e..c5f9069 100644
--- a/dev/gcdb/display/include/panel_nt35521_720p_video.h
+++ b/dev/gcdb/display/include/panel_nt35521_720p_video.h
@@ -1466,6 +1466,10 @@
0, 4, 0x20, 0x2D
};
+static struct panel_reset_sequence nt35521_720p_video_panel_reset_seq = {
+{ 1, 0, 1, }, { 20, 20, 20, }, 2
+};
+
/*---------------------------------------------------------------------------*/
/* Backlight Settings */
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_nt35590_720p_cmd.h b/dev/gcdb/display/include/panel_nt35590_720p_cmd.h
index ca0b4e5..47ec49f 100755
--- a/dev/gcdb/display/include/panel_nt35590_720p_cmd.h
+++ b/dev/gcdb/display/include/panel_nt35590_720p_cmd.h
@@ -2923,6 +2923,10 @@
0, 4, 0x20, 0x2c
};
+static struct panel_reset_sequence nt35590_720p_cmd_panel_reset_seq = {
+{ 1, 0, 1, }, { 20, 20, 20, }, 2
+};
+
/*---------------------------------------------------------------------------*/
/* Backlight Settings */
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_nt35590_720p_video.h b/dev/gcdb/display/include/panel_nt35590_720p_video.h
index 06c7dd5..ce740a7 100755
--- a/dev/gcdb/display/include/panel_nt35590_720p_video.h
+++ b/dev/gcdb/display/include/panel_nt35590_720p_video.h
@@ -2923,6 +2923,10 @@
0, 4, 0x20, 0x2c
};
+static struct panel_reset_sequence nt35590_720p_video_panel_reset_seq = {
+{ 1, 0, 1, }, { 20, 20, 20, }, 2
+};
+
/*---------------------------------------------------------------------------*/
/* Backlight Settings */
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_nt35596_1080p_video.h b/dev/gcdb/display/include/panel_nt35596_1080p_video.h
index e5dad1a..3d35b61 100644
--- a/dev/gcdb/display/include/panel_nt35596_1080p_video.h
+++ b/dev/gcdb/display/include/panel_nt35596_1080p_video.h
@@ -3251,6 +3251,10 @@
0, 4, 0x1e, 0x38
};
+static struct panel_reset_sequence nt35596_1080p_video_panel_reset_seq = {
+{ 1, 0, 1, }, { 20, 20, 20, }, 2
+};
+
/*---------------------------------------------------------------------------*/
/* Backlight Settings */
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_otm8018b_fwvga_video.h b/dev/gcdb/display/include/panel_otm8018b_fwvga_video.h
new file mode 100755
index 0000000..7fa9098
--- /dev/null
+++ b/dev/gcdb/display/include/panel_otm8018b_fwvga_video.h
@@ -0,0 +1,686 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PANEL_OTM8018B_FWVGA_VIDEO_H_
+
+#define _PANEL_OTM8018B_FWVGA_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct panel_config otm8018b_fwvga_video_panel_data = {
+ "qcom,mdss_dsi_otm8018b_fwvga_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution otm8018b_fwvga_video_panel_res = {
+ 480, 854, 80, 54, 8, 0, 12, 16, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Color Information */
+/*---------------------------------------------------------------------------*/
+static struct color_info otm8018b_fwvga_video_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Command information */
+/*---------------------------------------------------------------------------*/
+static char otm8018b_fwvga_video_on_cmd0[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x00, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd1[] = {
+0x04, 0x00, 0x29, 0xC0,
+0xff, 0x80, 0x09, 0x01,
+ };
+
+
+static char otm8018b_fwvga_video_on_cmd2[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x80, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd3[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xff, 0x80, 0x09, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd4[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x80, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd5[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xd6, 0x48, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd6[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x03, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd7[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xff, 0x01, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd8[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xB4, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd9[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xC0, 0x10, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd10[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x82, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd11[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xC5, 0xA3, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd12[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x90, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd13[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xC5, 0x96, 0x87, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd14[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x00, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd15[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xD8, 0x74, 0x72, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd16[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x00, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd17[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xD9, 0x56, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd18[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x00, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd19[] = {
+0x11, 0x00, 0x29, 0xC0,
+0xE1, 0x00, 0x06, 0x0A,
+0x07, 0x03, 0x16, 0x08,
+0x0A, 0x04, 0x06, 0x07,
+0x08, 0x0F, 0x23, 0x22,
+0x05, 0xFF, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd20[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x00, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd21[] = {
+0x11, 0x00, 0x29, 0xC0,
+0xE2, 0x00, 0x06, 0x0A,
+0x07, 0x03, 0x16, 0x08,
+0x0A, 0x04, 0x06, 0x07,
+0x08, 0x0F, 0x23, 0x22,
+0x05, 0xFF, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd22[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x81, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd23[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xC1, 0x77, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd24[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xA0, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd25[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xC1, 0xEA, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd26[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xA1, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd27[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xC1, 0x08, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd28[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x89, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd29[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xC4, 0x08, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd30[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x81, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd31[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xC4, 0x83, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd32[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x92, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd33[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xC5, 0x01, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd34[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xB1, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd35[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xC5, 0xA9, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd36[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x92, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd37[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xB3, 0x45, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd38[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x90, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd39[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xB3, 0x02, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd40[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x80, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd41[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xC0, 0x00, 0x58, 0x00,
+0x14, 0x16, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd42[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x80, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd43[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xC4, 0x30, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd44[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x90, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd45[] = {
+0x07, 0x00, 0x29, 0xC0,
+0xC0, 0x00, 0x44, 0x00,
+0x00, 0x00, 0x03, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd46[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xA6, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd47[] = {
+0x04, 0x00, 0x29, 0xC0,
+0xC1, 0x01, 0x00, 0x00,
+ };
+
+
+static char otm8018b_fwvga_video_on_cmd48[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x80, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd49[] = {
+0x0D, 0x00, 0x29, 0xC0,
+0xCE, 0x87, 0x03, 0x00,
+0x85, 0x03, 0x00, 0x86,
+0x03, 0x00, 0x84, 0x03,
+0x00, 0xFF, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd50[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xA0, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd51[] = {
+0x0f, 0x00, 0x29, 0xC0,
+0xCE, 0x38, 0x03, 0x03,
+0x58, 0x00, 0x00, 0x00,
+0x38, 0x02, 0x03, 0x59,
+0x00, 0x00, 0x00, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd52[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xB0, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd53[] = {
+0x0f, 0x00, 0x29, 0xC0,
+0xCE, 0x38, 0x01, 0x03,
+0x5A, 0x00, 0x00, 0x00,
+0x38, 0x00, 0x03, 0x5B,
+0x00, 0x00, 0x00, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd54[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xC0, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd55[] = {
+0x0f, 0x00, 0x29, 0xC0,
+0xCE, 0x30, 0x00, 0x03,
+0x5C, 0x00, 0x00, 0x00,
+0x30, 0x01, 0x03, 0x5D,
+0x00, 0x00, 0x00, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd56[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xD0, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd57[] = {
+0x0f, 0x00, 0x29, 0xC0,
+0xCE, 0x30, 0x02, 0x03,
+0x5E, 0x00, 0x00, 0x00,
+0x30, 0x03, 0x03, 0x5F,
+0x00, 0x00, 0x00, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd58[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xC7, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd59[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xCF, 0x00, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd60[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xC9, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd61[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xCF, 0x00, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd62[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xD0, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd63[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xCF, 0x00, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd64[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xC4, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd65[] = {
+0x07, 0x00, 0x29, 0xC0,
+0xCB, 0x04, 0x04, 0x04,
+0x04, 0x04, 0x04, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd66[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xD9, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd67[] = {
+0x07, 0x00, 0x29, 0xC0,
+0xCB, 0x04, 0x04, 0x04,
+0x04, 0x04, 0x04, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd68[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x84, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd69[] = {
+0x07, 0x00, 0x29, 0xC0,
+0xCC, 0x0C, 0x0A, 0x10,
+0x0E, 0x03, 0x04, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd70[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x9E, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd71[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xCC, 0x0B, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd72[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xA0, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd73[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xCC, 0x09, 0x0F, 0x0D,
+0x01, 0x02, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd74[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xB4, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd75[] = {
+0x07, 0x00, 0x29, 0xC0,
+0xCC, 0x0D, 0x0F, 0x09,
+0x0B, 0x02, 0x01, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd76[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xCE, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd77[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xCC, 0x0E, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd78[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0xD0, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd79[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xCC, 0x10, 0x0A, 0x0C,
+0x04, 0x03, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd80[] = {
+0x02, 0x00, 0x29, 0xC0,
+0x00, 0x00, 0xFF, 0xFF, };
+
+
+static char otm8018b_fwvga_video_on_cmd81[] = {
+0x04, 0x00, 0x29, 0xC0,
+0xff, 0xff, 0xff, 0xff,
+ };
+
+
+static char otm8018b_fwvga_video_on_cmd82[] = {
+0x11, 0x00, 0x05, 0x80 };
+
+
+static char otm8018b_fwvga_video_on_cmd83[] = {
+0x29, 0x00, 0x05, 0x80 };
+
+
+
+
+static struct mipi_dsi_cmd otm8018b_fwvga_video_on_command[] = {
+{ 0x8 , otm8018b_fwvga_video_on_cmd0},
+{ 0x8 , otm8018b_fwvga_video_on_cmd1},
+{ 0x8 , otm8018b_fwvga_video_on_cmd2},
+{ 0x8 , otm8018b_fwvga_video_on_cmd3},
+{ 0x8 , otm8018b_fwvga_video_on_cmd4},
+{ 0x8 , otm8018b_fwvga_video_on_cmd5},
+{ 0x8 , otm8018b_fwvga_video_on_cmd6},
+{ 0x8 , otm8018b_fwvga_video_on_cmd7},
+{ 0x8 , otm8018b_fwvga_video_on_cmd8},
+{ 0x8 , otm8018b_fwvga_video_on_cmd9},
+{ 0x8 , otm8018b_fwvga_video_on_cmd10},
+{ 0x8 , otm8018b_fwvga_video_on_cmd11},
+{ 0x8 , otm8018b_fwvga_video_on_cmd12},
+{ 0x8 , otm8018b_fwvga_video_on_cmd13},
+{ 0x8 , otm8018b_fwvga_video_on_cmd14},
+{ 0x8 , otm8018b_fwvga_video_on_cmd15},
+{ 0x8 , otm8018b_fwvga_video_on_cmd16},
+{ 0x8 , otm8018b_fwvga_video_on_cmd17},
+{ 0x8 , otm8018b_fwvga_video_on_cmd18},
+{ 0x18 , otm8018b_fwvga_video_on_cmd19},
+{ 0x8 , otm8018b_fwvga_video_on_cmd20},
+{ 0x18 , otm8018b_fwvga_video_on_cmd21},
+{ 0x8 , otm8018b_fwvga_video_on_cmd22},
+{ 0x8 , otm8018b_fwvga_video_on_cmd23},
+{ 0x8 , otm8018b_fwvga_video_on_cmd24},
+{ 0x8 , otm8018b_fwvga_video_on_cmd25},
+{ 0x8 , otm8018b_fwvga_video_on_cmd26},
+{ 0x8 , otm8018b_fwvga_video_on_cmd27},
+{ 0x8 , otm8018b_fwvga_video_on_cmd28},
+{ 0x8 , otm8018b_fwvga_video_on_cmd29},
+{ 0x8 , otm8018b_fwvga_video_on_cmd30},
+{ 0x8 , otm8018b_fwvga_video_on_cmd31},
+{ 0x8 , otm8018b_fwvga_video_on_cmd32},
+{ 0x8 , otm8018b_fwvga_video_on_cmd33},
+{ 0x8 , otm8018b_fwvga_video_on_cmd34},
+{ 0x8 , otm8018b_fwvga_video_on_cmd35},
+{ 0x8 , otm8018b_fwvga_video_on_cmd36},
+{ 0x8 , otm8018b_fwvga_video_on_cmd37},
+{ 0x8 , otm8018b_fwvga_video_on_cmd38},
+{ 0x8 , otm8018b_fwvga_video_on_cmd39},
+{ 0x8 , otm8018b_fwvga_video_on_cmd40},
+{ 0xc , otm8018b_fwvga_video_on_cmd41},
+{ 0x8 , otm8018b_fwvga_video_on_cmd42},
+{ 0x8 , otm8018b_fwvga_video_on_cmd43},
+{ 0x8 , otm8018b_fwvga_video_on_cmd44},
+{ 0xc , otm8018b_fwvga_video_on_cmd45},
+{ 0x8 , otm8018b_fwvga_video_on_cmd46},
+{ 0x8 , otm8018b_fwvga_video_on_cmd47},
+{ 0x8 , otm8018b_fwvga_video_on_cmd48},
+{ 0x14 , otm8018b_fwvga_video_on_cmd49},
+{ 0x8 , otm8018b_fwvga_video_on_cmd50},
+{ 0x14 , otm8018b_fwvga_video_on_cmd51},
+{ 0x8 , otm8018b_fwvga_video_on_cmd52},
+{ 0x14 , otm8018b_fwvga_video_on_cmd53},
+{ 0x8 , otm8018b_fwvga_video_on_cmd54},
+{ 0x14 , otm8018b_fwvga_video_on_cmd55},
+{ 0x8 , otm8018b_fwvga_video_on_cmd56},
+{ 0x14 , otm8018b_fwvga_video_on_cmd57},
+{ 0x8 , otm8018b_fwvga_video_on_cmd58},
+{ 0x8 , otm8018b_fwvga_video_on_cmd59},
+{ 0x8 , otm8018b_fwvga_video_on_cmd60},
+{ 0x8 , otm8018b_fwvga_video_on_cmd61},
+{ 0x8 , otm8018b_fwvga_video_on_cmd62},
+{ 0x8 , otm8018b_fwvga_video_on_cmd63},
+{ 0x8 , otm8018b_fwvga_video_on_cmd64},
+{ 0xc , otm8018b_fwvga_video_on_cmd65},
+{ 0x8 , otm8018b_fwvga_video_on_cmd66},
+{ 0xc , otm8018b_fwvga_video_on_cmd67},
+{ 0x8 , otm8018b_fwvga_video_on_cmd68},
+{ 0xc , otm8018b_fwvga_video_on_cmd69},
+{ 0x8 , otm8018b_fwvga_video_on_cmd70},
+{ 0x8 , otm8018b_fwvga_video_on_cmd71},
+{ 0x8 , otm8018b_fwvga_video_on_cmd72},
+{ 0xc , otm8018b_fwvga_video_on_cmd73},
+{ 0x8 , otm8018b_fwvga_video_on_cmd74},
+{ 0xc , otm8018b_fwvga_video_on_cmd75},
+{ 0x8 , otm8018b_fwvga_video_on_cmd76},
+{ 0x8 , otm8018b_fwvga_video_on_cmd77},
+{ 0x8 , otm8018b_fwvga_video_on_cmd78},
+{ 0xc , otm8018b_fwvga_video_on_cmd79},
+{ 0x8 , otm8018b_fwvga_video_on_cmd80},
+{ 0x8 , otm8018b_fwvga_video_on_cmd81},
+{ 0x4 , otm8018b_fwvga_video_on_cmd82},
+{ 0x4 , otm8018b_fwvga_video_on_cmd83}
+};
+#define OTM8018B_FWVGA_VIDEO_ON_COMMAND 84
+
+
+static char otm8018b_fwvga_videooff_cmd0[] = {
+0x28, 0x00, 0x05, 0x80 };
+
+
+static char otm8018b_fwvga_videooff_cmd1[] = {
+0x10, 0x00, 0x05, 0x80 };
+
+
+
+
+static struct mipi_dsi_cmd otm8018b_fwvga_video_off_command[] = {
+{ 0x4 , otm8018b_fwvga_videooff_cmd0},
+{ 0x4 , otm8018b_fwvga_videooff_cmd1}
+};
+#define OTM8018B_FWVGA_VIDEO_OFF_COMMAND 2
+
+
+static struct command_state otm8018b_fwvga_video_state = {
+ 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct commandpanel_info otm8018b_fwvga_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct videopanel_info otm8018b_fwvga_video_video_panel = {
+ 1, 0, 0, 0, 1, 1, 2, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane Configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct lane_configuration otm8018b_fwvga_video_lane_config = {
+ 2, 1, 1, 1, 0, 0
+};
+
+
+/*---------------------------------------------------------------------------*/
+/* Panel Timing */
+/*---------------------------------------------------------------------------*/
+static const uint32_t otm8018b_fwvga_video_timings[] = {
+ 0x72, 0x19, 0x11, 0x00, 0x3C, 0x46, 0x14, 0x1C, 0x1C, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing otm8018b_fwvga_video_timing_info = {
+ 0, 4, 0x04, 0x1b
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Reset Sequence */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence otm8018b_fwvga_video_reset_seq = {
+ { 2, 0, 2, }, { 20, 2, 20, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight Settings */
+/*---------------------------------------------------------------------------*/
+
+static struct backlight otm8018b_fwvga_video_backlight = {
+ 0, 1, 255, 0, 1, 0
+};
+
+
+#endif /*_PANEL_OTM8018B_FWVGA_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_sharp_qhd_video.h b/dev/gcdb/display/include/panel_sharp_qhd_video.h
new file mode 100755
index 0000000..df8c5a5
--- /dev/null
+++ b/dev/gcdb/display/include/panel_sharp_qhd_video.h
@@ -0,0 +1,190 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PANEL_SHARP_QHD_VIDEO_H_
+
+#define _PANEL_SHARP_QHD_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct panel_config sharp_qhd_video_panel_data = {
+ "qcom,mdss_dsi_sharp_qhd_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution sharp_qhd_video_panel_res = {
+ 540, 960, 48, 80, 32, 0, 3, 15, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Color Information */
+/*---------------------------------------------------------------------------*/
+static struct color_info sharp_qhd_video_color = {
+ 24, 2, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Command information */
+/*---------------------------------------------------------------------------*/
+static char sharp_qhd_video_on_cmd0[] = {
+0x01, 0x00, 0x05, 0x80 };
+
+
+static char sharp_qhd_video_on_cmd1[] = {
+0x11, 0x00, 0x05, 0x80 };
+
+
+static char sharp_qhd_video_on_cmd2[] = {
+0x53, 0x2c, 0x15, 0x80 };
+
+
+static char sharp_qhd_video_on_cmd3[] = {
+0x51, 0xff, 0x15, 0x80 };
+
+
+static char sharp_qhd_video_on_cmd4[] = {
+0x29, 0x00, 0x05, 0x80 };
+
+
+static char sharp_qhd_video_on_cmd5[] = {
+0xae, 0x03, 0x15, 0x80 };
+
+
+static char sharp_qhd_video_on_cmd6[] = {
+0x3a, 0x77, 0x15, 0x80 };
+
+
+
+
+static struct mipi_dsi_cmd sharp_qhd_video_on_command[] = {
+{ 0x4 , sharp_qhd_video_on_cmd0},
+{ 0x4 , sharp_qhd_video_on_cmd1},
+{ 0x4 , sharp_qhd_video_on_cmd2},
+{ 0x4 , sharp_qhd_video_on_cmd3},
+{ 0x4 , sharp_qhd_video_on_cmd4},
+{ 0x4 , sharp_qhd_video_on_cmd5},
+{ 0x4 , sharp_qhd_video_on_cmd6}
+};
+#define SHARP_QHD_VIDEO_ON_COMMAND 7
+
+
+static char sharp_qhd_videooff_cmd0[] = {
+0x28, 0x00, 0x05, 0x80 };
+
+
+static char sharp_qhd_videooff_cmd1[] = {
+0x10, 0x00, 0x05, 0x80 };
+
+
+
+
+static struct mipi_dsi_cmd sharp_qhd_video_off_command[] = {
+{ 0x4 , sharp_qhd_videooff_cmd0},
+{ 0x4 , sharp_qhd_videooff_cmd1}
+};
+#define SHARP_QHD_VIDEO_OFF_COMMAND 2
+
+
+static struct command_state sharp_qhd_video_state = {
+ 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct commandpanel_info sharp_qhd_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct videopanel_info sharp_qhd_video_video_panel = {
+ 1, 0, 0, 0, 1, 1, 0, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane Configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct lane_configuration sharp_qhd_video_lane_config = {
+ 2, 0, 1, 1, 0, 0
+};
+
+
+/*---------------------------------------------------------------------------*/
+/* Panel Timing */
+/*---------------------------------------------------------------------------*/
+const uint32_t sharp_qhd_video_timings[] = {
+ 0x46, 0x1d, 0x20, 0x00, 0x39, 0x3a, 0x21, 0x21, 0x32, 0x03, 0x04, 0x00
+};
+
+
+
+static struct mipi_dsi_cmd sharp_qhd_video_rotation[] = {
+
+};
+#define SHARP_QHD_VIDEO_ROTATION 0
+
+
+static struct panel_timing sharp_qhd_video_timing_info = {
+ 4, 4, 0x04, 0x1c
+};
+
+static struct panel_reset_sequence sharp_qhd_video_panel_reset_seq = {
+{ 1, 0, 1, }, { 20, 200, 20, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight Settings */
+/*---------------------------------------------------------------------------*/
+
+static struct backlight sharp_qhd_video_backlight = {
+ 1, 1, 4095, 100, 1, "PMIC_8941"
+};
+
+
+#endif /*_PANEL_SHARP_QHD_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_ssd2080m_720p_video.h b/dev/gcdb/display/include/panel_ssd2080m_720p_video.h
new file mode 100755
index 0000000..66c2b5a
--- /dev/null
+++ b/dev/gcdb/display/include/panel_ssd2080m_720p_video.h
@@ -0,0 +1,492 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PANEL_SSD2080M_720P_VIDEO_H_
+
+#define _PANEL_SSD2080M_720P_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct panel_config ssd2080m_720p_video_panel_data = {
+ "qcom,mdss_dsi_ssd2080m_720p_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution ssd2080m_720p_video_panel_res = {
+ 720, 1280, 80, 24, 14, 0, 12, 16, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Color Information */
+/*---------------------------------------------------------------------------*/
+static struct color_info ssd2080m_720p_video_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Command information */
+/*---------------------------------------------------------------------------*/
+static char ssd2080m_720p_video_on_cmd0[] = {
+0xFF, 0x01, 0x15, 0x80 };
+
+
+static char ssd2080m_720p_video_on_cmd1[] = {
+0x05, 0x00, 0x29, 0xC0,
+0xC6, 0x63, 0x00, 0x81,
+0x31, 0xFF, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd2[] = {
+0x05, 0x00, 0x29, 0xC0,
+0xCB, 0xE7, 0x80, 0x73,
+0x33, 0xFF, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd3[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xEC, 0xD2, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd4[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xB3, 0x04, 0x9F, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd5[] = {
+0x04, 0x00, 0x29, 0xC0,
+0xB2, 0x16, 0x1E, 0x10,
+ };
+
+
+static char ssd2080m_720p_video_on_cmd6[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xB4, 0x00, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd7[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xC1, 0x04, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd8[] = {
+0x04, 0x00, 0x29, 0xC0,
+0xC2, 0xBE, 0x00, 0x58,
+ };
+
+
+static char ssd2080m_720p_video_on_cmd9[] = {
+0x09, 0x00, 0x29, 0xC0,
+0xC3, 0x01, 0x22, 0x11,
+0x21, 0x0E, 0x80, 0x80,
+0x24, 0xFF, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd10[] = {
+0x08, 0x00, 0x29, 0xC0,
+0xB6, 0x09, 0x16, 0x42,
+0x01, 0x13, 0x00, 0x00,
+ };
+
+
+static char ssd2080m_720p_video_on_cmd11[] = {
+0x04, 0x00, 0x29, 0xC0,
+0xB7, 0x24, 0x26, 0x43,
+ };
+
+
+static char ssd2080m_720p_video_on_cmd12[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xB8, 0x16, 0x08, 0x25,
+0x44, 0x08, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd13[] = {
+0x09, 0x00, 0x29, 0xC0,
+0xB9, 0x06, 0x08, 0x07,
+0x09, 0x00, 0x00, 0x00,
+0x00, 0xFF, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd14[] = {
+0x09, 0x00, 0x29, 0xC0,
+0xBA, 0x0E, 0x10, 0x0A,
+0x0C, 0x16, 0x05, 0x00,
+0x00, 0xFF, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd15[] = {
+0x09, 0x00, 0x29, 0xC0,
+0xBB, 0xA1, 0xA1, 0xA1,
+0xA1, 0x00, 0x00, 0x00,
+0x00, 0xFF, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd16[] = {
+0x09, 0x00, 0x29, 0xC0,
+0xBC, 0x0F, 0x11, 0x0B,
+0x0D, 0x16, 0x05, 0x00,
+0x00, 0xFF, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd17[] = {
+0x09, 0x00, 0x29, 0xC0,
+0xBD, 0xA1, 0xA1, 0xA1,
+0xA1, 0x00, 0x00, 0x00,
+0x00, 0xFF, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd18[] = {
+0x04, 0x00, 0x29, 0xC0,
+0xE6, 0xFF, 0xFF, 0x0F,
+ };
+
+
+static char ssd2080m_720p_video_on_cmd19[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xC7, 0x3F, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd20[] = {
+0x07, 0x00, 0x29, 0xC0,
+0xB5, 0x47, 0x00, 0x00,
+0x08, 0x00, 0x01, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd21[] = {
+0x08, 0x00, 0x29, 0xC0,
+0xC4, 0xDF, 0x72, 0x12,
+0x12, 0x66, 0xE3, 0x99,
+ };
+
+
+static char ssd2080m_720p_video_on_cmd22[] = {
+0x07, 0x00, 0x29, 0xC0,
+0xD0, 0x0A, 0x00, 0x0D,
+0x15, 0x1F, 0x2E, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd23[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xD1, 0x28, 0x27, 0x14,
+0x02, 0x01, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd24[] = {
+0x07, 0x00, 0x29, 0xC0,
+0xD2, 0x0A, 0x00, 0x0D,
+0x15, 0x1F, 0x2E, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd25[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xD3, 0x28, 0x27, 0x14,
+0x02, 0x01, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd26[] = {
+0x07, 0x00, 0x29, 0xC0,
+0xD4, 0x0A, 0x00, 0x0D,
+0x15, 0x1F, 0x2E, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd27[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xD5, 0x28, 0x27, 0x14,
+0x02, 0x01, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd28[] = {
+0x07, 0x00, 0x29, 0xC0,
+0xD6, 0x0A, 0x00, 0x0D,
+0x15, 0x1F, 0x2E, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd29[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xD7, 0x28, 0x27, 0x14,
+0x02, 0x01, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd30[] = {
+0x07, 0x00, 0x29, 0xC0,
+0xD8, 0x0A, 0x00, 0x0D,
+0x15, 0x1F, 0x2E, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd31[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xD9, 0x28, 0x27, 0x14,
+0x02, 0x01, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd32[] = {
+0x07, 0x00, 0x29, 0xC0,
+0xDA, 0x0A, 0x00, 0x0D,
+0x15, 0x1F, 0x2E, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd33[] = {
+0x06, 0x00, 0x29, 0xC0,
+0xDB, 0x28, 0x27, 0x14,
+0x02, 0x01, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd34[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xCC, 0x10, 0x00, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd35[] = {
+0x04, 0x00, 0x29, 0xC0,
+0xCE, 0x4E, 0x55, 0xA5,
+ };
+
+
+static char ssd2080m_720p_video_on_cmd36[] = {
+0x04, 0x00, 0x29, 0xC0,
+0xE0, 0x01, 0x02, 0x02,
+ };
+
+
+static char ssd2080m_720p_video_on_cmd37[] = {
+0x05, 0x00, 0x29, 0xC0,
+0xF6, 0x00, 0x00, 0x00,
+0x00, 0xFF, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd38[] = {
+0x05, 0x00, 0x29, 0xC0,
+0xF7, 0x00, 0x00, 0x00,
+0x00, 0xFF, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd39[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xE1, 0x90, 0x00, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd40[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xDE, 0x95, 0xCF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd41[] = {
+0x02, 0x00, 0x29, 0xC0,
+0xCF, 0x46, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd42[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xC5, 0x77, 0x47, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd43[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xED, 0x00, 0x20, 0xFF, };
+
+
+static char ssd2080m_720p_video_on_cmd44[] = {
+0x11, 0x00, 0x05, 0x80 };
+
+
+static char ssd2080m_720p_video_on_cmd45[] = {
+0x29, 0x00, 0x05, 0x80 };
+
+
+static char ssd2080m_720p_video_on_cmd46[] = {
+0x53, 0x2c, 0x15, 0x80 };
+
+
+
+
+static struct mipi_dsi_cmd ssd2080m_720p_video_on_command[] = {
+{ 0x4 , ssd2080m_720p_video_on_cmd0},
+{ 0xc , ssd2080m_720p_video_on_cmd1},
+{ 0xc , ssd2080m_720p_video_on_cmd2},
+{ 0x8 , ssd2080m_720p_video_on_cmd3},
+{ 0x8 , ssd2080m_720p_video_on_cmd4},
+{ 0x8 , ssd2080m_720p_video_on_cmd5},
+{ 0x8 , ssd2080m_720p_video_on_cmd6},
+{ 0x8 , ssd2080m_720p_video_on_cmd7},
+{ 0x8 , ssd2080m_720p_video_on_cmd8},
+{ 0x10 , ssd2080m_720p_video_on_cmd9},
+{ 0xc , ssd2080m_720p_video_on_cmd10},
+{ 0x8 , ssd2080m_720p_video_on_cmd11},
+{ 0xc , ssd2080m_720p_video_on_cmd12},
+{ 0x10 , ssd2080m_720p_video_on_cmd13},
+{ 0x10 , ssd2080m_720p_video_on_cmd14},
+{ 0x10 , ssd2080m_720p_video_on_cmd15},
+{ 0x10 , ssd2080m_720p_video_on_cmd16},
+{ 0x10 , ssd2080m_720p_video_on_cmd17},
+{ 0x8 , ssd2080m_720p_video_on_cmd18},
+{ 0x8 , ssd2080m_720p_video_on_cmd19},
+{ 0xc , ssd2080m_720p_video_on_cmd20},
+{ 0xc , ssd2080m_720p_video_on_cmd21},
+{ 0xc , ssd2080m_720p_video_on_cmd22},
+{ 0xc , ssd2080m_720p_video_on_cmd23},
+{ 0xc , ssd2080m_720p_video_on_cmd24},
+{ 0xc , ssd2080m_720p_video_on_cmd25},
+{ 0xc , ssd2080m_720p_video_on_cmd26},
+{ 0xc , ssd2080m_720p_video_on_cmd27},
+{ 0xc , ssd2080m_720p_video_on_cmd28},
+{ 0xc , ssd2080m_720p_video_on_cmd29},
+{ 0xc , ssd2080m_720p_video_on_cmd30},
+{ 0xc , ssd2080m_720p_video_on_cmd31},
+{ 0xc , ssd2080m_720p_video_on_cmd32},
+{ 0xc , ssd2080m_720p_video_on_cmd33},
+{ 0x8 , ssd2080m_720p_video_on_cmd34},
+{ 0x8 , ssd2080m_720p_video_on_cmd35},
+{ 0x8 , ssd2080m_720p_video_on_cmd36},
+{ 0xc , ssd2080m_720p_video_on_cmd37},
+{ 0xc , ssd2080m_720p_video_on_cmd38},
+{ 0x8 , ssd2080m_720p_video_on_cmd39},
+{ 0x8 , ssd2080m_720p_video_on_cmd40},
+{ 0x8 , ssd2080m_720p_video_on_cmd41},
+{ 0x8 , ssd2080m_720p_video_on_cmd42},
+{ 0x8 , ssd2080m_720p_video_on_cmd43},
+{ 0x4 , ssd2080m_720p_video_on_cmd44},
+{ 0x4 , ssd2080m_720p_video_on_cmd45},
+{ 0x4 , ssd2080m_720p_video_on_cmd46}
+};
+#define SSD2080M_720P_VIDEO_ON_COMMAND 47
+
+
+static char ssd2080m_720p_videooff_cmd0[] = {
+0x10, 0x00, 0x05, 0x80 };
+
+
+static char ssd2080m_720p_videooff_cmd1[] = {
+0x53, 0x00, 0x05, 0x80 };
+
+
+static char ssd2080m_720p_videooff_cmd2[] = {
+0xc2, 0x00, 0x05, 0x80 };
+
+
+static char ssd2080m_720p_videooff_cmd3[] = {
+0x02, 0x00, 0x39, 0xC0,
+0xcf, 0x40, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_videooff_cmd4[] = {
+0xde, 0x84, 0x00, 0x05, 0x80 };
+
+
+static char ssd2080m_720p_videooff_cmd5[] = {
+0x02, 0x00, 0x39, 0xC0,
+0xcb, 0x22, 0xFF, 0xFF, };
+
+
+static char ssd2080m_720p_videooff_cmd6[] = {
+0xc3, 0x00, 0x05, 0x80 };
+
+
+
+
+static struct mipi_dsi_cmd ssd2080m_720p_video_off_command[] = {
+{ 0x4 , ssd2080m_720p_videooff_cmd0},
+{ 0x4 , ssd2080m_720p_videooff_cmd1},
+{ 0x4 , ssd2080m_720p_videooff_cmd2},
+{ 0x8 , ssd2080m_720p_videooff_cmd3},
+{ 0x4 , ssd2080m_720p_videooff_cmd4},
+{ 0x8 , ssd2080m_720p_videooff_cmd5},
+{ 0x4 , ssd2080m_720p_videooff_cmd6}
+};
+#define SSD2080M_720P_VIDEO_OFF_COMMAND 7
+
+
+static struct command_state ssd2080m_720p_video_state = {
+ 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct commandpanel_info ssd2080m_720p_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct videopanel_info ssd2080m_720p_video_video_panel = {
+ 1, 0, 0, 0, 1, 0, 2, 0, 0x8
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane Configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct lane_configuration ssd2080m_720p_video_lane_config = {
+ 4, 0, 1, 1, 1, 1
+};
+
+
+/*---------------------------------------------------------------------------*/
+/* Panel Timing */
+/*---------------------------------------------------------------------------*/
+static const uint32_t ssd2080m_720p_video_timings[] = {
+ 0xA8, 0x1F, 0x17, 0x00, 0x2F, 0x2D, 0x1C, 0x21, 0x29, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing ssd2080m_720p_video_timing_info = {
+ 0, 4, 0x20, 0x2F
+};
+
+static struct panel_reset_sequence ssd2080m_720p_video_panel_reset_seq = {
+{ 1, 0, 1, }, { 20, 20, 20, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight Settings */
+/*---------------------------------------------------------------------------*/
+
+static struct backlight ssd2080m_720p_video_backlight = {
+ 1, 1, 4095, 100, 1, "bl_ctrl_wled"
+};
+
+
+#endif /*_PANEL_SSD2080M_720P_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_toshiba_720p_video.h b/dev/gcdb/display/include/panel_toshiba_720p_video.h
index 4c09f45..312aade 100755
--- a/dev/gcdb/display/include/panel_toshiba_720p_video.h
+++ b/dev/gcdb/display/include/panel_toshiba_720p_video.h
@@ -332,6 +332,10 @@
0x0, 0x04, 0x04, 0x1b
};
+static struct panel_reset_sequence toshiba_720p_video_panel_reset_seq = {
+{ 1, 0, 1, }, { 20, 200, 20, }, 2
+};
+
/*---------------------------------------------------------------------------*/
/* Backlight Settings */
/*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_truly_wvga_cmd.h b/dev/gcdb/display/include/panel_truly_wvga_cmd.h
new file mode 100644
index 0000000..e088b8d
--- /dev/null
+++ b/dev/gcdb/display/include/panel_truly_wvga_cmd.h
@@ -0,0 +1,320 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PANEL_TRULY_WVGA_CMD_H_
+
+#define _PANEL_TRULY_WVGA_CMD_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct panel_config truly_wvga_cmd_panel_data = {
+ "qcom,mdss_dsi_truly_wvga_cmd", "dsi:0:", "qcom,mdss-dsi-panel",
+ 11, 1, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution truly_wvga_cmd_panel_res = {
+ 480, 800, 160, 40, 8, 0, 12, 10, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Color Information */
+/*---------------------------------------------------------------------------*/
+static struct color_info truly_wvga_cmd_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Command information */
+/*---------------------------------------------------------------------------*/
+static char truly_wvga_cmd_on_cmd0[] = {
+0x01, 0x00, 0x05, 0x80 };
+
+
+static char truly_wvga_cmd_on_cmd1[] = {
+0xb0, 0x04, 0x23, 0x80 };
+
+
+static char truly_wvga_cmd_on_cmd2[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xb3, 0x02, 0x00, 0xFF, };
+
+
+static char truly_wvga_cmd_on_cmd3[] = {
+0xbd, 0x00, 0x23, 0x80 };
+
+
+static char truly_wvga_cmd_on_cmd4[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xc0, 0x18, 0x66, 0xFF, };
+
+
+static char truly_wvga_cmd_on_cmd5[] = {
+0x10, 0x00, 0x29, 0xC0,
+0xc1, 0x23, 0x31, 0x99,
+0x21, 0x20, 0x00, 0x30,
+0x28, 0x0c, 0x0c, 0x00,
+0x00, 0x00, 0x21, 0x01,
+ };
+
+
+static char truly_wvga_cmd_on_cmd6[] = {
+0x07, 0x00, 0x29, 0xC0,
+0xc2, 0x00, 0x06, 0x06,
+0x01, 0x03, 0x00, 0xFF, };
+
+
+static char truly_wvga_cmd_on_cmd7[] = {
+0x19, 0x00, 0x29, 0xC0,
+0xc8, 0x04, 0x10, 0x18,
+0x20, 0x2e, 0x46, 0x3c,
+0x28, 0x1f, 0x18, 0x10,
+0x04, 0x04, 0x10, 0x18,
+0x20, 0x2e, 0x46, 0x3c,
+0x28, 0x1f, 0x18, 0x10,
+0x04, 0xFF, 0xFF, 0xFF, };
+
+
+static char truly_wvga_cmd_on_cmd8[] = {
+0x19, 0x00, 0x29, 0xC0,
+0xc9, 0x04, 0x10, 0x18,
+0x20, 0x2e, 0x46, 0x3c,
+0x28, 0x1f, 0x18, 0x10,
+0x04, 0x04, 0x10, 0x18,
+0x20, 0x2e, 0x46, 0x3c,
+0x28, 0x1f, 0x18, 0x10,
+0x04, 0xFF, 0xFF, 0xFF, };
+
+
+static char truly_wvga_cmd_on_cmd9[] = {
+0x19, 0x00, 0x29, 0xC0,
+0xca, 0x04, 0x10, 0x18,
+0x20, 0x2e, 0x46, 0x3c,
+0x28, 0x1f, 0x18, 0x10,
+0x04, 0x04, 0x10, 0x18,
+0x20, 0x2e, 0x46, 0x3c,
+0x28, 0x1f, 0x18, 0x10,
+0x04, 0xFF, 0xFF, 0xFF, };
+
+
+static char truly_wvga_cmd_on_cmd10[] = {
+0x11, 0x00, 0x29, 0xC0,
+0xd0, 0x29, 0x03, 0xce,
+0xa6, 0x00, 0x43, 0x20,
+0x10, 0x01, 0x00, 0x01,
+0x01, 0x00, 0x03, 0x01,
+0x00, 0xFF, 0xFF, 0xFF, };
+
+
+static char truly_wvga_cmd_on_cmd11[] = {
+0x08, 0x00, 0x29, 0xC0,
+0xd1, 0x18, 0x0C, 0x23,
+0x03, 0x75, 0x02, 0x50,
+ };
+
+
+static char truly_wvga_cmd_on_cmd12[] = {
+0xd3, 0x11, 0x23, 0x80 };
+
+
+static char truly_wvga_cmd_on_cmd13[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xd5, 0x2a, 0x2a, 0xFF, };
+
+
+static char truly_wvga_cmd_on_cmd14[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xde, 0x01, 0x51, 0xFF, };
+
+
+static char truly_wvga_cmd_on_cmd15[] = {
+0xe6, 0x51, 0x23, 0x80 };
+
+
+static char truly_wvga_cmd_on_cmd16[] = {
+0xfa, 0x03, 0x23, 0x80 };
+
+
+static char truly_wvga_cmd_on_cmd17[] = {
+0xd6, 0x28, 0x23, 0x80 };
+
+
+static char truly_wvga_cmd_on_cmd18[] = {
+0x36, 0x41, 0x15, 0x80 };
+
+
+static char truly_wvga_cmd_on_cmd19[] = {
+0x05, 0x00, 0x39, 0xC0,
+0x2a, 0x00, 0x00, 0x01,
+0xdf, 0xFF, 0xFF, 0xFF, };
+
+
+static char truly_wvga_cmd_on_cmd20[] = {
+0x05, 0x00, 0x39, 0xC0,
+0x2b, 0x00, 0x00, 0x03,
+0x1f, 0xFF, 0xFF, 0xFF, };
+
+
+static char truly_wvga_cmd_on_cmd21[] = {
+0x35, 0x00, 0x15, 0x80 };
+
+
+static char truly_wvga_cmd_on_cmd22[] = {
+0x03, 0x00, 0x39, 0xC0,
+0x44, 0x00, 0x50, 0xFF, };
+
+
+static char truly_wvga_cmd_on_cmd23[] = {
+0x11, 0x00, 0x05, 0x80 };
+
+
+static char truly_wvga_cmd_on_cmd24[] = {
+0x29, 0x00, 0x05, 0x80 };
+
+
+
+
+static struct mipi_dsi_cmd truly_wvga_cmd_on_command[] = {
+{ 0x4 , truly_wvga_cmd_on_cmd0},
+{ 0x4 , truly_wvga_cmd_on_cmd1},
+{ 0x8 , truly_wvga_cmd_on_cmd2},
+{ 0x4 , truly_wvga_cmd_on_cmd3},
+{ 0x8 , truly_wvga_cmd_on_cmd4},
+{ 0x14 , truly_wvga_cmd_on_cmd5},
+{ 0xc , truly_wvga_cmd_on_cmd6},
+{ 0x20 , truly_wvga_cmd_on_cmd7},
+{ 0x20 , truly_wvga_cmd_on_cmd8},
+{ 0x20 , truly_wvga_cmd_on_cmd9},
+{ 0x18 , truly_wvga_cmd_on_cmd10},
+{ 0xc , truly_wvga_cmd_on_cmd11},
+{ 0x4 , truly_wvga_cmd_on_cmd12},
+{ 0x8 , truly_wvga_cmd_on_cmd13},
+{ 0x8 , truly_wvga_cmd_on_cmd14},
+{ 0x4 , truly_wvga_cmd_on_cmd15},
+{ 0x4 , truly_wvga_cmd_on_cmd16},
+{ 0x4 , truly_wvga_cmd_on_cmd17},
+{ 0x4 , truly_wvga_cmd_on_cmd18},
+{ 0xc , truly_wvga_cmd_on_cmd19},
+{ 0xc , truly_wvga_cmd_on_cmd20},
+{ 0x4 , truly_wvga_cmd_on_cmd21},
+{ 0x8 , truly_wvga_cmd_on_cmd22},
+{ 0x4 , truly_wvga_cmd_on_cmd23},
+{ 0x4 , truly_wvga_cmd_on_cmd24}
+};
+#define TRULY_WVGA_CMD_ON_COMMAND 25
+
+
+static char truly_wvga_cmdoff_cmd0[] = {
+0x28, 0x00, 0x05, 0x80 };
+
+
+static char truly_wvga_cmdoff_cmd1[] = {
+0x10, 0x00, 0x05, 0x80 };
+
+
+
+
+static struct mipi_dsi_cmd truly_wvga_cmd_off_command[] = {
+{ 0x4 , truly_wvga_cmdoff_cmd0},
+{ 0x4 , truly_wvga_cmdoff_cmd1}
+};
+#define TRULY_WVGA_CMD_OFF_COMMAND 2
+
+
+static struct command_state truly_wvga_cmd_state = {
+ 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct commandpanel_info truly_wvga_cmd_command_panel = {
+ 1, 1, 1, 0, 0, 0x2c, 0, 0, 0, 1, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct videopanel_info truly_wvga_cmd_video_panel = {
+ 0, 0, 0, 0, 1, 1, 1, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane Configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct lane_configuration truly_wvga_cmd_lane_config = {
+ 2, 0, 1, 1, 0, 0
+};
+
+
+/*---------------------------------------------------------------------------*/
+/* Panel Timing */
+/*---------------------------------------------------------------------------*/
+const uint32_t truly_wvga_cmd_timings[] = {
+ 0x5D, 0x12, 0x0C, 0x00, 0x33, 0x38, 0x10, 0x16, 0x1E, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing truly_wvga_cmd_timing_info = {
+ 2, 4, 0x04, 0x1b
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Reset Sequence */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence truly_wvga_cmd_reset_seq = {
+ { 2, 0, 2, }, { 20, 2, 20, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight Settings */
+/*---------------------------------------------------------------------------*/
+
+static struct backlight truly_wvga_cmd_backlight = {
+ 0, 1, 255, 0, 1, 0
+};
+
+
+#endif /*_PANEL_TRULY_WVGA_CMD_H_*/
diff --git a/dev/gcdb/display/include/panel_truly_wvga_video.h b/dev/gcdb/display/include/panel_truly_wvga_video.h
new file mode 100644
index 0000000..ee1ab28
--- /dev/null
+++ b/dev/gcdb/display/include/panel_truly_wvga_video.h
@@ -0,0 +1,325 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PANEL_TRULY_WVGA_VIDEO_H_
+
+#define _PANEL_TRULY_WVGA_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct panel_config truly_wvga_video_panel_data = {
+ "qcom,mdss_dsi_truly_wvga_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution truly_wvga_video_panel_res = {
+ 480, 800, 160, 40, 8, 0, 12, 10, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Color Information */
+/*---------------------------------------------------------------------------*/
+static struct color_info truly_wvga_video_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Command information */
+/*---------------------------------------------------------------------------*/
+static char truly_wvga_video_on_cmd0[] = {
+0x01, 0x00, 0x05, 0x80 };
+
+
+static char truly_wvga_video_on_cmd1[] = {
+0xb0, 0x04, 0x23, 0x80 };
+
+
+static char truly_wvga_video_on_cmd2[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xb3, 0x02, 0x00, 0xFF, };
+
+
+static char truly_wvga_video_on_cmd3[] = {
+0xbd, 0x00, 0x23, 0x80 };
+
+
+static char truly_wvga_video_on_cmd4[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xc0, 0x18, 0x66, 0xFF, };
+
+
+static char truly_wvga_video_on_cmd5[] = {
+0x10, 0x00, 0x29, 0xC0,
+0xc1, 0x23, 0x31, 0x99,
+0x21, 0x20, 0x00, 0x30,
+0x28, 0x0c, 0x0c, 0x00,
+0x00, 0x00, 0x21, 0x01,
+ };
+
+
+static char truly_wvga_video_on_cmd6[] = {
+0x07, 0x00, 0x29, 0xC0,
+0xc2, 0x00, 0x06, 0x06,
+0x01, 0x03, 0x00, 0xFF, };
+
+
+static char truly_wvga_video_on_cmd7[] = {
+0x19, 0x00, 0x29, 0xC0,
+0xc8, 0x04, 0x10, 0x18,
+0x20, 0x2e, 0x46, 0x3c,
+0x28, 0x1f, 0x18, 0x10,
+0x04, 0x04, 0x10, 0x18,
+0x20, 0x2e, 0x46, 0x3c,
+0x28, 0x1f, 0x18, 0x10,
+0x04, 0xFF, 0xFF, 0xFF, };
+
+
+static char truly_wvga_video_on_cmd8[] = {
+0x19, 0x00, 0x29, 0xC0,
+0xc9, 0x04, 0x10, 0x18,
+0x20, 0x2e, 0x46, 0x3c,
+0x28, 0x1f, 0x18, 0x10,
+0x04, 0x04, 0x10, 0x18,
+0x20, 0x2e, 0x46, 0x3c,
+0x28, 0x1f, 0x18, 0x10,
+0x04, 0xFF, 0xFF, 0xFF, };
+
+
+static char truly_wvga_video_on_cmd9[] = {
+0x19, 0x00, 0x29, 0xC0,
+0xca, 0x04, 0x10, 0x18,
+0x20, 0x2e, 0x46, 0x3c,
+0x28, 0x1f, 0x18, 0x10,
+0x04, 0x04, 0x10, 0x18,
+0x20, 0x2e, 0x46, 0x3c,
+0x28, 0x1f, 0x18, 0x10,
+0x04, 0xFF, 0xFF, 0xFF, };
+
+
+static char truly_wvga_video_on_cmd10[] = {
+0x11, 0x00, 0x29, 0xC0,
+0xd0, 0x29, 0x03, 0xce,
+0xa6, 0x00, 0x43, 0x20,
+0x10, 0x01, 0x00, 0x01,
+0x01, 0x00, 0x03, 0x01,
+0x00, 0xFF, 0xFF, 0xFF, };
+
+
+static char truly_wvga_video_on_cmd11[] = {
+0x08, 0x00, 0x29, 0xC0,
+0xd1, 0x18, 0x0C, 0x23,
+0x03, 0x75, 0x02, 0x50,
+ };
+
+
+static char truly_wvga_video_on_cmd12[] = {
+0xd3, 0x11, 0x23, 0x80 };
+
+
+static char truly_wvga_video_on_cmd13[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xd5, 0x2a, 0x2a, 0xFF, };
+
+
+static char truly_wvga_video_on_cmd14[] = {
+0x03, 0x00, 0x29, 0xC0,
+0xde, 0x01, 0x51, 0xFF, };
+
+
+static char truly_wvga_video_on_cmd15[] = {
+0xe6, 0x51, 0x23, 0x80 };
+
+
+static char truly_wvga_video_on_cmd16[] = {
+0xfa, 0x03, 0x23, 0x80 };
+
+
+static char truly_wvga_video_on_cmd17[] = {
+0xd6, 0x28, 0x23, 0x80 };
+
+
+static char truly_wvga_video_on_cmd18[] = {
+0x05, 0x00, 0x39, 0xC0,
+0x2a, 0x00, 0x00, 0x01,
+0xdf, 0xFF, 0xFF, 0xFF, };
+
+
+static char truly_wvga_video_on_cmd19[] = {
+0x05, 0x00, 0x39, 0xC0,
+0x2b, 0x00, 0x00, 0x03,
+0x1f, 0xFF, 0xFF, 0xFF, };
+
+
+static char truly_wvga_video_on_cmd20[] = {
+0x35, 0x00, 0x15, 0x80 };
+
+
+static char truly_wvga_video_on_cmd21[] = {
+0x03, 0x00, 0x39, 0xC0,
+0x44, 0x00, 0x50, 0xFF, };
+
+
+static char truly_wvga_video_on_cmd22[] = {
+0x36, 0xc1, 0x15, 0x80 };
+
+
+static char truly_wvga_video_on_cmd23[] = {
+0x3a, 0x77, 0x15, 0x80 };
+
+
+static char truly_wvga_video_on_cmd24[] = {
+0x11, 0x00, 0x05, 0x80 };
+
+
+static char truly_wvga_video_on_cmd25[] = {
+0x29, 0x00, 0x05, 0x80 };
+
+
+
+
+static struct mipi_dsi_cmd truly_wvga_video_on_command[] = {
+{ 0x4 , truly_wvga_video_on_cmd0},
+{ 0x4 , truly_wvga_video_on_cmd1},
+{ 0x8 , truly_wvga_video_on_cmd2},
+{ 0x4 , truly_wvga_video_on_cmd3},
+{ 0x8 , truly_wvga_video_on_cmd4},
+{ 0x14 , truly_wvga_video_on_cmd5},
+{ 0xc , truly_wvga_video_on_cmd6},
+{ 0x20 , truly_wvga_video_on_cmd7},
+{ 0x20 , truly_wvga_video_on_cmd8},
+{ 0x20 , truly_wvga_video_on_cmd9},
+{ 0x18 , truly_wvga_video_on_cmd10},
+{ 0xc , truly_wvga_video_on_cmd11},
+{ 0x4 , truly_wvga_video_on_cmd12},
+{ 0x8 , truly_wvga_video_on_cmd13},
+{ 0x8 , truly_wvga_video_on_cmd14},
+{ 0x4 , truly_wvga_video_on_cmd15},
+{ 0x4 , truly_wvga_video_on_cmd16},
+{ 0x4 , truly_wvga_video_on_cmd17},
+{ 0xc , truly_wvga_video_on_cmd18},
+{ 0xc , truly_wvga_video_on_cmd19},
+{ 0x4 , truly_wvga_video_on_cmd20},
+{ 0x8 , truly_wvga_video_on_cmd21},
+{ 0x4 , truly_wvga_video_on_cmd22},
+{ 0x4 , truly_wvga_video_on_cmd23},
+{ 0x4 , truly_wvga_video_on_cmd24},
+{ 0x4 , truly_wvga_video_on_cmd25}
+};
+#define TRULY_WVGA_VIDEO_ON_COMMAND 26
+
+
+static char truly_wvga_videooff_cmd0[] = {
+0x28, 0x00, 0x05, 0x80 };
+
+
+static char truly_wvga_videooff_cmd1[] = {
+0x10, 0x00, 0x05, 0x80 };
+
+
+
+
+static struct mipi_dsi_cmd truly_wvga_video_off_command[] = {
+{ 0x4 , truly_wvga_videooff_cmd0},
+{ 0x4 , truly_wvga_videooff_cmd1}
+};
+#define TRULY_WVGA_VIDEO_OFF_COMMAND 2
+
+
+static struct command_state truly_wvga_video_state = {
+ 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct commandpanel_info truly_wvga_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+
+static struct videopanel_info truly_wvga_video_video_panel = {
+ 0, 0, 0, 0, 1, 1, 1, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane Configuration */
+/*---------------------------------------------------------------------------*/
+
+static struct lane_configuration truly_wvga_video_lane_config = {
+ 2, 0, 1, 1, 0, 0
+};
+
+
+/*---------------------------------------------------------------------------*/
+/* Panel Timing */
+/*---------------------------------------------------------------------------*/
+const uint32_t truly_wvga_video_timings[] = {
+ 0x5D, 0x12, 0x0C, 0x00, 0x33, 0x38, 0x10, 0x16, 0x1E, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing truly_wvga_video_timing_info = {
+ 0, 4, 0x04, 0x1b
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Reset Sequence */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence truly_wvga_video_reset_seq = {
+ { 2, 0, 2, }, { 20, 2, 20, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight Settings */
+/*---------------------------------------------------------------------------*/
+
+static struct backlight truly_wvga_video_backlight = {
+ 0, 1, 255, 0, 1, 0
+};
+
+
+#endif /*_PANEL_TRULY_WVGA_VIDEO_H_*/
diff --git a/dev/gcdb/display/panel_display.c b/dev/gcdb/display/panel_display.c
index da69f20..21936f5 100644
--- a/dev/gcdb/display/panel_display.c
+++ b/dev/gcdb/display/panel_display.c
@@ -112,6 +112,7 @@
pinfo->mipi.stream = pstruct->paneldata->dsi_stream;
pinfo->mipi.dual_dsi = (pstruct->paneldata->panel_operating_mode
& 0x1);
+ pinfo->mipi.mode_gpio_state = pstruct->paneldata->mode_gpio_state;
pinfo->mipi.bitclock = pstruct->paneldata->panel_bitclock_freq;
/* Video Panel configuration */
diff --git a/dev/gcdb/display/panel_display.h b/dev/gcdb/display/panel_display.h
index 195a82c..e141a0c 100755
--- a/dev/gcdb/display/panel_display.h
+++ b/dev/gcdb/display/panel_display.h
@@ -43,15 +43,16 @@
/* struct definition */
/*---------------------------------------------------------------------------*/
typedef struct panel_struct{
- struct panel_config *paneldata;
- struct panel_resolution *panelres;
- struct color_info *color;
- struct videopanel_info *videopanel;
- struct commandpanel_info *commandpanel;
- struct command_state *state;
- struct lane_configuration *laneconfig;
- struct panel_timing *paneltiminginfo;
- struct backlight *backlightinfo;
+ struct panel_config *paneldata;
+ struct panel_resolution *panelres;
+ struct color_info *color;
+ struct videopanel_info *videopanel;
+ struct commandpanel_info *commandpanel;
+ struct command_state *state;
+ struct lane_configuration *laneconfig;
+ struct panel_timing *paneltiminginfo;
+ struct panel_reset_sequence *panelresetseq;
+ struct backlight *backlightinfo;
};
diff --git a/dev/gcdb/display/rules.mk b/dev/gcdb/display/rules.mk
index 438c6c7..71e35f2 100755
--- a/dev/gcdb/display/rules.mk
+++ b/dev/gcdb/display/rules.mk
@@ -5,5 +5,4 @@
OBJS += \
$(LOCAL_DIR)/gcdb_display.o \
$(LOCAL_DIR)/panel_display.o \
- $(LOCAL_DIR)/oem_panel.o \
$(LOCAL_DIR)/gcdb_autopll.o
diff --git a/dev/panel/msm/mipi_nt35590_video_720p.c b/dev/panel/msm/mipi_nt35590_video_720p.c
index af74b43..9e53a8d 100644
--- a/dev/panel/msm/mipi_nt35590_video_720p.c
+++ b/dev/panel/msm/mipi_nt35590_video_720p.c
@@ -2425,22 +2425,22 @@
static struct mdss_dsi_phy_ctrl dsi_video_mode_phy_db = {
/* 720x1280, RGB888, 4 Lane 60 fps video mode */
/* regulator */
- {0x07, 0x09, 0x03, 0x00, 0x20, 0x00, 0x01},
+ {0x02, 0x08, 0x05, 0x00, 0x20, 0x03},
/* timing */
- {0x7d, 0x25, 0x1d, 0x00, 0x37, 0x33, 0x22, 0x27,
- 0x1e, 0x03, 0x04, 0x00},
+ {0x86, 0x1E, 0x14, 0x00, 0x43, 0x4D,
+ 0x19, 0x21, 0x30, 0x03, 0x04, 0x00},
/* phy ctrl */
- {0x5f, 0x00, 0x00, 0x10},
+ {0x7f, 0x00, 0x00, 0x00},
/* strength */
{0xff, 0x06},
/* bist control */
- {0x00, 0x00, 0xb1, 0xff, 0x00, 0x00},
+ {0x03, 0x03, 0x00, 0x00, 0x0f, 0x00},
/* lanes config */
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
- 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x01, 0x97,
- 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x97,
- 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x01, 0x97,
- 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xbb},
+ {0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+ 0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+ 0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+ 0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+ 0x40, 0x67, 0x00, 0x00, 0x00, 0x01, 0x88, 0x00, 0x00},
};
void mipi_nt35590_video_720p_init(struct msm_panel_info *pinfo)
diff --git a/dev/panel/msm/rules.mk b/dev/panel/msm/rules.mk
index ddeb6dd..cfce68d 100644
--- a/dev/panel/msm/rules.mk
+++ b/dev/panel/msm/rules.mk
@@ -38,5 +38,6 @@
$(LOCAL_DIR)/mipi_truly_video_wvga.o \
$(LOCAL_DIR)/mipi_truly_cmd_wvga.o \
$(LOCAL_DIR)/mipi_hx8379a_video_wvga.o \
- $(LOCAL_DIR)/mipi_otm8018b_video_fwvga.o
+ $(LOCAL_DIR)/mipi_otm8018b_video_fwvga.o \
+ $(LOCAL_DIR)/mipi_nt35590_video_720p.o
endif
diff --git a/dev/pmic/pm8x41/include/pm8x41.h b/dev/pmic/pm8x41/include/pm8x41.h
index 236aed7..dcd4549 100644
--- a/dev/pmic/pm8x41/include/pm8x41.h
+++ b/dev/pmic/pm8x41/include/pm8x41.h
@@ -203,4 +203,5 @@
void pm8x41_enable_mpp(struct pm8x41_mpp *mpp, enum mpp_en_ctl enable);
uint8_t pm8x41_get_is_cold_boot();
void pm8x41_diff_clock_ctrl(uint8_t enable);
+void pm8x41_clear_pmic_watchdog(void);
#endif
diff --git a/dev/pmic/pm8x41/include/pm8x41_hw.h b/dev/pmic/pm8x41/include/pm8x41_hw.h
index c8c83ce..9239ce7 100644
--- a/dev/pmic/pm8x41/include/pm8x41_hw.h
+++ b/dev/pmic/pm8x41/include/pm8x41_hw.h
@@ -72,6 +72,7 @@
#define PON_RESIN_N_RESET_S2_CTL 0x846 /* bit 7: S2_RESET_EN, bit 0:3 : RESET_TYPE */
#define PON_PS_HOLD_RESET_CTL 0x85A /* bit 7: S2_RESET_EN, bit 0:3 : RESET_TYPE */
#define PON_PS_HOLD_RESET_CTL2 0x85B
+#define PMIC_WD_RESET_S2_CTL2 0x857
/* PON Peripheral register bit values */
#define RESIN_ON_INT_BIT 1
diff --git a/dev/pmic/pm8x41/include/pm8x41_wled.h b/dev/pmic/pm8x41/include/pm8x41_wled.h
index 0ef9091..300c0b9 100644
--- a/dev/pmic/pm8x41/include/pm8x41_wled.h
+++ b/dev/pmic/pm8x41/include/pm8x41_wled.h
@@ -42,6 +42,7 @@
#define PM_WLED_LED3_BRIGHTNESS_MSB PM_WLED_CTNL_REG(0x45)
#define PM_WLED_ENABLE PM_WLED_CTNL_REG(0x46)
#define PM_WLED_ILED_SYNC_BIT PM_WLED_CTNL_REG(0x47)
+#define PM_WLED_FDBCK_CONTROL PM_WLED_CTNL_REG(0x48)
#define PM_WLED_MODULATION_SCHEME PM_WLED_CTNL_REG(0x4A)
#define PM_WLED_MAX_DUTY_CYCLE PM_WLED_CTNL_REG(0x4B)
#define PM_WLED_OVP PM_WLED_CTNL_REG(0x4D)
@@ -65,7 +66,8 @@
uint16_t led3_brightness;
uint8_t max_duty_cycle;
uint8_t ovp;
- uint8_t full_current_scale;;
+ uint8_t full_current_scale;
+ uint8_t fdbck;
};
void pm8x41_wled_config(struct pm8x41_wled_data *wled_ctrl);
diff --git a/dev/pmic/pm8x41/pm8x41.c b/dev/pmic/pm8x41/pm8x41.c
index 915cf52..91f1daa 100644
--- a/dev/pmic/pm8x41/pm8x41.c
+++ b/dev/pmic/pm8x41/pm8x41.c
@@ -401,3 +401,8 @@
REG_WRITE(DIFF_CLK1_EN_CTL, reg);
}
+
+void pm8x41_clear_pmic_watchdog(void)
+{
+ pm8x41_reg_write(PMIC_WD_RESET_S2_CTL2, 0x0);
+}
diff --git a/dev/pmic/pm8x41/pm8x41_adc.c b/dev/pmic/pm8x41/pm8x41_adc.c
index 6e4aa29..a4b3a82 100644
--- a/dev/pmic/pm8x41/pm8x41_adc.c
+++ b/dev/pmic/pm8x41/pm8x41_adc.c
@@ -242,7 +242,7 @@
calib_result = vadc_calibrate(result, adc->calib_type);
- dprintf(SPEW, "Result: Raw %u\tCalibrated:%llu\n", result, calib_result);
+ dprintf(SPEW, "Result: Raw %u\tCalibrated:%u\n", result, calib_result);
return calib_result;
}
diff --git a/dev/pmic/pm8x41/pm8x41_wled.c b/dev/pmic/pm8x41/pm8x41_wled.c
index 8c37e12..e879f1f 100644
--- a/dev/pmic/pm8x41/pm8x41_wled.c
+++ b/dev/pmic/pm8x41/pm8x41_wled.c
@@ -72,6 +72,7 @@
wled_reg_write(LEDn_FULL_SCALE_CURRENT(2), wled_ctrl->full_current_scale);
wled_reg_write(LEDn_FULL_SCALE_CURRENT(3), wled_ctrl->full_current_scale);
+ wled_reg_write(PM_WLED_FDBCK_CONTROL, wled_ctrl->fdbck);
dprintf(SPEW, "WLED Configuration Success.\n");
}
@@ -98,8 +99,8 @@
if (enable) {
value = PM_WLED_LED1_ILED_SYNC_MASK |
- PM_WLED_LED1_ILED_SYNC_MASK |
- PM_WLED_LED1_ILED_SYNC_MASK;
+ PM_WLED_LED2_ILED_SYNC_MASK |
+ PM_WLED_LED3_ILED_SYNC_MASK;
}
wled_reg_write(PM_WLED_ILED_SYNC_BIT, value);
diff --git a/include/dev/fbcon.h b/include/dev/fbcon.h
index 7ab5ca1..a817675 100644
--- a/include/dev/fbcon.h
+++ b/include/dev/fbcon.h
@@ -31,6 +31,25 @@
#ifndef __DEV_FBCON_H
#define __DEV_FBCON_H
+#include <stdint.h>
+#define LOGO_IMG_OFFSET (12*1024*1024)
+#define LOGO_IMG_MAGIC "SPLASH!!"
+#define LOGO_IMG_MAGIC_SIZE sizeof(LOGO_IMG_MAGIC) - 1
+
+
+struct logo_img_header {
+ unsigned char magic[LOGO_IMG_MAGIC_SIZE]; // "SPLASH!!"
+ uint32_t width; // logo's width, little endian
+ uint32_t height; // logo's height, little endian
+ uint32_t offset;
+ unsigned char reserved[512-20];
+};
+
+struct fbimage {
+ struct logo_img_header header;
+ void *image;
+};
+
#define FB_FORMAT_RGB565 0
#define FB_FORMAT_RGB666 1
#define FB_FORMAT_RGB666_LOOSE 2
diff --git a/platform/apq8084/acpuclock.c b/platform/apq8084/acpuclock.c
index 93921fb..8c3f841 100644
--- a/platform/apq8084/acpuclock.c
+++ b/platform/apq8084/acpuclock.c
@@ -32,28 +32,148 @@
#include <mmc.h>
#include <clock.h>
#include <platform/clock.h>
+#include <platform/iomap.h>
void hsusb_clock_init(void)
{
+ int ret;
+ struct clk *iclk, *cclk;
+
+ ret = clk_get_set_enable("usb_iface_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_iface_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb_core_clk", 75000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_core_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Wait for the clocks to be stable since we are disabling soon after. */
+ mdelay(1);
+
+ iclk = clk_get("usb_iface_clk");
+ cclk = clk_get("usb_core_clk");
+
+ clk_disable(iclk);
+ clk_disable(cclk);
+
+ /* Wait for the clock disable to complete. */
+ mdelay(1);
+
+ /* Start the block reset for usb */
+ writel(1, USB_HS_BCR);
+
+ /* Wait for reset to complete. */
+ mdelay(1);
+
+ /* Take usb block out of reset */
+ writel(0, USB_HS_BCR);
+
+ /* Wait for the block to be brought out of reset. */
+ mdelay(1);
+
+ ret = clk_enable(iclk);
+
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_enable(cclk);
+
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
+ ASSERT(0);
+ }
+
}
void clock_init_mmc(uint32_t interface)
{
+ char clk_name[64];
+ int ret;
+
+ snprintf(clk_name, 64, "sdc%u_iface_clk", interface);
+
+ /* enable interface clock */
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set sdc%u_iface_clk ret = %d\n", interface, ret);
+ ASSERT(0);
+ }
}
/* Configure MMC clock */
void clock_config_mmc(uint32_t interface, uint32_t freq)
{
- /* Disalbe MCI_CLK before changing the sdcc clock */
- mmc_boot_mci_clk_disable();
+ int ret;
+ uint32_t reg;
+ char clk_name[64];
- /* Enable MCI CLK */
- mmc_boot_mci_clk_enable();
+ snprintf(clk_name, 64, "sdc%u_core_clk", interface);
+
+ if(freq == MMC_CLK_400KHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 400000, 1);
+ }
+ else if(freq == MMC_CLK_50MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 50000000, 1);
+ }
+ else if(freq == MMC_CLK_96MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 100000000, 1);
+ }
+ else if(freq == MMC_CLK_200MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 200000000, 1);
+ }
+ else
+ {
+ dprintf(CRITICAL, "sdc frequency (%u) is not supported\n", freq);
+ ASSERT(0);
+ }
+
+
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set sdc%u_core_clk ret = %d\n", interface, ret);
+ ASSERT(0);
+ }
+
}
/* Configure UART clock based on the UART block id*/
void clock_config_uart_dm(uint8_t id)
{
+ int ret;
+ char iclk[64];
+ char cclk[64];
+
+ snprintf(iclk, 64, "uart%u_iface_clk", id);
+ snprintf(cclk, 64, "uart%u_core_clk", id);
+
+ ret = clk_get_set_enable(iclk, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set uart%u_iface_clk ret = %d\n", id, ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable(cclk, 7372800, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set uart%u_core_clk ret = %d\n", id, ret);
+ ASSERT(0);
+ }
}
/* Function to asynchronously reset CE (Crypto Engine).
diff --git a/platform/apq8084/apq8084-clock.c b/platform/apq8084/apq8084-clock.c
index b40ee29..c939bad 100644
--- a/platform/apq8084/apq8084-clock.c
+++ b/platform/apq8084/apq8084-clock.c
@@ -98,11 +98,201 @@
},
};
+static struct pll_vote_clk gpll0_clk_src =
+{
+ .en_reg = (void *) APCS_GPLL_ENA_VOTE,
+ .en_mask = BIT(0),
+ .status_reg = (void *) GPLL0_STATUS,
+ .status_mask = BIT(17),
+ .parent = &cxo_clk_src.c,
+
+ .c = {
+ .rate = 600000000,
+ .dbg_name = "gpll0_clk_src",
+ .ops = &clk_ops_pll_vote,
+ },
+};
+
+/* UART Clocks */
+static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] =
+{
+ F( 3686400, gpll0, 1, 96, 15625),
+ F( 7372800, gpll0, 1, 192, 15625),
+ F(14745600, gpll0, 1, 384, 15625),
+ F(16000000, gpll0, 5, 2, 15),
+ F(19200000, cxo, 1, 0, 0),
+ F(24000000, gpll0, 5, 1, 5),
+ F(32000000, gpll0, 1, 4, 75),
+ F(40000000, gpll0, 15, 0, 0),
+ F(46400000, gpll0, 1, 29, 375),
+ F(48000000, gpll0, 12.5, 0, 0),
+ F(51200000, gpll0, 1, 32, 375),
+ F(56000000, gpll0, 1, 7, 75),
+ F(58982400, gpll0, 1, 1536, 15625),
+ F(60000000, gpll0, 10, 0, 0),
+ F_END
+};
+
+static struct rcg_clk blsp2_uart2_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) BLSP2_UART2_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP2_UART2_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP2_UART2_APPS_M,
+ .n_reg = (uint32_t *) BLSP2_UART2_APPS_N,
+ .d_reg = (uint32_t *) BLSP2_UART2_APPS_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "blsp1_uart2_apps_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_blsp2_uart2_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) BLSP2_UART2_APPS_CBCR,
+ .parent = &blsp2_uart2_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp2_uart2_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct vote_clk gcc_blsp1_ahb_clk = {
+ .cbcr_reg = (uint32_t *) BLSP1_AHB_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(17),
+
+ .c = {
+ .dbg_name = "gcc_blsp1_ahb_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+static struct vote_clk gcc_blsp2_ahb_clk = {
+ .cbcr_reg = (uint32_t *) BLSP2_AHB_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(15),
+
+ .c = {
+ .dbg_name = "gcc_blsp2_ahb_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+/* USB Clocks */
+static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] =
+{
+ F(75000000, gpll0, 8, 0, 0),
+ F_END
+};
+
+static struct rcg_clk usb_hs_system_clk_src =
+{
+ .cmd_reg = (uint32_t *) USB_HS_SYSTEM_CMD_RCGR,
+ .cfg_reg = (uint32_t *) USB_HS_SYSTEM_CFG_RCGR,
+
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_usb_hs_system_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "usb_hs_system_clk",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_usb_hs_system_clk =
+{
+ .cbcr_reg = (uint32_t *) USB_HS_SYSTEM_CBCR,
+ .parent = &usb_hs_system_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_usb_hs_system_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_usb_hs_ahb_clk =
+{
+ .cbcr_reg = (uint32_t *) USB_HS_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_usb_hs_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+/* SDCC Clocks */
+static struct clk_freq_tbl ftbl_gcc_sdcc1_2_apps_clk[] =
+{
+ F( 144000, cxo, 16, 3, 25),
+ F( 400000, cxo, 12, 1, 4),
+ F( 20000000, gpll0, 15, 1, 2),
+ F( 25000000, gpll0, 12, 1, 2),
+ F( 50000000, gpll0, 12, 0, 0),
+ F(100000000, gpll0, 6, 0, 0),
+ F(200000000, gpll0, 3, 0, 0),
+ F_END
+};
+
+static struct rcg_clk sdcc1_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) SDCC1_CMD_RCGR,
+ .cfg_reg = (uint32_t *) SDCC1_CFG_RCGR,
+ .m_reg = (uint32_t *) SDCC1_M,
+ .n_reg = (uint32_t *) SDCC1_N,
+ .d_reg = (uint32_t *) SDCC1_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "sdc1_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_sdcc1_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) SDCC1_APPS_CBCR,
+ .parent = &sdcc1_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_sdcc1_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_sdcc1_ahb_clk =
+{
+ .cbcr_reg = (uint32_t *) SDCC1_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_sdcc1_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
/* Clock lookup table */
static struct clk_lookup msm_clocks_8084[] =
{
-};
+ CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
+ CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c),
+ CLK_LOOKUP("uart7_iface_clk", gcc_blsp2_ahb_clk.c),
+ CLK_LOOKUP("uart7_core_clk", gcc_blsp2_uart2_apps_clk.c),
+
+ CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c),
+ CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c),
+};
void platform_clock_init(void)
{
diff --git a/platform/apq8084/gpio.c b/platform/apq8084/gpio.c
index 32c55f4..a976518 100644
--- a/platform/apq8084/gpio.c
+++ b/platform/apq8084/gpio.c
@@ -54,6 +54,13 @@
/* Configure gpio for blsp uart 2 */
void gpio_config_uart_dm(uint8_t id)
{
+ /* configure rx gpio */
+ gpio_tlmm_config(52, 2, GPIO_INPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+
+ /* configure tx gpio */
+ gpio_tlmm_config(51, 2, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
}
void gpio_config_blsp_i2c(uint8_t blsp_id, uint8_t qup_id)
diff --git a/platform/apq8084/include/platform/iomap.h b/platform/apq8084/include/platform/iomap.h
index d7dbb44..ef26cbb 100644
--- a/platform/apq8084/include/platform/iomap.h
+++ b/platform/apq8084/include/platform/iomap.h
@@ -31,6 +31,15 @@
#define MSM_SHARED_BASE 0x0FA00000
+#define SYSTEM_IMEM_BASE 0xFE800000
+
+#define MSM_IOMAP_BASE 0xF9000000
+#define MSM_IOMAP_END 0xFEFFFFFF
+
+#define MSM_SHARED_IMEM_BASE 0xFE805000
+
+#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
+
#define KPSS_BASE 0xF9000000
#define MSM_GIC_DIST_BASE KPSS_BASE
@@ -61,6 +70,44 @@
#define BLSP1_UART4_BASE (PERIPH_SS_BASE + 0x00121000)
#define BLSP1_UART5_BASE (PERIPH_SS_BASE + 0x00122000)
+#define BLSP2_UART1_BASE (PERIPH_SS_BASE + 0x0015E000)
+
+#define CLK_CTL_BASE 0xFC400000
+
+/* GPLL */
+#define GPLL0_STATUS (CLK_CTL_BASE + 0x001C)
+#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x1480)
+#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x1484)
+
+/* UART */
+#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x5C4)
+#define BLSP2_AHB_CBCR (CLK_CTL_BASE + 0x944)
+#define BLSP2_UART2_APPS_CBCR (CLK_CTL_BASE + 0xA44)
+#define BLSP2_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0xA4C)
+#define BLSP2_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0xA50)
+#define BLSP2_UART2_APPS_M (CLK_CTL_BASE + 0xA54)
+#define BLSP2_UART2_APPS_N (CLK_CTL_BASE + 0xA58)
+#define BLSP2_UART2_APPS_D (CLK_CTL_BASE + 0xA5C)
+
+/* USB */
+#define USB_HS_BCR (CLK_CTL_BASE + 0x480)
+
+#define USB_HS_SYSTEM_CBCR (CLK_CTL_BASE + 0x484)
+#define USB_HS_AHB_CBCR (CLK_CTL_BASE + 0x488)
+#define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x490)
+#define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x494)
+
+/* SDCC */
+#define SDCC1_BCR (CLK_CTL_BASE + 0x4C0) /* block reset */
+#define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x4C4) /* branch control */
+#define SDCC1_AHB_CBCR (CLK_CTL_BASE + 0x4C8)
+#define SDCC1_CMD_RCGR (CLK_CTL_BASE + 0x4D0) /* cmd */
+#define SDCC1_CFG_RCGR (CLK_CTL_BASE + 0x4D4) /* cfg */
+#define SDCC1_M (CLK_CTL_BASE + 0x4D8) /* m */
+#define SDCC1_N (CLK_CTL_BASE + 0x4DC) /* n */
+#define SDCC1_D (CLK_CTL_BASE + 0x4E0) /* d */
+#define SDCC1_CDCCAL_SLEEP_CBCR (CLK_CTL_BASE + 0x4E4)
+
/* Addresses below this point needs to be verified.
* Included only for compilation purposes.
*/
@@ -92,7 +139,10 @@
#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x00002044)
/* SDHCI */
-#define SDCC_MCI_HC_MODE (PERIPH_SS_BASE + 0x00024078)
-#define SDCC_HC_PWRCTL_MASK_REG (PERIPH_SS_BASE + 0x000240E0)
-#define SDCC_HC_PWRCTL_CTL_REG (PERIPH_SS_BASE + 0x000240E8)
+#define SDCC_MCI_HC_MODE (0x00000078)
+#define SDCC_HC_PWRCTL_STATUS_REG (0x000000DC)
+#define SDCC_HC_PWRCTL_MASK_REG (0x000000E0)
+#define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4)
+#define SDCC_HC_PWRCTL_CTL_REG (0x000000E8)
+
#endif
diff --git a/platform/apq8084/include/platform/irqs.h b/platform/apq8084/include/platform/irqs.h
index 9db58bb..8b25b0c 100644
--- a/platform/apq8084/include/platform/irqs.h
+++ b/platform/apq8084/include/platform/irqs.h
@@ -62,5 +62,8 @@
#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + \
NR_BOARD_IRQS)
-#define SDCC_PWRCTRL_IRQ (GIC_SPI_START + 138)
+#define SDCC1_PWRCTL_IRQ (GIC_SPI_START + 138)
+#define SDCC2_PWRCTL_IRQ (GIC_SPI_START + 221)
+#define SDCC3_PWRCTL_IRQ (GIC_SPI_START + 224)
+#define SDCC4_PWRCTL_IRQ (GIC_SPI_START + 227)
#endif /* __IRQS_APQ8084_H */
diff --git a/platform/apq8084/platform.c b/platform/apq8084/platform.c
index d31a519..85aba7e 100644
--- a/platform/apq8084/platform.c
+++ b/platform/apq8084/platform.c
@@ -37,10 +37,33 @@
#include <smem.h>
#include <board.h>
+#define MB (1024*1024)
+
+#define MSM_IOMAP_SIZE ((MSM_IOMAP_END - MSM_IOMAP_BASE)/MB)
+
+/* LK memory - cacheable, write through */
+#define LK_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_WRITE)
+
+/* Peripherals - non-shared device */
+#define IOMAP_MEMORY (MMU_MEMORY_TYPE_DEVICE_SHARED | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
+/* IMEM memory - cacheable, write through */
+#define IMEM_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
+static mmu_section_t mmu_section_table[] = {
+/* Physical addr, Virtual addr, Size (in MB), Flags */
+ { MEMBASE, MEMBASE, (MEMSIZE / MB), LK_MEMORY},
+ { MSM_IOMAP_BASE, MSM_IOMAP_BASE, MSM_IOMAP_SIZE, IOMAP_MEMORY},
+ /* IMEM needs a seperate entry in the table as it's length is only 0x8000. */
+ { SYSTEM_IMEM_BASE, SYSTEM_IMEM_BASE, 1, IMEM_MEMORY},
+};
+
void platform_early_init(void)
{
- /* Uncomment board_init when bootchain is available. */
- /* board_init(); */
+ board_init();
platform_clock_init();
qgic_init();
qtimer_init();
@@ -59,3 +82,78 @@
qtimer_uninit();
}
+
+int platform_use_identity_mmu_mappings(void)
+{
+ /* Use only the mappings specified in this file. */
+ return 0;
+}
+
+/* Setup memory for this platform */
+void platform_init_mmu_mappings(void)
+{
+ uint32_t i;
+ uint32_t sections;
+ ram_partition ptn_entry;
+ uint32_t table_size = ARRAY_SIZE(mmu_section_table);
+ uint32_t len = 0;
+
+ ASSERT(smem_ram_ptable_init_v1());
+
+ len = smem_get_ram_ptable_len();
+
+ /* Configure the MMU page entries for SDRAM and IMEM memory read
+ from the smem ram table*/
+ for(i = 0; i < len; i++)
+ {
+ smem_get_ram_ptable_entry(&ptn_entry, i);
+ if(ptn_entry.type == SYS_MEMORY)
+ {
+ if((ptn_entry.category == SDRAM) ||
+ (ptn_entry.category == IMEM))
+ {
+ /* Check to ensure that start address is 1MB aligned */
+ ASSERT((ptn_entry.start & (MB-1)) == 0);
+
+ sections = (ptn_entry.size) / MB;
+ while(sections--)
+ {
+ arm_mmu_map_section(ptn_entry.start +
+ sections * MB,
+ ptn_entry.start +
+ sections * MB,
+ (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN));
+ }
+ }
+ }
+ }
+
+ /* Configure the MMU page entries for memory read from the
+ mmu_section_table */
+ for (i = 0; i < table_size; i++)
+ {
+ sections = mmu_section_table[i].num_of_sections;
+
+ while (sections--)
+ {
+ arm_mmu_map_section(mmu_section_table[i].paddress +
+ sections * MB,
+ mmu_section_table[i].vaddress +
+ sections * MB,
+ mmu_section_table[i].flags);
+ }
+ }
+}
+
+addr_t platform_get_virt_to_phys_mapping(addr_t virt_addr)
+{
+ /* Using 1-1 mapping on this platform. */
+ return virt_addr;
+}
+
+addr_t platform_get_phys_to_virt_mapping(addr_t phys_addr)
+{
+ /* Using 1-1 mapping on this platform. */
+ return phys_addr;
+}
diff --git a/platform/apq8084/rules.mk b/platform/apq8084/rules.mk
index 4738c69..260dc2d 100644
--- a/platform/apq8084/rules.mk
+++ b/platform/apq8084/rules.mk
@@ -11,7 +11,7 @@
DEFINES += PERIPH_BLK_BLSP=1
DEFINES += WITH_CPU_EARLY_INIT=0 WITH_CPU_WARM_BOOT=0 \
MMC_SLOT=$(MMC_SLOT)
-DEFINES += TZ_SAVE_KERNEL_HASH
+#DEFINES += TZ_SAVE_KERNEL_HASH
INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared/include
diff --git a/platform/fsm9900/include/platform/clock.h b/platform/fsm9900/include/platform/clock.h
index e19920d..eb55033 100644
--- a/platform/fsm9900/include/platform/clock.h
+++ b/platform/fsm9900/include/platform/clock.h
@@ -32,7 +32,7 @@
#include <clock.h>
#include <clock_lib2.h>
-#define UART_DM_CLK_RX_TX_BIT_RATE 0xFF
+#define UART_DM_CLK_RX_TX_BIT_RATE 0xcc
void platform_clock_init(void);
diff --git a/platform/fsm9900/include/platform/iomap.h b/platform/fsm9900/include/platform/iomap.h
index 4cc017b..1efb9a6 100644
--- a/platform/fsm9900/include/platform/iomap.h
+++ b/platform/fsm9900/include/platform/iomap.h
@@ -35,7 +35,7 @@
#define SDRAM_START_ADDR 0x00000000
#define SDRAM_SEC_BANK_START_ADDR 0x10000000
-#define MSM_SHARED_BASE 0x0FA00000
+#define MSM_SHARED_BASE 0x1C100000
#define RPM_MSG_RAM_BASE 0xFC42B000
#define SYSTEM_IMEM_BASE 0xFE800000
diff --git a/platform/fsm9900/rules.mk b/platform/fsm9900/rules.mk
index e115234..23b1040 100644
--- a/platform/fsm9900/rules.mk
+++ b/platform/fsm9900/rules.mk
@@ -10,7 +10,7 @@
DEFINES += PERIPH_BLK_BLSP=1
DEFINES += WITH_CPU_EARLY_INIT=0 WITH_CPU_WARM_BOOT=0 \
- MMC_SLOT=$(MMC_SLOT) SSD_ENABLE
+ MMC_SLOT=$(MMC_SLOT)
INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared/include
diff --git a/platform/msm8974/acpuclock.c b/platform/msm8974/acpuclock.c
index 5284d0f..e66208c 100644
--- a/platform/msm8974/acpuclock.c
+++ b/platform/msm8974/acpuclock.c
@@ -481,6 +481,83 @@
}
}
+void mmss_clock_auto_pll_init(uint32_t dsi_pixel0_cfg_rcgr, uint32_t dual_dsi,
+ uint8_t pclk0_m, uint8_t pclk0_n, uint8_t pclk0_d)
+{
+ int ret;
+
+ /* Configure Byte clock -autopll- This will not change because
+ byte clock does not need any divider*/
+ writel(0x100, DSI_BYTE0_CFG_RCGR);
+ writel(0x1, DSI_BYTE0_CMD_RCGR);
+ writel(0x1, DSI_BYTE0_CBCR);
+
+ /* Configure ESC clock */
+ ret = clk_get_set_enable("mdss_esc0_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set esc0_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Configure MMSSNOC AXI clock */
+ ret = clk_get_set_enable("mmss_mmssnoc_axi_clk", 100000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set mmssnoc_axi_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Configure S0 AXI clock */
+ ret = clk_get_set_enable("mmss_s0_axi_clk", 100000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set mmss_s0_axi_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Configure AXI clock */
+ ret = clk_get_set_enable("mdss_axi_clk", 100000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set mdss_axi_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Configure Pixel clock */
+ writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL0_CFG_RCGR);
+ writel(0x1, DSI_PIXEL0_CMD_RCGR);
+ writel(0x1, DSI_PIXEL0_CBCR);
+
+ writel(pclk0_m, DSI_PIXEL0_M);
+ writel(pclk0_n, DSI_PIXEL0_N);
+ writel(pclk0_d, DSI_PIXEL0_D);
+
+ if (dual_dsi) {
+ /* Configure Byte 1 clock */
+ writel(0x100, DSI_BYTE1_CFG_RCGR);
+ writel(0x1, DSI_BYTE1_CMD_RCGR);
+ writel(0x1, DSI_BYTE1_CBCR);
+
+ /* Configure ESC clock */
+ ret = clk_get_set_enable("mdss_esc1_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set esc1_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Configure Pixel clock */
+ writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL1_CFG_RCGR);
+ writel(0x1, DSI_PIXEL1_CMD_RCGR);
+ writel(0x1, DSI_PIXEL1_CBCR);
+
+ writel(pclk0_m, DSI_PIXEL0_M);
+ writel(pclk0_n, DSI_PIXEL0_N);
+ writel(pclk0_d, DSI_PIXEL0_D);
+ }
+}
+
void mmss_clock_disable(uint32_t dual_dsi)
{
diff --git a/platform/msm8974/include/platform/clock.h b/platform/msm8974/include/platform/clock.h
index f83c2ae..3f6bd14 100644
--- a/platform/msm8974/include/platform/clock.h
+++ b/platform/msm8974/include/platform/clock.h
@@ -67,6 +67,9 @@
#define DSI_PIXEL0_CMD_RCGR REG_MM(0x2000)
#define DSI_PIXEL0_CFG_RCGR REG_MM(0x2004)
#define DSI_PIXEL0_CBCR REG_MM(0x2314)
+#define DSI_PIXEL0_M REG_MM(0x2008)
+#define DSI_PIXEL0_N REG_MM(0x200C)
+#define DSI_PIXEL0_D REG_MM(0x2010)
#define DSI0_PHY_PLL_OUT BIT(8)
#define PIXEL_SRC_DIV_1_5 BIT(1)
@@ -80,6 +83,9 @@
#define DSI_PIXEL1_CMD_RCGR REG_MM(0x2020)
#define DSI_PIXEL1_CFG_RCGR REG_MM(0x2024)
#define DSI_PIXEL1_CBCR REG_MM(0x2318)
+#define DSI_PIXEL1_M REG_MM(0x2028)
+#define DSI_PIXEL1_N REG_MM(0x202C)
+#define DSI_PIXEL1_D REG_MM(0x2030)
#define MDSS_EDPPIXEL_CBCR REG_MM(0x232C)
#define MDSS_EDPLINK_CBCR REG_MM(0x2330)
diff --git a/platform/msm_shared/dev_tree.c b/platform/msm_shared/dev_tree.c
index 4e1d44f..ef81891 100644
--- a/platform/msm_shared/dev_tree.c
+++ b/platform/msm_shared/dev_tree.c
@@ -45,6 +45,9 @@
uint32_t size;
};
+static struct dt_mem_node_info mem_node;
+
+static int platform_dt_match(struct dt_entry *cur_dt_entry, uint32_t target_variant_id, uint32_t subtype_mask);
extern int target_is_emmc_boot(void);
extern uint32_t target_dev_tree_mem(void *fdt, uint32_t memory_node_offset);
/* TODO: This function needs to be moved to target layer to check violations
@@ -52,23 +55,32 @@
*/
extern int check_aboot_addr_range_overlap(uint32_t start, uint32_t size);
-struct msm_id
-{
- uint32_t platform_id;
- uint32_t hardware_id;
- uint32_t soc_rev;
-};
-
/* Returns soc version if platform id and hardware id matches
otherwise return 0xFFFFFFFF */
#define INVALID_SOC_REV_ID 0XFFFFFFFF
static uint32_t dev_tree_compatible(void *dtb)
{
int root_offset;
- const void *prop;
- char model[128];
- struct msm_id msm_id;
+ const void *prop = NULL;
+ const char *plat_prop = NULL;
+ const char *board_prop = NULL;
+ char *model = NULL;
+ struct dt_entry cur_dt_entry;
+ struct dt_entry *dt_entry_v2 = NULL;
+ struct board_id *board_data = NULL;
+ struct plat_id *platform_data = NULL;
int len;
+ int len_board_id;
+ int len_plat_id;
+ int min_plat_id_len = 0;
+ uint32_t target_variant_id;
+ uint32_t dtb_ver;
+ uint32_t num_entries = 0;
+ uint32_t i, j, k;
+ uint32_t found = 0;
+ uint32_t msm_data_count;
+ uint32_t board_data_count;
+ uint32_t soc_rev;
root_offset = fdt_path_offset(dtb, "/");
if (root_offset < 0)
@@ -76,49 +88,199 @@
prop = fdt_getprop(dtb, root_offset, "model", &len);
if (prop && len > 0) {
- memcpy(model, prop, MIN((int)sizeof(model), len));
- model[sizeof(model) - 1] = '\0';
+ model = (char *) malloc(sizeof(char) * len);
+ ASSERT(model);
+ strlcpy(model, prop, len);
} else {
model[0] = '\0';
}
- prop = fdt_getprop(dtb, root_offset, "qcom,msm-id", &len);
- if (!prop || len <= 0) {
+ /* Find the board-id prop from DTB , if board-id is present then
+ * the DTB is version 2 */
+ board_prop = (const char *)fdt_getprop(dtb, root_offset, "qcom,board-id", &len_board_id);
+ if (board_prop)
+ {
+ dtb_ver = DEV_TREE_VERSION_V2;
+ min_plat_id_len = PLAT_ID_SIZE;
+ }
+ else
+ {
+ dtb_ver = DEV_TREE_VERSION_V1;
+ min_plat_id_len = DT_ENTRY_V1_SIZE;
+ }
+
+ /* Get the msm-id prop from DTB */
+ plat_prop = (const char *)fdt_getprop(dtb, root_offset, "qcom,msm-id", &len_plat_id);
+ if (!plat_prop || len_plat_id <= 0) {
dprintf(INFO, "qcom,msm-id entry not found\n");
return false;
- } else if (len < (int)sizeof(struct msm_id)) {
- dprintf(INFO, "qcom,msm-id entry size mismatch (%d != %d)\n",
- len, sizeof(struct msm_id));
+ } else if (len_plat_id % min_plat_id_len) {
+ dprintf(INFO, "qcom,msm-id in device tree is (%d) not a multiple of (%d)\n",
+ len_plat_id, min_plat_id_len);
return false;
}
- msm_id.platform_id = fdt32_to_cpu(((const struct msm_id *)prop)->platform_id);
- msm_id.hardware_id = fdt32_to_cpu(((const struct msm_id *)prop)->hardware_id);
- msm_id.soc_rev = fdt32_to_cpu(((const struct msm_id *)prop)->soc_rev);
- dprintf(INFO, "Found an appended flattened device tree (%s - %d %d 0x%x)\n",
- *model ? model : "unknown",
- msm_id.platform_id, msm_id.hardware_id, msm_id.soc_rev);
+ /*
+ * If DTB version is '1' look for <x y z> pair in the DTB
+ * x: platform_id
+ * y: variant_id
+ * z: SOC rev
+ */
+ if (dtb_ver == DEV_TREE_VERSION_V1)
+ {
+ while (len_plat_id)
+ {
+ cur_dt_entry.platform_id = fdt32_to_cpu(((const struct dt_entry_v1 *)plat_prop)->platform_id);
+ cur_dt_entry.variant_id = fdt32_to_cpu(((const struct dt_entry_v1 *)plat_prop)->variant_id);
+ cur_dt_entry.soc_rev = fdt32_to_cpu(((const struct dt_entry_v1 *)plat_prop)->soc_rev);
+ cur_dt_entry.board_hw_subtype = board_hardware_subtype();
- if (msm_id.platform_id != board_platform_id() ||
- msm_id.hardware_id != board_hardware_id()) {
- dprintf(INFO, "Device tree's msm_id doesn't match the board: <%d %d 0x%x> != <%d %d 0x%x>\n",
- msm_id.platform_id,
- msm_id.hardware_id,
- msm_id.soc_rev,
- board_platform_id(),
- board_hardware_id(),
- board_soc_version());
- return INVALID_SOC_REV_ID;
+ target_variant_id = board_hardware_id();
+
+ dprintf(SPEW, "Found an appended flattened device tree (%s - %u %u 0x%x)\n",
+ *model ? model : "unknown",
+ cur_dt_entry.platform_id, cur_dt_entry.variant_id, cur_dt_entry.soc_rev);
+
+ if (platform_dt_match(&cur_dt_entry, target_variant_id, 0) == 1)
+ {
+ dprintf(SPEW, "Device tree's msm_id doesn't match the board: <%u %u 0x%x> != <%u %u 0x%x>\n",
+ cur_dt_entry.platform_id,
+ cur_dt_entry.variant_id,
+ cur_dt_entry.soc_rev,
+ board_platform_id(),
+ board_hardware_id(),
+ board_soc_version());
+ plat_prop += DT_ENTRY_V1_SIZE;
+ len_plat_id -= DT_ENTRY_V1_SIZE;
+ continue;
+ }
+ else
+ {
+ found = 1;
+ break;
+ }
+ }
+ }
+ /*
+ * If DTB Version is '2' then we have split DTB with board & msm data
+ * populated saperately in board-id & msm-id prop respectively.
+ * Extract the data & prepare a look up table
+ */
+ else if (dtb_ver == DEV_TREE_VERSION_V2)
+ {
+ board_data_count = (len_board_id / BOARD_ID_SIZE);
+ msm_data_count = (len_plat_id / PLAT_ID_SIZE);
+
+ /* If we are using dtb v2.0, then we have split board & msm data in the DTB */
+ board_data = (struct board_id *) malloc(sizeof(struct board_id) * (len_board_id / BOARD_ID_SIZE));
+ ASSERT(board_data);
+ platform_data = (struct plat_id *) malloc(sizeof(struct plat_id) * (len_plat_id / PLAT_ID_SIZE));
+ ASSERT(platform_data);
+ i = 0;
+
+ /* Extract board data from DTB */
+ for(i = 0 ; i < board_data_count; i++)
+ {
+ board_data[i].variant_id = fdt32_to_cpu(((struct board_id *)board_prop)->variant_id);
+ board_data[i].platform_subtype = fdt32_to_cpu(((struct board_id *)board_prop)->platform_subtype);
+ len_board_id -= sizeof(struct board_id);
+ board_prop += sizeof(struct board_id);
+ }
+
+ /* Extract platform data from DTB */
+ for(i = 0 ; i < msm_data_count; i++)
+ {
+ platform_data[i].platform_id = fdt32_to_cpu(((struct plat_id *)plat_prop)->platform_id);
+ platform_data[i].soc_rev = fdt32_to_cpu(((struct plat_id *)plat_prop)->soc_rev);
+ len_plat_id -= sizeof(struct plat_id);
+ plat_prop += sizeof(struct plat_id);
+ }
+
+ /* We need to merge board & platform data into dt entry structure */
+ num_entries = msm_data_count * board_data_count;
+ dt_entry_v2 = (struct dt_entry*) malloc(sizeof(struct dt_entry) * num_entries);
+ ASSERT(dt_entry_v2);
+
+ /* If we have '<X>; <Y>; <Z>' as platform data & '<A>; <B>; <C>' as board data.
+ * Then dt entry should look like
+ * <X ,A >;<X, B>;<X, C>;
+ * <Y ,A >;<Y, B>;<Y, C>;
+ * <Z ,A >;<Z, B>;<Z, C>;
+ */
+ i = 0;
+ k = 0;
+ for (i = 0; i < msm_data_count; i++)
+ {
+ for (j = 0; j < board_data_count; j++)
+ {
+ dt_entry_v2[k].platform_id = platform_data[i].platform_id;
+ dt_entry_v2[k].soc_rev = platform_data[i].soc_rev;
+ dt_entry_v2[k].variant_id = board_data[j].variant_id;
+ dt_entry_v2[k].board_hw_subtype = board_data[j].platform_subtype;
+ k++;
+ }
+ }
+
+ /* Now find the matching entry in the merged list */
+ if (board_hardware_id() == HW_PLATFORM_QRD)
+ target_variant_id = board_target_id();
+ else
+ target_variant_id = board_hardware_id() | ((board_hardware_subtype() & 0xff) << 24);
+
+ for (i=0 ;i < num_entries; i++)
+ {
+ dprintf(SPEW, "Found an appended flattened device tree (%s - %u %u %u 0x%x)\n",
+ *model ? model : "unknown",
+ dt_entry_v2[i].platform_id, dt_entry_v2[i].variant_id, dt_entry_v2[i].board_hw_subtype, dt_entry_v2[i].soc_rev);
+
+ if (platform_dt_match(&dt_entry_v2[i], target_variant_id, 0xff) == 1)
+ {
+ dprintf(SPEW, "Device tree's msm_id doesn't match the board: <%u %u %u 0x%x> != <%u %u %u 0x%x>\n",
+ dt_entry_v2[i].platform_id,
+ dt_entry_v2[i].variant_id,
+ dt_entry_v2[i].soc_rev,
+ dt_entry_v2[i].board_hw_subtype,
+ board_platform_id(),
+ board_hardware_id(),
+ board_hardware_subtype(),
+ board_soc_version());
+ continue;
+ }
+ else
+ {
+ /* If found a match, return the cur_dt_entry */
+ found = 1;
+ cur_dt_entry = dt_entry_v2[i];
+ break;
+ }
+ }
}
- dprintf(INFO, "Device tree's msm_id matches the board: <%d %d 0x%x> == <%d %d 0x%x>\n",
- msm_id.platform_id,
- msm_id.hardware_id,
- msm_id.soc_rev,
+ if (!found)
+ {
+ soc_rev = INVALID_SOC_REV_ID;
+ goto end;
+ }
+ else
+ soc_rev = cur_dt_entry.soc_rev;
+
+ dprintf(INFO, "Device tree's msm_id matches the board: <%u %u %u 0x%x> == <%u %u %u 0x%x>\n",
+ cur_dt_entry.platform_id,
+ cur_dt_entry.variant_id,
+ cur_dt_entry.board_hw_subtype,
+ cur_dt_entry.soc_rev,
board_platform_id(),
board_hardware_id(),
+ board_hardware_subtype(),
board_soc_version());
- return msm_id.soc_rev;
+
+end:
+ free(board_data);
+ free(platform_data);
+ free(dt_entry_v2);
+ free(model);
+
+ return soc_rev;
}
/*
@@ -197,9 +359,10 @@
}
/* Returns 0 if the device tree is valid. */
-int dev_tree_validate(struct dt_table *table, unsigned int page_size)
+int dev_tree_validate(struct dt_table *table, unsigned int page_size, uint32_t *dt_hdr_size)
{
int dt_entry_size;
+ uint32_t hdr_size;
/* Validate the device tree table header */
if(table->magic != DEV_TREE_MAGIC) {
@@ -217,8 +380,11 @@
return -1;
}
- /* Restriction that the device tree entry table should be less than a page*/
- ASSERT(((table->num_entries * dt_entry_size)+ DEV_TREE_HEADER_SIZE) < page_size);
+ hdr_size = table->num_entries * dt_entry_size + DEV_TREE_HEADER_SIZE;
+ /* Roundup to page_size. */
+ hdr_size = ROUNDUP(hdr_size, page_size);
+
+ *dt_hdr_size = hdr_size;
return 0;
}
@@ -387,7 +553,6 @@
ret);
}
-
ret = fdt_appendprop_u32(fdt, offset, "reg", size);
if (ret)
@@ -399,37 +564,172 @@
return ret;
}
-/* Function to add the subsequent RAM partition info to the device tree. */
-int dev_tree_add_mem_info(void *fdt, uint32_t offset, uint32_t addr, uint32_t size)
+static int dev_tree_query_memory_cell_sizes(void *fdt, struct dt_mem_node_info *mem_node, uint32_t mem_node_offset)
{
- static int mem_info_cnt = 0;
- int ret;
+ int len;
+ uint32_t *valp;
+ int ret;
+ uint32_t offset;
- if (!mem_info_cnt)
+ mem_node->offset = mem_node_offset;
+
+ /* Get offset of the root node */
+ ret = fdt_path_offset(fdt, "/");
+ if (ret < 0)
+ {
+ dprintf(CRITICAL, "Could not find memory node.\n");
+ return ret;
+ }
+
+ offset = ret;
+
+ /* Find the #address-cells size. */
+ valp = (uint32_t*)fdt_getprop(fdt, offset, "#address-cells", &len);
+ if (len <= 0)
+ {
+ if (len == -FDT_ERR_NOTFOUND)
+ {
+ /* Property not found.
+ * Assume standard sizes.
+ */
+ mem_node->addr_cell_size = 2;
+ dprintf(CRITICAL, "Using default #addr_cell_size: %u\n", mem_node->addr_cell_size);
+ }
+ else
+ {
+ dprintf(CRITICAL, "Error finding the #address-cells property\n");
+ return len;
+ }
+ }
+ else
+ mem_node->addr_cell_size = fdt32_to_cpu(*valp);
+
+ /* Find the #size-cells size. */
+ valp = (uint32_t*)fdt_getprop(fdt, offset, "#size-cells", &len);
+ if (len <= 0)
+ {
+ if (len == -FDT_ERR_NOTFOUND)
+ {
+ /* Property not found.
+ * Assume standard sizes.
+ */
+ mem_node->size_cell_size = 1;
+ dprintf(CRITICAL, "Using default #size_cell_size: %u\n", mem_node->size_cell_size);
+ }
+ else
+ {
+ dprintf(CRITICAL, "Error finding the #size-cells property\n");
+ return len;
+ }
+ }
+ else
+ mem_node->size_cell_size = fdt32_to_cpu(*valp);
+
+ return 0;
+}
+
+static void dev_tree_update_memory_node(uint32_t offset)
+{
+ mem_node.offset = offset;
+ mem_node.addr_cell_size = 1;
+ mem_node.size_cell_size = 1;
+}
+
+/* Function to add the subsequent RAM partition info to the device tree. */
+int dev_tree_add_mem_info(void *fdt, uint32_t offset, uint64_t addr, uint64_t size)
+{
+ int ret = 0;
+
+ if(smem_get_ram_ptable_version() >= 1)
+ {
+ ret = dev_tree_query_memory_cell_sizes(fdt, &mem_node, offset);
+ if (ret < 0)
+ {
+ dprintf(CRITICAL, "Could not find #address-cells and #size-cells properties: ret %d\n", ret);
+ return ret;
+ }
+
+ }
+ else
+ {
+ dev_tree_update_memory_node(offset);
+ }
+
+ if (!(mem_node.mem_info_cnt))
{
/* Replace any other reg prop in the memory node. */
- ret = fdt_setprop_u32(fdt, offset, "reg", addr);
- mem_info_cnt = 1;
+
+ /* cell_size is the number of 32 bit words used to represent an address/length in the device tree.
+ * memory node in DT can be either 32-bit(cell-size = 1) or 64-bit(cell-size = 2).So when updating
+ * the memory node in the device tree, we write one word or two words based on cell_size = 1 or 2.
+ */
+
+ if(mem_node.addr_cell_size == 2)
+ {
+ ret = fdt_setprop_u32(fdt, mem_node.offset, "reg", addr >> 32);
+ if(ret)
+ {
+ dprintf(CRITICAL, "ERROR: Could not set prop reg for memory node\n");
+ return ret;
+ }
+
+ ret = fdt_appendprop_u32(fdt, mem_node.offset, "reg", (uint32_t)addr);
+ if(ret)
+ {
+ dprintf(CRITICAL, "ERROR: Could not append prop reg for memory node\n");
+ return ret;
+ }
+ }
+ else
+ {
+ ret = fdt_setprop_u32(fdt, mem_node.offset, "reg", (uint32_t)addr);
+ if(ret)
+ {
+ dprintf(CRITICAL, "ERROR: Could not set prop reg for memory node\n");
+ return ret;
+ }
+ }
+
+ mem_node.mem_info_cnt = 1;
}
else
{
/* Append the mem info to the reg prop for subsequent nodes. */
- ret = fdt_appendprop_u32(fdt, offset, "reg", addr);
+ if(mem_node.addr_cell_size == 2)
+ {
+ ret = fdt_appendprop_u32(fdt, mem_node.offset, "reg", addr >> 32);
+ if(ret)
+ {
+ dprintf(CRITICAL, "ERROR: Could not append prop reg for memory node\n");
+ return ret;
+ }
+ }
+
+ ret = fdt_appendprop_u32(fdt, mem_node.offset, "reg", (uint32_t)addr);
+ if(ret)
+ {
+ dprintf(CRITICAL, "ERROR: Could not append prop reg for memory node\n");
+ return ret;
+ }
}
- if (ret)
+ if(mem_node.size_cell_size == 2)
{
- dprintf(CRITICAL, "Failed to add the memory information addr: %d\n",
- ret);
+ ret = fdt_appendprop_u32(fdt, mem_node.offset, "reg", size>>32);
+ if(ret)
+ {
+ dprintf(CRITICAL, "ERROR: Could not append prop reg for memory node\n");
+ return ret;
+ }
}
-
- ret = fdt_appendprop_u32(fdt, offset, "reg", size);
+ ret = fdt_appendprop_u32(fdt, mem_node.offset, "reg", (uint32_t)size);
if (ret)
{
dprintf(CRITICAL, "Failed to add the memory information size: %d\n",
ret);
+ return ret;
}
return ret;
diff --git a/platform/msm_shared/include/dev_tree.h b/platform/msm_shared/include/dev_tree.h
index 2a8ee01..1d9b9ad 100644
--- a/platform/msm_shared/include/dev_tree.h
+++ b/platform/msm_shared/include/dev_tree.h
@@ -43,6 +43,18 @@
#define DTB_PAD_SIZE 1024
+/*
+ * For DTB V1: The DTB entries would be of the format
+ * qcom,msm-id = <msm8974, CDP, rev_1>; (3 * sizeof(uint32_t))
+ * For DTB V2: The DTB entries would be of the format
+ * qcom,msm-id = <msm8974, rev_1>; (2 * sizeof(uint32_t))
+ * qcom,board-id = <CDP, subtype_ID>; (2 * sizeof(uint32_t))
+ * The macros below are defined based on these.
+ */
+#define DT_ENTRY_V1_SIZE 0xC
+#define PLAT_ID_SIZE 0x8
+#define BOARD_ID_SIZE 0x8
+
struct dt_entry
{
uint32_t platform_id;
@@ -60,15 +72,35 @@
uint32_t num_entries;
};
+struct plat_id
+{
+ uint32_t platform_id;
+ uint32_t soc_rev;
+};
+
+struct board_id
+{
+ uint32_t variant_id;
+ uint32_t platform_subtype;
+};
+
+struct dt_mem_node_info
+{
+ uint32_t offset;
+ uint32_t mem_info_cnt;
+ uint32_t addr_cell_size;
+ uint32_t size_cell_size;
+};
+
enum dt_err_codes
{
DT_OP_SUCCESS,
DT_OP_FAILURE = -1,
};
-int dev_tree_validate(struct dt_table *table, unsigned int page_size);
+int dev_tree_validate(struct dt_table *table, unsigned int page_size, uint32_t *dt_hdr_size);
int dev_tree_get_entry_info(struct dt_table *table, struct dt_entry *dt_entry_info);
-int update_device_tree(void *, const char *, void *, unsigned);
-int dev_tree_add_mem_info(void *fdt, uint32_t offset, uint32_t size, uint32_t addr);
+int update_device_tree(void *fdt, const char *, void *, unsigned);
+int dev_tree_add_mem_info(void *fdt, uint32_t offset, uint64_t size, uint64_t addr);
void *dev_tree_appended(void *kernel, uint32_t kernel_size, void *tags);
#endif
diff --git a/platform/msm_shared/include/msm_panel.h b/platform/msm_shared/include/msm_panel.h
index 1cf0e64..b7b57ad 100755
--- a/platform/msm_shared/include/msm_panel.h
+++ b/platform/msm_shared/include/msm_panel.h
@@ -160,6 +160,7 @@
char lane_swap;
uint8_t dual_dsi;
uint8_t broadcast;
+ uint8_t mode_gpio_state;
};
struct edp_panel_info {
diff --git a/platform/msm_shared/mipi_dsi_autopll.c b/platform/msm_shared/mipi_dsi_autopll.c
index 5616956..72f2f94 100755
--- a/platform/msm_shared/mipi_dsi_autopll.c
+++ b/platform/msm_shared/mipi_dsi_autopll.c
@@ -64,220 +64,8 @@
return dividend / divisor;
}
-static uint32_t dsi_pll_enable_seq_m(void)
-{
- uint32_t i = 0;
- uint32_t pll_locked = 0;
-
- mdss_dsi_uniphy_pll_sw_reset(MIPI_DSI_BASE);
-
- /*
- * Add hardware recommended delays between register writes for
- * the updates to take effect. These delays are necessary for the
- * PLL to successfully lock
- */
- writel(0x01, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x05, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x0f, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(1000);
-
- mdss_dsi_uniphy_pll_lock_detect_setting(MIPI_DSI_BASE);
- pll_locked = readl(MIPI_DSI_BASE + 0x02c0) & 0x01;
- for (i = 0; (i < 4) && !pll_locked; i++) {
- writel(0x07, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- if (i != 0)
- writel(0x34, MIPI_DSI_BASE + 0x00270); /* CAL CFG1*/
- udelay(1);
- writel(0x0f, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(1000);
- mdss_dsi_uniphy_pll_lock_detect_setting(MIPI_DSI_BASE);
- pll_locked = readl(MIPI_DSI_BASE + 0x02c0) & 0x01;
- }
-
- return pll_locked;
-}
-
-static uint32_t dsi_pll_enable_seq_d(void)
-{
- uint32_t pll_locked = 0;
-
- mdss_dsi_uniphy_pll_sw_reset(MIPI_DSI_BASE);
-
- /*
- * Add hardware recommended delays between register writes for
- * the updates to take effect. These delays are necessary for the
- * PLL to successfully lock
- */
- writel(0x01, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x05, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x07, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x05, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x07, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x0f, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(1000);
-
- mdss_dsi_uniphy_pll_lock_detect_setting(MIPI_DSI_BASE);
- pll_locked = readl(MIPI_DSI_BASE + 0x02c0) & 0x01;
-
- return pll_locked;
-}
-
-static uint32_t dsi_pll_enable_seq_f1(void)
-{
- uint32_t pll_locked = 0;
-
- mdss_dsi_uniphy_pll_sw_reset(MIPI_DSI_BASE);
-
- /*
- * Add hardware recommended delays between register writes for
- * the updates to take effect. These delays are necessary for the
- * PLL to successfully lock
- */
- writel(0x01, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x05, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x0f, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x0d, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x0f, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(1000);
-
- mdss_dsi_uniphy_pll_lock_detect_setting(MIPI_DSI_BASE);
- pll_locked = readl(MIPI_DSI_BASE + 0x02c0) & 0x01;
-
- return pll_locked;
-}
-
-static uint32_t dsi_pll_enable_seq_c(void)
-{
- uint32_t pll_locked = 0;
-
- mdss_dsi_uniphy_pll_sw_reset(MIPI_DSI_BASE);
-
- /*
- * Add hardware recommended delays between register writes for
- * the updates to take effect. These delays are necessary for the
- * PLL to successfully lock
- */
- writel(0x01, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x05, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x0f, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(1000);
-
- mdss_dsi_uniphy_pll_lock_detect_setting(MIPI_DSI_BASE);
- pll_locked = readl(MIPI_DSI_BASE + 0x02c0) & 0x01;
-
- return pll_locked;
-}
-
-static uint32_t dsi_pll_enable_seq_e(void)
-{
- uint32_t pll_locked = 0;
-
- mdss_dsi_uniphy_pll_sw_reset(MIPI_DSI_BASE);
-
- /*
- * Add hardware recommended delays between register writes for
- * the updates to take effect. These delays are necessary for the
- * PLL to successfully lock
- */
- writel(0x01, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x05, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(200);
- writel(0x0d, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(1);
- writel(0x0f, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- udelay(1000);
-
- mdss_dsi_uniphy_pll_lock_detect_setting(MIPI_DSI_BASE);
- pll_locked = readl(MIPI_DSI_BASE + 0x02c0) & 0x01;
-
- return pll_locked;
-}
-
-
-
-static uint32_t dsi_pll_enable_seq_8974(void)
-{
- uint32_t rc = 0;
-
- mdss_dsi_uniphy_pll_sw_reset(MIPI_DSI_BASE);
-
- writel(0x01, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x05, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x07, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x0f, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- mdelay(1);
-
- mdss_dsi_uniphy_pll_lock_detect_setting(MIPI_DSI_BASE);
-
- while (!(readl(MIPI_DSI_BASE + 0x02c0) & 0x01)) {
- mdss_dsi_uniphy_pll_sw_reset(MIPI_DSI_BASE);
- writel(0x01, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x05, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x07, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x05, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x07, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x0f, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
- mdelay(2);
- mdss_dsi_uniphy_pll_lock_detect_setting(MIPI_DSI_BASE);
- }
- return rc;
-}
-
-static uint32_t dsi_pll_enable_seq(void)
-{
- uint32_t platformid = board_platform_id();
-
- /* Only one enable seq for 8974 target */
- if (platformid == MSM8974) {
- dsi_pll_enable_seq_8974();
- }
-
- /* 6 enable seq for 8226 target */
- else if (platformid == MSM8826 ||
- platformid == MSM8626 ||
- platformid == MSM8226 ||
- platformid == MSM8926 ||
- platformid == MSM8126 ||
- platformid == MSM8326 ||
- platformid == APQ8026) {
- if (dsi_pll_enable_seq_m()) {
- } else if (dsi_pll_enable_seq_d()) {
- } else if (dsi_pll_enable_seq_d()) {
- } else if (dsi_pll_enable_seq_f1()) {
- } else if (dsi_pll_enable_seq_c()) {
- } else if (dsi_pll_enable_seq_e()) {
- } else {
- dprintf(CRITICAL, "Not able to enable the pll\n");
- }
- } else {
- dprintf(CRITICAL, "Target not supported in auto PLL\n");
- }
-
-}
-
-int32_t mdss_dsi_auto_pll_config(struct mdss_dsi_pll_config *pd)
+int32_t mdss_dsi_auto_pll_config(uint32_t ctl_base,
+ struct mdss_dsi_pll_config *pd)
{
uint32_t rem, divider;
uint32_t refclk_cfg = 0, frac_n_mode = 0, ref_doubler_en_b = 0;
@@ -299,25 +87,25 @@
return rc;
}
- mdss_dsi_phy_sw_reset(MIPI_DSI_BASE);
+ mdss_dsi_phy_sw_reset(ctl_base);
/* Loop filter resistance value */
- writel(lpfr_lut[i].resistance, MIPI_DSI_BASE + 0x022c);
+ writel(lpfr_lut[i].resistance, ctl_base + 0x022c);
/* Loop filter capacitance values : c1 and c2 */
- writel(0x70, MIPI_DSI_BASE + 0x0230);
- writel(0x15, MIPI_DSI_BASE + 0x0234);
+ writel(0x70, ctl_base + 0x0230);
+ writel(0x15, ctl_base + 0x0234);
- writel(0x02, MIPI_DSI_BASE + 0x0208); /* ChgPump */
+ writel(0x02, ctl_base + 0x0208); /* ChgPump */
/* postDiv1 - calculated in pll config*/
- writel(pd->posdiv1, MIPI_DSI_BASE + 0x0204);
+ writel(pd->posdiv1, ctl_base + 0x0204);
/* postDiv2 - fixed devision 4 */
- writel(0x03, MIPI_DSI_BASE + 0x0224);
+ writel(0x03, ctl_base + 0x0224);
/* postDiv3 - calculated in pll config */
- writel(pd->posdiv3, MIPI_DSI_BASE + 0x0228); /* postDiv3 */
+ writel(pd->posdiv3, ctl_base + 0x0228); /* postDiv3 */
- writel(0x2b, MIPI_DSI_BASE + 0x0278); /* Cal CFG3 */
- writel(0x66, MIPI_DSI_BASE + 0x027c); /* Cal CFG4 */
- writel(0x05, MIPI_DSI_BASE + 0x0264); /* LKDetect CFG2 */
+ writel(0x2b, ctl_base + 0x0278); /* Cal CFG3 */
+ writel(0x66, ctl_base + 0x027c); /* Cal CFG4 */
+ writel(0x05, ctl_base + 0x0264); /* LKDetect CFG2 */
rem = pd->vco_clock % VCO_REF_CLOCK_RATE;
if (rem) {
@@ -361,27 +149,25 @@
cal_cfg11 = gen_vco_clk / 256000000;
cal_cfg10 = (gen_vco_clk % 256000000) / 1000000;
- writel(sdm_cfg1 , MIPI_DSI_BASE + 0x023c); /* SDM CFG1 */
- writel(sdm_cfg2 , MIPI_DSI_BASE + 0x0240); /* SDM CFG2 */
- writel(sdm_cfg3 , MIPI_DSI_BASE + 0x0244); /* SDM CFG3 */
- writel(0x00, MIPI_DSI_BASE + 0x0248); /* SDM CFG4 */
+ writel(sdm_cfg1 , ctl_base + 0x023c); /* SDM CFG1 */
+ writel(sdm_cfg2 , ctl_base + 0x0240); /* SDM CFG2 */
+ writel(sdm_cfg3 , ctl_base + 0x0244); /* SDM CFG3 */
+ writel(0x00, ctl_base + 0x0248); /* SDM CFG4 */
udelay(10);
- writel(refclk_cfg, MIPI_DSI_BASE + 0x0200); /* REFCLK CFG */
- writel(0x00, MIPI_DSI_BASE + 0x0214); /* PWRGEN CFG */
- writel(0x71, MIPI_DSI_BASE + 0x020c); /* VCOLPF CFG */
- writel(pd->directpath, MIPI_DSI_BASE + 0x0210); /* VREG CFG */
- writel(sdm_cfg0, MIPI_DSI_BASE + 0x0238); /* SDM CFG0 */
+ writel(refclk_cfg, ctl_base + 0x0200); /* REFCLK CFG */
+ writel(0x00, ctl_base + 0x0214); /* PWRGEN CFG */
+ writel(0x71, ctl_base + 0x020c); /* VCOLPF CFG */
+ writel(pd->directpath, ctl_base + 0x0210); /* VREG CFG */
+ writel(sdm_cfg0, ctl_base + 0x0238); /* SDM CFG0 */
- writel(0x0a, MIPI_DSI_BASE + 0x026c); /* CAL CFG0 */
- writel(0x30, MIPI_DSI_BASE + 0x0284); /* CAL CFG6 */
- writel(0x00, MIPI_DSI_BASE + 0x0288); /* CAL CFG7 */
- writel(0x60, MIPI_DSI_BASE + 0x028c); /* CAL CFG8 */
- writel(0x00, MIPI_DSI_BASE + 0x0290); /* CAL CFG9 */
- writel(cal_cfg10, MIPI_DSI_BASE + 0x0294); /* CAL CFG10 */
- writel(cal_cfg11, MIPI_DSI_BASE + 0x0298); /* CAL CFG11 */
- writel(0x20, MIPI_DSI_BASE + 0x029c); /* EFUSE CFG */
-
- dsi_pll_enable_seq();
+ writel(0x0a, ctl_base + 0x026c); /* CAL CFG0 */
+ writel(0x30, ctl_base + 0x0284); /* CAL CFG6 */
+ writel(0x00, ctl_base + 0x0288); /* CAL CFG7 */
+ writel(0x60, ctl_base + 0x028c); /* CAL CFG8 */
+ writel(0x00, ctl_base + 0x0290); /* CAL CFG9 */
+ writel(cal_cfg10, ctl_base + 0x0294); /* CAL CFG10 */
+ writel(cal_cfg11, ctl_base + 0x0298); /* CAL CFG11 */
+ writel(0x20, ctl_base + 0x029c); /* EFUSE CFG */
}
diff --git a/platform/msm_shared/mipi_dsi_phy.c b/platform/msm_shared/mipi_dsi_phy.c
index e3a4527..90e541a 100644
--- a/platform/msm_shared/mipi_dsi_phy.c
+++ b/platform/msm_shared/mipi_dsi_phy.c
@@ -213,154 +213,6 @@
udelay(1);
}
-int mdss_dsi_uniphy_pll_config(uint32_t ctl_base)
-{
- mdss_dsi_phy_sw_reset(ctl_base);
-
- /* Configuring the Pll Vco clk to 424 Mhz */
-
- /* Loop filter resistance value */
- writel(0x08, ctl_base + 0x022c);
- /* Loop filter capacitance values : c1 and c2 */
- writel(0x70, ctl_base + 0x0230);
- writel(0x15, ctl_base + 0x0234);
-
- writel(0x02, ctl_base + 0x0208); /* ChgPump */
- writel(0x00, ctl_base + 0x0204); /* postDiv1 */
- writel(0x03, ctl_base + 0x0224); /* postDiv2 */
- writel(0x05, ctl_base + 0x0228); /* postDiv3 */
-
- writel(0x2b, ctl_base + 0x0278); /* Cal CFG3 */
- writel(0x66, ctl_base + 0x027c); /* Cal CFG4 */
- writel(0x05, ctl_base + 0x0264); /* LKDetect CFG2 */
-
- writel(0x0a, ctl_base + 0x023c); /* SDM CFG1 */
- writel(0xab, ctl_base + 0x0240); /* SDM CFG2 */
- writel(0x0a, ctl_base + 0x0244); /* SDM CFG3 */
- writel(0x00, ctl_base + 0x0248); /* SDM CFG4 */
-
- udelay(10);
-
- writel(0x01, ctl_base + 0x0200); /* REFCLK CFG */
- writel(0x00, ctl_base + 0x0214); /* PWRGEN CFG */
- writel(0x71, ctl_base + 0x020c); /* VCOLPF CFG */
- writel(0x02, ctl_base + 0x0210); /* VREG CFG */
- writel(0x00, ctl_base + 0x0238); /* SDM CFG0 */
-
- writel(0x5f, ctl_base + 0x028c); /* CAL CFG8 */
- writel(0xa8, ctl_base + 0x0294); /* CAL CFG10 */
- writel(0x01, ctl_base + 0x0298); /* CAL CFG11 */
- writel(0x0a, ctl_base + 0x026c); /* CAL CFG0 */
- writel(0x30, ctl_base + 0x0284); /* CAL CFG6 */
- writel(0x00, ctl_base + 0x0288); /* CAL CFG7 */
- writel(0x00, ctl_base + 0x0290); /* CAL CFG9 */
- writel(0x20, ctl_base + 0x029c); /* EFUSE CFG */
-
- mdss_dsi_uniphy_pll_sw_reset(ctl_base);
- writel(0x01, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
-
- mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
-
- while (!(readl(ctl_base + 0x02c0) & 0x01)) {
- mdss_dsi_uniphy_pll_sw_reset(ctl_base);
- writel(0x01, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
- mdelay(2);
- mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
- }
-
-}
-
-int mdss_sharp_dsi_uniphy_pll_config(uint32_t ctl_base)
-{
- mdss_dsi_phy_sw_reset(ctl_base);
-
- /* Configuring the Pll Vco clk to 500 Mhz */
-
- /* Loop filter resistance value */
- writel(0x08, ctl_base + 0x022c);
- /* Loop filter capacitance values : c1 and c2 */
- writel(0x70, ctl_base + 0x0230);
- writel(0x15, ctl_base + 0x0234);
-
- writel(0x02, ctl_base + 0x0208); /* ChgPump */
- writel(0x00, ctl_base + 0x0204); /* postDiv1 */
- writel(0x03, ctl_base + 0x0224); /* postDiv2 */
- writel(0x0b, ctl_base + 0x0228); /* postDiv3 */
-
- writel(0x2b, ctl_base + 0x0278); /* Cal CFG3 */
- writel(0x66, ctl_base + 0x027c); /* Cal CFG4 */
- writel(0x05, ctl_base + 0x0264); /* LKDetect CFG2 */
-
- writel(0x0c, ctl_base + 0x023c); /* SDM CFG1 */
- writel(0x55, ctl_base + 0x0240); /* SDM CFG2 */
- writel(0x05, ctl_base + 0x0244); /* SDM CFG3 */
- writel(0x00, ctl_base + 0x0248); /* SDM CFG4 */
-
- udelay(10);
-
- writel(0x01, ctl_base + 0x0200); /* REFCLK CFG */
- writel(0x00, ctl_base + 0x0214); /* PWRGEN CFG */
- writel(0x01, ctl_base + 0x020c); /* VCOLPF CFG */
- writel(0x02, ctl_base + 0x0210); /* VREG CFG */
- writel(0x00, ctl_base + 0x0238); /* SDM CFG0 */
-
- writel(0x60, ctl_base + 0x028c); /* CAL CFG8 */
- writel(0xf4, ctl_base + 0x0294); /* CAL CFG10 */
- writel(0x01, ctl_base + 0x0298); /* CAL CFG11 */
- writel(0x0a, ctl_base + 0x026c); /* CAL CFG0 */
- writel(0x30, ctl_base + 0x0284); /* CAL CFG6 */
- writel(0x00, ctl_base + 0x0288); /* CAL CFG7 */
- writel(0x00, ctl_base + 0x0290); /* CAL CFG9 */
- writel(0x20, ctl_base + 0x029c); /* EFUSE CFG */
-
- mdss_dsi_uniphy_pll_sw_reset(ctl_base);
- writel(0x01, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
-
- mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
-
- while (!(readl(ctl_base + 0x02c0) & 0x01)) {
- mdss_dsi_uniphy_pll_sw_reset(ctl_base);
- writel(0x01, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
- mdelay(1);
- writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
- mdelay(2);
- mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
- }
-
-}
-
int mdss_dsi_phy_regulator_init(struct mdss_dsi_phy_ctrl *pd)
{
/* DSI0 and DSI1 have a common regulator */
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index ccf164c..00be808 100755
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -86,6 +86,7 @@
$(LOCAL_DIR)/display.o \
$(LOCAL_DIR)/mipi_dsi.o \
$(LOCAL_DIR)/mipi_dsi_phy.o \
+ $(LOCAL_DIR)/mipi_dsi_autopll.o \
$(LOCAL_DIR)/spmi.o \
$(LOCAL_DIR)/bam.o \
$(LOCAL_DIR)/qpic_nand.o \
diff --git a/platform/msm_shared/sdhci.c b/platform/msm_shared/sdhci.c
index 03996f9..4399c60 100644
--- a/platform/msm_shared/sdhci.c
+++ b/platform/msm_shared/sdhci.c
@@ -383,8 +383,11 @@
static uint8_t sdhci_cmd_complete(struct sdhci_host *host, struct mmc_command *cmd)
{
uint8_t i;
+ uint8_t ret = 0;
+ uint8_t need_reset = 0;
uint32_t retry = 0;
uint32_t int_status;
+ uint32_t trans_complete = 0;
do {
int_status = REG_READ16(host, SDHCI_NRML_INT_STS_REG);
@@ -397,6 +400,7 @@
udelay(500);
if (retry == SDHCI_MAX_CMD_RETRY) {
dprintf(CRITICAL, "Error: Command never completed\n");
+ ret = 1;
goto err;
}
} while(1);
@@ -435,12 +439,16 @@
int_status &= SDHCI_INT_STS_TRANS_COMPLETE;
if (int_status & SDHCI_INT_STS_TRANS_COMPLETE)
+ {
+ trans_complete = 1;
break;
+ }
retry++;
udelay(1000);
if (retry == SDHCI_MAX_TRANS_RETRY) {
dprintf(CRITICAL, "Error: Transfer never completed\n");
+ ret = 1;
goto err;
}
} while(1);
@@ -452,20 +460,41 @@
err:
/* Look for errors */
int_status = REG_READ16(host, SDHCI_NRML_INT_STS_REG);
- if (int_status & SDHCI_ERR_INT_STAT_MASK) {
- if (sdhci_cmd_err_status(host)) {
- dprintf(CRITICAL, "Error: Command completed with errors\n");
- /* Reset the command & Data line */
- sdhci_reset(host, (SOFT_RESET_CMD | SOFT_RESET_DATA));
- return 1;
+
+ if (int_status & SDHCI_ERR_INT_STAT_MASK)
+ {
+ /*
+ * As per SDHC spec transfer complete has higher priority than data timeout
+ * If both transfer complete & data timeout are set then we should ignore
+ * data timeout error.
+ * ---------------------------------------------------------------------------
+ * | Transfer complete | Data timeout error | Meaning of the Status |
+ * |--------------------------------------------------------------------------|
+ * | 0 | 0 | Interrupted by another factor |
+ * |--------------------------------------------------------------------------|
+ * | 0 | 1 | Time out occured during transfer|
+ * |--------------------------------------------------------------------------|
+ * | 1 | Don't Care | Command execution complete |
+ * --------------------------------------------------------------------------
+ */
+ if ((REG_READ16(host, SDHCI_ERR_INT_STS_REG) & SDHCI_DAT_TIMEOUT_MASK) && trans_complete)
+ {
+ ret = 0;
}
+ else if (sdhci_cmd_err_status(host))
+ {
+ dprintf(CRITICAL, "Error: Command completed with errors\n");
+ ret = 1;
+ }
+ /* Reset Command & Dat lines on error */
+ need_reset = 1;
}
/* Reset data & command line */
- if (cmd->data_present)
+ if (cmd->data_present || need_reset)
sdhci_reset(host, (SOFT_RESET_CMD | SOFT_RESET_DATA));
- return 0;
+ return ret;
}
/*
diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h
old mode 100755
new mode 100644
index 0182cb3..ae105e7
--- a/platform/msm_shared/smem.h
+++ b/platform/msm_shared/smem.h
@@ -37,6 +37,20 @@
#define SMEM_V8_SMEM_MAX_PMIC_DEVICES 3
#define SMEM_MAX_PMIC_DEVICES SMEM_V8_SMEM_MAX_PMIC_DEVICES
+#define SMEM_RAM_PTABLE_VERSION_OFFSET 8
+
+#define RAM_PART_NAME_LENGTH 16
+#define RAM_NUM_PART_ENTRIES 32
+
+#define _SMEM_RAM_PTABLE_MAGIC_1 0x9DA5E0A8
+#define _SMEM_RAM_PTABLE_MAGIC_2 0xAF9EC4E2
+
+enum smem_ram_ptable_version
+{
+ SMEM_RAM_PTABLE_VERSION_0,
+ SMEM_RAM_PTABLE_VERSION_1,
+};
+
struct smem_proc_comm {
unsigned command;
unsigned status;
@@ -292,6 +306,7 @@
MSM8125 = 167,
MDM9310 = 171,
APQ8064AA = 172, /* aka V2 SLOW_PRIME */
+ APQ8084 = 178,
MSM8130 = 179,
MSM8130AA = 180,
MSM8130AB = 181,
@@ -320,6 +335,12 @@
MSM8674AC = 216,
MSM8974AA = 217,
MSM8974AB = 218,
+ APQ8028 = 219,
+ MSM8128 = 220,
+ MSM8228 = 221,
+ MSM8528 = 222,
+ MSM8628 = 223,
+ MSM8928 = 224,
};
enum platform {
@@ -339,7 +360,9 @@
HW_PLATFORM_RUMI = 15,
HW_PLATFORM_VIRTIO = 16,
HW_PLATFORM_BTS = 19,
+ HW_PLATFORM_RCM = 21,
HW_PLATFORM_DMA = 22,
+ HW_PLATFORM_STP = 23,
HW_PLATFORM_32BITS = 0x7FFFFFFF,
};
@@ -428,28 +451,33 @@
struct smem_ram_ptn {
char name[16];
- unsigned start;
- unsigned size;
+ uint32_t start;
+ uint32_t size;
+ uint32_t attr; /* RAM Partition attribute: READ_ONLY, READWRITE etc.*/
+ uint32_t category; /* RAM Partition category: EBI0, EBI1, IRAM, IMEM */
+ uint32_t domain; /* RAM Partition domain: APPS, MODEM, APPS & MODEM (SHARED) etc. */
+ uint32_t type; /* RAM Partition type: system, bootloader, appsboot, apps etc. */
+ uint32_t num_partitions;/* Number of memory partitions */
+ uint32_t reserved3;
+ uint32_t reserved4;
+ uint32_t reserved5;
+} __attribute__ ((__packed__));
- /* RAM Partition attribute: READ_ONLY, READWRITE etc. */
- unsigned attr;
-
- /* RAM Partition category: EBI0, EBI1, IRAM, IMEM */
- unsigned category;
-
- /* RAM Partition domain: APPS, MODEM, APPS & MODEM (SHARED) etc. */
- unsigned domain;
-
- /* RAM Partition type: system, bootloader, appsboot, apps etc. */
- unsigned type;
-
- /* reserved for future expansion without changing version number */
- unsigned reserved2, reserved3, reserved4, reserved5;
+struct smem_ram_ptn_v1 {
+ char name[RAM_PART_NAME_LENGTH];
+ uint64_t start;
+ uint64_t size;
+ uint32_t attr; /* RAM Partition attribute: READ_ONLY, READWRITE etc.*/
+ uint32_t category; /* RAM Partition category: EBI0, EBI1, IRAM, IMEM */
+ uint32_t domain; /* RAM Partition domain: APPS, MODEM, APPS & MODEM (SHARED) etc. */
+ uint32_t type; /* RAM Partition type: system, bootloader, appsboot, apps etc. */
+ uint32_t num_partitions;/* Number of memory partitions */
+ uint32_t reserved3;
+ uint32_t reserved4; /* Reserved for future use */
+ uint32_t reserved5; /* Reserved for future use */
} __attribute__ ((__packed__));
struct smem_ram_ptable {
-#define _SMEM_RAM_PTABLE_MAGIC_1 0x9DA5E0A8
-#define _SMEM_RAM_PTABLE_MAGIC_2 0xAF9EC4E2
unsigned magic[2];
unsigned version;
unsigned reserved1;
@@ -458,6 +486,20 @@
unsigned buf;
} __attribute__ ((__packed__));
+struct smem_ram_ptable_hdr
+{
+ uint32_t magic[2];
+ uint32_t version;
+ uint32_t reserved1;
+ uint32_t len;
+} __attribute__ ((__packed__));
+
+struct smem_ram_ptable_v1 {
+ struct smem_ram_ptable_hdr hdr;
+ uint32_t reserved2; /* Added for 8 bytes alignment of header */
+ struct smem_ram_ptn_v1 parts[RAM_NUM_PART_ENTRIES];
+} __attribute__ ((__packed__));
+
/* Power on reason/status info */
#define PWR_ON_EVENT_RTC_ALARM 0x2
#define PWR_ON_EVENT_USB_CHG 0x20
@@ -486,7 +528,13 @@
struct smem_ptn parts[SMEM_PTABLE_MAX_PARTS];
} __attribute__ ((__packed__));
+typedef struct smem_ram_ptable_v1 ram_partition_table;
+typedef struct smem_ram_ptn_v1 ram_partition;
+
unsigned smem_read_alloc_entry_offset(smem_mem_type_t type, void *buf, int len, int offset);
int smem_ram_ptable_init(struct smem_ram_ptable *smem_ram_ptable);
-
+int smem_ram_ptable_init_v1(); /* Used on platforms that use ram ptable v1 */
+void smem_get_ram_ptable_entry(ram_partition*, uint32_t entry);
+uint32_t smem_get_ram_ptable_version(void);
+uint32_t smem_get_ram_ptable_len(void);
#endif /* __PLATFORM_MSM_SHARED_SMEM_H */
diff --git a/platform/msm_shared/smem_ptable.c b/platform/msm_shared/smem_ptable.c
index 291b242..6ec563a 100644
--- a/platform/msm_shared/smem_ptable.c
+++ b/platform/msm_shared/smem_ptable.c
@@ -42,6 +42,8 @@
static struct smem_ptable smem_ptable;
static unsigned smem_apps_flash_start = 0xFFFFFFFF;
+static ram_partition_table ptable;
+
static void dump_smem_ptable(void)
{
unsigned i;
@@ -150,6 +152,44 @@
}
}
+static void smem_copy_ram_ptable(void *buf)
+{
+ struct smem_ram_ptable *table_v0;
+ struct smem_ram_ptable_v1 *table_v1;
+ uint32_t pentry = 0;
+
+ ptable.hdr = *(struct smem_ram_ptable_hdr*)buf;
+
+ /* Perform member to member copy from smem_ram_ptable to wrapper struct ram_ptable */
+ if(ptable.hdr.version == SMEM_RAM_PTABLE_VERSION_1)
+ {
+ table_v1 = (struct smem_ram_ptable_v1*)buf;
+
+ memcpy(&ptable, table_v1, sizeof(ram_partition_table));
+ }
+ else if(ptable.hdr.version == SMEM_RAM_PTABLE_VERSION_0)
+ {
+ table_v0 = (struct smem_ram_ptable*)buf;
+
+ for(pentry = 0; pentry < ((struct smem_ram_ptable_hdr*)buf)->len; pentry++)
+ {
+ ptable.parts[pentry].start = table_v0->parts[pentry].start;
+ ptable.parts[pentry].size = table_v0->parts[pentry].size;
+ ptable.parts[pentry].attr = table_v0->parts[pentry].attr;
+ ptable.parts[pentry].category = table_v0->parts[pentry].category;
+ ptable.parts[pentry].domain = table_v0->parts[pentry].domain;
+ ptable.parts[pentry].type = table_v0->parts[pentry].type;
+ ptable.parts[pentry].num_partitions = table_v0->parts[pentry].num_partitions;
+ }
+
+ }
+ else
+ {
+ dprintf(CRITICAL,"ERROR: Unknown smem ram ptable version: %u", ptable.hdr.version);
+ ASSERT(0);
+ }
+}
+
/* RAM Partition table from SMEM */
int smem_ram_ptable_init(struct smem_ram_ptable *smem_ram_ptable)
{
@@ -168,5 +208,71 @@
dprintf(SPEW, "smem ram ptable found: ver: %d len: %d\n",
smem_ram_ptable->version, smem_ram_ptable->len);
+ smem_copy_ram_ptable((void*)smem_ram_ptable);
+
return 1;
}
+
+/* RAM Partition table from SMEM */
+static uint32_t buffer[sizeof(struct smem_ram_ptable_v1)];
+int smem_ram_ptable_init_v1()
+{
+ uint32_t i;
+ uint32_t ret;
+ uint32_t version;
+ uint32_t smem_ram_ptable_size;
+ struct smem_ram_ptable_hdr *ram_ptable_hdr;
+
+ /* Check smem ram partition table version and decide on length of ram_ptable */
+ ret = smem_read_alloc_entry_offset(SMEM_USABLE_RAM_PARTITION_TABLE,
+ &version,
+ sizeof(version),
+ SMEM_RAM_PTABLE_VERSION_OFFSET);
+
+ if(ret)
+ return 0;
+
+ if(version == SMEM_RAM_PTABLE_VERSION_1)
+ smem_ram_ptable_size = sizeof(struct smem_ram_ptable_v1);
+ else if(version == SMEM_RAM_PTABLE_VERSION_0)
+ smem_ram_ptable_size = sizeof(struct smem_ram_ptable);
+ else
+ {
+ dprintf(CRITICAL,"ERROR: Wrong smem_ram_ptable version: %u", version);
+ ASSERT(0);
+ }
+
+ i = smem_read_alloc_entry(SMEM_USABLE_RAM_PARTITION_TABLE,
+ (void*)buffer,
+ smem_ram_ptable_size);
+ if (i != 0)
+ return 0;
+
+ ram_ptable_hdr = (struct smem_ram_ptable_hdr *)buffer;
+
+ if (ram_ptable_hdr->magic[0] != _SMEM_RAM_PTABLE_MAGIC_1 ||
+ ram_ptable_hdr->magic[1] != _SMEM_RAM_PTABLE_MAGIC_2)
+ return 0;
+
+ smem_copy_ram_ptable((void*)buffer);
+
+ dprintf(SPEW, "smem ram ptable found: ver: %u len: %u\n",
+ ram_ptable_hdr->version, ram_ptable_hdr->len);
+
+ return 1;
+}
+
+void smem_get_ram_ptable_entry(ram_partition *ptn, uint32_t entry)
+{
+ memcpy(ptn, &(ptable.parts[entry]), sizeof(ram_partition));
+}
+
+uint32_t smem_get_ram_ptable_len(void)
+{
+ return ptable.hdr.len;
+}
+
+uint32_t smem_get_ram_ptable_version(void)
+{
+ return ptable.hdr.version;
+}
diff --git a/project/apq8084.mk b/project/apq8084.mk
index cbf43c8..8b1075b 100644
--- a/project/apq8084.mk
+++ b/project/apq8084.mk
@@ -8,7 +8,7 @@
DEBUG := 1
EMMC_BOOT := 1
-ENABLE_SDHCI_SUPPORT := 0
+ENABLE_SDHCI_SUPPORT := 1
#DEFINES += WITH_DEBUG_DCC=1
DEFINES += WITH_DEBUG_UART=1
diff --git a/project/fsm9900.mk b/project/fsm9900.mk
index 8945556..2745b63 100644
--- a/project/fsm9900.mk
+++ b/project/fsm9900.mk
@@ -10,14 +10,13 @@
EMMC_BOOT := 1
ENABLE_SDHCI_SUPPORT := 0
-#DEFINES += WITH_DEBUG_DCC=1
+DEFINES += WITH_DEBUG_DCC=1
DEFINES += WITH_DEBUG_UART=1
#DEFINES += WITH_DEBUG_FBCON=1
DEFINES += DEVICE_TREE=1
#DEFINES += MMC_BOOT_BAM=1
DEFINES += CRYPTO_BAM=1
DEFINES += CRYPTO_REG_ACCESS=1
-DEFINES += ABOOT_IGNORE_BOOT_HEADER_ADDRS=1
#Disable thumb mode
ENABLE_THUMB := false
diff --git a/project/msm8974.mk b/project/msm8974.mk
index b12ea6b..80b310c 100644
--- a/project/msm8974.mk
+++ b/project/msm8974.mk
@@ -9,7 +9,6 @@
DEBUG := 1
EMMC_BOOT := 1
ENABLE_SDHCI_SUPPORT := 1
-ENABLE_USB30_SUPPORT := 1
#DEFINES += WITH_DEBUG_DCC=1
DEFINES += WITH_DEBUG_UART=1
@@ -34,7 +33,3 @@
ifeq ($(ENABLE_SDHCI_SUPPORT),1)
DEFINES += MMC_SDHCI_SUPPORT=1
endif
-
-ifeq ($(ENABLE_USB30_SUPPORT),1)
-DEFINES += USB30_SUPPORT=1
-endif
diff --git a/target/apq8084/init.c b/target/apq8084/init.c
index 0de99e1..3a66d38 100644
--- a/target/apq8084/init.c
+++ b/target/apq8084/init.c
@@ -28,6 +28,7 @@
#include <debug.h>
#include <platform/iomap.h>
+#include <platform/irqs.h>
#include <platform/gpio.h>
#include <reg.h>
#include <target.h>
@@ -48,28 +49,85 @@
#include <scm.h>
#include <platform/clock.h>
#include <platform/gpio.h>
+#include <platform/timer.h>
#include <stdlib.h>
-static uint32_t mmc_sdc_base[] =
- { MSM_SDC1_BASE, MSM_SDC2_BASE, MSM_SDC3_BASE, MSM_SDC4_BASE };
+#define PMIC_ARB_CHANNEL_NUM 0
+#define PMIC_ARB_OWNER_ID 0
+
+#define FASTBOOT_MODE 0x77665500
+
+enum cdp_subtype
+{
+ CDP_SUBTYPE_SMB349 = 0,
+ CDP_SUBTYPE_9x25_SMB349,
+ CDP_SUBTYPE_9x25_SMB1357,
+ CDP_SUBTYPE_9x35,
+ CDP_SUBTYPE_SMB1357
+};
+
+enum mtp_subtype
+{
+ MTP_SUBTYPE_SMB349 = 0,
+ MTP_SUBTYPE_9x25_SMB349,
+ MTP_SUBTYPE_9x25_SMB1357,
+ MTP_SUBTYPE_9x35,
+};
+
+enum rcm_subtype
+{
+ RCM_SUBTYPE_SMB349 = 0,
+ RCM_SUBTYPE_9x25_SMB349,
+ RCM_SUBTYPE_9x25_SMB1357,
+ RCM_SUBTYPE_9x35,
+ RCM_SUBTYPE_SMB1357,
+};
+
+static void set_sdc_power_ctrl(void);
+static uint32_t mmc_pwrctl_base[] =
+ { MSM_SDC1_BASE, MSM_SDC2_BASE };
+
+static uint32_t mmc_sdhci_base[] =
+ { MSM_SDC1_SDHCI_BASE, MSM_SDC2_SDHCI_BASE };
+
+static uint32_t mmc_sdc_pwrctl_irq[] =
+ { SDCC1_PWRCTL_IRQ, SDCC2_PWRCTL_IRQ };
+
+struct mmc_device *dev;
+
+extern void ulpi_write(unsigned val, unsigned reg);
void target_early_init(void)
{
#if WITH_DEBUG_UART
- uart_dm_init(2, 0, BLSP1_UART1_BASE);
+ uart_dm_init(7, 0, BLSP2_UART1_BASE);
#endif
}
/* Return 1 if vol_up pressed */
static int target_volume_up()
{
- return 0;
+ uint8_t status = 0;
+ struct pm8x41_gpio gpio;
+
+ /* Configure the GPIO */
+ gpio.direction = PM_GPIO_DIR_IN;
+ gpio.function = 0;
+ gpio.pull = PM_GPIO_PULL_UP_30;
+ gpio.vin_sel = 2;
+
+ pm8x41_gpio_config(2, &gpio);
+
+ /* Get status of P_GPIO_2 */
+ pm8x41_gpio_get(2, &status);
+
+ return !status; /* active low */
}
/* Return 1 if vol_down pressed */
uint32_t target_volume_down()
{
- return 0;
+ return pm8x41_resin_status();
}
static void target_keystatus()
@@ -83,30 +141,33 @@
keys_post_event(KEY_VOLUMEUP, 1);
}
-static void target_mmc_mci_init()
+void target_uninit(void)
{
- uint32_t base_addr;
- uint8_t slot;
-
- slot = MMC_SLOT;
- base_addr = mmc_sdc_base[slot - 1];
-
- if (mmc_boot_main(slot, base_addr))
- {
- dprintf(CRITICAL, "mmc init failed!");
- ASSERT(0);
- }
+ mmc_put_card_to_sleep(dev);
}
-/*
- * Function to set the capabilities for the host
- */
-void target_mmc_caps(struct mmc_host *host)
+/* Do target specific usb initialization */
+void target_usb_init(void)
{
- host->caps.bus_width = MMC_BOOT_BUS_WIDTH_8_BIT;
- host->caps.ddr_mode = 1;
- host->caps.hs200_mode = 1;
- host->caps.hs_clk_rate = MMC_CLK_96MHZ;
+ uint32_t val;
+
+ /* Select and enable external configuration with USB PHY */
+ ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_SET);
+
+ /* Enable sess_vld */
+ val = readl(USB_GENCONFIG_2) | GEN2_SESS_VLD_CTRL_EN;
+ writel(val, USB_GENCONFIG_2);
+
+ /* Enable external vbus configuration in the LINK */
+ val = readl(USB_USBCMD);
+ val |= SESS_VLD_CTRL;
+ writel(val, USB_USBCMD);
+}
+
+void target_usb_stop(void)
+{
+ /* Disable VBUS mimicing in the controller. */
+ ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_CLEAR);
}
static void set_sdc_power_ctrl()
@@ -132,24 +193,38 @@
tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg));
}
-void target_init(void)
+void target_sdc_init()
{
- dprintf(INFO, "target_init()\n");
+ struct mmc_config_data config;
- target_keystatus();
+ /* Set drive strength & pull ctrl values */
+ set_sdc_power_ctrl();
- /*
- * Set drive strength & pull ctrl for
- * emmc
- */
- /*Uncomment during bringup after the pull up values are finalized*/
- //set_sdc_power_ctrl();
+ config.bus_width = DATA_BUS_WIDTH_8BIT;
+ config.max_clk_rate = MMC_CLK_200MHZ;
- target_mmc_mci_init();
+ /* Try slot 1*/
+ config.slot = 1;
+ config.sdhc_base = mmc_sdhci_base[config.slot - 1];
+ config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
+ config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
- /*
- * MMC initialization is complete, read the partition table info
- */
+ if (!(dev = mmc_init(&config)))
+ {
+ /* Try slot 2 */
+ config.slot = 2;
+ config.sdhc_base = mmc_sdhci_base[config.slot - 1];
+ config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
+ config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
+
+ if (!(dev = mmc_init(&config)))
+ {
+ dprintf(CRITICAL, "mmc init failed!");
+ ASSERT(0);
+ }
+ }
+
+ /* MMC initialization is complete, read the partition table info */
if (partition_read_table())
{
dprintf(CRITICAL, "Error reading the partition table info\n");
@@ -157,53 +232,132 @@
}
}
+struct mmc_device *target_mmc_device()
+{
+ return dev;
+}
+
+void target_init(void)
+{
+ dprintf(INFO, "target_init()\n");
+
+ spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID);
+
+ target_keystatus();
+
+ target_sdc_init();
+}
+
unsigned board_machtype(void)
{
return LINUX_MACHTYPE_UNKNOWN;
}
-void target_fastboot_init(void)
-{
- /* Set the BOOT_DONE flag in PM8921 */
-}
-
/* Detect the target type */
void target_detect(struct board_data *board)
{
board->target = LINUX_MACHTYPE_UNKNOWN;
}
+void set_cdp_baseband(struct board_data *board)
+{
+
+ uint32_t platform_subtype;
+ platform_subtype = board->platform_subtype;
+
+ switch(platform_subtype) {
+ case CDP_SUBTYPE_9x25_SMB349:
+ case CDP_SUBTYPE_9x25_SMB1357:
+ case CDP_SUBTYPE_9x35:
+ board->baseband = BASEBAND_MDM;
+ break;
+ case CDP_SUBTYPE_SMB349:
+ case CDP_SUBTYPE_SMB1357:
+ board->baseband = BASEBAND_APQ;
+ break;
+ default:
+ dprintf(CRITICAL, "CDP platform subtype :%u is not supported\n",
+ platform_subtype);
+ ASSERT(0);
+ };
+
+}
+
+void set_mtp_baseband(struct board_data *board)
+{
+
+ uint32_t platform_subtype;
+ platform_subtype = board->platform_subtype;
+
+ switch(platform_subtype) {
+ case MTP_SUBTYPE_9x25_SMB349:
+ case MTP_SUBTYPE_9x25_SMB1357:
+ case MTP_SUBTYPE_9x35:
+ board->baseband = BASEBAND_MDM;
+ break;
+ case MTP_SUBTYPE_SMB349:
+ board->baseband = BASEBAND_APQ;
+ break;
+ default:
+ dprintf(CRITICAL, "MTP platform subtype :%u is not supported\n",
+ platform_subtype);
+ ASSERT(0);
+ };
+}
+
+void set_rcm_baseband(struct board_data *board)
+{
+ uint32_t platform_subtype;
+ platform_subtype = board->platform_subtype;
+
+ switch(platform_subtype) {
+ case RCM_SUBTYPE_9x25_SMB349:
+ case RCM_SUBTYPE_9x25_SMB1357:
+ case RCM_SUBTYPE_9x35:
+ board->baseband = BASEBAND_MDM;
+ break;
+ case RCM_SUBTYPE_SMB349:
+ case RCM_SUBTYPE_SMB1357:
+ board->baseband = BASEBAND_APQ;
+ break;
+ default:
+ dprintf(CRITICAL, "RCM platform subtype :%u is not supported\n",
+ platform_subtype);
+ ASSERT(0);
+ };
+}
+
+
+
/* Detect the modem type */
void target_baseband_detect(struct board_data *board)
{
uint32_t platform;
uint32_t platform_subtype;
+ uint32_t platform_hardware;
platform = board->platform;
- platform_subtype = board->platform_subtype;
- /*
- * Look for platform subtype if present, else
- * check for platform type to decide on the
- * baseband type
- */
- switch(platform_subtype) {
- case HW_PLATFORM_SUBTYPE_UNKNOWN:
+ platform_hardware = board->platform_hw;
+
+ switch(platform_hardware) {
+ case HW_PLATFORM_SURF:
+ set_cdp_baseband(board);
break;
-
- default:
- dprintf(CRITICAL, "Platform Subtype : %u is not supported\n",platform_subtype);
- ASSERT(0);
- };
-
- switch(platform) {
- case APQ8084:
+ case HW_PLATFORM_MTP:
+ set_mtp_baseband(board);
+ break;
+ case HW_PLATFORM_RCM:
+ set_rcm_baseband(board);
+ break;
+ case HW_PLATFORM_LIQUID:
board->baseband = BASEBAND_APQ;
break;
default:
- dprintf(CRITICAL, "Platform type: %u is not supported\n",platform);
+ dprintf(CRITICAL, "Platform :%u is not supported\n",
+ platform_hardware);
ASSERT(0);
- }
+ };
}
unsigned target_baseband()
@@ -222,8 +376,36 @@
unsigned check_reboot_mode(void)
{
+ uint32_t restart_reason = 0;
+ uint32_t restart_reason_addr;
+
+ restart_reason_addr = RESTART_REASON_ADDR;
+
+ /* Read reboot reason and scrub it */
+ restart_reason = readl(restart_reason_addr);
+ writel(0x00, restart_reason_addr);
+
+ return restart_reason;
}
void reboot_device(unsigned reboot_reason)
{
+ uint8_t reset_type = 0;
+
+ /* Write the reboot reason */
+ writel(reboot_reason, RESTART_REASON_ADDR);
+
+ if(reboot_reason == FASTBOOT_MODE)
+ reset_type = PON_PSHOLD_WARM_RESET;
+ else
+ reset_type = PON_PSHOLD_HARD_RESET;
+
+ pm8x41_reset_configure(reset_type);
+
+ /* Drop PS_HOLD for MSM */
+ writel(0x00, MPM2_MPM_PS_HOLD);
+
+ mdelay(5000);
+
+ dprintf(CRITICAL, "Rebooting failed\n");
}
diff --git a/target/apq8084/meminfo.c b/target/apq8084/meminfo.c
index 745657b..7358027 100644
--- a/target/apq8084/meminfo.c
+++ b/target/apq8084/meminfo.c
@@ -35,31 +35,32 @@
#include <platform/iomap.h>
#include <dev_tree.h>
-/* Funtion to add the ram partition entries into device tree.
- * The function assumes that all the entire fixed memory regions should
- * be listed in the first bank of the passed in ddr regions.
- */
uint32_t target_dev_tree_mem(void *fdt, uint32_t memory_node_offset)
{
- struct smem_ram_ptable ram_ptable;
- unsigned int i;
+ ram_partition ptn_entry;
+ unsigned int index;
int ret = 0;
+ uint32_t len = 0;
/* Make sure RAM partition table is initialized */
- ASSERT(smem_ram_ptable_init(&ram_ptable));
+ ASSERT(smem_ram_ptable_init_v1());
+
+ len = smem_get_ram_ptable_len();
/* Calculating the size of the mem_info_ptr */
- for (i = 0 ; i < ram_ptable.len; i++)
+ for (index = 0 ; index < len; index++)
{
- if((ram_ptable.parts[i].category == SDRAM) &&
- (ram_ptable.parts[i].type == SYS_MEMORY))
+ smem_get_ram_ptable_entry(&ptn_entry, index);
+
+ if((ptn_entry.category == SDRAM) &&
+ (ptn_entry.type == SYS_MEMORY))
{
/* Pass along all other usable memory regions to Linux */
ret = dev_tree_add_mem_info(fdt,
memory_node_offset,
- ram_ptable.parts[i].start,
- ram_ptable.parts[i].size);
+ ptn_entry.start,
+ ptn_entry.size);
if (ret)
{
diff --git a/target/apq8084/rules.mk b/target/apq8084/rules.mk
index aa2abf1..ef4c377 100644
--- a/target/apq8084/rules.mk
+++ b/target/apq8084/rules.mk
@@ -9,7 +9,7 @@
BASE_ADDR := 0x0000000
-SCRATCH_ADDR := 0xFF00000
+SCRATCH_ADDR := 0x10000000
DEFINES += DISPLAY_SPLASH_SCREEN=0
DEFINES += DISPLAY_TYPE_MIPI=1
diff --git a/target/fsm9900/init.c b/target/fsm9900/init.c
index 8bfc791..eed402c 100644
--- a/target/fsm9900/init.c
+++ b/target/fsm9900/init.c
@@ -410,12 +410,27 @@
/* Check if MSM needs VBUS mimic for USB */
static int target_needs_vbus_mimic()
{
- return 0;
+ return 1;
}
/* Do target specific usb initialization */
void target_usb_init(void)
{
+ uint32_t val;
+
+ if (target_needs_vbus_mimic()) {
+ /* Select and enable external configuration with USB PHY */
+ ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_SET);
+
+ /* Enable sess_vld */
+ val = readl(USB_GENCONFIG_2) | GEN2_SESS_VLD_CTRL_EN;
+ writel(val, USB_GENCONFIG_2);
+
+ /* Enable external vbus configuration in the LINK */
+ val = readl(USB_USBCMD);
+ val |= SESS_VLD_CTRL;
+ writel(val, USB_USBCMD);
+ }
}
/* Returns 1 if target supports continuous splash screen. */
diff --git a/target/msm8226/include/target/display.h b/target/msm8226/include/target/display.h
index a2cb92d..62f0eac 100755
--- a/target/msm8226/include/target/display.h
+++ b/target/msm8226/include/target/display.h
@@ -53,11 +53,6 @@
0, 0, 0, 0, 0, 0
};
-static struct panel_reset_sequence reset_sequence = {
- { 1, 0, 1, }, { 20, 20, 20, }, 2
-};
-
-
/*---------------------------------------------------------------------------*/
/* LDO configuration */
/*---------------------------------------------------------------------------*/
@@ -103,7 +98,7 @@
#define msm8226_DSI_FEATURE_ENABLE 0
-#define MIPI_FB_ADDR 0x0F100000
+#define MIPI_FB_ADDR 0x03200000
#define MIPI_HSYNC_PULSE_WIDTH 12
#define MIPI_HSYNC_BACK_PORCH_DCLK 32
@@ -114,6 +109,4 @@
#define MIPI_VSYNC_FRONT_PORCH_LINES 9
extern int mdss_dsi_phy_init(struct mipi_dsi_panel_config *, uint32_t ctl_base);
-extern int mdss_dsi_uniphy_pll_config(uint32_t ctl_base);
-int mdss_dsi_auto_pll_config(struct mipi_dsi_panel_config *);
#endif
diff --git a/target/msm8226/init.c b/target/msm8226/init.c
index 7b31f43..cc97909 100644
--- a/target/msm8226/init.c
+++ b/target/msm8226/init.c
@@ -245,6 +245,8 @@
target_keystatus();
+ target_sdc_init();
+
/* Display splash screen if enabled */
#if DISPLAY_SPLASH_SCREEN
dprintf(SPEW, "Display Init: Start\n");
@@ -252,8 +254,6 @@
dprintf(SPEW, "Display Init: Done\n");
#endif
- target_sdc_init();
-
if (target_use_signed_kernel())
target_crypto_init_params();
}
@@ -317,9 +317,15 @@
case MSM8926:
case MSM8126:
case MSM8326:
+ case MSM8528:
+ case MSM8628:
+ case MSM8228:
+ case MSM8928:
+ case MSM8128:
board->baseband = BASEBAND_MSM;
break;
case APQ8026:
+ case APQ8028:
board->baseband = BASEBAND_APQ;
break;
default:
@@ -456,6 +462,8 @@
dload_util_write_cookie(mode == NORMAL_DLOAD ?
DLOAD_MODE_ADDR : EMERGENCY_DLOAD_MODE_ADDR, mode);
+ pm8x41_clear_pmic_watchdog();
+
return 0;
}
diff --git a/dev/gcdb/display/oem_panel.c b/target/msm8226/oem_panel.c
similarity index 80%
rename from dev/gcdb/display/oem_panel.c
rename to target/msm8226/oem_panel.c
index ce90e75..17955a7 100755
--- a/dev/gcdb/display/oem_panel.c
+++ b/target/msm8226/oem_panel.c
@@ -46,6 +46,7 @@
#include "include/panel_hx8394a_720p_video.h"
#include "include/panel_nt35596_1080p_video.h"
#include "include/panel_nt35521_720p_video.h"
+#include "include/panel_ssd2080m_720p_video.h"
/*---------------------------------------------------------------------------*/
/* static panel selection variable */
@@ -56,7 +57,8 @@
NT35590_720P_VIDEO_PANEL,
NT35596_1080P_VIDEO_PANEL,
HX8394A_720P_VIDEO_PANEL,
-NT35521_720P_VIDEO_PANEL
+NT35521_720P_VIDEO_PANEL,
+SSD2080M_720P_VIDEO_PANEL
};
static uint32_t panel_id;
@@ -112,6 +114,8 @@
panelstruct->laneconfig = &toshiba_720p_video_lane_config;
panelstruct->paneltiminginfo
= &toshiba_720p_video_timing_info;
+ panelstruct->panelresetseq
+ = &toshiba_720p_video_panel_reset_seq;
panelstruct->backlightinfo = &toshiba_720p_video_backlight;
pinfo->mipi.panel_cmds
= toshiba_720p_video_on_command;
@@ -130,6 +134,8 @@
panelstruct->laneconfig = &nt35590_720p_video_lane_config;
panelstruct->paneltiminginfo
= &nt35590_720p_video_timing_info;
+ panelstruct->panelresetseq
+ = &nt35590_720p_video_panel_reset_seq;
panelstruct->backlightinfo = &nt35590_720p_video_backlight;
pinfo->mipi.panel_cmds
= nt35590_720p_video_on_command;
@@ -148,6 +154,8 @@
panelstruct->laneconfig = &nt35521_720p_video_lane_config;
panelstruct->paneltiminginfo
= &nt35521_720p_video_timing_info;
+ panelstruct->panelresetseq
+ = &nt35521_720p_video_panel_reset_seq;
panelstruct->backlightinfo = &nt35521_720p_video_backlight;
pinfo->mipi.panel_cmds
= nt35521_720p_video_on_command;
@@ -156,6 +164,26 @@
memcpy(phy_db->timing,
nt35521_720p_video_timings, TIMING_SIZE);
break;
+ case SSD2080M_720P_VIDEO_PANEL:
+ panelstruct->paneldata = &ssd2080m_720p_video_panel_data;
+ panelstruct->panelres = &ssd2080m_720p_video_panel_res;
+ panelstruct->color = &ssd2080m_720p_video_color;
+ panelstruct->videopanel = &ssd2080m_720p_video_video_panel;
+ panelstruct->commandpanel = &ssd2080m_720p_video_command_panel;
+ panelstruct->state = &ssd2080m_720p_video_state;
+ panelstruct->laneconfig = &ssd2080m_720p_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &ssd2080m_720p_video_timing_info;
+ panelstruct->panelresetseq
+ = &ssd2080m_720p_video_panel_reset_seq;
+ panelstruct->backlightinfo = &ssd2080m_720p_video_backlight;
+ pinfo->mipi.panel_cmds
+ = ssd2080m_720p_video_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = SSD2080M_720P_VIDEO_ON_COMMAND;
+ memcpy(phy_db->timing,
+ ssd2080m_720p_video_timings, TIMING_SIZE);
+ break;
case HX8394A_720P_VIDEO_PANEL:
panelstruct->paneldata = &hx8394a_720p_video_panel_data;
panelstruct->panelres = &hx8394a_720p_video_panel_res;
@@ -166,6 +194,8 @@
panelstruct->laneconfig = &hx8394a_720p_video_lane_config;
panelstruct->paneltiminginfo
= &hx8394a_720p_video_timing_info;
+ panelstruct->panelresetseq
+ = &hx8394a_720p_video_panel_reset_seq;
panelstruct->backlightinfo = &hx8394a_720p_video_backlight;
pinfo->mipi.panel_cmds
= hx8394a_720p_video_on_command;
@@ -184,6 +214,8 @@
panelstruct->state = &nt35590_720p_cmd_state;
panelstruct->laneconfig = &nt35590_720p_cmd_lane_config;
panelstruct->paneltiminginfo = &nt35590_720p_cmd_timing_info;
+ panelstruct->panelresetseq
+ = &nt35590_720p_cmd_panel_reset_seq;
panelstruct->backlightinfo = &nt35590_720p_cmd_backlight;
pinfo->mipi.panel_cmds
= nt35590_720p_cmd_on_command;
@@ -202,6 +234,8 @@
panelstruct->laneconfig = &nt35596_1080p_video_lane_config;
panelstruct->paneltiminginfo
= &nt35596_1080p_video_timing_info;
+ panelstruct->panelresetseq
+ = &nt35596_1080p_video_panel_reset_seq;
panelstruct->backlightinfo
= &nt35596_1080p_video_backlight;
pinfo->mipi.panel_cmds
@@ -219,7 +253,6 @@
struct mdss_dsi_phy_ctrl *phy_db)
{
uint32_t hw_id = board_hardware_id();
- uint32_t platformid = board_platform_id();
uint32_t target_id = board_target_id();
uint32_t nt35590_panel_id = NT35590_720P_VIDEO_PANEL;
@@ -227,56 +260,31 @@
nt35590_panel_id = NT35590_720P_CMD_PANEL;
#endif
- switch (platformid) {
- case MSM8974:
- switch (hw_id) {
- case HW_PLATFORM_FLUID:
- case HW_PLATFORM_MTP:
- case HW_PLATFORM_SURF:
- panel_id = TOSHIBA_720P_VIDEO_PANEL;
- break;
- default:
- dprintf(CRITICAL, "Display not enabled for %d HW type\n"
- , hw_id);
- return false;
+ switch (hw_id) {
+ case HW_PLATFORM_QRD:
+ if (board_hardware_subtype() == 2) { //HW_PLATFORM_SUBTYPE_SKUF
+ panel_id = NT35521_720P_VIDEO_PANEL;
+ } else if (board_hardware_subtype() == 5) { //HW_PLATFORM_SUBTYPE_SKUG
+ panel_id = SSD2080M_720P_VIDEO_PANEL;
+ } else {
+ if (((target_id >> 16) & 0xFF) == 0x1) //EVT
+ panel_id = nt35590_panel_id;
+ else if (((target_id >> 16) & 0xFF) == 0x2) //DVT
+ panel_id = HX8394A_720P_VIDEO_PANEL;
+ else {
+ dprintf(CRITICAL, "Not supported device, target_id=%x\n"
+ , target_id);
+ return false;
+ }
}
break;
- case MSM8826:
- case MSM8626:
- case MSM8226:
- case MSM8926:
- case MSM8126:
- case MSM8326:
- case APQ8026:
- switch (hw_id) {
- case HW_PLATFORM_QRD:
- if (board_hardware_subtype() == 2) {
- panel_id = NT35521_720P_VIDEO_PANEL;
- } else {
- if (((target_id >> 16) & 0xFF) == 0x1) //EVT
- panel_id = nt35590_panel_id;
- else if (((target_id >> 16) & 0xFF) == 0x2) //DVT
- panel_id = HX8394A_720P_VIDEO_PANEL;
- else {
- dprintf(CRITICAL, "Not supported device, target_id=%x\n"
- , target_id);
- return false;
- }
- }
- break;
- case HW_PLATFORM_MTP:
- case HW_PLATFORM_SURF:
- panel_id = nt35590_panel_id;
- break;
- default:
- dprintf(CRITICAL, "Display not enabled for %d HW type\n"
- , hw_id);
- return false;
- }
+ case HW_PLATFORM_MTP:
+ case HW_PLATFORM_SURF:
+ panel_id = nt35590_panel_id;
break;
default:
- dprintf(CRITICAL, "GCDB:Display: Platform id:%d not supported\n"
- , platformid);
+ dprintf(CRITICAL, "Display not enabled for %d HW type\n"
+ , hw_id);
return false;
}
diff --git a/target/msm8226/rules.mk b/target/msm8226/rules.mk
index 0d338c8..f5c9596 100755
--- a/target/msm8226/rules.mk
+++ b/target/msm8226/rules.mk
@@ -41,4 +41,5 @@
OBJS += \
$(LOCAL_DIR)/init.o \
$(LOCAL_DIR)/meminfo.o \
- $(LOCAL_DIR)/target_display.o
+ $(LOCAL_DIR)/target_display.o \
+ $(LOCAL_DIR)/oem_panel.o
diff --git a/target/msm8226/target_display.c b/target/msm8226/target_display.c
index 5b719cc..04e0615 100755
--- a/target/msm8226/target_display.c
+++ b/target/msm8226/target_display.c
@@ -40,6 +40,7 @@
#include <platform/iomap.h>
#include <target/display.h>
+#include "include/panel.h"
#include "include/display_resource.h"
#define HFPLL_LDO_ID 8
@@ -49,9 +50,153 @@
.led1_brightness = (0x0F << 8) | 0xEF,
.max_duty_cycle = 0x01,
.ovp = 0x0,
- .full_current_scale = 0x19
+ .full_current_scale = 0x19,
+ .fdbck = 0x1
};
+static uint32_t dsi_pll_enable_seq_m(uint32_t ctl_base)
+{
+ uint32_t i = 0;
+ uint32_t pll_locked = 0;
+
+ mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+
+ /*
+ * Add hardware recommended delays between register writes for
+ * the updates to take effect. These delays are necessary for the
+ * PLL to successfully lock
+ */
+ writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ udelay(1000);
+
+ mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
+ pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+ for (i = 0; (i < 4) && !pll_locked; i++) {
+ writel(0x07, ctl_base + 0x0220); /* GLB CFG */
+ if (i != 0)
+ writel(0x34, ctl_base + 0x00270); /* CAL CFG1*/
+ udelay(1);
+ writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ udelay(1000);
+ mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
+ pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+ }
+
+ return pll_locked;
+}
+
+static uint32_t dsi_pll_enable_seq_d(uint32_t ctl_base)
+{
+ uint32_t pll_locked = 0;
+
+ mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+
+ /*
+ * Add hardware recommended delays between register writes for
+ * the updates to take effect. These delays are necessary for the
+ * PLL to successfully lock
+ */
+ writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x07, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x07, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ udelay(1000);
+
+ mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
+ pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+
+ return pll_locked;
+}
+
+static uint32_t dsi_pll_enable_seq_f1(uint32_t ctl_base)
+{
+ uint32_t pll_locked = 0;
+
+ mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+
+ /*
+ * Add hardware recommended delays between register writes for
+ * the updates to take effect. These delays are necessary for the
+ * PLL to successfully lock
+ */
+ writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x0d, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ udelay(1000);
+
+ mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
+ pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+
+ return pll_locked;
+}
+
+static uint32_t dsi_pll_enable_seq_c(uint32_t ctl_base)
+{
+ uint32_t pll_locked = 0;
+
+ mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+
+ /*
+ * Add hardware recommended delays between register writes for
+ * the updates to take effect. These delays are necessary for the
+ * PLL to successfully lock
+ */
+ writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ udelay(1000);
+
+ mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
+ pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+
+ return pll_locked;
+}
+
+static uint32_t dsi_pll_enable_seq_e(uint32_t ctl_base)
+{
+ uint32_t pll_locked = 0;
+
+ mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+
+ /*
+ * Add hardware recommended delays between register writes for
+ * the updates to take effect. These delays are necessary for the
+ * PLL to successfully lock
+ */
+ writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ udelay(200);
+ writel(0x0d, ctl_base + 0x0220); /* GLB CFG */
+ udelay(1);
+ writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ udelay(1000);
+
+ mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
+ pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+
+ return pll_locked;
+}
+
int target_backlight_ctrl(uint8_t enable)
{
dprintf(SPEW, "target_backlight_ctrl\n");
@@ -64,6 +209,19 @@
return 0;
}
+static void dsi_pll_enable_seq(uint32_t ctl_base)
+{
+ if (dsi_pll_enable_seq_m(ctl_base)) {
+ } else if (dsi_pll_enable_seq_d(ctl_base)) {
+ } else if (dsi_pll_enable_seq_d(ctl_base)) {
+ } else if (dsi_pll_enable_seq_f1(ctl_base)) {
+ } else if (dsi_pll_enable_seq_c(ctl_base)) {
+ } else if (dsi_pll_enable_seq_e(ctl_base)) {
+ } else {
+ dprintf(CRITICAL, "Not able to enable the pll\n");
+ }
+}
+
int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
{
struct mdss_dsi_pll_config *pll_data;
@@ -74,7 +232,8 @@
if (enable) {
mdp_gdsc_ctrl(enable);
mdp_clock_init();
- mdss_dsi_auto_pll_config(pll_data);
+ mdss_dsi_auto_pll_config(MIPI_DSI0_BASE, pll_data);
+ dsi_pll_enable_seq(MIPI_DSI0_BASE);
mmss_clock_auto_pll_init(pll_data->pclk_m,
pll_data->pclk_n,
pll_data->pclk_d);
@@ -89,40 +248,37 @@
return 0;
}
-int target_panel_reset(uint8_t enable,
- struct gpio_pin *resetgpio,
- struct gpio_pin *enablegpio,
- struct panel_reset_sequence *resetseq)
+int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
+ struct msm_panel_info *pinfo)
{
int ret = NO_ERROR;
if (enable) {
- gpio_tlmm_config(resetgpio->pin_id, 0,
- resetgpio->pin_direction, resetgpio->pin_pull,
- resetgpio->pin_strength, resetgpio->pin_state);
+ gpio_tlmm_config(reset_gpio.pin_id, 0,
+ reset_gpio.pin_direction, reset_gpio.pin_pull,
+ reset_gpio.pin_strength, reset_gpio.pin_state);
- gpio_set_dir(resetgpio->pin_id, 2);
+ gpio_set_dir(reset_gpio.pin_id, 2);
- gpio_set_value(resetgpio->pin_id, resetseq->pin_state[0]);
+ gpio_set_value(reset_gpio.pin_id, resetseq->pin_state[0]);
mdelay(resetseq->sleep[0]);
- gpio_set_value(resetgpio->pin_id, resetseq->pin_state[1]);
+ gpio_set_value(reset_gpio.pin_id, resetseq->pin_state[1]);
mdelay(resetseq->sleep[1]);
- gpio_set_value(resetgpio->pin_id, resetseq->pin_state[2]);
+ gpio_set_value(reset_gpio.pin_id, resetseq->pin_state[2]);
mdelay(resetseq->sleep[2]);
} else if(!target_cont_splash_screen()) {
- gpio_set_value(resetgpio->pin_id, 0);
+ gpio_set_value(reset_gpio.pin_id, 0);
}
return ret;
}
-int target_ldo_ctrl(uint8_t enable, struct ldo_entry ldo_entry_array[],
- uint8_t ldo_array_size)
+int target_ldo_ctrl(uint8_t enable)
{
uint32_t ret = NO_ERROR;
uint32_t ldocounter = 0;
uint32_t pm8x41_ldo_base = 0x13F00;
- while (ldocounter < ldo_array_size) {
+ while (ldocounter < TOTAL_LDO_DEFINED) {
struct pm8x41_ldo ldo_entry = LDO((pm8x41_ldo_base +
0x100 * ldo_entry_array[ldocounter].ldo_id),
ldo_entry_array[ldocounter].ldo_type);
diff --git a/target/msm8610/include/target/display.h b/target/msm8610/include/target/display.h
index 4c8bd15..c6e93c4 100644
--- a/target/msm8610/include/target/display.h
+++ b/target/msm8610/include/target/display.h
@@ -29,8 +29,80 @@
#ifndef _TARGET_MSM8610_DISPLAY_H
#define _TARGET_MSM8610_DISPLAY_H
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include <display_resource.h>
-#define MIPI_FB_ADDR 0x0D200000
+/*---------------------------------------------------------------------------*/
+/* GPIO configuration */
+/*---------------------------------------------------------------------------*/
+static struct gpio_pin reset_gpio = {
+ "msmgpio", 41, 3, 1, 0, 1
+};
+
+static struct gpio_pin enable_gpio = {
+ 0, 0, 0, 0, 0, 0
+};
+
+static struct gpio_pin te_gpio = {
+ "msmgpio", 12, 0, 2, 0, 1
+};
+
+static struct gpio_pin pwm_gpio = {
+ 0, 0, 0, 0, 0, 0
+};
+
+static struct gpio_pin mode_gpio = {
+ "msmgpio", 7, 3, 1, 0, 1
+};
+
+
+/*---------------------------------------------------------------------------*/
+/* Supply configuration */
+/*---------------------------------------------------------------------------*/
+static struct ldo_entry ldo_entry_array[] = {
+{ "vddio", 14, 0, 1800000, 100000, 100, 0, 0, 0, 0},
+{ "vdda", 19, 0, 2850000, 100000, 100, 0, 0, 0, 0},
+};
+
+#define TOTAL_LDO_DEFINED 2
+
+/*---------------------------------------------------------------------------*/
+/* Target Physical configuration */
+/*---------------------------------------------------------------------------*/
+
+static const uint32_t panel_strength_ctrl[] = {
+ 0xff, 0x06
+};
+
+static const char panel_bist_ctrl[] = {
+ 0x03, 0x03, 0x00, 0x00, 0x0f, 0x00
+};
+
+static const uint32_t panel_regulator_settings[] = {
+ 0x02, 0x08, 0x05, 0x00, 0x20, 0x03, 0x00
+};
+
+static const char panel_lane_config[] = {
+ 0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+ 0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+ 0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+ 0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+ 0x40, 0x67, 0x00, 0x00, 0x00, 0x01, 0x88, 0x00, 0x00
+};
+
+static const uint32_t panel_physical_ctrl[] = {
+ 0x7f, 0x00, 0x00, 0x00
+};
+
+/*---------------------------------------------------------------------------*/
+/* Other Configuration */
+/*---------------------------------------------------------------------------*/
+
+#define msm8610_DSI_FEATURE_ENABLE 0
+
+#define MIPI_FB_ADDR 0x03200000
#define MIPI_HSYNC_PULSE_WIDTH 8
#define MIPI_HSYNC_BACK_PORCH_DCLK 40
diff --git a/target/msm8610/init.c b/target/msm8610/init.c
index a116dbe..f28677f 100644
--- a/target/msm8610/init.c
+++ b/target/msm8610/init.c
@@ -122,12 +122,6 @@
/* Set drive strength & pull ctrl values */
set_sdc_power_ctrl();
- /* Display splash screen if enabled */
- dprintf(SPEW, "Display Init: Start\n");
- display_init();
- dprintf(SPEW, "Display Init: Done\n");
-
-
config.bus_width = DATA_BUS_WIDTH_8BIT;
config.max_clk_rate = MMC_CLK_200MHZ;
@@ -169,6 +163,11 @@
target_keystatus();
target_sdc_init();
+
+ /* Display splash screen if enabled */
+ dprintf(SPEW, "Display Init: Start\n");
+ display_init();
+ dprintf(SPEW, "Display Init: Done\n");
}
void target_uninit(void)
diff --git a/target/msm8610/oem_panel.c b/target/msm8610/oem_panel.c
new file mode 100755
index 0000000..e532b56
--- /dev/null
+++ b/target/msm8610/oem_panel.c
@@ -0,0 +1,226 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <err.h>
+#include <smem.h>
+#include <msm_panel.h>
+#include <board.h>
+#include <mipi_dsi.h>
+
+#include "include/panel.h"
+#include "panel_display.h"
+
+/*---------------------------------------------------------------------------*/
+/* GCDB Panel Database */
+/*---------------------------------------------------------------------------*/
+#include "include/panel_truly_wvga_cmd.h"
+#include "include/panel_truly_wvga_video.h"
+#include "include/panel_hx8379a_wvga_video.h"
+#include "include/panel_otm8018b_fwvga_video.h"
+#include "include/panel_nt35590_720p_video.h"
+
+/*---------------------------------------------------------------------------*/
+/* static panel selection variable */
+/*---------------------------------------------------------------------------*/
+enum {
+TRULY_WVGA_CMD_PANEL,
+TRULY_WVGA_VIDEO_PANEL,
+HX8379A_WVGA_VIDEO_PANEL,
+OTM8018B_FWVGA_VIDEO_PANEL,
+NT35590_720P_VIDEO_PANEL,
+};
+
+static uint32_t panel_id;
+
+int oem_panel_rotation()
+{
+ /* OEM can keep there panel spefic on instructions in this
+ function */
+ return NO_ERROR;
+}
+
+
+int oem_panel_on()
+{
+ /* OEM can keep there panel spefic on instructions in this
+ function */
+ return NO_ERROR;
+}
+
+int oem_panel_off()
+{
+ /* OEM can keep there panel spefic off instructions in this
+ function */
+ return NO_ERROR;
+}
+
+static bool init_panel_data(struct panel_struct *panelstruct,
+ struct msm_panel_info *pinfo,
+ struct mdss_dsi_phy_ctrl *phy_db)
+{
+ switch (panel_id) {
+ case TRULY_WVGA_CMD_PANEL:
+ panelstruct->paneldata = &truly_wvga_cmd_panel_data;
+ panelstruct->panelres = &truly_wvga_cmd_panel_res;
+ panelstruct->color = &truly_wvga_cmd_color;
+ panelstruct->videopanel = &truly_wvga_cmd_video_panel;
+ panelstruct->commandpanel = &truly_wvga_cmd_command_panel;
+ panelstruct->state = &truly_wvga_cmd_state;
+ panelstruct->laneconfig = &truly_wvga_cmd_lane_config;
+ panelstruct->paneltiminginfo
+ = &truly_wvga_cmd_timing_info;
+ panelstruct->panelresetseq
+ = &truly_wvga_cmd_reset_seq;
+ panelstruct->backlightinfo = &truly_wvga_cmd_backlight;
+ pinfo->mipi.panel_cmds
+ = truly_wvga_cmd_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = TRULY_WVGA_CMD_ON_COMMAND;
+ memcpy(phy_db->timing,
+ truly_wvga_cmd_timings, TIMING_SIZE);
+ break;
+ case TRULY_WVGA_VIDEO_PANEL:
+ panelstruct->paneldata = &truly_wvga_video_panel_data;
+ panelstruct->panelres = &truly_wvga_video_panel_res;
+ panelstruct->color = &truly_wvga_video_color;
+ panelstruct->videopanel = &truly_wvga_video_video_panel;
+ panelstruct->commandpanel = &truly_wvga_video_command_panel;
+ panelstruct->state = &truly_wvga_video_state;
+ panelstruct->laneconfig = &truly_wvga_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &truly_wvga_video_timing_info;
+ panelstruct->panelresetseq
+ = &truly_wvga_video_reset_seq;
+ panelstruct->backlightinfo = &truly_wvga_video_backlight;
+ pinfo->mipi.panel_cmds
+ = truly_wvga_video_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = TRULY_WVGA_VIDEO_ON_COMMAND;
+ memcpy(phy_db->timing,
+ truly_wvga_video_timings, TIMING_SIZE);
+ break;
+ case HX8379A_WVGA_VIDEO_PANEL:
+ panelstruct->paneldata = &hx8379a_wvga_video_panel_data;
+ panelstruct->panelres = &hx8379a_wvga_video_panel_res;
+ panelstruct->color = &hx8379a_wvga_video_color;
+ panelstruct->videopanel = &hx8379a_wvga_video_video_panel;
+ panelstruct->commandpanel = &hx8379a_wvga_video_command_panel;
+ panelstruct->state = &hx8379a_wvga_video_state;
+ panelstruct->laneconfig = &hx8379a_wvga_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &hx8379a_wvga_video_timing_info;
+ panelstruct->panelresetseq
+ = &hx8379a_wvga_video_reset_seq;
+ panelstruct->backlightinfo = &hx8379a_wvga_video_backlight;
+ pinfo->mipi.panel_cmds
+ = hx8379a_wvga_video_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = HX8379A_WVGA_VIDEO_ON_COMMAND;
+ memcpy(phy_db->timing,
+ hx8379a_wvga_video_timings, TIMING_SIZE);
+ break;
+ case OTM8018B_FWVGA_VIDEO_PANEL:
+ panelstruct->paneldata = &otm8018b_fwvga_video_panel_data;
+ panelstruct->panelres = &otm8018b_fwvga_video_panel_res;
+ panelstruct->color = &otm8018b_fwvga_video_color;
+ panelstruct->videopanel = &otm8018b_fwvga_video_video_panel;
+ panelstruct->commandpanel = &otm8018b_fwvga_video_command_panel;
+ panelstruct->state = &otm8018b_fwvga_video_state;
+ panelstruct->laneconfig = &otm8018b_fwvga_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &otm8018b_fwvga_video_timing_info;
+ panelstruct->panelresetseq
+ = &otm8018b_fwvga_video_reset_seq;
+ panelstruct->backlightinfo = &otm8018b_fwvga_video_backlight;
+ pinfo->mipi.panel_cmds
+ = otm8018b_fwvga_video_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = OTM8018B_FWVGA_VIDEO_ON_COMMAND;
+ memcpy(phy_db->timing,
+ otm8018b_fwvga_video_timings, TIMING_SIZE);
+ break;
+ case NT35590_720P_VIDEO_PANEL:
+ panelstruct->paneldata = &nt35590_720p_video_panel_data;
+ panelstruct->panelres = &nt35590_720p_video_panel_res;
+ panelstruct->color = &nt35590_720p_video_color;
+ panelstruct->videopanel = &nt35590_720p_video_video_panel;
+ panelstruct->commandpanel = &nt35590_720p_video_command_panel;
+ panelstruct->state = &nt35590_720p_video_state;
+ panelstruct->laneconfig = &nt35590_720p_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &nt35590_720p_video_timing_info;
+ panelstruct->panelresetseq
+ = &nt35590_720p_video_panel_reset_seq;
+ panelstruct->backlightinfo = &nt35590_720p_video_backlight;
+ pinfo->mipi.panel_cmds
+ = nt35590_720p_video_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = NT35590_720P_VIDEO_ON_COMMAND;
+ memcpy(phy_db->timing,
+ nt35590_720p_video_timings, TIMING_SIZE);
+ break;
+ default:
+ dprintf(CRITICAL, "Panel ID not detected %d\n", panel_id);
+ return false;
+ }
+ return true;
+}
+
+bool oem_panel_select(struct panel_struct *panelstruct,
+ struct msm_panel_info *pinfo,
+ struct mdss_dsi_phy_ctrl *phy_db)
+{
+ uint32_t hw_id = board_hardware_id();
+ uint32_t platform_subtype = board_hardware_subtype();
+
+ switch (hw_id) {
+ case HW_PLATFORM_QRD:
+ if ((0 == platform_subtype) || (1 == platform_subtype))
+ panel_id = HX8379A_WVGA_VIDEO_PANEL;
+ else if (3 == platform_subtype)
+ panel_id = OTM8018B_FWVGA_VIDEO_PANEL;
+ break;
+ case HW_PLATFORM_MTP:
+ if (0 == platform_subtype)
+ panel_id = TRULY_WVGA_VIDEO_PANEL;
+ else
+ panel_id = NT35590_720P_VIDEO_PANEL;
+ break;
+
+ case HW_PLATFORM_SURF:
+ panel_id = TRULY_WVGA_VIDEO_PANEL;
+ break;
+ default:
+ dprintf(CRITICAL, "Display not enabled for %d HW type\n", hw_id);
+ return false;
+ }
+
+ return init_panel_data(panelstruct, pinfo, phy_db);
+}
diff --git a/target/msm8610/rules.mk b/target/msm8610/rules.mk
index 92c669f..909e673 100644
--- a/target/msm8610/rules.mk
+++ b/target/msm8610/rules.mk
@@ -1,6 +1,7 @@
LOCAL_DIR := $(GET_LOCAL_DIR)
INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared
+INCLUDES += -I$(LK_TOP_DIR)/dev/gcdb/display -I$(LK_TOP_DIR)/dev/gcdb/display/include
PLATFORM := msm8610
@@ -23,6 +24,7 @@
lib/ptable \
dev/pmic/pm8x41 \
dev/panel/msm \
+ dev/gcdb/display \
lib/libfdt
DEFINES += \
@@ -38,4 +40,5 @@
OBJS += \
$(LOCAL_DIR)/init.o \
$(LOCAL_DIR)/meminfo.o \
- $(LOCAL_DIR)/target_display.o
+ $(LOCAL_DIR)/target_display.o \
+ $(LOCAL_DIR)/oem_panel.o
diff --git a/target/msm8610/target_display.c b/target/msm8610/target_display.c
index 80d8316..3610413 100644
--- a/target/msm8610/target_display.c
+++ b/target/msm8610/target_display.c
@@ -29,7 +29,9 @@
#include <debug.h>
#include <smem.h>
+#include <err.h>
#include <msm_panel.h>
+#include <mipi_dsi.h>
#include <pm8x41.h>
#include <pm8x41_wled.h>
#include <board.h>
@@ -37,21 +39,20 @@
#include <platform/iomap.h>
#include <target/display.h>
-static struct msm_fb_panel_data panel;
-static uint8_t display_enable;
+#include "include/panel.h"
+#include "include/display_resource.h"
-extern int msm_display_init(struct msm_fb_panel_data *pdata);
-extern int msm_display_off();
-extern void dsi_phy_init(struct msm_panel_info *pinfo);
+#define MODE_GPIO_STATE_ENABLE 1
-static int msm8610_backlight(uint8_t enable)
+#define MODE_GPIO_STATE_DISABLE 2
+
+int target_backlight_ctrl(uint8_t enable)
{
struct pm8x41_mpp mpp;
mpp.base = PM8x41_MMP3_BASE;
mpp.mode = MPP_HIGH;
mpp.vin = MPP_VIN3;
- if (enable)
- {
+ if (enable) {
pm8x41_config_output_mpp(&mpp);
pm8x41_enable_mpp(&mpp, MPP_ENABLE);
} else {
@@ -62,41 +63,18 @@
return 0;
}
-void dsi_calc_clk_rate(uint32_t *dsiclk_rate, uint32_t *byteclk_rate)
+int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
{
- uint32_t hbp, hfp, vbp, vfp, hspw, vspw, width, height;
- uint32_t bitclk_rate;
- int frame_rate, lanes;
+ struct mdss_dsi_pll_config *pll_data;
+ dprintf(SPEW, "target_panel_clock\n");
- width = panel.panel_info.xres;
- height = panel.panel_info.yres;
- hbp = panel.panel_info.lcdc.h_back_porch;
- hfp = panel.panel_info.lcdc.h_front_porch;
- hspw = panel.panel_info.lcdc.h_pulse_width;
- vbp = panel.panel_info.lcdc.v_back_porch;
- vfp = panel.panel_info.lcdc.v_front_porch;
- vspw = panel.panel_info.lcdc.v_pulse_width;
- lanes = panel.panel_info.mipi.num_of_lanes;
- frame_rate = panel.panel_info.mipi.frame_rate;
+ pll_data = pinfo->mipi.dsi_pll_config;
- bitclk_rate = (width + hbp + hfp + hspw) * (height + vbp + vfp + vspw);
- bitclk_rate *= frame_rate;
- bitclk_rate *= panel.panel_info.bpp;
- bitclk_rate /= lanes;
-
- *byteclk_rate = bitclk_rate / 8;
- *dsiclk_rate = *byteclk_rate * lanes;
-}
-
-static int msm8610_mdss_dsi_panel_clock(uint8_t enable)
-{
- uint32_t dsiclk_rate, byteclk_rate;
-
- if (enable)
- {
+ if (enable) {
mdp_clock_enable();
- dsi_calc_clk_rate(&dsiclk_rate, &byteclk_rate);
- dsi_clock_enable(dsiclk_rate, byteclk_rate);
+ dsi_clock_enable(
+ pll_data->byte_clock * pinfo->mipi.num_of_lanes,
+ pll_data->byte_clock);
} else if(!target_cont_splash_screen()) {
dsi_clock_disable();
mdp_clock_disable();
@@ -105,118 +83,72 @@
return 0;
}
-static void msm8610_mdss_mipi_panel_reset(int enable)
+int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
+ struct msm_panel_info *pinfo)
{
dprintf(SPEW, "msm8610_mdss_mipi_panel_reset, enable = %d\n", enable);
- if (enable)
- {
- gpio_tlmm_config(41, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_8MA, GPIO_DISABLE);
- gpio_tlmm_config(7, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_8MA, GPIO_DISABLE);
+ if (enable) {
+ gpio_tlmm_config(reset_gpio.pin_id, 0,
+ reset_gpio.pin_direction, reset_gpio.pin_pull,
+ reset_gpio.pin_strength, reset_gpio.pin_state);
+
+ gpio_tlmm_config(mode_gpio.pin_id, 0,
+ mode_gpio.pin_direction, mode_gpio.pin_pull,
+ mode_gpio.pin_strength, mode_gpio.pin_state);
/* reset */
- gpio_set(41, 2);
- mdelay(20);
- gpio_set(41, 0);
- udelay(20);
- gpio_set(41, 2);
- mdelay(20);
+ gpio_set(reset_gpio.pin_id, resetseq->pin_state[0]);
+ mdelay(resetseq->sleep[0]);
+ gpio_set(reset_gpio.pin_id, resetseq->pin_state[1]);
+ mdelay(resetseq->sleep[1]);
+ gpio_set(reset_gpio.pin_id, resetseq->pin_state[2]);
+ mdelay(resetseq->sleep[2]);
- if (panel.panel_info.type == MIPI_VIDEO_PANEL)
- gpio_set(7, 2);
- else if (panel.panel_info.type == MIPI_CMD_PANEL)
- gpio_set(7, 0);
+ if (pinfo->mipi.mode_gpio_state == MODE_GPIO_STATE_ENABLE)
+ gpio_set(mode_gpio.pin_id, 2);
+ else if (pinfo->mipi.mode_gpio_state == MODE_GPIO_STATE_DISABLE)
+ gpio_set(mode_gpio.pin_id, 0);
} else if(!target_cont_splash_screen()) {
- gpio_set(7, 0);
- gpio_set(41, 0);
+ gpio_set(reset_gpio.pin_id, 0);
+ gpio_set(mode_gpio.pin_id, 0);
}
- return;
+ return 0;
}
-static int msm8610_mipi_panel_power(uint8_t enable)
+int target_ldo_ctrl(uint8_t enable)
{
- int ret;
- struct pm8x41_ldo ldo14 = LDO(PM8x41_LDO14, PLDO_TYPE);
- struct pm8x41_ldo ldo19 = LDO(PM8x41_LDO19, PLDO_TYPE);
+ uint32_t ldocounter = 0;
+ uint32_t pm8x41_ldo_base = 0x13F00;
- dprintf(SPEW, "msm8610_mipi_panel_power, enable = %d\n", enable);
- if (enable)
- {
- /* backlight */
- msm8610_backlight(enable);
+ while (ldocounter < TOTAL_LDO_DEFINED) {
+ struct pm8x41_ldo ldo_entry = LDO((pm8x41_ldo_base +
+ 0x100 * ldo_entry_array[ldocounter].ldo_id),
+ ldo_entry_array[ldocounter].ldo_type);
- /* regulators */
- pm8x41_ldo_set_voltage(&ldo14, 1800000);
- pm8x41_ldo_control(&ldo14, enable);
- pm8x41_ldo_set_voltage(&ldo19, 2850000);
- pm8x41_ldo_control(&ldo19, enable);
+ dprintf(SPEW, "Setting %s\n",
+ ldo_entry_array[ldocounter].ldo_id);
- /* reset */
- msm8610_mdss_mipi_panel_reset(enable);
- } else if(!target_cont_splash_screen()) {
- msm8610_backlight(0);
- msm8610_mdss_mipi_panel_reset(enable);
-
- pm8x41_ldo_control(&ldo19, enable);
- pm8x41_ldo_control(&ldo14, enable);
+ /* Set voltage during power on */
+ if (enable) {
+ pm8x41_ldo_set_voltage(&ldo_entry,
+ ldo_entry_array[ldocounter].ldo_voltage);
+ pm8x41_ldo_control(&ldo_entry, enable);
+ } else if(!target_cont_splash_screen()) {
+ pm8x41_ldo_control(&ldo_entry, enable);
+ }
+ ldocounter++;
}
+
return 0;
}
void display_init(void)
{
- uint32_t hw_id = board_hardware_id();
- uint32_t platform_subtype = board_hardware_subtype();
-
- dprintf(SPEW, "display_init(),target_id=%d.\n", hw_id);
- dprintf(SPEW, "display_init(),platform_subtype=%d.\n",
- platform_subtype);
-
- switch (hw_id) {
- case HW_PLATFORM_QRD:
- if ((0 == platform_subtype) || (1 == platform_subtype))
- mipi_hx8379a_video_wvga_init(&(panel.panel_info));
- else if (3 == platform_subtype)
- mipi_otm8018b_video_wvga_init(&(panel.panel_info));
-
- panel.clk_func = msm8610_mdss_dsi_panel_clock;
- panel.power_func = msm8610_mipi_panel_power;
- panel.fb.base = MIPI_FB_ADDR;
- panel.fb.width = panel.panel_info.xres;
- panel.fb.height = panel.panel_info.yres;
- panel.fb.stride = panel.panel_info.xres;
- panel.fb.bpp = panel.panel_info.bpp;
- panel.fb.format = FB_FORMAT_RGB888;
- panel.mdp_rev = MDP_REV_304;
- break;
- case HW_PLATFORM_MTP:
- case HW_PLATFORM_SURF:
- mipi_truly_video_wvga_init(&(panel.panel_info));
- panel.clk_func = msm8610_mdss_dsi_panel_clock;
- panel.power_func = msm8610_mipi_panel_power;
- panel.fb.base = MIPI_FB_ADDR;
- panel.fb.width = panel.panel_info.xres;
- panel.fb.height = panel.panel_info.yres;
- panel.fb.stride = panel.panel_info.xres;
- panel.fb.bpp = panel.panel_info.bpp;
- panel.fb.format = FB_FORMAT_RGB888;
- panel.mdp_rev = MDP_REV_304;
- break;
- default:
- return;
- };
-
- if (msm_display_init(&panel))
- {
- dprintf(CRITICAL, "Display init failed!\n");
- return;
- }
-
- display_enable = 1;
+ gcdb_display_init(MDP_REV_304, MIPI_FB_ADDR);
}
void display_shutdown(void)
{
- if (display_enable)
- msm_display_off();
+ gcdb_display_shutdown();
}
diff --git a/target/msm8974/include/target/display.h b/target/msm8974/include/target/display.h
index 468b6d5..8897239 100644
--- a/target/msm8974/include/target/display.h
+++ b/target/msm8974/include/target/display.h
@@ -29,8 +29,68 @@
#ifndef _TARGET_COPPER_DISPLAY_H
#define _TARGET_COPPER_DISPLAY_H
-#define MIPI_FB_ADDR 0x0D200000
-#define EDP_FB_ADDR 0x7EF00000
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include <display_resource.h>
+
+/*---------------------------------------------------------------------------*/
+/* GPIO configuration */
+/*---------------------------------------------------------------------------*/
+static struct gpio_pin reset_gpio = {
+ "pm8941_gpios", 19, 2, 1, 0, 1
+};
+
+static struct gpio_pin enable_gpio = {
+ "msmgpio", 58, 3, 1, 0, 1
+};
+
+
+/*---------------------------------------------------------------------------*/
+/* LDO configuration */
+/*---------------------------------------------------------------------------*/
+static struct ldo_entry ldo_entry_array[] = {
+ { "vdd", 22, 0, 3000000, 100000, 100, 0, 20, 0, 0},
+{ "vddio", 12, 0, 1800000, 100000, 100, 0, 20, 0, 0},
+{ "vdda", 2, 1, 1200000, 100000, 100, 0, 0, 0, 0},
+};
+
+#define TOTAL_LDO_DEFINED 3
+
+/*---------------------------------------------------------------------------*/
+/* Target Physical configuration */
+/*---------------------------------------------------------------------------*/
+
+static const uint32_t panel_strength_ctrl[] = {
+ 0xff, 0x06
+};
+
+static const char panel_bist_ctrl[] = {
+ 0x00, 0x00, 0xb1, 0xff, 0x00, 0x00
+};
+
+static const uint32_t panel_regulator_settings[] = {
+ 0x07, 0x09, 0x03, 0x00, 0x20, 0x00, 0x01
+};
+
+static const char panel_lane_config[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x01, 0x97,
+ 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xbb
+};
+
+static const uint32_t panel_physical_ctrl[] = {
+ 0x5f, 0x00, 0x00, 0x10
+};
+
+/*---------------------------------------------------------------------------*/
+/* Other Configuration */
+/*---------------------------------------------------------------------------*/
+
+#define MIPI_FB_ADDR 0x03200000
+#define EDP_FB_ADDR MIPI_FB_ADDR
#define MIPI_HSYNC_PULSE_WIDTH 12
#define MIPI_HSYNC_BACK_PORCH_DCLK 32
@@ -41,6 +101,5 @@
#define MIPI_VSYNC_FRONT_PORCH_LINES 9
extern int mdss_dsi_phy_init(struct mipi_dsi_panel_config *, uint32_t ctl_base);
-extern int mdss_dsi_uniphy_pll_config(uint32_t ctl_base);
#endif
diff --git a/target/msm8974/oem_panel.c b/target/msm8974/oem_panel.c
new file mode 100755
index 0000000..3ea115e
--- /dev/null
+++ b/target/msm8974/oem_panel.c
@@ -0,0 +1,151 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <err.h>
+#include <smem.h>
+#include <msm_panel.h>
+#include <board.h>
+#include <mipi_dsi.h>
+
+#include "include/panel.h"
+#include "panel_display.h"
+
+/*---------------------------------------------------------------------------*/
+/* GCDB Panel Database */
+/*---------------------------------------------------------------------------*/
+#include "include/panel_toshiba_720p_video.h"
+#include "include/panel_sharp_qhd_video.h"
+
+/*---------------------------------------------------------------------------*/
+/* static panel selection variable */
+/*---------------------------------------------------------------------------*/
+enum {
+TOSHIBA_720P_VIDEO_PANEL,
+SHARP_QHD_VIDEO_PANEL
+};
+
+static uint32_t panel_id;
+
+int oem_panel_rotation()
+{
+ /* OEM can keep there panel spefic on instructions in this
+ function */
+ return NO_ERROR;
+}
+
+
+int oem_panel_on()
+{
+ /* OEM can keep there panel spefic on instructions in this
+ function */
+ return NO_ERROR;
+}
+
+int oem_panel_off()
+{
+ /* OEM can keep there panel spefic off instructions in this
+ function */
+ return NO_ERROR;
+}
+
+static void init_panel_data(struct panel_struct *panelstruct,
+ struct msm_panel_info *pinfo,
+ struct mdss_dsi_phy_ctrl *phy_db)
+{
+ switch (panel_id) {
+ case TOSHIBA_720P_VIDEO_PANEL:
+ panelstruct->paneldata = &toshiba_720p_video_panel_data;
+ panelstruct->panelres = &toshiba_720p_video_panel_res;
+ panelstruct->color = &toshiba_720p_video_color;
+ panelstruct->videopanel = &toshiba_720p_video_video_panel;
+ panelstruct->commandpanel = &toshiba_720p_video_command_panel;
+ panelstruct->state = &toshiba_720p_video_state;
+ panelstruct->laneconfig = &toshiba_720p_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &toshiba_720p_video_timing_info;
+ panelstruct->panelresetseq
+ = &toshiba_720p_video_panel_reset_seq;
+ panelstruct->backlightinfo = &toshiba_720p_video_backlight;
+ pinfo->mipi.panel_cmds
+ = toshiba_720p_video_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = TOSHIBA_720P_VIDEO_ON_COMMAND;
+ memcpy(phy_db->timing,
+ toshiba_720p_video_timings, TIMING_SIZE);
+ break;
+ case SHARP_QHD_VIDEO_PANEL:
+ panelstruct->paneldata = &sharp_qhd_video_panel_data;
+ panelstruct->panelres = &sharp_qhd_video_panel_res;
+ panelstruct->color = &sharp_qhd_video_color;
+ panelstruct->videopanel = &sharp_qhd_video_video_panel;
+ panelstruct->commandpanel = &sharp_qhd_video_command_panel;
+ panelstruct->state = &sharp_qhd_video_state;
+ panelstruct->laneconfig = &sharp_qhd_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &sharp_qhd_video_timing_info;
+ panelstruct->panelresetseq
+ = &sharp_qhd_video_panel_reset_seq;
+ panelstruct->backlightinfo = &sharp_qhd_video_backlight;
+ pinfo->mipi.panel_cmds
+ = sharp_qhd_video_on_command;
+ pinfo->mipi.num_of_panel_cmds
+ = SHARP_QHD_VIDEO_ON_COMMAND;
+ memcpy(phy_db->timing,
+ sharp_qhd_video_timings, TIMING_SIZE);
+ break;
+ }
+}
+
+bool oem_panel_select(struct panel_struct *panelstruct,
+ struct msm_panel_info *pinfo,
+ struct mdss_dsi_phy_ctrl *phy_db)
+{
+ uint32_t hw_id = board_hardware_id();
+ uint32_t target_id = board_target_id();
+
+ switch (hw_id) {
+ case HW_PLATFORM_MTP:
+ case HW_PLATFORM_FLUID:
+ case HW_PLATFORM_SURF:
+ panel_id = TOSHIBA_720P_VIDEO_PANEL;
+ break;
+ case HW_PLATFORM_DRAGON:
+ panel_id = SHARP_QHD_VIDEO_PANEL;
+ break;
+ default:
+ dprintf(CRITICAL, "Display not enabled for %d HW type\n"
+ , hw_id);
+ return false;
+ }
+
+ init_panel_data(panelstruct, pinfo, phy_db);
+
+ return true;
+}
diff --git a/target/msm8974/rules.mk b/target/msm8974/rules.mk
index e2acd10..ab9a431 100644
--- a/target/msm8974/rules.mk
+++ b/target/msm8974/rules.mk
@@ -1,6 +1,7 @@
LOCAL_DIR := $(GET_LOCAL_DIR)
INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared
+INCLUDES += -I$(LK_TOP_DIR)/dev/gcdb/display -I$(LK_TOP_DIR)/dev/gcdb/display/include
PLATFORM := msm8974
@@ -22,6 +23,7 @@
dev/keys \
dev/pmic/pm8x41 \
dev/panel/msm \
+ dev/gcdb/display \
lib/ptable \
lib/libfdt
@@ -38,4 +40,5 @@
OBJS += \
$(LOCAL_DIR)/init.o \
$(LOCAL_DIR)/meminfo.o \
- $(LOCAL_DIR)/target_display.o
+ $(LOCAL_DIR)/target_display.o \
+ $(LOCAL_DIR)/oem_panel.o
diff --git a/target/msm8974/target_display.c b/target/msm8974/target_display.c
index 10aefc7..e02ea22 100644
--- a/target/msm8974/target_display.c
+++ b/target/msm8974/target_display.c
@@ -29,7 +29,9 @@
#include <debug.h>
#include <smem.h>
+#include <err.h>
#include <msm_panel.h>
+#include <mipi_dsi.h>
#include <pm8x41.h>
#include <pm8x41_wled.h>
#include <board.h>
@@ -38,15 +40,13 @@
#include <platform/clock.h>
#include <platform/iomap.h>
#include <target/display.h>
+#include "include/panel.h"
+#include "include/display_resource.h"
static struct msm_fb_panel_data panel;
-static uint8_t display_enable;
+static uint8_t edp_enable;
-extern int msm_display_init(struct msm_fb_panel_data *pdata);
-extern int msm_display_off();
-extern int mdss_dsi_uniphy_pll_config(uint32_t ctl_base);
-extern int mdss_sharp_dsi_uniphy_pll_config(uint32_t ctl_base);
-extern void edp_auo_1080p_init(struct edp_panel_data *edp_panel);
+#define HFPLL_LDO_ID 12
static struct pm8x41_wled_data wled_ctrl = {
.mod_scheme = 0x00,
@@ -58,39 +58,85 @@
.full_current_scale = 0x19
};
-static int msm8974_backlight_on()
+static uint32_t dsi_pll_enable_seq(uint32_t ctl_base)
+{
+ uint32_t rc = 0;
+
+ mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+
+ writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x07, ctl_base + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ mdelay(1);
+
+ mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
+
+ while (!(readl(ctl_base + 0x02c0) & 0x01)) {
+ mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+ writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x07, ctl_base + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x07, ctl_base + 0x0220); /* GLB CFG */
+ mdelay(1);
+ writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ mdelay(2);
+ mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
+ }
+ return rc;
+}
+
+int target_backlight_ctrl(uint8_t enable)
{
uint32_t platform_id = board_platform_id();
uint32_t hardware_id = board_hardware_id();
- uint8_t slave_id = 1, i;
- struct board_pmic_data *pmic_info;
+ uint8_t slave_id = 1;
- if (platform_id == MSM8974AC)
- if ((hardware_id == HW_PLATFORM_SURF)
- || (hardware_id == HW_PLATFORM_MTP)
- || (hardware_id == HW_PLATFORM_LIQUID))
- slave_id = 3;
+ if (enable) {
+ if (platform_id == MSM8974AC)
+ if ((hardware_id == HW_PLATFORM_MTP)
+ || (hardware_id == HW_PLATFORM_LIQUID))
+ slave_id = 3;
- pm8x41_wled_config_slave_id(slave_id);
- pm8x41_wled_config(&wled_ctrl);
- pm8x41_wled_sink_control(1);
- pm8x41_wled_iled_sync_control(1);
- pm8x41_wled_enable(1);
+ pm8x41_wled_config_slave_id(slave_id);
+ pm8x41_wled_config(&wled_ctrl);
+ pm8x41_wled_sink_control(enable);
+ pm8x41_wled_iled_sync_control(enable);
+ }
+ pm8x41_wled_enable(enable);
- return 0;
+ return NO_ERROR;
}
-static int msm8974_mdss_dsi_panel_clock(uint8_t enable)
+int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
{
- uint32_t dual_dsi = panel.panel_info.mipi.dual_dsi;
+ struct mdss_dsi_pll_config *pll_data;
+ uint32_t dual_dsi = pinfo->mipi.dual_dsi;
+ dprintf(SPEW, "target_panel_clock\n");
+
+ pll_data = pinfo->mipi.dsi_pll_config;
if (enable) {
mdp_gdsc_ctrl(enable);
mdp_clock_init();
- mdss_dsi_uniphy_pll_config(MIPI_DSI0_BASE);
+ mdss_dsi_auto_pll_config(MIPI_DSI0_BASE, pll_data);
+ dsi_pll_enable_seq(MIPI_DSI0_BASE);
if (panel.panel_info.mipi.dual_dsi &&
- !(panel.panel_info.mipi.broadcast))
- mdss_dsi_uniphy_pll_config(MIPI_DSI1_BASE);
- mmss_clock_init(DSI0_PHY_PLL_OUT, dual_dsi);
+ !(panel.panel_info.mipi.broadcast)) {
+ mdss_dsi_auto_pll_config(MIPI_DSI1_BASE, pll_data);
+ dsi_pll_enable_seq(MIPI_DSI1_BASE);
+ }
+ mmss_clock_auto_pll_init(DSI0_PHY_PLL_OUT, dual_dsi,
+ pll_data->pclk_m,
+ pll_data->pclk_n,
+ pll_data->pclk_d);
} else if(!target_cont_splash_screen()) {
// * Add here for continuous splash *
mmss_clock_disable(dual_dsi);
@@ -98,107 +144,78 @@
mdp_gdsc_ctrl(enable);
}
- return 0;
-}
-
-static int msm8974_mdss_sharp_dsi_panel_clock(uint8_t enable)
-{
- if (enable) {
- mdp_gdsc_ctrl(enable);
- mdp_clock_init();
- mdss_sharp_dsi_uniphy_pll_config(MIPI_DSI0_BASE);
- mmss_clock_init(DSI0_PHY_PLL_OUT);
- } else if (!target_cont_splash_screen()) {
- /* Add here for continuous splash */
- mmss_clock_disable();
- mdp_clock_disable();
- mdp_gdsc_ctrl(enable);
- }
-
- return 0;
+ return NO_ERROR;
}
/* Pull DISP_RST_N high to get panel out of reset */
-static void msm8974_mdss_mipi_panel_reset(uint8_t enable)
+int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
+ struct msm_panel_info *pinfo)
{
- uint32_t rst_gpio = 19;
+ uint32_t rst_gpio = reset_gpio.pin_id;
uint32_t platform_id = board_platform_id();
uint32_t hardware_id = board_hardware_id();
- struct pm8x41_gpio gpio_param = {
+ struct pm8x41_gpio resetgpio_param = {
.direction = PM_GPIO_DIR_OUT,
.output_buffer = PM_GPIO_OUT_CMOS,
.out_strength = PM_GPIO_OUT_DRIVE_MED,
};
if (platform_id == MSM8974AC)
- if ((hardware_id == HW_PLATFORM_SURF)
- || (hardware_id == HW_PLATFORM_MTP)
+ if ((hardware_id == HW_PLATFORM_MTP)
|| (hardware_id == HW_PLATFORM_LIQUID))
rst_gpio = 20;
dprintf(SPEW, "platform_id: %u, rst_gpio: %u\n",
platform_id, rst_gpio);
- pm8x41_gpio_config(rst_gpio, &gpio_param);
+ pm8x41_gpio_config(rst_gpio, &resetgpio_param);
if (enable) {
- gpio_tlmm_config(58, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_8MA, GPIO_DISABLE);
+ gpio_tlmm_config(enable_gpio.pin_id, 0,
+ enable_gpio.pin_direction, enable_gpio.pin_pull,
+ enable_gpio.pin_strength, enable_gpio.pin_state);
- pm8x41_gpio_set(rst_gpio, PM_GPIO_FUNC_HIGH);
- mdelay(2);
- pm8x41_gpio_set(rst_gpio, PM_GPIO_FUNC_LOW);
- mdelay(5);
- pm8x41_gpio_set(rst_gpio, PM_GPIO_FUNC_HIGH);
- mdelay(2);
- gpio_set(58, 2);
+ gpio_set(enable_gpio.pin_id, resetseq->pin_direction);
+ pm8x41_gpio_set(rst_gpio, resetseq->pin_state[0]);
+ mdelay(resetseq->sleep[0]);
+ pm8x41_gpio_set(rst_gpio, resetseq->pin_state[1]);
+ mdelay(resetseq->sleep[1]);
+ pm8x41_gpio_set(rst_gpio, resetseq->pin_state[2]);
+ mdelay(resetseq->sleep[2]);
} else {
- gpio_param.out_strength = PM_GPIO_OUT_DRIVE_LOW;
- pm8x41_gpio_config(rst_gpio, &gpio_param);
+ resetgpio_param.out_strength = PM_GPIO_OUT_DRIVE_LOW;
+ pm8x41_gpio_config(rst_gpio, &resetgpio_param);
pm8x41_gpio_set(rst_gpio, PM_GPIO_FUNC_LOW);
- gpio_set(58, 2);
+ gpio_set(enable_gpio.pin_id, resetseq->pin_direction);
}
+ return NO_ERROR;
}
-static int msm8974_mipi_panel_power(uint8_t enable)
+int target_ldo_ctrl(uint8_t enable)
{
+ uint32_t ldocounter = 0;
+ uint32_t pm8x41_ldo_base = 0x13F00;
- struct pm8x41_ldo ldo2 = LDO(PM8x41_LDO2, NLDO_TYPE);
- struct pm8x41_ldo ldo12 = LDO(PM8x41_LDO12, PLDO_TYPE);
- struct pm8x41_ldo ldo22 = LDO(PM8x41_LDO22, PLDO_TYPE);
+ while (ldocounter < TOTAL_LDO_DEFINED) {
+ struct pm8x41_ldo ldo_entry = LDO((pm8x41_ldo_base +
+ 0x100 * ldo_entry_array[ldocounter].ldo_id),
+ ldo_entry_array[ldocounter].ldo_type);
- if (enable) {
+ dprintf(SPEW, "Setting %s\n",
+ ldo_entry_array[ldocounter].ldo_id);
- /* Enable backlight */
- msm8974_backlight_on();
-
- /* Turn on LDO8 for lcd1 mipi vdd */
- dprintf(SPEW, " Setting LDO22\n");
- pm8x41_ldo_set_voltage(&ldo22, 3000000);
- pm8x41_ldo_control(&ldo22, enable);
-
- dprintf(SPEW, " Setting LDO12\n");
- /* Turn on LDO23 for lcd1 mipi vddio */
- pm8x41_ldo_set_voltage(&ldo12, 1800000);
- pm8x41_ldo_control(&ldo12, enable);
-
- dprintf(SPEW, " Setting LDO2\n");
- /* Turn on LDO2 for vdda_mipi_dsi */
- pm8x41_ldo_set_voltage(&ldo2, 1200000);
- pm8x41_ldo_control(&ldo2, enable);
-
- dprintf(SPEW, " Panel Reset \n");
- /* Panel Reset */
- msm8974_mdss_mipi_panel_reset(enable);
- dprintf(SPEW, " Panel Reset Done\n");
- } else {
- msm8974_mdss_mipi_panel_reset(enable);
- pm8x41_wled_enable(enable);
- pm8x41_ldo_control(&ldo2, enable);
- pm8x41_ldo_control(&ldo22, enable);
-
+ /* Set voltage during power on */
+ if (enable) {
+ pm8x41_ldo_set_voltage(&ldo_entry,
+ ldo_entry_array[ldocounter].ldo_voltage);
+ pm8x41_ldo_control(&ldo_entry, enable);
+ } else if(ldo_entry_array[ldocounter].ldo_id != HFPLL_LDO_ID) {
+ pm8x41_ldo_control(&ldo_entry, enable);
+ }
+ ldocounter++;
}
- return 0;
+ return NO_ERROR;
}
static int msm8974_mdss_edp_panel_clock(int enable)
@@ -258,40 +275,7 @@
void display_init(void)
{
uint32_t hw_id = board_hardware_id();
- uint32_t soc_ver = board_soc_version();
-
- dprintf(INFO, "display_init(),target_id=%d.\n", hw_id);
-
switch (hw_id) {
- case HW_PLATFORM_MTP:
- case HW_PLATFORM_FLUID:
- case HW_PLATFORM_SURF:
- mipi_toshiba_video_720p_init(&(panel.panel_info));
- panel.clk_func = msm8974_mdss_dsi_panel_clock;
- panel.power_func = msm8974_mipi_panel_power;
- panel.fb.base = MIPI_FB_ADDR;
- panel.fb.width = panel.panel_info.xres;
- panel.fb.height = panel.panel_info.yres;
- panel.fb.stride = panel.panel_info.xres;
- panel.fb.bpp = panel.panel_info.bpp;
- panel.fb.format = FB_FORMAT_RGB888;
- panel.mdp_rev = MDP_REV_50;
- break;
- case HW_PLATFORM_DRAGON:
- mipi_sharp_video_qhd_init(&(panel.panel_info));
- wled_ctrl.ovp = 0x0; /* 35V */
- wled_ctrl.full_current_scale = 0x14; /* 20mA */
- wled_ctrl.max_duty_cycle = 0; /* 26ns */
- panel.clk_func = msm8974_mdss_sharp_dsi_panel_clock;
- panel.power_func = msm8974_mipi_panel_power;
- panel.fb.base = MIPI_FB_ADDR;
- panel.fb.width = panel.panel_info.xres;
- panel.fb.height = panel.panel_info.yres;
- panel.fb.stride = panel.panel_info.xres;
- panel.fb.bpp = panel.panel_info.bpp;
- panel.fb.format = FB_FORMAT_RGB888;
- panel.mdp_rev = MDP_REV_50;
- break;
case HW_PLATFORM_LIQUID:
edp_panel_init(&(panel.panel_info));
panel.clk_func = msm8974_mdss_edp_panel_clock;
@@ -299,21 +283,30 @@
panel.fb.base = (void *)EDP_FB_ADDR;
panel.fb.format = FB_FORMAT_RGB888;
panel.mdp_rev = MDP_REV_50;
+
+ if (msm_display_init(&panel)) {
+ dprintf(CRITICAL, "edp init failed!\n");
+ return;
+ }
+
+ edp_enable = 1;
break;
default:
- return;
- };
-
- if (msm_display_init(&panel)) {
- dprintf(CRITICAL, "Display init failed!\n");
- return;
+ gcdb_display_init(MDP_REV_50, MIPI_FB_ADDR);
+ break;
}
-
- display_enable = 1;
}
void display_shutdown(void)
{
- if (display_enable)
- msm_display_off();
+ uint32_t hw_id = board_hardware_id();
+ switch (hw_id) {
+ case HW_PLATFORM_LIQUID:
+ if (edp_enable)
+ msm_display_off();
+ break;
+ default:
+ gcdb_display_shutdown();
+ break;
+ }
}