Merge "arch: arm: Fix the cache routines"
diff --git a/arch/arm/cache-ops.S b/arch/arm/cache-ops.S
index 974fb9b..0179456 100644
--- a/arch/arm/cache-ops.S
+++ b/arch/arm/cache-ops.S
@@ -331,11 +331,13 @@
/* void arch_flush_cache_range(addr_t start, size_t len); */
FUNCTION(arch_clean_cache_range)
+ add r2, r0, r1 // Calculate the end address
+ bic r0,#(CACHE_LINE-1) // Align start with cache line
0:
mcr p15, 0, r0, c7, c10, 1 // clean cache to PoC by MVA
add r0, r0, #CACHE_LINE
- subs r1, r1, #CACHE_LINE
- bhs 0b
+ cmp r0, r2
+ blo 0b
mov r0, #0
mcr p15, 0, r0, c7, c10, 4 // data sync barrier (formerly drain write buffer)
@@ -344,11 +346,13 @@
/* void arch_flush_invalidate_cache_range(addr_t start, size_t len); */
FUNCTION(arch_clean_invalidate_cache_range)
+ add r2, r0, r1 // Calculate the end address
+ bic r0,#(CACHE_LINE-1) // Align start with cache line
0:
mcr p15, 0, r0, c7, c14, 1 // clean & invalidate cache to PoC by MVA
add r0, r0, #CACHE_LINE
- subs r1, r1, #CACHE_LINE
- bhs 0b
+ cmp r0, r2
+ blo 0b
mov r0, #0
mcr p15, 0, r0, c7, c10, 4 // data sync barrier (formerly drain write buffer)
@@ -357,12 +361,14 @@
/* void arch_invalidate_cache_range(addr_t start, size_t len); */
FUNCTION(arch_invalidate_cache_range)
-0:
/* invalidate cache line */
+ add r2, r0, r1 // Calculate the end address
+ bic r0,#(CACHE_LINE-1) // Align start with cache line
+0:
mcr p15, 0, r0, c7, c6, 1
add r0, r0, #CACHE_LINE
- subs r1, r1, #CACHE_LINE
- bhs 0b
+ cmp r0, r2
+ blo 0b
mov r0, #0
/* data sync barrier (formerly drain write buffer*/
mcr p15, 0, r0, c7, c10, 4