[msm7x27a]: Initial commit to support 7x27a target.
Change-Id: Ibc8e40c40fe1ea8071f51d9f1d65f3b766bf2f9c
diff --git a/arch/arm/mmu.c b/arch/arm/mmu.c
index 74e9ecd..94fcd42 100644
--- a/arch/arm/mmu.c
+++ b/arch/arm/mmu.c
@@ -49,11 +49,11 @@
uint CB;
uint TEX = 0;
-#if defined(PLATFORM_MSM7K)
+#if (defined(PLATFORM_MSM7K) || defined(PLATFORM_MSM7X27A))
if ((paddr >= 0x88000000) && (paddr < 0xD0000000)) {
- /* peripherals in the 0x88000000 - 0xD0000000 range must
- * be mapped as DEVICE NON-SHARED: TEX=2, C=0, B=0
- */
+ /* peripherals in the 0x88000000 - 0xD0000000 range must
+ * be mapped as DEVICE NON-SHARED: TEX=2, C=0, B=0
+ */
TEX = 2;
flags &= (~(MMU_FLAG_CACHED | MMU_FLAG_BUFFERED));
}
diff --git a/platform/msm7x27a/acpuclock.c b/platform/msm7x27a/acpuclock.c
new file mode 100755
index 0000000..71b9e5c
--- /dev/null
+++ b/platform/msm7x27a/acpuclock.c
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2008, Google Inc.
+ * All rights reserved.
+ * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <kernel/thread.h>
+#include <platform/iomap.h>
+#include <reg.h>
+
+#define ARRAY_SIZE(x) (sizeof(x)/sizeof((x)[0]))
+
+#define A11S_CLK_CNTL_ADDR (MSM_CSR_BASE + 0x100)
+#define A11S_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104)
+#define VDD_SVS_PLEVEL_ADDR (MSM_CSR_BASE + 0x124)
+#define PLL2_L_VAL_ADDR (MSM_CLK_CTL_BASE + 0x33C)
+
+#define SRC_SEL_PLL1 1 /* PLL1. */
+#define SRC_SEL_PLL2 2 /* PLL2. */
+#define SRC_SEL_PLL3 3 /* PLL3. Used for 7x25. */
+#define DIV_4 3
+#define DIV_2 1
+#define WAIT_CNT 100
+#define VDD_LEVEL 7
+#define MIN_AXI_HZ 120000000
+#define ACPU_800MHZ 41
+
+void pll_request(unsigned pll, unsigned enable);
+void axi_clock_init(unsigned rate);
+
+/* The stepping frequencies have been choosen to make sure the step
+ * is <= 256 MHz for both turbo mode and normal mode targets. The
+ * table also assumes the ACPU is running at TCXO freq and AHB div is
+ * set to DIV_1.
+ *
+ * To use the tables:
+ * - Start at location 0/1 depending on clock source sel bit.
+ * - Set values till end of table skipping every other entry.
+ * - When you reach the end of the table, you are done scaling.
+ *
+ * TODO: Need to fix SRC_SEL_PLL1 for 7x25.
+ */
+
+uint32_t const clk_cntl_reg_val_7625[] = {
+ (WAIT_CNT << 16) | (SRC_SEL_PLL1 << 4) | DIV_4,
+ (WAIT_CNT << 16) | (SRC_SEL_PLL1 << 12) | (DIV_4 << 8),
+ (WAIT_CNT << 16) | (SRC_SEL_PLL1 << 12) | (DIV_2 << 8),
+ (WAIT_CNT << 16) | (SRC_SEL_PLL1 << 4) | DIV_2,
+ (WAIT_CNT << 16) | (SRC_SEL_PLL3 << 4) | DIV_2,
+ (WAIT_CNT << 16) | (SRC_SEL_PLL3 << 12) | (DIV_2 << 8),
+};
+
+uint32_t const clk_cntl_reg_val_7627[] = {
+ (WAIT_CNT << 16) | (SRC_SEL_PLL1 << 4) | DIV_4,
+ (WAIT_CNT << 16) | (SRC_SEL_PLL1 << 12) | (DIV_4 << 8),
+ (WAIT_CNT << 16) | (SRC_SEL_PLL1 << 12) | (DIV_2 << 8),
+ (WAIT_CNT << 16) | (SRC_SEL_PLL1 << 4) | DIV_2,
+ (WAIT_CNT << 16) | (SRC_SEL_PLL2 << 4) | DIV_2,
+ (WAIT_CNT << 16) | (SRC_SEL_PLL2 << 12) | (DIV_2 << 8),
+};
+
+uint32_t const clk_cntl_reg_val_7627T[] = {
+ (WAIT_CNT << 16) | (SRC_SEL_PLL1 << 4) | DIV_4,
+ (WAIT_CNT << 16) | (SRC_SEL_PLL1 << 12) | (DIV_4 << 8),
+ (WAIT_CNT << 16) | (SRC_SEL_PLL1 << 12) | (DIV_2 << 8),
+ (WAIT_CNT << 16) | (SRC_SEL_PLL1 << 4) | DIV_2,
+ (WAIT_CNT << 16) | (SRC_SEL_PLL2 << 4),
+ (WAIT_CNT << 16) | (SRC_SEL_PLL2 << 12),
+};
+
+/* Using DIV_4 for all cases to avoid worrying about turbo vs. normal
+ * mode. Able to use DIV_4 for all steps because it's the largest AND
+ * the final value. */
+uint32_t const clk_sel_reg_val[] = {
+ DIV_4 << 1 | 1,
+ DIV_4 << 1 | 0,
+ DIV_4 << 1 | 0,
+ DIV_4 << 1 | 1,
+ DIV_4 << 1 | 1,
+ DIV_4 << 1 | 0,
+};
+
+void mdelay(unsigned msecs);
+
+
+void acpu_clock_init(void)
+{
+ unsigned i,clk;
+
+#if (!ENABLE_NANDWRITE)
+ int *modem_stat_check = (MSM_SHARED_BASE + 0x14);
+
+ /* Wait for modem to be ready before clock init */
+ while (readl(modem_stat_check) != 1);
+#endif
+
+ /* Increase VDD level to the final value. */
+ writel((1 << 7) | (VDD_LEVEL << 3), VDD_SVS_PLEVEL_ADDR);
+#if (!ENABLE_NANDWRITE)
+ thread_sleep(1);
+#else
+ mdelay(1);
+#endif
+
+ /* Read clock source select bit. */
+ i = readl(A11S_CLK_SEL_ADDR) & 1;
+ clk = readl(PLL2_L_VAL_ADDR) & 0x3F;
+
+ /* Jump into table and set every other entry. */
+ for(; i < ARRAY_SIZE(clk_cntl_reg_val_7627); i += 2) {
+#ifdef ENABLE_PLL3
+ writel(clk_cntl_reg_val_7625[i], A11S_CLK_CNTL_ADDR);
+#else
+ if(clk == ACPU_800MHZ)
+ writel(clk_cntl_reg_val_7627T[i], A11S_CLK_CNTL_ADDR);
+ else
+ writel(clk_cntl_reg_val_7627[i], A11S_CLK_CNTL_ADDR);
+#endif
+ /* Would need a dmb() here but the whole address space is
+ * strongly ordered, so it should be fine.
+ */
+ writel(clk_sel_reg_val[i], A11S_CLK_SEL_ADDR);
+#if (!ENABLE_NANDWRITE)
+ thread_sleep(1);
+#else
+ mdelay(1);
+#endif
+ }
+}
diff --git a/platform/msm7x27a/arch_init.S b/platform/msm7x27a/arch_init.S
new file mode 100644
index 0000000..4d4a7c5
--- /dev/null
+++ b/platform/msm7x27a/arch_init.S
@@ -0,0 +1,252 @@
+/*
+ * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Google, Inc. nor the names of its contributors
+ * may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+.globl SET_SA
+SET_SA:
+ //; routine complete
+ B _cpu_early_init_complete
+.ltorg
+
+.globl __cpu_early_init
+__cpu_early_init:
+ //; Zero out r0 for use throughout this code. All other GPRs
+ //; (r1-r3) are set throughout this code to help establish
+ //; a consistent startup state for any code that follows.
+ //; Users should add code at the end of this routine to establish
+ //; their own stack address (r13), add translation page tables, enable
+ //; the caches, etc.
+ MOV r0, #0x0
+
+
+ //; Remove hardcoded cache settings. appsbl_handler.s calls Set_SA
+ //; API to dynamically configure cache for slow/nominal/fast parts
+
+
+ //; Initialize ASID to zero
+ MCR p15, 0, r0, c13, c0, 1 //; WCP15_CONTEXTIDR r0
+
+ //; ICIALL to invalidate entire I-Cache
+ MCR p15, 0, r0, c7, c5, 0 //; ICIALLU
+
+ //; Initialize ADFSR to zero
+ MCR p15, 0, r0, c5, c1, 0 //; ADFSR r0
+
+ //; Ensure the MCR's above have completed their operation before continuing
+ DSB
+ ISB
+
+ //;-------------------------------------------------------------------
+ //; There are a number of registers that must be set prior to enabling
+ //; the MMU. The DCAR is one of these registers. We are setting
+ //; it to zero (no access) to easily detect improper setup in subsequent
+ //; code sequences
+ //;-------------------------------------------------------------------
+ //; Setup DACR (Domain Access Control Register) to zero
+ MCR p15, 0, r0, c3, c0, 0 //; WCP15_DACR r0
+
+ //;Make sure TLBLKCR is complete before continuing
+ ISB
+
+ //; Invalidate the UTLB
+ MCR p15, 0, r0, c8, c7, 0 //; UTLBIALL
+
+ //; Make sure UTLB request has been presented to macro before continuing
+ ISB
+
+SYSI2:
+ //; Enable Z bit to enable branch prediction (default is off)
+ MRC p15, 0, r2, c1, c0, 0 //; RCP15_SCTLR r2
+ ORR r2, r2, #0x00000800
+ MCR p15, 0, r2, c1, c0, 0 //; WCP15_SCTLR r2
+
+ //; Make sure Link stack is initialized with branch and links to sequential addresses
+ //; This aids in creating a predictable startup environment
+ BL SEQ1
+SEQ1: BL SEQ2
+SEQ2: BL SEQ3
+SEQ3: BL SEQ4
+SEQ4: BL SEQ5
+SEQ5: BL SEQ6
+SEQ6: BL SEQ7
+SEQ7: BL SEQ8
+SEQ8:
+
+ ISB
+
+ //; Initialize the Watchpoint Control Registers to zero (optional)
+ //;;; MCR p14, 0, r0, c0, c0, 7 ; WCP14_DBGWCR0 r0
+ //;;; MCR p14, 0, r0, c0, c1, 7 ; WCP14_DBGWCR1 r0
+
+
+ //;----------------------------------------------------------------------
+ //; The saved Program Status Registers (SPSRs) should be setup
+ //; prior to any automatic mode switches. The following
+ //; code sets these registers up to a known state. Users will need to
+ //; customize these settings to meet their needs.
+ //;----------------------------------------------------------------------
+ MOV r2, #0x1f
+ MOV r1, #0xd7 //;ABT mode
+ msr cpsr_c, r1 //;ABT mode
+ msr spsr_cxfs, r2 //;clear the spsr
+ MOV r1, #0xdb //;UND mode
+ msr cpsr_c, r1 //;UND mode
+ msr spsr_cxfs, r2 //;clear the spsr
+ MOV r1, #0xd1 //;FIQ mode
+ msr cpsr_c, r1 //;FIQ mode
+ msr spsr_cxfs, r2 //;clear the spsr
+ MOV r1, #0xd2 //;IRQ mode
+ msr cpsr_c, r1 //;IRQ mode
+ msr spsr_cxfs, r2 //;clear the spsr
+ MOV r1, #0xd6 //;Monitor mode
+ msr cpsr_c, r1 //;Monitor mode
+ msr spsr_cxfs, r2 //;clear the spsr
+ MOV r1, #0xd3 //;SVC mode
+ msr cpsr_c, r1 //;SVC mode
+ msr spsr_cxfs, r2 //;clear the spsr
+
+
+ //;----------------------------------------------------------------------
+ //; Enabling Error reporting is something users may want to do at
+ //; some other point in time. We have chosen some default settings
+ //; that should be reviewed. Most of these registers come up in an
+ //; unpredictable state after reset.
+ //;----------------------------------------------------------------------
+//;Start of error and control setting
+
+
+ //; Set ACTLR (reset unpredictable)
+ //; Set AVIVT control, error reporting, etc.
+ //; MOV r3, #0x07
+ //; Enable I and D cache parity
+ //;ACTLR[2:0] = 3'h7 - enable parity error reporting from L2/I$/D$)
+ //;ACTLR[5:4] = 2'h3 - enable parity
+ //;ACTLR[19:18] =2'h3 - always generate and check parity(when MMU disabled).
+ //;Value to be written #0xC0037
+ // MOVW r3, #0x0037
+//; .word 0xe3003037 // hardcoded MOVW instruction due to lack of compiler support
+ // MOVT r3, #0x000C
+//; .word 0xe340300c // hardcoded MOVW instruction due to lack of compiler support
+ //; MCR p15, 0, r3, c1, c0, 1 //; WCP15_ACTLR r3
+
+//;End of error and control setting
+
+/*
+#ifdef APPSBL_ETM_ENABLE
+ ;----------------------------------------------------------------------
+ ; Optionally Enable the ETM (Embedded Trace Macro) which is used for debug
+ ;----------------------------------------------------------------------
+
+ ; enable ETM clock if disabled
+ MRC p15, 7, r1, c15, c0, 5 ; RCP15_CPMR r1
+ ORR r1, r1, #0x00000008
+ MCR p15, 7, r1, c15, c0, 5 ; WCP15_CPMR r1
+ ISB
+
+ ; set trigger event to counter1 being zero
+ MOV r3, #0x00000040
+ MCR p14, 1, r3, c0, c2, 0 ; WCP14_ETMTRIGGER r3
+
+ ; clear ETMSR
+ MOV r2, #0x00000000
+ MCR p14, 1, r2, c0, c4, 0 ; WCP14_ETMSR r2
+
+ ; clear trace enable single address comparator usage
+ MCR p14, 1, r2, c0, c7, 0 ; WCP14_ETMTECR2 r2
+
+ ; set trace enable to always
+ MOV r2, #0x0000006F
+ MCR p14, 1, r2, c0, c8, 0 ; WCP14_ETMTEEVR r2
+
+ ; clear trace enable address range comparator usage and exclude nothing
+ MOV r2, #0x01000000
+ MCR p14, 1, r2, c0, c9, 0 ; WCP14_ETMTECR1 r2
+
+ ; set view data to always
+ MOV r2, #0x0000006F
+ MCR p14, 1, r2, c0, c12, 0 ; WCP14_ETMVDEVR r2
+
+ ; clear view data single address comparator usage
+ MOV r2, #0x00000000
+ MCR p14, 1, r2, c0, c13, 0 ; WCP14_ETMVDCR1 r2
+
+ ; clear view data address range comparator usage and exclude nothing
+ MOV r2, #0x00010000
+ MCR p14, 1, r2, c0, c15, 0 ; WCP14_ETMVDCR3 r2
+
+ ; set counter1 to 194
+ MOV r2, #0x000000C2
+ MCR p14, 1, r2, c0, c0, 5 ; WCP14_ETMCNTRLDVR1 r2
+
+ ; set counter1 to never reload
+ MOV r2, #0x0000406F
+ MCR p14, 1, r2, c0, c8, 5 ; WCP14_ETMCNTRLDEVR1 r2
+
+ ; set counter1 to decrement every cycle
+ MOV r2, #0x0000006F
+ MCR p14, 1, r2, c0, c4, 5 ; WCP14_ETMCNTENR1 r2
+
+ ; Set trace synchronization frequency 1024 bytes
+ MOV r2, #0x00000400
+ MCR p14, 1, r2, c0, c8, 7 ; WCP14_ETMSYNCFR r2
+
+ ; Program etm control register
+ ; - Set the CPU to ETM clock ratio to 1:1
+ ; - Set the ETM to perform data address tracing
+ MOV r2, #0x00002008
+ MCR p14, 1, r2, c0, c0, 0 ; WCP14_ETMCR r2
+ ISB
+#endif *//* APPSBL_ETM_ENABLE */
+
+/*
+#ifdef APPSBL_VFP_ENABLE
+ ;----------------------------------------------------------------------
+ ; Perform the following operations if you intend to make use of
+ ; the VFP/Neon unit. Note that the FMXR instruction requires a CPU ID
+ ; indicating the VFP unit is present (i.e.Cortex-A8). .
+ ; Some tools will require full double precision floating point support
+ ; which will become available in Scorpion pass 2
+ ;----------------------------------------------------------------------
+ ; allow full access to CP 10 and 11 space for VFP/NEON use
+ MRC p15, 0, r1, c1, c0, 2 ; Read CP Access Control Register
+ ORR r1, r1, #0x00F00000 ; enable full access for p10,11
+ MCR p15, 0, r1, c1, c0, 2 ; Write CPACR
+
+ ;make sure the CPACR is complete before continuing
+ ISB
+
+ ; Enable VFP itself (certain OSes may want to dynamically set/clear
+ ; the enable bit based on the application being executed
+ MOV r1, #0x40000000
+ FMXR FPEXC, r1
+#endif *//* APPSBL_VFP_ENABLE */
+
+ /* we have no stack, so just tail-call into the SET_SA routine... */
+
+ B SET_SA
+.ltorg
diff --git a/platform/msm7x27a/gpio.c b/platform/msm7x27a/gpio.c
new file mode 100644
index 0000000..a49efec
--- /dev/null
+++ b/platform/msm7x27a/gpio.c
@@ -0,0 +1,228 @@
+/*
+ * Copyright (c) 2008, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <reg.h>
+#include <platform/iomap.h>
+#include <dev/gpio.h>
+
+#define GPIO1_REG(off) (MSM_GPIO1_BASE + 0x800 + (off))
+#define GPIO2_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off))
+
+/* output value */
+#define GPIO_OUT_0 GPIO1_REG(0x00) /* gpio 15-0 */
+#define GPIO_OUT_1 GPIO2_REG(0x00) /* gpio 42-16 */
+#define GPIO_OUT_2 GPIO1_REG(0x04) /* gpio 67-43 */
+#define GPIO_OUT_3 GPIO1_REG(0x08) /* gpio 94-68 */
+#define GPIO_OUT_4 GPIO1_REG(0x0C) /* gpio 106-95 */
+
+/* same pin map as above, output enable */
+#define GPIO_OE_0 GPIO1_REG(0x10)
+#define GPIO_OE_1 GPIO2_REG(0x08)
+#define GPIO_OE_2 GPIO1_REG(0x14)
+#define GPIO_OE_3 GPIO1_REG(0x18)
+#define GPIO_OE_4 GPIO1_REG(0x1C)
+
+/* same pin map as above, input read */
+#define GPIO_IN_0 GPIO1_REG(0x34)
+#define GPIO_IN_1 GPIO2_REG(0x20)
+#define GPIO_IN_2 GPIO1_REG(0x38)
+#define GPIO_IN_3 GPIO1_REG(0x3C)
+#define GPIO_IN_4 GPIO1_REG(0x40)
+
+/* same pin map as above, 1=edge 0=level interrup */
+#define GPIO_INT_EDGE_0 GPIO1_REG(0x60)
+#define GPIO_INT_EDGE_1 GPIO2_REG(0x50)
+#define GPIO_INT_EDGE_2 GPIO1_REG(0x64)
+#define GPIO_INT_EDGE_3 GPIO1_REG(0x68)
+#define GPIO_INT_EDGE_4 GPIO1_REG(0x6C)
+
+/* same pin map as above, 1=positive 0=negative */
+#define GPIO_INT_POS_0 GPIO1_REG(0x70)
+#define GPIO_INT_POS_1 GPIO2_REG(0x58)
+#define GPIO_INT_POS_2 GPIO1_REG(0x74)
+#define GPIO_INT_POS_3 GPIO1_REG(0x78)
+#define GPIO_INT_POS_4 GPIO1_REG(0x7C)
+
+/* same pin map as above, interrupt enable */
+#define GPIO_INT_EN_0 GPIO1_REG(0x80)
+#define GPIO_INT_EN_1 GPIO2_REG(0x60)
+#define GPIO_INT_EN_2 GPIO1_REG(0x84)
+#define GPIO_INT_EN_3 GPIO1_REG(0x88)
+#define GPIO_INT_EN_4 GPIO1_REG(0x8C)
+
+/* same pin map as above, write 1 to clear interrupt */
+#define GPIO_INT_CLEAR_0 GPIO1_REG(0x90)
+#define GPIO_INT_CLEAR_1 GPIO2_REG(0x68)
+#define GPIO_INT_CLEAR_2 GPIO1_REG(0x94)
+#define GPIO_INT_CLEAR_3 GPIO1_REG(0x98)
+#define GPIO_INT_CLEAR_4 GPIO1_REG(0x9C)
+
+/* same pin map as above, 1=interrupt pending */
+#define GPIO_INT_STATUS_0 GPIO1_REG(0xA0)
+#define GPIO_INT_STATUS_1 GPIO2_REG(0x70)
+#define GPIO_INT_STATUS_2 GPIO1_REG(0xA4)
+#define GPIO_INT_STATUS_3 GPIO1_REG(0xA8)
+#define GPIO_INT_STATUS_4 GPIO1_REG(0xAC)
+
+typedef struct gpioregs gpioregs;
+
+struct gpioregs
+{
+ unsigned out;
+ unsigned in;
+ unsigned int_status;
+ unsigned int_clear;
+ unsigned int_en;
+ unsigned int_edge;
+ unsigned int_pos;
+ unsigned oe;
+};
+
+static gpioregs GPIO_REGS[] = {
+ {
+ .out = GPIO_OUT_0,
+ .in = GPIO_IN_0,
+ .int_status = GPIO_INT_STATUS_0,
+ .int_clear = GPIO_INT_CLEAR_0,
+ .int_en = GPIO_INT_EN_0,
+ .int_edge = GPIO_INT_EDGE_0,
+ .int_pos = GPIO_INT_POS_0,
+ .oe = GPIO_OE_0,
+ },
+ {
+ .out = GPIO_OUT_1,
+ .in = GPIO_IN_1,
+ .int_status = GPIO_INT_STATUS_1,
+ .int_clear = GPIO_INT_CLEAR_1,
+ .int_en = GPIO_INT_EN_1,
+ .int_edge = GPIO_INT_EDGE_1,
+ .int_pos = GPIO_INT_POS_1,
+ .oe = GPIO_OE_1,
+ },
+ {
+ .out = GPIO_OUT_2,
+ .in = GPIO_IN_2,
+ .int_status = GPIO_INT_STATUS_2,
+ .int_clear = GPIO_INT_CLEAR_2,
+ .int_en = GPIO_INT_EN_2,
+ .int_edge = GPIO_INT_EDGE_2,
+ .int_pos = GPIO_INT_POS_2,
+ .oe = GPIO_OE_2,
+ },
+ {
+ .out = GPIO_OUT_3,
+ .in = GPIO_IN_3,
+ .int_status = GPIO_INT_STATUS_3,
+ .int_clear = GPIO_INT_CLEAR_3,
+ .int_en = GPIO_INT_EN_3,
+ .int_edge = GPIO_INT_EDGE_3,
+ .int_pos = GPIO_INT_POS_3,
+ .oe = GPIO_OE_3,
+ },
+ {
+ .out = GPIO_OUT_4,
+ .in = GPIO_IN_4,
+ .int_status = GPIO_INT_STATUS_4,
+ .int_clear = GPIO_INT_CLEAR_4,
+ .int_en = GPIO_INT_EN_4,
+ .int_edge = GPIO_INT_EDGE_4,
+ .int_pos = GPIO_INT_POS_4,
+ .oe = GPIO_OE_4,
+ },
+};
+
+static gpioregs *find_gpio(unsigned n, unsigned *bit)
+{
+ if(n > 106)
+ return 0;
+ if(n > 94) {
+ *bit = 1 << (n - 95);
+ return GPIO_REGS + 4;
+ }
+ if(n > 67) {
+ *bit = 1 << (n - 68);
+ return GPIO_REGS + 3;
+ }
+ if(n > 42) {
+ *bit = 1 << (n - 43);
+ return GPIO_REGS + 2;
+ }
+ if(n > 15) {
+ *bit = 1 << (n - 16);
+ return GPIO_REGS + 1;
+ }
+ *bit = 1 << n;
+ return GPIO_REGS + 0;
+}
+
+int gpio_config(unsigned n, unsigned flags)
+{
+ gpioregs *r;
+ unsigned b;
+ unsigned v;
+
+ if ((r = find_gpio(n, &b)) == 0)
+ return -1;
+
+ v = readl(r->oe);
+ if (flags & GPIO_OUTPUT) {
+ writel(v | b, r->oe);
+ } else {
+ writel(v & (~b), r->oe);
+ }
+ return 0;
+}
+
+void gpio_set(unsigned n, unsigned on)
+{
+ gpioregs *r;
+ unsigned b;
+ unsigned v;
+
+ if((r = find_gpio(n, &b)) == 0)
+ return;
+
+ v = readl(r->out);
+ if(on) {
+ writel(v | b, r->out);
+ } else {
+ writel(v & (~b), r->out);
+ }
+}
+
+int gpio_get(unsigned n)
+{
+ gpioregs *r;
+ unsigned b;
+
+ if((r = find_gpio(n, &b)) == 0) return 0;
+
+ return (readl(r->in) & b) ? 1 : 0;
+}
+
diff --git a/platform/msm7x27a/include/platform/iomap.h b/platform/msm7x27a/include/platform/iomap.h
new file mode 100644
index 0000000..963d9ba
--- /dev/null
+++ b/platform/msm7x27a/include/platform/iomap.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2008, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Google, Inc. nor the names of its contributors
+ * may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _PLATFORM_MSM7K_IOMAP_H_
+#define _PLATFORM_MSM7K_IOMAP_H_
+
+#define MSM_GPIO1_BASE 0xA9200000
+#define MSM_GPIO2_BASE 0xA9300000
+
+#define MSM_UART1_BASE 0xA9A00000
+#define MSM_UART2_BASE 0xA9B00000
+#define MSM_UART3_BASE 0xA9C00000
+
+#define MSM_VIC_BASE 0xC0000000
+#define MSM_GPT_BASE 0xC0100000
+#define MSM_CSR_BASE 0xC0100000
+#define MSM_CLK_CTL_BASE 0xA8600000
+
+#define MSM_SHARED_BASE 0x00100000
+
+#define MSM_SDC1_BASE 0xA0400000
+
+#endif
diff --git a/platform/msm7x27a/include/platform/irqs.h b/platform/msm7x27a/include/platform/irqs.h
new file mode 100644
index 0000000..76a41d5
--- /dev/null
+++ b/platform/msm7x27a/include/platform/irqs.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2008, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Google, Inc. nor the names of its contributors
+ * may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _PLATFORM_MSM7K_IRQS_H_
+#define _PLATFORM_MSM7K_IRQS_H_
+
+#define INT_A9_M2A_0 0
+#define INT_A9_M2A_1 1
+#define INT_A9_M2A_2 2
+#define INT_A9_M2A_3 3
+#define INT_A9_M2A_4 4
+#define INT_A9_M2A_5 5
+#define INT_A9_M2A_6 6
+#define INT_GP_TIMER_EXP 7
+#define INT_DEBUG_TIMER_EXP 8
+#define INT_UART1 9
+#define INT_UART2 10
+#define INT_UART3 11
+#define INT_UART1_RX 12
+#define INT_UART2_RX 13
+#define INT_UART3_RX 14
+#define INT_USB_OTG 15
+#define INT_MDDI_PRI 16
+#define INT_MDDI_EXT 17
+#define INT_MDDI_CLIENT 18
+#define INT_MDP 19
+#define INT_GRAPHICS 20
+#define INT_ADM_AARM 21
+#define INT_ADSP_A11 22
+#define INT_ADSP_A9_A11 23
+#define INT_SDC1_0 24
+#define INT_SDC1_1 25
+#define INT_SDC2_0 26
+#define INT_SDC2_1 27
+#define INT_KEYSENSE 28
+#define INT_TCHSCRN_SSBI 29
+#define INT_TCHSCRN1 30
+#define INT_TCHSCRN2 31
+
+#define INT_GPIO_GROUP1 (32 + 0)
+#define INT_GPIO_GROUP2 (32 + 1)
+#define INT_PWB_I2C (32 + 2)
+#define INT_NAND_WR_ER_DONE (32 + 3)
+#define INT_NAND_OP_DONE (32 + 4)
+#define INT_SOFTRESET (32 + 5)
+#define INT_PBUS_ARM11 (32 + 6)
+#define INT_AXI_MPU_SMI (32 + 7)
+#define INT_AXI_MPU_EBI1 (32 + 8)
+#define INT_AD_HSSD (32 + 9)
+#define INT_ARM11_PM (32 + 10)
+#define INT_ARM11_DMA (32 + 11)
+#define INT_TSIF_IRQ (32 + 12)
+#define INT_UART1DM_IRQ (32 + 13)
+#define INT_UART1DM_RX (32 + 14)
+#define INT_USB_HS (32 + 15)
+#define INT_SDC3_0 (32 + 16)
+#define INT_SDC3_1 (32 + 17)
+#define INT_SDC4_0 (32 + 18)
+#define INT_SDC4_1 (32 + 19)
+#define INT_UART2DM_RX (32 + 20)
+#define INT_UART2DM_IRQ (32 + 21)
+
+#define MSM_IRQ_BIT(irq) (1 << ((irq) & 31))
+
+#define NR_IRQS 54
+
+#endif
diff --git a/platform/msm7x27a/interrupts.c b/platform/msm7x27a/interrupts.c
new file mode 100644
index 0000000..aca4cdc
--- /dev/null
+++ b/platform/msm7x27a/interrupts.c
@@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2008, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Google, Inc. nor the names of its contributors
+ * may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <arch/arm.h>
+#include <reg.h>
+#include <kernel/thread.h>
+#include <platform/interrupts.h>
+
+#include <platform/irqs.h>
+#include <platform/iomap.h>
+
+#define VIC_REG(off) (MSM_VIC_BASE + (off))
+
+#define VIC_INT_SELECT0 VIC_REG(0x0000) /* 1: FIQ, 0: IRQ */
+#define VIC_INT_SELECT1 VIC_REG(0x0004) /* 1: FIQ, 0: IRQ */
+#define VIC_INT_EN0 VIC_REG(0x0010)
+#define VIC_INT_EN1 VIC_REG(0x0014)
+#define VIC_INT_ENCLEAR0 VIC_REG(0x0020)
+#define VIC_INT_ENCLEAR1 VIC_REG(0x0024)
+#define VIC_INT_ENSET0 VIC_REG(0x0030)
+#define VIC_INT_ENSET1 VIC_REG(0x0034)
+#define VIC_INT_TYPE0 VIC_REG(0x0040) /* 1: EDGE, 0: LEVEL */
+#define VIC_INT_TYPE1 VIC_REG(0x0044) /* 1: EDGE, 0: LEVEL */
+#define VIC_INT_POLARITY0 VIC_REG(0x0050) /* 1: NEG, 0: POS */
+#define VIC_INT_POLARITY1 VIC_REG(0x0054) /* 1: NEG, 0: POS */
+#define VIC_NO_PEND_VAL VIC_REG(0x0060)
+#define VIC_INT_MASTEREN VIC_REG(0x0064) /* 1: IRQ, 2: FIQ */
+#define VIC_PROTECTION VIC_REG(0x006C) /* 1: ENABLE */
+#define VIC_CONFIG VIC_REG(0x0068) /* 1: USE ARM1136 VIC */
+#define VIC_IRQ_STATUS0 VIC_REG(0x0080)
+#define VIC_IRQ_STATUS1 VIC_REG(0x0084)
+#define VIC_FIQ_STATUS0 VIC_REG(0x0090)
+#define VIC_FIQ_STATUS1 VIC_REG(0x0094)
+#define VIC_RAW_STATUS0 VIC_REG(0x00A0)
+#define VIC_RAW_STATUS1 VIC_REG(0x00A4)
+#define VIC_INT_CLEAR0 VIC_REG(0x00B0)
+#define VIC_INT_CLEAR1 VIC_REG(0x00B4)
+#define VIC_SOFTINT0 VIC_REG(0x00C0)
+#define VIC_SOFTINT1 VIC_REG(0x00C4)
+#define VIC_IRQ_VEC_RD VIC_REG(0x00D0) /* pending int # */
+#define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4) /* pending vector addr */
+#define VIC_IRQ_VEC_WR VIC_REG(0x00D8)
+#define VIC_IRQ_IN_SERVICE VIC_REG(0x00E0)
+#define VIC_IRQ_IN_STACK VIC_REG(0x00E4)
+#define VIC_TEST_BUS_SEL VIC_REG(0x00E8)
+
+struct ihandler {
+ int_handler func;
+ void *arg;
+};
+
+static struct ihandler handler[NR_IRQS];
+
+void platform_init_interrupts(void)
+{
+ writel(0xffffffff, VIC_INT_CLEAR0);
+ writel(0xffffffff, VIC_INT_CLEAR1);
+ writel(0, VIC_INT_SELECT0);
+ writel(0, VIC_INT_SELECT1);
+ writel(0xffffffff, VIC_INT_TYPE0);
+ writel(0xffffffff, VIC_INT_TYPE1);
+ writel(0, VIC_CONFIG);
+ writel(1, VIC_INT_MASTEREN);
+}
+
+enum handler_return platform_irq(struct arm_iframe *frame)
+{
+ unsigned num;
+ enum handler_return ret;
+ num = readl(VIC_IRQ_VEC_RD);
+ num = readl(VIC_IRQ_VEC_PEND_RD);
+ if (num > NR_IRQS)
+ return 0;
+ writel(1 << (num & 31), (num > 31) ? VIC_INT_CLEAR1 : VIC_INT_CLEAR0);
+ ret = handler[num].func(handler[num].arg);
+ writel(0, VIC_IRQ_VEC_WR);
+ return ret;
+}
+
+void platform_fiq(struct arm_iframe *frame)
+{
+ PANIC_UNIMPLEMENTED;
+}
+
+status_t mask_interrupt(unsigned int vector)
+{
+ unsigned reg = (vector > 31) ? VIC_INT_ENCLEAR1 : VIC_INT_ENCLEAR0;
+ unsigned bit = 1 << (vector & 31);
+ writel(bit, reg);
+ return 0;
+}
+
+status_t unmask_interrupt(unsigned int vector)
+{
+ unsigned reg = (vector > 31) ? VIC_INT_ENSET1 : VIC_INT_ENSET0;
+ unsigned bit = 1 << (vector & 31);
+ writel(bit, reg);
+ return 0;
+}
+
+void register_int_handler(unsigned int vector, int_handler func, void *arg)
+{
+ if (vector >= NR_IRQS)
+ return;
+
+ enter_critical_section();
+ handler[vector].func = func;
+ handler[vector].arg = arg;
+ exit_critical_section();
+}
+
diff --git a/platform/msm7x27a/panel.c b/platform/msm7x27a/panel.c
new file mode 100644
index 0000000..8afcd19
--- /dev/null
+++ b/platform/msm7x27a/panel.c
@@ -0,0 +1,471 @@
+/* Copyright 2007, Google Inc. */
+
+#include <debug.h>
+#include <dev/gpio.h>
+#include <kernel/thread.h>
+#include <mddi.h>
+
+#define MDDI_CLIENT_CORE_BASE 0x108000
+#define LCD_CONTROL_BLOCK_BASE 0x110000
+#define SPI_BLOCK_BASE 0x120000
+#define I2C_BLOCK_BASE 0x130000
+#define PWM_BLOCK_BASE 0x140000
+#define GPIO_BLOCK_BASE 0x150000
+#define SYSTEM_BLOCK1_BASE 0x160000
+#define SYSTEM_BLOCK2_BASE 0x170000
+
+
+#define MDDICAP0 (MDDI_CLIENT_CORE_BASE|0x00)
+#define MDDICAP1 (MDDI_CLIENT_CORE_BASE|0x04)
+#define MDDICAP2 (MDDI_CLIENT_CORE_BASE|0x08)
+#define MDDICAP3 (MDDI_CLIENT_CORE_BASE|0x0C)
+#define MDCAPCHG (MDDI_CLIENT_CORE_BASE|0x10)
+#define MDCRCERC (MDDI_CLIENT_CORE_BASE|0x14)
+#define TTBUSSEL (MDDI_CLIENT_CORE_BASE|0x18)
+#define DPSET0 (MDDI_CLIENT_CORE_BASE|0x1C)
+#define DPSET1 (MDDI_CLIENT_CORE_BASE|0x20)
+#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24)
+#define DPRUN (MDDI_CLIENT_CORE_BASE|0x28)
+#define SYSCKENA (MDDI_CLIENT_CORE_BASE|0x2C)
+#define TESTMODE (MDDI_CLIENT_CORE_BASE|0x30)
+#define FIFOMONI (MDDI_CLIENT_CORE_BASE|0x34)
+#define INTMONI (MDDI_CLIENT_CORE_BASE|0x38)
+#define MDIOBIST (MDDI_CLIENT_CORE_BASE|0x3C)
+#define MDIOPSET (MDDI_CLIENT_CORE_BASE|0x40)
+#define BITMAP0 (MDDI_CLIENT_CORE_BASE|0x44)
+#define BITMAP1 (MDDI_CLIENT_CORE_BASE|0x48)
+#define BITMAP2 (MDDI_CLIENT_CORE_BASE|0x4C)
+#define BITMAP3 (MDDI_CLIENT_CORE_BASE|0x50)
+#define BITMAP4 (MDDI_CLIENT_CORE_BASE|0x54)
+
+
+#define SRST (LCD_CONTROL_BLOCK_BASE|0x00)
+#define PORT_ENB (LCD_CONTROL_BLOCK_BASE|0x04)
+#define START (LCD_CONTROL_BLOCK_BASE|0x08)
+#define PORT (LCD_CONTROL_BLOCK_BASE|0x0C)
+#define CMN (LCD_CONTROL_BLOCK_BASE|0x10)
+#define GAMMA (LCD_CONTROL_BLOCK_BASE|0x14)
+#define INTFLG (LCD_CONTROL_BLOCK_BASE|0x18)
+#define INTMSK (LCD_CONTROL_BLOCK_BASE|0x1C)
+#define MPLFBUF (LCD_CONTROL_BLOCK_BASE|0x20)
+#define HDE_LEFT (LCD_CONTROL_BLOCK_BASE|0x24)
+#define VDE_TOP (LCD_CONTROL_BLOCK_BASE|0x28)
+
+#define PXL (LCD_CONTROL_BLOCK_BASE|0x30)
+#define HCYCLE (LCD_CONTROL_BLOCK_BASE|0x34)
+#define HSW (LCD_CONTROL_BLOCK_BASE|0x38)
+#define HDE_START (LCD_CONTROL_BLOCK_BASE|0x3C)
+#define HDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x40)
+#define VCYCLE (LCD_CONTROL_BLOCK_BASE|0x44)
+#define VSW (LCD_CONTROL_BLOCK_BASE|0x48)
+#define VDE_START (LCD_CONTROL_BLOCK_BASE|0x4C)
+#define VDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x50)
+#define WAKEUP (LCD_CONTROL_BLOCK_BASE|0x54)
+#define WSYN_DLY (LCD_CONTROL_BLOCK_BASE|0x58)
+#define REGENB (LCD_CONTROL_BLOCK_BASE|0x5C)
+#define VSYNIF (LCD_CONTROL_BLOCK_BASE|0x60)
+#define WRSTB (LCD_CONTROL_BLOCK_BASE|0x64)
+#define RDSTB (LCD_CONTROL_BLOCK_BASE|0x68)
+#define ASY_DATA (LCD_CONTROL_BLOCK_BASE|0x6C)
+#define ASY_DATB (LCD_CONTROL_BLOCK_BASE|0x70)
+#define ASY_DATC (LCD_CONTROL_BLOCK_BASE|0x74)
+#define ASY_DATD (LCD_CONTROL_BLOCK_BASE|0x78)
+#define ASY_DATE (LCD_CONTROL_BLOCK_BASE|0x7C)
+#define ASY_DATF (LCD_CONTROL_BLOCK_BASE|0x80)
+#define ASY_DATG (LCD_CONTROL_BLOCK_BASE|0x84)
+#define ASY_DATH (LCD_CONTROL_BLOCK_BASE|0x88)
+#define ASY_CMDSET (LCD_CONTROL_BLOCK_BASE|0x8C)
+
+#define MONI (LCD_CONTROL_BLOCK_BASE|0xB0)
+
+#define Current (LCD_CONTROL_BLOCK_BASE|0xC0)
+#define LCD (LCD_CONTROL_BLOCK_BASE|0xC4)
+#define COMMAND (LCD_CONTROL_BLOCK_BASE|0xC8)
+
+
+#define SSICTL (SPI_BLOCK_BASE|0x00)
+#define SSITIME (SPI_BLOCK_BASE|0x04)
+#define SSITX (SPI_BLOCK_BASE|0x08)
+#define SSIRX (SPI_BLOCK_BASE|0x0C)
+#define SSIINTC (SPI_BLOCK_BASE|0x10)
+#define SSIINTS (SPI_BLOCK_BASE|0x14)
+#define SSIDBG1 (SPI_BLOCK_BASE|0x18)
+#define SSIDBG2 (SPI_BLOCK_BASE|0x1C)
+#define SSIID (SPI_BLOCK_BASE|0x20)
+
+
+#define I2CSETUP (I2C_BLOCK_BASE|0x00)
+#define I2CCTRL (I2C_BLOCK_BASE|0x04)
+
+
+#define TIMER0LOAD (PWM_BLOCK_BASE|0x00)
+#define TIMER0VALUE (PWM_BLOCK_BASE|0x04)
+#define TIMER0CONTROL (PWM_BLOCK_BASE|0x08)
+#define TIMER0INTCLR (PWM_BLOCK_BASE|0x0C)
+#define TIMER0RIS (PWM_BLOCK_BASE|0x10)
+#define TIMER0MIS (PWM_BLOCK_BASE|0x14)
+#define TIMER0BGLOAD (PWM_BLOCK_BASE|0x18)
+#define PWM0OFF (PWM_BLOCK_BASE|0x1C)
+#define TIMER1LOAD (PWM_BLOCK_BASE|0x20)
+#define TIMER1VALUE (PWM_BLOCK_BASE|0x24)
+#define TIMER1CONTROL (PWM_BLOCK_BASE|0x28)
+#define TIMER1INTCLR (PWM_BLOCK_BASE|0x2C)
+#define TIMER1RIS (PWM_BLOCK_BASE|0x30)
+#define TIMER1MIS (PWM_BLOCK_BASE|0x34)
+#define TIMER1BGLOAD (PWM_BLOCK_BASE|0x38)
+#define PWM1OFF (PWM_BLOCK_BASE|0x3C)
+#define TIMERITCR (PWM_BLOCK_BASE|0x60)
+#define TIMERITOP (PWM_BLOCK_BASE|0x64)
+#define PWMCR (PWM_BLOCK_BASE|0x68)
+#define PWMID (PWM_BLOCK_BASE|0x6C)
+#define PWMMON (PWM_BLOCK_BASE|0x70)
+
+
+#define GPIODATA (GPIO_BLOCK_BASE|0x00)
+#define GPIODIR (GPIO_BLOCK_BASE|0x04)
+#define GPIOIS (GPIO_BLOCK_BASE|0x08)
+#define GPIOIBE (GPIO_BLOCK_BASE|0x0C)
+#define GPIOIEV (GPIO_BLOCK_BASE|0x10)
+#define GPIOIE (GPIO_BLOCK_BASE|0x14)
+#define GPIORIS (GPIO_BLOCK_BASE|0x18)
+#define GPIOMIS (GPIO_BLOCK_BASE|0x1C)
+#define GPIOIC (GPIO_BLOCK_BASE|0x20)
+#define GPIOOMS (GPIO_BLOCK_BASE|0x24)
+#define GPIOPC (GPIO_BLOCK_BASE|0x28)
+
+#define GPIOID (GPIO_BLOCK_BASE|0x30)
+
+
+#define WKREQ (SYSTEM_BLOCK1_BASE|0x00)
+#define CLKENB (SYSTEM_BLOCK1_BASE|0x04)
+#define DRAMPWR (SYSTEM_BLOCK1_BASE|0x08)
+#define INTMASK (SYSTEM_BLOCK1_BASE|0x0C)
+#define GPIOSEL (SYSTEM_BLOCK2_BASE|0x00)
+
+struct init_table {
+ unsigned int reg;
+ unsigned int val;
+};
+
+static struct init_table toshiba_480x640_init_table[] = {
+ { DPSET0, 0x4BEC0066 }, // # MDC.DPSET0 # Setup DPLL parameters
+ { DPSET1, 0x00000113 }, // # MDC.DPSET1
+ { DPSUS, 0x00000000 }, // # MDC.DPSUS # Set DPLL oscillation enable
+ { DPRUN, 0x00000001 }, // # MDC.DPRUN # Release reset signal for DPLL
+ { 0, 14 }, // wait_ms(14);
+ { SYSCKENA, 0x00000001 }, // # MDC.SYSCKENA # Enable system clock output
+ { CLKENB, 0x000000EF }, // # SYS.CLKENB # Enable clocks for each module (without DCLK , i2cCLK)
+ { GPIO_BLOCK_BASE, 0x03FF0000 }, // # GPI .GPIODATA # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0
+ { GPIODIR, 0x0000024D }, // # GPI .GPIODIR # Select direction of GPIO port (0,2,3,6,9 output)
+ { SYSTEM_BLOCK2_BASE, 0x00000173 }, // # SYS.GPIOSEL # GPIO port multiplexing control
+ { GPIOPC, 0x03C300C0 }, // # GPI .GPIOPC # GPIO2,3 PD cut
+ { SYSTEM_BLOCK1_BASE, 0x00000000 }, // # SYS.WKREQ # Wake-up request event is VSYNC alignment
+ { GPIOIS, 0x00000000 }, // # GPI .GPIOIS # Set interrupt sense of GPIO
+ { GPIOIEV, 0x00000001 }, // # GPI .GPIOIEV # Set interrupt event of GPIO
+ { GPIOIC, 0x000003FF }, // # GPI .GPIOIC # GPIO interrupt clear
+ { GPIO_BLOCK_BASE, 0x00060006 }, // # GPI .GPIODATA # Release LCDD reset
+ { GPIO_BLOCK_BASE, 0x00080008 }, // # GPI .GPIODATA # eDRAM VD supply
+ { GPIO_BLOCK_BASE, 0x02000200 }, // # GPI .GPIODATA # TEST LED ON
+ { DRAMPWR, 0x00000001 }, // # SYS.DRAMPWR # eDRAM power up
+ { TIMER0CONTROL, 0x00000060 }, // # PWM.Timer0Control # PWM0 output stop
+ { PWM_BLOCK_BASE, 0x00001388 }, // # PWM.Timer0Load # PWM0 10kHz , Duty 99 (BackLight OFF)
+ //{PWM0OFF, 0x00000001 }, // # PWM.PWM0OFF
+#if 0
+ { PWM0OFF, 0x00001387 }, // SURF 100% backlight
+ { PWM0OFF, 0x00000000 }, // FFA 100% backlight
+#endif
+ { PWM0OFF, 0x000009C3 }, // 50% BL
+ { TIMER1CONTROL, 0x00000060 }, // # PWM.Timer1Control # PWM1 output stop
+ { TIMER1LOAD, 0x00001388 }, // # PWM.Timer1Load # PWM1 10kHz , Duty 99 (BackLight OFF)
+ //{PWM1OFF, 0x00000001 }, // # PWM.PWM1OFF
+ { PWM1OFF, 0x00001387 },
+ { TIMER0CONTROL, 0x000000E0 }, // # PWM.Timer0Control # PWM0 output start
+ { TIMER1CONTROL, 0x000000E0 }, // # PWM.Timer1Control # PWM1 output start
+ { PWMCR, 0x00000003 }, // # PWM.PWMCR # PWM output enable
+ { 0, 1 }, // wait_ms(1);
+ { SPI_BLOCK_BASE, 0x00000799 }, // # SPI .SSICTL # SPI operation mode setting
+ { SSITIME, 0x00000100 }, // # SPI .SSITIME # SPI serial interface timing setting
+ { SPI_BLOCK_BASE, 0x0000079b }, // # SPI .SSICTL # Set SPI active mode
+
+ { SSITX, 0x00000000 }, // # SPI.SSITX # Release from Deep Stanby mode
+ { 0, 1 }, // wait_ms(1);
+ { SSITX, 0x00000000 }, // # SPI.SSITX
+ { 0, 1 }, // wait_ms(1);
+ { SSITX, 0x00000000 }, // # SPI.SSITX
+ { 0, 1 }, // wait_ms(1);
+ { SSITX, 0x000800BA }, // # SPI.SSITX *NOTE 1 # Command setting of SPI block
+ { SSITX, 0x00000111 }, // # Display mode setup(1) : Normaly Black
+ { SSITX, 0x00080036 }, // # Command setting of SPI block
+ { SSITX, 0x00000100 }, // # Memory access control
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800BB }, // # Command setting of SPI block
+ { SSITX, 0x00000100 }, // # Display mode setup(2)
+ { SSITX, 0x0008003A }, // # Command setting of SPI block
+ { SSITX, 0x00000160 }, // # RGB Interface data format
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800BF }, // # Command setting of SPI block
+ { SSITX, 0x00000100 }, // # Drivnig method
+ { SSITX, 0x000800B1 }, // # Command setting of SPI block
+ { SSITX, 0x0000015D }, // # Booster operation setup
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800B2 }, // # Command setting of SPI block
+ { SSITX, 0x00000133 }, // # Booster mode setup
+ { SSITX, 0x000800B3 }, // # Command setting of SPI block
+ { SSITX, 0x00000122 }, // # Booster frequencies setup
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800B4 }, // # Command setting of SPI block
+ { SSITX, 0x00000102 }, // # OP-amp capability/System clock freq. division setup
+ { SSITX, 0x000800B5 }, // # Command setting of SPI block
+ { SSITX, 0x0000011F }, // # VCS Voltage adjustment (1C->1F for Rev 2)
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800B6 }, // # Command setting of SPI block
+ { SSITX, 0x00000128 }, // # VCOM Voltage adjustment
+ { SSITX, 0x000800B7 }, // # Command setting of SPI block
+ { SSITX, 0x00000103 }, // # Configure an external display signal
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800B9 }, // # Command setting of SPI block
+ { SSITX, 0x00000120 }, // # DCCK/DCEV timing setup
+ { SSITX, 0x000800BD }, // # Command setting of SPI block
+ { SSITX, 0x00000102 }, // # ASW signal control
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800BE }, // # Command setting of SPI block
+ { SSITX, 0x00000100 }, // # Dummy display (white/black) count setup for QUAD Data operation
+ { SSITX, 0x000800C0 }, // # Command setting of SPI block
+ { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (A)
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800C1 }, // # Command setting of SPI block
+ { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (B)
+ { SSITX, 0x000800C2 }, // # Command setting of SPI block
+ { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (C)
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800C3 }, // # Command setting of SPI block
+ { SSITX, 0x0008010A }, // # wait_ms(-in line clock count setup (D)
+ { SSITX, 0x0000010A }, //
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800C4 }, // # Command setting of SPI block
+ { SSITX, 0x00080160 }, // # Seep-in line clock count setup (E)
+ { SSITX, 0x00000160 }, //
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800C5 }, // # Command setting of SPI block
+ { SSITX, 0x00080160 }, // # wait_ms(-in line clock count setup (F)
+ { SSITX, 0x00000160 }, //
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800C6 }, // # Command setting of SPI block
+ { SSITX, 0x00080160 }, // # wait_ms(-in line clock setup (G)
+ { SSITX, 0x00000160 }, //
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800C7 }, // # Command setting of SPI block
+ { SSITX, 0x00080133 }, // # Gamma 1 fine tuning (1)
+ { SSITX, 0x00000143 }, //
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800C8 }, // # Command setting of SPI block
+ { SSITX, 0x00000144 }, // # Gamma 1 fine tuning (2)
+ { SSITX, 0x000800C9 }, // # Command setting of SPI block
+ { SSITX, 0x00000133 }, // # Gamma 1 inclination adjustment
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800CA }, // # Command setting of SPI block
+ { SSITX, 0x00000100 }, // # Gamma 1 blue offset adjustment
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800EC }, // # Command setting of SPI block
+ { SSITX, 0x00080102 }, // # Total number of horizontal clock cycles (1) [PCLK Sync. VGA setting]
+ { SSITX, 0x00000118 }, //
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800CF }, // # Command setting of SPI block
+ { SSITX, 0x00000101 }, // # Blanking period control (1) [PCLK Sync. Table1 for VGA]
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800D0 }, // # Command setting of SPI block
+ { SSITX, 0x00080110 }, // # Blanking period control (2) [PCLK Sync. Table1 for VGA]
+ { SSITX, 0x00000104 }, //
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800D1 }, // # Command setting of SPI block
+ { SSITX, 0x00000101 }, // # CKV timing control on/off [PCLK Sync. Table1 for VGA]
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800D2 }, // # Command setting of SPI block
+ { SSITX, 0x00080100 }, // # CKV1,2 timing control [PCLK Sync. Table1 for VGA]
+ { SSITX, 0x0000013A }, //
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800D3 }, // # Command setting of SPI block
+ { SSITX, 0x00080100 }, // # OEV timing control [PCLK Sync. Table1 for VGA]
+ { SSITX, 0x0000013A }, //
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800D4 }, // # Command setting of SPI block
+ { SSITX, 0x00080124 }, // # ASW timing control (1) [PCLK Sync. Table1 for VGA]
+ { SSITX, 0x0000016E }, //
+ { 0, 1 }, // wait_ms(1); // # Wait SPI fifo empty
+ { SSITX, 0x000800D5 }, // # Command setting of SPI block
+ { SSITX, 0x00000124 }, // # ASW timing control (2) [PCLK Sync. Table1 for VGA]
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800ED }, // # Command setting of SPI block
+ { SSITX, 0x00080101 }, // # Total number of horizontal clock cycles (2) [PCLK Sync. Table1 for QVGA ]
+ { SSITX, 0x0000010A }, //
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800D6 }, // # Command setting of SPI block
+ { SSITX, 0x00000101 }, // # Blanking period control (1) [PCLK Sync. Table2 for QVGA]
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800D7 }, // # Command setting of SPI block
+ { SSITX, 0x00080110 }, // # Blanking period control (2) [PCLK Sync. Table2 for QVGA]
+ { SSITX, 0x0000010A }, //
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800D8 }, // # Command setting of SPI block
+ { SSITX, 0x00000101 }, // # CKV timing control on/off [PCLK Sync. Table2 for QVGA]
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800D9 }, // # Command setting of SPI block
+ { SSITX, 0x00080100 }, // # CKV1,2 timing control [PCLK Sync. Table2 for QVGA]
+ { SSITX, 0x00000114 }, //
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800DE }, // # Command setting of SPI block
+ { SSITX, 0x00080100 }, // # OEV timing control [PCLK Sync. Table2 for QVGA]
+ { SSITX, 0x00000114 }, //
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800DF }, // # Command setting of SPI block
+ { SSITX, 0x00080112 }, // # ASW timing control (1) [PCLK Sync. Table2 for QVGA]
+ { SSITX, 0x0000013F }, //
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800E0 }, // # Command setting of SPI block
+ { SSITX, 0x0000010B }, // # ASW timing control (2) [PCLK Sync. Table2 for QVGA]
+ { SSITX, 0x000800E2 }, // # Command setting of SPI block
+ { SSITX, 0x00000101 }, // # Built-in oscillator frequency division setup [Frequency division ratio : 2 (60Hq)
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800E3 }, // # Command setting of SPI block
+ { SSITX, 0x00000136 }, // # Built-in oscillator clock count setup
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800E4 }, // # Command setting of SPI block
+ { SSITX, 0x00080100 }, // # CKV timing control for using build-in osc
+ { SSITX, 0x00000103 }, //
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800E5 }, // # Command setting of SPI block
+ { SSITX, 0x00080102 }, // # OEV timing control for using build-in osc
+ { SSITX, 0x00000104 }, //
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800E6 }, // # Command setting of SPI block
+ { SSITX, 0x00000103 }, // # DCEV timing control for using build-in osc
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800E7 }, // # Command setting of SPI block
+ { SSITX, 0x00080104 }, // # ASW timing setup for using build-in osc(1)
+ { SSITX, 0x0000010A }, //
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800E8 }, // # Command setting of SPI block
+ { SSITX, 0x00000104 }, // # ASW timing setup for using build-in osc(2)
+
+
+ { CLKENB, 0x000001EF }, // # SYS.CLKENB # DCLK enable
+ { START, 0x00000000 }, // # LCD.START # LCDC wait_ms( mode
+ { WRSTB, 0x0000003F }, // # LCD.WRSTB # write_client_reg( strobe
+ { RDSTB, 0x00000432 }, // # LCD.RDSTB # Read strobe
+ { PORT_ENB, 0x00000002 }, // # LCD.PORT_ENB # Asynchronous port enable
+ { VSYNIF, 0x00000000 }, // # LCD.VSYNCIF # VSYNC I/F mode set
+ { ASY_DATA, 0x80000000 }, // # LCD.ASY_DATx # Index setting of SUB LCDD
+ { ASY_DATB, 0x00000001 }, // # Oscillator start
+ { ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable
+ { ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable
+ { 0, 10 }, // wait_ms(10);
+ { ASY_DATA, 0x80000000 }, // # LCD.ASY_DATx # DUMMY write_client_reg(@*NOTE2
+ { ASY_DATB, 0x80000000 }, //
+ { ASY_DATC, 0x80000000 }, //
+ { ASY_DATD, 0x80000000 }, //
+ { ASY_CMDSET, 0x00000009 }, // # LCD.ASY_CMDSET
+ { ASY_CMDSET, 0x00000008 }, // # LCD.ASY_CMDSET
+ { ASY_DATA, 0x80000007 }, // # LCD.ASY_DATx # Index setting of SUB LCDD
+ { ASY_DATB, 0x00004005 }, // # LCD driver control
+ { ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable
+ { ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable
+ { 0, 20 }, // wait_ms(20);
+ { ASY_DATA, 0x80000059 }, // # LCD.ASY_DATx # Index setting of SUB LCDD
+ { ASY_DATB, 0x00000000 }, // # LTPS I/F control
+ { ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable
+ { ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable
+
+ { VSYNIF, 0x00000001 }, // # LCD.VSYNCIF # VSYNC I/F mode OFF
+ { PORT_ENB, 0x00000001 }, // # LCD.PORT_ENB # SYNC I/F output select
+
+ /******************************/
+
+ { VSYNIF, 0x00000001 }, // VSYNC I/F mode OFF
+ { PORT_ENB, 0x00000001 }, // SYNC I/F mode ON
+
+ { BITMAP1, 0x01E000F0 }, // MDC.BITMAP2 ); // Setup of PITCH size to Frame buffer1
+ { BITMAP2, 0x01E000F0 }, // MDC.BITMAP3 ); // Setup of PITCH size to Frame buffer2
+ { BITMAP3, 0x01E000F0 }, // MDC.BITMAP4 ); // Setup of PITCH size to Frame buffer3
+ { BITMAP4, 0x00DC00B0 }, // MDC.BITMAP5 ); // Setup of PITCH size to Frame buffer4
+ { CLKENB, 0x000001EF }, // SYS.CLKENB ); // DCLK supply
+ { PORT_ENB, 0x00000001 }, // LCD.PORT_ENB ); // Synchronous port enable
+ { PORT, 0x00000004 }, // LCD.PORT ); // Polarity of DE is set to high active
+ { PXL, 0x00000002 }, // LCD.PXL ); // ACTMODE 2 set (1st frame black data output)
+ { MPLFBUF, 0x00000000 }, // LCD.MPLFBUF ); // Select the reading buffer
+ { HCYCLE, 0x0000010b }, // LCD.HCYCLE ); // Setup to VGA size
+ { HSW, 0x00000003 }, // LCD.HSW
+ { HDE_START, 0x00000007 }, // LCD.HDE_START
+ { HDE_SIZE, 0x000000EF }, // LCD.HDE_SIZE
+ { VCYCLE, 0x00000285 }, // LCD.VCYCLE
+ { VSW, 0x00000001 }, // LCD.VSW
+ { VDE_START, 0x00000003 }, // LCD.VDE_START
+ { VDE_SIZE, 0x0000027F }, // LCD.VDE_SIZE
+
+ { START, 0x00000001 }, // LCD.START ); // LCDC - Pixel data transfer start
+
+ { 0, 10 }, // wait_ms( 10 );
+ { SSITX, 0x000800BC }, // SPI.SSITX ); // Command setting of SPI block
+ { SSITX, 0x00000180 }, // Display data setup
+ { SSITX, 0x0008003B }, // Command setting of SPI block
+ { SSITX, 0x00000100 }, // Quad Data configuration - VGA
+ { 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty
+ { SSITX, 0x000800B0 }, // Command setting of SPI block
+ { SSITX, 0x00000116 }, // Power supply ON/OFF control
+ { 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty
+ { SSITX, 0x000800B8 }, // Command setting of SPI block
+ { SSITX, 0x000801FF }, // Output control
+ { SSITX, 0x000001F5 },
+ { 0, 1 }, // wait_ms( 1); // Wait SPI fifo empty
+ { SSITX, 0x00000011 }, // wait_ms(-out (Command only)
+ { SSITX, 0x00000029 }, // Display on (Command only)
+
+ { SYSTEM_BLOCK1_BASE, 0x00000002 }, // # wakeREQ -> GPIO
+
+ { 0, 0 }
+};
+
+static void _panel_init(struct init_table *init_table)
+{
+ unsigned n;
+
+ dprintf(INFO, "panel_init()\n");
+
+ n = 0;
+ while (init_table[n].reg != 0 || init_table[n].val != 0) {
+ if (init_table[n].reg != 0)
+ mddi_remote_write(init_table[n].val, init_table[n].reg);
+ else
+ mdelay(init_table[n].val);
+ n++;
+ }
+
+ dprintf(INFO, "panel_init() done\n");
+}
+
+void panel_init(struct mddi_client_caps *client_caps)
+{
+ switch(client_caps->manufacturer_name) {
+ case 0xd263: // Toshiba
+ dprintf(INFO, "Found Toshiba panel\n");
+ _panel_init(toshiba_480x640_init_table);
+ break;
+ case 0x4474: //??
+ if (client_caps->product_code == 0xc065)
+ dprintf(INFO, "Found WVGA panel\n");
+ break;
+ }
+}
+
+void panel_poweron(void)
+{
+ gpio_set(88, 0);
+ gpio_config(88, GPIO_OUTPUT);
+ udelay(10);
+ gpio_set(88, 1);
+ mdelay(10);
+
+ //mdelay(1000); // uncomment for second stage boot
+}
+
+void panel_backlight(int on)
+{}
diff --git a/platform/msm7x27a/platform.c b/platform/msm7x27a/platform.c
new file mode 100644
index 0000000..43ea05b
--- /dev/null
+++ b/platform/msm7x27a/platform.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2008, Google Inc.
+ * All rights reserved.
+ *
+ * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Google, Inc. nor the names of its contributors
+ * may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <kernel/thread.h>
+#include <platform/debug.h>
+#include <mddi.h>
+#include <dev/fbcon.h>
+
+static struct fbcon_config *fb_config;
+
+void platform_init_interrupts(void);
+void platform_init_timer();
+
+void uart3_clock_init(void);
+void uart_init(void);
+
+void acpu_clock_init(void);
+
+void mddi_clock_init(unsigned num, unsigned rate);
+
+void platform_early_init(void)
+{
+ //uart3_clock_init();
+ //uart_init();
+
+ platform_init_interrupts();
+ platform_init_timer();
+}
+
+void platform_init(void)
+{
+ dprintf(INFO, "platform_init()\n");
+#if 0
+ acpu_clock_init();
+#endif
+}
+
+void display_init(void)
+{
+#if DISPLAY_TYPE_MDDI
+ fb_config = mddi_init();
+ ASSERT(fb_config);
+ fbcon_setup(fb_config);
+#endif
+#if DISPLAY_TYPE_LCDC
+ fb_config = lcdc_init();
+ ASSERT(fb_config);
+ fbcon_setup(fb_config);
+#endif
+}
diff --git a/platform/msm7x27a/rules.mk b/platform/msm7x27a/rules.mk
new file mode 100644
index 0000000..6fdbc4a
--- /dev/null
+++ b/platform/msm7x27a/rules.mk
@@ -0,0 +1,26 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+ARCH := arm
+# Cann't use cortex-a5 as its not supported by gcc 4.4.0
+ARM_CPU := cortex-a8
+CPU := generic
+
+MMC_SLOT := 1
+DEFINES += WITH_CPU_EARLY_INIT=1 MMC_SLOT=$(MMC_SLOT)
+
+INCLUDES += -I$(LOCAL_DIR)/include
+
+MODULES += dev/fbcon
+
+OBJS += \
+ $(LOCAL_DIR)/arch_init.o \
+ $(LOCAL_DIR)/platform.o \
+ $(LOCAL_DIR)/interrupts.o \
+ $(LOCAL_DIR)/gpio.o \
+ $(LOCAL_DIR)/panel.o \
+ $(LOCAL_DIR)/acpuclock.o
+
+LINKER_SCRIPT += $(BUILDDIR)/system-onesegment.ld
+
+include platform/msm_shared/rules.mk
+
diff --git a/platform/msm_shared/nand.c b/platform/msm_shared/nand.c
index 975b653..ef3f1b5 100644
--- a/platform/msm_shared/nand.c
+++ b/platform/msm_shared/nand.c
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2008, Google Inc.
* All rights reserved.
- * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -139,6 +139,7 @@
{0x005c00ec, 0xFFFFFFFF, (256<<20), 0, 2048, (2048<<6), 64, 1}, /*Sams*/
{0x005800ec, 0xFFFFFFFF, (256<<20), 0, 2048, (2048<<6), 64, 1}, /*Sams*/
{0x6600bcec, 0xFF00FFFF, (512<<20), 1, 4096, (4096<<6), 128, 0}, /*Sams*/
+ {0x5580ba2c, 0xFFFFFFFF, (256<<20), 1, 2048, (2048<<6), 64, 0}, /*Hynx*/
/* Note: Width flag is 0 for 8 bit Flash and 1 for 16 bit flash */
/* Note: Onenand flag is 0 for NAND Flash and 1 for OneNAND flash */
/* Note: The First row will be filled at runtime during ONFI probe */
diff --git a/project/msm7627a.mk b/project/msm7627a.mk
new file mode 100644
index 0000000..1f07401
--- /dev/null
+++ b/project/msm7627a.mk
@@ -0,0 +1,11 @@
+# top level project rules for the msm7627_surf project
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+TARGET := msm7627a
+
+MODULES += app/aboot
+
+#DEFINES += WITH_DEBUG_DCC=1
+#DEFINES += WITH_DEBUG_UART=1
+#DEFINES += WITH_DEBUG_FBCON=1
diff --git a/project/msm7627a_nandwrite.mk b/project/msm7627a_nandwrite.mk
new file mode 100644
index 0000000..e17a060
--- /dev/null
+++ b/project/msm7627a_nandwrite.mk
@@ -0,0 +1,14 @@
+# top level project rules for the msm7627_surf_nandwrite project
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+TARGET := msm7627a
+
+MODULES += app/nandwrite
+
+DEFINES += WITH_DEBUG_JTAG=1
+DEFINES += ENABLE_NANDWRITE=1
+#DEFINES += WITH_DEBUG_DCC=1
+#DEFINES += WITH_DEBUG_UART=1
+#DEFINES += WITH_DEBUG_FBCON=1
+
diff --git a/target/msm7627a/atags.c b/target/msm7627a/atags.c
new file mode 100644
index 0000000..64c7d0c
--- /dev/null
+++ b/target/msm7627a/atags.c
@@ -0,0 +1,72 @@
+/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Code Aurora nor
+ * the names of its contributors may be used to endorse or promote
+ * products derived from this software without specific prior written
+ * permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <reg.h>
+#include <debug.h>
+#include <smem.h>
+
+#define SIZE_1M 0x00100000
+
+unsigned* target_atag_mem(unsigned* ptr)
+{
+ struct smem_ram_ptable ram_ptable;
+ unsigned i = 0;
+
+ if (smem_ram_ptable_init(&ram_ptable))
+ {
+ for (i = 0; i < ram_ptable.len; i++)
+ {
+ if ((ram_ptable.parts[i].attr == READWRITE)
+ && (ram_ptable.parts[i].domain == APPS_DOMAIN)
+ && (ram_ptable.parts[i].start != 0x0)
+ && (!(ram_ptable.parts[i].size < SIZE_1M)))
+ {
+ /* ATAG_MEM */
+ *ptr++ = 4;
+ *ptr++ = 0x54410002;
+ /* FIXME: RAM partition table currently reports 2M extra
+ Fix this by subracting 2M, until modem ram partition table
+ starts reporting the right values. Also need fixes for
+ RAM partition table to have emmc entries correct */
+ if (target_is_emmc_boot())
+ *ptr++ = ram_ptable.parts[i].size - (2*SIZE_1M) - (6*SIZE_1M);
+ else
+ *ptr++ = ram_ptable.parts[i].size - (2*SIZE_1M);
+
+ *ptr++ = ram_ptable.parts[i].start;
+ }
+ }
+ }
+ else
+ {
+ dprintf(CRITICAL, "ERROR: Unable to read RAM partition\n");
+ ASSERT(0);
+ }
+ return ptr;
+}
+
diff --git a/target/msm7627a/include/target/display.h b/target/msm7627a/include/target/display.h
new file mode 100644
index 0000000..a36628d
--- /dev/null
+++ b/target/msm7627a/include/target/display.h
@@ -0,0 +1,47 @@
+/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef _TARGET_MSM7627_SURF_DISPLAY_H
+#define _TARGET_MSM7627_SURF_DISPLAY_H
+
+#define TARGET_XRES 800
+#define TARGET_YRES 480
+
+#define LCDC_FB_WIDTH 800
+#define LCDC_FB_HEIGHT 480
+
+#define LCDC_HSYNC_PULSE_WIDTH_DCLK 60
+#define LCDC_HSYNC_BACK_PORCH_DCLK 81
+#define LCDC_HSYNC_FRONT_PORCH_DCLK 81
+#define LCDC_HSYNC_SKEW_DCLK 0
+
+#define LCDC_VSYNC_PULSE_WIDTH_LINES 2
+#define LCDC_VSYNC_BACK_PORCH_LINES 20
+#define LCDC_VSYNC_FRONT_PORCH_LINES 27
+
+#endif
diff --git a/target/msm7627a/init.c b/target/msm7627a/init.c
new file mode 100644
index 0000000..22dcd51
--- /dev/null
+++ b/target/msm7627a/init.c
@@ -0,0 +1,233 @@
+/*
+ * Copyright (c) 2009, Google Inc.
+ * All rights reserved.
+ * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Google, Inc. nor the names of its contributors
+ * may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <dev/keys.h>
+#include <dev/gpio_keypad.h>
+#include <lib/ptable.h>
+#include <dev/flash.h>
+#include <smem.h>
+#include <platform/iomap.h>
+
+#define MSM7X27A_FFA 3351
+#define MSM7X27A_SURF 3352
+#define MSM7X27A_RUMI3 3353
+#define LINUX_MACHTYPE MSM7X27A_RUMI3
+
+#define VARIABLE_LENGTH 0x10101010
+#define DIFF_START_ADDR 0xF0F0F0F0
+#define NUM_PAGES_PER_BLOCK 0x40
+
+static struct ptable flash_ptable;
+
+/* for these partitions, start will be offset by either what we get from
+ * smem, or from the above offset if smem is not useful. Also, we should
+ * probably have smem_ptable code populate our flash_ptable.
+ *
+ * When smem provides us with a full partition table, we can get rid of
+ * this altogether.
+ *
+ */
+static struct ptentry board_part_list[] = {
+ {
+ .start = 0,
+ .length = 10 /* In MB */,
+ .name = "boot",
+ },
+ {
+ .start = DIFF_START_ADDR,
+ .length = 105 /* In MB */,
+ .name = "system",
+ },
+ {
+ .start = DIFF_START_ADDR,
+ .length = 1 /* In MB */,
+ .name = "cache",
+ },
+ {
+ .start = DIFF_START_ADDR,
+ .length = 1 /* In MB */,
+ .name = "misc",
+ },
+ {
+ .start = DIFF_START_ADDR,
+ .length = VARIABLE_LENGTH,
+ .name = "userdata",
+ },
+ {
+ .start = DIFF_START_ADDR,
+ .length = 2 /* In MB */,
+ .name = "persist",
+ },
+ {
+ .start = DIFF_START_ADDR,
+ .length = 5 /* In MB */,
+ .name = "recovery",
+ },
+};
+static int num_parts = sizeof(board_part_list)/sizeof(struct ptentry);
+
+void smem_ptable_init(void);
+unsigned smem_get_apps_flash_start(void);
+
+void keypad_init(void);
+
+int target_is_emmc_boot(void);
+
+void target_init(void)
+{
+ unsigned offset;
+ struct flash_info *flash_info;
+ unsigned total_num_of_blocks;
+ unsigned next_ptr_start_adr = 0;
+ unsigned blocks_per_1MB = 8; /* Default value of 2k page size on 256MB flash drive*/
+ int i;
+
+ dprintf(INFO, "target_init()\n");
+
+/* TODO: Enable keypad support */
+#if 0
+#if (!ENABLE_NANDWRITE)
+ keys_init();
+ keypad_init();
+#endif
+#endif
+
+ if (target_is_emmc_boot())
+ {
+ if(mmc_boot_main(MMC_SLOT, MSM_SDC1_BASE))
+ {
+ dprintf(CRITICAL, "mmc init failed!");
+ ASSERT(0);
+ }
+ return;
+ }
+
+ ptable_init(&flash_ptable);
+ smem_ptable_init();
+
+ flash_init();
+ flash_info = flash_get_info();
+ ASSERT(flash_info);
+
+ offset = smem_get_apps_flash_start();
+ if (offset == 0xffffffff)
+ while(1);
+
+ total_num_of_blocks = flash_info->num_blocks;
+ blocks_per_1MB = (1 << 20) / (flash_info->block_size);
+
+ for (i = 0; i < num_parts; i++) {
+ struct ptentry *ptn = &board_part_list[i];
+ unsigned len = ((ptn->length) * blocks_per_1MB);
+
+ if(ptn->start != 0)
+ ASSERT(ptn->start == DIFF_START_ADDR);
+
+ ptn->start = next_ptr_start_adr;
+
+ if(ptn->length == VARIABLE_LENGTH)
+ {
+ unsigned length_for_prt = 0;
+ unsigned j;
+ for (j = i+1; j < num_parts; j++)
+ {
+ struct ptentry *temp_ptn = &board_part_list[j];
+ ASSERT(temp_ptn->length != VARIABLE_LENGTH);
+ length_for_prt += ((temp_ptn->length) * blocks_per_1MB);
+ }
+ len = (total_num_of_blocks - 1) - (offset + ptn->start + length_for_prt);
+ ASSERT(len >= 0);
+ }
+ next_ptr_start_adr = ptn->start + len;
+ ptable_add(&flash_ptable, ptn->name, offset + ptn->start,
+ len, ptn->flags, TYPE_APPS_PARTITION, PERM_WRITEABLE);
+ }
+
+ smem_add_modem_partitions(&flash_ptable);
+
+ ptable_dump(&flash_ptable);
+ flash_set_ptable(&flash_ptable);
+}
+
+unsigned board_machtype(void)
+{
+ return LINUX_MACHTYPE;
+}
+
+void reboot_device(unsigned reboot_reason)
+{
+ reboot(reboot_reason);
+}
+
+unsigned check_reboot_mode(void)
+{
+ unsigned mode[2] = {0, 0};
+ unsigned int mode_len = sizeof(mode);
+ unsigned smem_status;
+
+ smem_status = smem_read_alloc_entry(SMEM_APPS_BOOT_MODE,
+ &mode, mode_len );
+ if(smem_status)
+ {
+ dprintf(CRITICAL, "ERROR: unable to read shared memory for reboot mode\n");
+ return 0;
+ }
+ return mode[0];
+}
+
+static unsigned target_check_power_on_reason(void)
+{
+ unsigned power_on_status = 0;
+ unsigned int status_len = sizeof(power_on_status);
+ unsigned smem_status;
+
+ smem_status = smem_read_alloc_entry(SMEM_POWER_ON_STATUS_INFO,
+ &power_on_status, status_len);
+ if (!smem_status)
+ {
+ dprintf(CRITICAL, "ERROR: unable to read shared memory for power on reason\n");
+ }
+
+ return power_on_status;
+}
+
+unsigned target_pause_for_battery_charge(void)
+{
+ if (target_check_power_on_reason() == PWR_ON_EVENT_USB_CHG)
+ return 1;
+ return 0;
+}
+
+void target_battery_charging_enable(unsigned enable, unsigned disconnect)
+{
+}
diff --git a/target/msm7627a/keypad.c b/target/msm7627a/keypad.c
new file mode 100644
index 0000000..c51c015
--- /dev/null
+++ b/target/msm7627a/keypad.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2009, Google Inc.
+ * All rights reserved.
+ * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Google, Inc. nor the names of its contributors
+ * may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <dev/keys.h>
+#include <dev/gpio_keypad.h>
+
+#define ARRAY_SIZE(x) (sizeof(x)/sizeof((x)[0]))
+
+/* don't turn this on without updating the ffa support */
+#define SCAN_FUNCTION_KEYS 0
+
+static unsigned int halibut_row_gpios[] = {
+ 31, 32, 33, 34, 35, 41
+#if SCAN_FUNCTION_KEYS
+ , 42
+#endif
+};
+
+static unsigned int halibut_col_gpios[] = { 36, 37, 38, 39, 40 };
+
+#define KEYMAP_INDEX(row, col) ((row)*ARRAY_SIZE(halibut_col_gpios) + (col))
+
+static const unsigned short halibut_keymap[ARRAY_SIZE(halibut_col_gpios) * ARRAY_SIZE(halibut_row_gpios)] = {
+ [KEYMAP_INDEX(0, 0)] = KEY_5,
+ [KEYMAP_INDEX(0, 1)] = KEY_9,
+ [KEYMAP_INDEX(0, 2)] = KEY_SOFT1,
+ [KEYMAP_INDEX(0, 3)] = KEY_6,
+ [KEYMAP_INDEX(0, 4)] = KEY_LEFT,
+
+ [KEYMAP_INDEX(1, 0)] = KEY_0,
+ [KEYMAP_INDEX(1, 1)] = KEY_RIGHT,
+ [KEYMAP_INDEX(1, 2)] = KEY_1,
+ [KEYMAP_INDEX(1, 3)] = KEY_SHARP,
+ [KEYMAP_INDEX(1, 4)] = KEY_SEND,
+
+ [KEYMAP_INDEX(2, 0)] = KEY_VOLUMEUP,
+ [KEYMAP_INDEX(2, 1)] = KEY_HOME, /* FA */
+ [KEYMAP_INDEX(2, 2)] = KEY_F8, /* QCHT */
+ [KEYMAP_INDEX(2, 3)] = KEY_F6, /* R+ */
+ [KEYMAP_INDEX(2, 4)] = KEY_F7, /* R- */
+
+ [KEYMAP_INDEX(3, 0)] = KEY_UP,
+ [KEYMAP_INDEX(3, 1)] = KEY_CLEAR,
+ [KEYMAP_INDEX(3, 2)] = KEY_4,
+ [KEYMAP_INDEX(3, 3)] = KEY_MUTE, /* SPKR */
+ [KEYMAP_INDEX(3, 4)] = KEY_2,
+
+ [KEYMAP_INDEX(4, 0)] = KEY_SOFT2, /* SOFT2 */
+ [KEYMAP_INDEX(4, 1)] = KEY_CENTER, /* KEY_CENTER */
+ [KEYMAP_INDEX(4, 2)] = KEY_DOWN,
+ [KEYMAP_INDEX(4, 3)] = KEY_BACK, /* FB */
+ [KEYMAP_INDEX(4, 4)] = KEY_8,
+
+ [KEYMAP_INDEX(5, 0)] = KEY_VOLUMEDOWN,
+ [KEYMAP_INDEX(5, 1)] = KEY_STAR, /* KEY_STAR */
+ [KEYMAP_INDEX(5, 2)] = KEY_MAIL, /* MESG */
+ [KEYMAP_INDEX(5, 3)] = KEY_3,
+ [KEYMAP_INDEX(5, 4)] = KEY_7,
+
+#if SCAN_FUNCTION_KEYS
+ [KEYMAP_INDEX(6, 0)] = KEY_F5,
+ [KEYMAP_INDEX(6, 1)] = KEY_F4,
+ [KEYMAP_INDEX(6, 2)] = KEY_F3,
+ [KEYMAP_INDEX(6, 3)] = KEY_F2,
+ [KEYMAP_INDEX(6, 4)] = KEY_F1
+#endif
+};
+
+static struct gpio_keypad_info halibut_keypad_info = {
+ .keymap = halibut_keymap,
+ .output_gpios = halibut_row_gpios,
+ .input_gpios = halibut_col_gpios,
+ .noutputs = ARRAY_SIZE(halibut_row_gpios),
+ .ninputs = ARRAY_SIZE(halibut_col_gpios),
+ .settle_time = 5 /* msec */,
+ .poll_time = 20 /* msec */,
+ .flags = GPIOKPF_DRIVE_INACTIVE,
+};
+
+void keypad_init(void)
+{
+ gpio_keypad_init(&halibut_keypad_info);
+}
diff --git a/target/msm7627a/rules.mk b/target/msm7627a/rules.mk
new file mode 100644
index 0000000..eae0c46
--- /dev/null
+++ b/target/msm7627a/rules.mk
@@ -0,0 +1,40 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared
+
+PLATFORM := msm7x27a
+
+MEMBASE := 0x00000000 # SMI
+MEMSIZE := 0x00100000 # 1MB
+
+BASE_ADDR := 0x00200000
+
+TAGS_ADDR := BASE_ADDR+0x00000100
+KERNEL_ADDR := BASE_ADDR+0x00008000
+RAMDISK_ADDR := BASE_ADDR+0x01000000
+SCRATCH_ADDR := BASE_ADDR+0x04000000
+
+KEYS_USE_GPIO_KEYPAD := 1
+
+DEFINES += DISPLAY_TYPE_MDDI=0
+DEFINES += DISPLAY_TYPE_LCDC=0
+DEFINES += DISPLAY_SPLASH_SCREEN=0
+
+MODULES += \
+ dev/keys \
+ lib/ptable
+
+DEFINES += \
+ SDRAM_SIZE=$(MEMSIZE) \
+ MEMBASE=$(MEMBASE) \
+ BASE_ADDR=$(BASE_ADDR) \
+ TAGS_ADDR=$(TAGS_ADDR) \
+ KERNEL_ADDR=$(KERNEL_ADDR) \
+ RAMDISK_ADDR=$(RAMDISK_ADDR) \
+ SCRATCH_ADDR=$(SCRATCH_ADDR)
+
+
+OBJS += \
+ $(LOCAL_DIR)/init.o \
+ $(LOCAL_DIR)/keypad.o \
+ $(LOCAL_DIR)/atags.o
diff --git a/target/msm7627a/tools/makefile b/target/msm7627a/tools/makefile
new file mode 100644
index 0000000..09bc134
--- /dev/null
+++ b/target/msm7627a/tools/makefile
@@ -0,0 +1,38 @@
+#Makefile to generate appsboot.mbn
+
+ifeq ($(BOOTLOADER_OUT),.)
+APPSBOOTHEADER_DIR := $(BUILDDIR)
+else
+APPSBOOTHEADER_DIR := $(BOOTLOADER_OUT)/../../
+endif
+
+SRC_DIR := target/$(TARGET)/tools
+COMPILER := gcc
+
+ifeq ($(EMMC_BOOT), 1)
+ APPSBOOTHDR_FILES := EMMCBOOT.MBN emmc_appsboothd.mbn
+else
+ ifeq ($(BUILD_NANDWRITE), 1)
+ APPSBOOTHDR_FILES :=
+ else
+ APPSBOOTHDR_FILES := appsboot.mbn appsboothd.mbn
+ endif
+endif
+
+APPSBOOTHEADER: $(APPSBOOTHDR_FILES)
+
+appsboot.mbn: $(OUTBIN)
+ cp -f $(OUTBIN) $(APPSBOOTHEADER_DIR)/appsboot.mbn
+
+appsboothd.mbn: mkheader $(OUTBIN)
+ $(SRC_DIR)/mkheader $(OUTBIN) $(APPSBOOTHEADER_DIR)/appsboothd.mbn
+
+EMMCBOOT.MBN: $(OUTBIN)
+ cp -f $(OUTBIN) $(APPSBOOTHEADER_DIR)/EMMCBOOT.MBN
+ cp -f $(OUTBIN) $(APPSBOOTHEADER_DIR)/emmc_appsboot.mbn
+
+emmc_appsboothd.mbn: mkheader $(OUTBIN)
+ $(SRC_DIR)/mkheader $(OUTBIN) $(APPSBOOTHEADER_DIR)/emmc_appsboothd.mbn unified-boot
+
+mkheader: $(SRC_DIR)/mkheader.c
+ ${COMPILER} $(SRC_DIR)/mkheader.c -o $(SRC_DIR)/mkheader
diff --git a/target/msm7627a/tools/mkheader.c b/target/msm7627a/tools/mkheader.c
new file mode 100644
index 0000000..2bd3479
--- /dev/null
+++ b/target/msm7627a/tools/mkheader.c
@@ -0,0 +1,87 @@
+/* Copyright 2007, Google Inc. */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <fcntl.h>
+
+#include <sys/stat.h>
+
+int main(int argc, char *argv[])
+{
+ struct stat s;
+ unsigned size, base;
+ int unified_boot = 0;
+ unsigned unified_boot_magic[20];
+ unsigned non_unified_boot_magic[10];
+ unsigned magic_len = 0;
+ unsigned *magic;
+ int fd;
+
+ if(argc < 3) {
+ fprintf(stderr,"usage: mkheader <bin> <hdr>\n");
+ return -1;
+ }
+
+ if (argc == 4) {
+ if(!strcmp("unified-boot",argv[3])) {
+ unified_boot = 1;
+ }
+ }
+
+ if(stat(argv[1], &s)) {
+ perror("cannot stat binary");
+ return -1;
+ }
+
+ if(unified_boot) {
+ magic = unified_boot_magic;
+ magic_len = sizeof(unified_boot_magic);
+ } else {
+ magic = non_unified_boot_magic;
+ magic_len = sizeof(non_unified_boot_magic);
+ }
+
+ size = s.st_size;
+ base = 0;
+
+ magic[0] = 0x00000005; /* appsbl */
+ magic[1] = 0x00000002; /* nand */
+ magic[2] = 0x00000000;
+ magic[3] = base;
+ magic[4] = size;
+ magic[5] = size;
+ magic[6] = size + base;
+ magic[7] = 0x00000000;
+ magic[8] = size + base;
+ magic[9] = 0x00000000;
+
+ if (unified_boot == 1)
+ {
+ magic[10] = 0x33836685; /* cookie magic number */
+ magic[11] = 0x00000001; /* cookie version */
+ magic[12] = 0x00000002; /* file formats */
+ magic[13] = 0x00000000;
+ magic[14] = 0x00000000; /* not setting size for boot.img */
+ magic[15] = 0x00000000;
+ magic[16] = 0x00000000;
+ magic[17] = 0x00000000;
+ magic[18] = 0x00000000;
+ magic[19] = 0x00000000;
+ }
+
+ fd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, 0644);
+ if(fd < 0) {
+ perror("cannot open header for writing");
+ return -1;
+ }
+ if(write(fd, magic, magic_len) != magic_len) {
+ perror("cannot write header");
+ close(fd);
+ unlink(argv[2]);
+ return -1;
+ }
+ close(fd);
+
+ return 0;
+}