Merge "[msm8x60]: Remove support for bringing secondary core out of reset"
diff --git a/platform/msm8x60/acpuclock.c b/platform/msm8x60/acpuclock.c
index 9709966..37d49b0 100644
--- a/platform/msm8x60/acpuclock.c
+++ b/platform/msm8x60/acpuclock.c
@@ -43,32 +43,6 @@
}
-void config_mdp_axi_clk(uint8_t use_pxo){
- /* Program MM_PLL0 (PLL1) @ 1320 MHz and turn it on. */
- rmwreg(0, MM_PLL0_MODE_REG, (1<<0)); /* Disable output */
- writel(48, MM_PLL0_L_VAL_REG);
- writel(8, MM_PLL0_M_VAL_REG);
- writel(9, MM_PLL0_N_VAL_REG);
- /* Set ref, enable. */
- if (use_pxo)
- rmwreg((1<<1), MM_PLL0_MODE_REG, (1<<4)|(1<<1)); /* PXO */
- else
- rmwreg((1<<4)|(1<<1), MM_PLL0_MODE_REG, (1<<4)|(1<<1)); /* MXO */
- udelay(10);
- writel(0x14580, MM_PLL0_CONFIG_REG); /* Enable MN, set VCO, misc */
- rmwreg((1<<2), MM_PLL0_MODE_REG, (1<<2)); /* Deassert reset */
- rmwreg((1<<0), MM_PLL0_MODE_REG, (1<<0)); /* Enable output */
-
- /* Set up MM AHB clock to PLL8/5. */
- //local_src_enable(PLL_8);
- rmwreg(0x0102, AHB_NS_REG, 0x43C7);
- udelay(200); /* Wait before using registers clocked by MM AHB_CLK. */
-
- /* Set up MM Fabric (AXI). */
- writel(0x4248451, AXI_NS_REG);
-}
-
-
/* Enable/disable for non-shared NT PLLs. */
int nt_pll_enable(uint8_t src, uint8_t enable)
{
@@ -297,21 +271,3 @@
writel(val, USB_HS1_XVCR_FS_CLK_NS);
}
-/* Return true if PXO is 27MHz. */
-int pxo_is_27mhz(void)
-{
- uint32_t xo_sel;
- int pll8_ref_is_27mhz = 0;
-
- /* PLL8 is assumed to be at 384MHz. Check if the 384/(L+M/N) == 27. */
- if (readl(BB_PLL8_L_VAL_REG) == 14 && readl(BB_PLL8_M_VAL_REG) == 2
- && readl(BB_PLL8_N_VAL_REG) == 9)
- pll8_ref_is_27mhz = 1;
-
- /* Check which source is used with above L, M, N vals.
- * xo_sel: 0=PXO, else MXO */
- xo_sel = readl(BB_PLL8_MODE_REG) & (1 << 4);
-
- return (xo_sel == 0 && pll8_ref_is_27mhz);
-}
-
diff --git a/platform/msm8x60/panel.c b/platform/msm8x60/panel.c
index 6782773..ee94eb8 100644
--- a/platform/msm8x60/panel.c
+++ b/platform/msm8x60/panel.c
@@ -346,10 +346,6 @@
void mdp_clock_init(void)
{
- int uxo = pxo_is_27mhz();
- /* Set the MDP_AXI_CLK to 165MHz, use MX0 for now */
- config_mdp_axi_clk(uxo);
-
/* Turn on the PLL2, to ramp up the MDP clock to max (200MHz) */
nt_pll_enable(PLL_2, 1);