| commit | 278ff00103de8a0d50a595793a5067b3df3670ea | [log] [tgz] |
|---|---|---|
| author | Channagoud Kadabi <ckadabi@codeaurora.org> | Tue May 13 14:23:27 2014 -0700 |
| committer | Channagoud Kadabi <ckadabi@codeaurora.org> | Tue May 13 14:24:47 2014 -0700 |
| tree | 9aeef3d71e08936a99a4a016258fe0de17ac9f1e | |
| parent | e9f643b3d23989f7b3108cd2ff81c98d92a7f83e [diff] |
arch: arm: Fix cache enable code Cache enable code uses ACTLR register to enable L2 cache, ACTLR register is implementation defined and for krait cpu this code is disabling i-cache forcefully. This code impacts hlos performace by disabling i-cache forcefully. CRs-Fixed: 663851 Change-Id: I896cdc7d3f756b5c7ee98cf789f9c03ec0b6e723