arch: arm: Fix cache enable code
Cache enable code uses ACTLR register to enable L2 cache, ACTLR
register is implementation defined and for krait cpu this code
is disabling i-cache forcefully. This code impacts hlos performace
by disabling i-cache forcefully.
CRs-Fixed: 663851
Change-Id: I896cdc7d3f756b5c7ee98cf789f9c03ec0b6e723
diff --git a/arch/arm/cache-ops.S b/arch/arm/cache-ops.S
index 4f66c00..a1151ab 100644
--- a/arch/arm/cache-ops.S
+++ b/arch/arm/cache-ops.S
@@ -190,13 +190,6 @@
// NOTE: trashes a bunch of registers, can't be spilling stuff to the stack
bl invalidate_cache_v7
-#if ARM_WITH_L2
- // enable the L2, if present
- mrc p15, 0, r0, c1, c0, 1 // aux cr1
- orr r0, #(1<<1)
- mcr p15, 0, r0, c1, c0, 1 // enable L2 dcache
-#endif
-
mrc p15, 0, r0, c1, c0, 0 // cr1
orr r0, #(1<<2)
mcr p15, 0, r0, c1, c0, 0 // enable dcache