[msm]: Enable display driver by default for splash screen on 7627 & 8650
If rgb565 image is available in splash partition then display it
as splash screen.
On Linux, splash.img can be created as follows:
convert -depth 8 splash.png rgb:- | out/host/linux-x86/bin/rgb2565 > splash.img
Change-Id: I24b61cbc94af4bac14b9a49b030b59484a0b283e
diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
old mode 100755
new mode 100644
index 5b09a2b..fb80f38
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -278,7 +278,6 @@
struct ptable *ptable;
unsigned offset = 0;
const char *cmdline;
- struct fbcon_config *fb_display = NULL;
if (target_is_emmc_boot()) {
hdr = (struct boot_img_hdr *)EMMC_BOOT_IMG_HEADER_ADDR;
@@ -295,22 +294,6 @@
return -1;
}
-#if DISPLAY_SPLASH_SCREEN
- ptn = ptable_find(ptable, "splash");
- if (ptn == NULL) {
- dprintf(CRITICAL, "ERROR: No splash partition found\n");
- } else {
- fb_display = fbcon_display();
- if (fb_display) {
- if (flash_read(ptn, 0, fb_display->base,
- (fb_display->width * fb_display->height * fb_display->bpp/8))) {
- fbcon_clear();
- dprintf(CRITICAL, "ERROR: Cannot read splash image\n");
- }
- }
- }
-#endif
-
if(!boot_into_recovery)
{
ptn = ptable_find(ptable, "boot");
@@ -535,17 +518,43 @@
reboot_device(FASTBOOT_MODE);
}
+void splash_screen ()
+{
+ struct ptentry *ptn;
+ struct ptable *ptable;
+ struct fbcon_config *fb_display = NULL;
+
+ if (!target_is_emmc_boot())
+ {
+ ptable = flash_get_ptable();
+ if (ptable == NULL) {
+ dprintf(CRITICAL, "ERROR: Partition table not found\n");
+ return -1;
+ }
+
+ ptn = ptable_find(ptable, "splash");
+ if (ptn == NULL) {
+ dprintf(CRITICAL, "ERROR: No splash partition found\n");
+ } else {
+ fb_display = fbcon_display();
+ if (fb_display) {
+ if (flash_read(ptn, 0, fb_display->base,
+ (fb_display->width * fb_display->height * fb_display->bpp/8))) {
+ fbcon_clear();
+ dprintf(CRITICAL, "ERROR: Cannot read splash image\n");
+ }
+ }
+ }
+ }
+}
+
void aboot_init(const struct app_descriptor *app)
{
unsigned reboot_mode = 0;
unsigned disp_init = 0;
unsigned usb_init = 0;
- #if DISPLAY_SPLASH_SCREEN
- display_init();
- dprintf(INFO, "Diplay initialized\n");
- disp_init = 1;
- #endif
+ /* Setup page size information for nand/emmc reads */
if (target_is_emmc_boot())
{
page_size = 2048;
@@ -557,6 +566,15 @@
page_mask = page_size - 1;
}
+ /* Display splash screen if enabled */
+ #if DISPLAY_SPLASH_SCREEN
+ display_init();
+ dprintf(INFO, "Diplay initialized\n");
+ disp_init = 1;
+ splash_screen();
+ #endif
+
+ /* Check if we should do something other than booting up */
if (keys_get_state(KEY_HOME) != 0)
boot_into_recovery = 1;
if (keys_get_state(KEY_BACK) != 0)
@@ -592,12 +610,7 @@
"to fastboot mode.\n");
fastboot:
- if(!disp_init) {
- display_init();
- } else {
- fbcon_clear();
- }
- dprintf(INFO, "Diplay initialized\n");
+
if(!usb_init)
udc_init(&surf_udc_device);
diff --git a/app/aboot/recovery.c b/app/aboot/recovery.c
old mode 100755
new mode 100644
diff --git a/app/aboot/recovery.h b/app/aboot/recovery.h
old mode 100755
new mode 100644
diff --git a/dev/fbcon/fbcon.c b/dev/fbcon/fbcon.c
index 5aadb1f..1daca98 100644
--- a/dev/fbcon/fbcon.c
+++ b/dev/fbcon/fbcon.c
@@ -42,7 +42,7 @@
static struct fbcon_config *config = NULL;
-#define RGB565_BLUE 0x001f
+#define RGB565_BLACK 0x0000
#define RGB565_WHITE 0xffff
#define FONT_WIDTH 5
@@ -179,7 +179,7 @@
switch (config->format) {
case FB_FORMAT_RGB565:
- bg = RGB565_BLUE;
+ bg = RGB565_BLACK;
fg = RGB565_WHITE;
break;
@@ -191,7 +191,7 @@
fbcon_set_colors(bg, fg);
- fbcon_clear();
+ //fbcon_clear();
fbcon_flush();
cur_pos.x = 0;
diff --git a/target/msm7627_ffa/panel.c b/platform/msm7k/panel.c
similarity index 99%
rename from target/msm7627_ffa/panel.c
rename to platform/msm7k/panel.c
index c2b56a1..672339d 100644
--- a/target/msm7627_ffa/panel.c
+++ b/platform/msm7k/panel.c
@@ -3,7 +3,7 @@
#include <debug.h>
#include <dev/gpio.h>
#include <kernel/thread.h>
-#include <platform/mddi.h>
+#include <mddi.h>
#define MDDI_CLIENT_CORE_BASE 0x108000
#define LCD_CONTROL_BLOCK_BASE 0x110000
diff --git a/platform/msm7k/platform.c b/platform/msm7k/platform.c
index 409af52..45d51a9 100755
--- a/platform/msm7k/platform.c
+++ b/platform/msm7k/platform.c
@@ -34,7 +34,7 @@
#include <debug.h>
#include <kernel/thread.h>
#include <platform/debug.h>
-#include <platform/mddi.h>
+#include <mddi.h>
#include <dev/fbcon.h>
static struct fbcon_config *fb_config;
diff --git a/platform/msm7k/rules.mk b/platform/msm7k/rules.mk
index 408303a..d073796 100755
--- a/platform/msm7k/rules.mk
+++ b/platform/msm7k/rules.mk
@@ -11,8 +11,8 @@
OBJS += \
$(LOCAL_DIR)/platform.o \
$(LOCAL_DIR)/interrupts.o \
- $(LOCAL_DIR)/mddi.o \
$(LOCAL_DIR)/gpio.o \
+ $(LOCAL_DIR)/panel.o \
$(LOCAL_DIR)/acpuclock.o
LINKER_SCRIPT += $(BUILDDIR)/system-onesegment.ld
diff --git a/platform/msm_shared/hsusb.c b/platform/msm_shared/hsusb.c
old mode 100755
new mode 100644
diff --git a/platform/msm7k/include/platform/mddi.h b/platform/msm_shared/include/mddi.h
similarity index 100%
rename from platform/msm7k/include/platform/mddi.h
rename to platform/msm_shared/include/mddi.h
diff --git a/platform/msm_shared/lcdc.c b/platform/msm_shared/lcdc.c
index 9970923..fbbbb2d 100755
--- a/platform/msm_shared/lcdc.c
+++ b/platform/msm_shared/lcdc.c
@@ -102,8 +102,6 @@
fb_cfg.base =
memalign(4096, fb_cfg.width * fb_cfg.height * (fb_cfg.bpp / 8));
- lcdc_clock_init(1000000000 / LCDC_PIXCLK_IN_PS);
-
writel((unsigned) fb_cfg.base, MSM_MDP_BASE1 + 0x90008);
writel((fb_cfg.height << 16) | fb_cfg.width, MSM_MDP_BASE1 + 0x90004);
diff --git a/platform/msm7k/mddi.c b/platform/msm_shared/mddi.c
similarity index 80%
rename from platform/msm7k/mddi.c
rename to platform/msm_shared/mddi.c
index 7472953..2b26e1c 100644
--- a/platform/msm7k/mddi.c
+++ b/platform/msm_shared/mddi.c
@@ -32,8 +32,8 @@
#include <string.h>
#include <dev/fbcon.h>
#include <kernel/thread.h>
-#include <platform/iomap.h>
-#include <platform/mddi.h>
+#include <mddi.h>
+#include <target/display.h>
#include "mddi_hw.h"
@@ -41,7 +41,7 @@
static mddi_llentry *mlist_remote_write = NULL;
#define MDDI_MAX_REV_PKT_SIZE 0x60
-#define MDDI_REV_PKT_BUF_SIZE (MDDI_MAX_REV_PKT_SIZE * 4)
+#define MDDI_REV_PKT_BUF_SIZE 256
static void *rev_pkt_buf;
/* functions provided by the target specific panel code */
@@ -140,6 +140,8 @@
memset(rev_pkt_buf, 0xee, MDDI_REV_PKT_BUF_SIZE);
writel((unsigned) rev_pkt_buf, MDDI_REV_PTR);
writel((unsigned) rev_pkt_buf, MDDI_REV_PTR);
+ writel(MDDI_REV_PKT_BUF_SIZE, MDDI_REV_SIZE);
+ writel(MDDI_REV_PKT_BUF_SIZE, MDDI_REV_ENCAP_SZ);
mddi_do_cmd(CMD_FORCE_NEW_REV_PTR);
}
@@ -150,6 +152,52 @@
mddi_do_cmd(CMD_HIBERNATE | !!on);
}
+void mddi_set_caps(mddi_client_caps *c)
+{
+ /* Hardcoding the capability values */
+ c->length = 74;
+ c->type = 66;
+ c->client_id = 0;
+ c->protocol_ver = 1;
+ c->min_protocol_ver = 1;
+ c->data_rate_cap = 400;
+ c->interface_type_cap = 0;
+ c->num_alt_displays = 1;
+ c->postcal_data_rate = 400;
+ c->bitmap_width = TARGET_XRES;
+ c->bitmap_height = TARGET_YRES;
+ c->display_window_width = TARGET_XRES;
+ c->display_window_height = TARGET_YRES;
+ c->cmap_size = 0;
+ c->cmap_rgb_width = 0;
+ c->rgb_cap = 34592;
+ c->mono_cap = 0;
+ c->reserved1 = 0;
+ c->ycbcr_cap = 0;
+ c->bayer_cap = 0;
+ c->alpha_cursor_planes = 0;
+ c->client_feature_cap = 4489216;
+ c->max_video_frame_rate_cap = 60;
+ c->min_video_frame_rate_cap = 0;
+ c->min_sub_frame_rate = 0;
+ c->audio_buf_depth = 0;
+ c->audio_channel_cap = 0;
+ c->audio_sampe_rate_rap = 0;
+ c->audio_sample_res = 0;
+ c->mic_audio_sample_res = 0;
+ c->mic_sample_rate_cap = 0;
+ c->keyboard_data_fmt = 0;
+ c->pointing_device_data_fmt = 0;
+ c->content_protection_type = 0;
+ c->manufacturer_name = 53859;
+ c->product_code = 34594;
+ c->reserved3 = 0;
+ c->serial_no = 1;
+ c->week_of_manufacture = 0;
+ c->year_of_manufacture = 0;
+ c->crc = 53536;
+}
+
static void mddi_get_caps(struct mddi_client_caps *caps)
{
unsigned timeout = 100000;
@@ -182,7 +230,6 @@
static unsigned mddi_init_regs(void)
{
- mddi_set_auto_hibernate(0);
mddi_do_cmd(CMD_RESET);
mddi_do_cmd(CMD_PERIODIC_REV_ENC);
@@ -192,17 +239,11 @@
writel(0x0003, MDDI_SPM);
writel(0x0005, MDDI_TA1_LEN);
- writel(0x000C, MDDI_TA2_LEN);
+ writel(0x001A, MDDI_TA2_LEN);
writel(0x0096, MDDI_DRIVE_HI);
writel(0x0050, MDDI_DRIVE_LO);
writel(0x003C, MDDI_DISP_WAKE);
- writel(0x0002, MDDI_REV_RATE_DIV);
-
- writel(MDDI_REV_PKT_BUF_SIZE, MDDI_REV_SIZE);
-// writel(MDDI_REV_PKT_BUF_SIZE, MDDI_REV_ENCAP_SZ);
- writel(MDDI_MAX_REV_PKT_SIZE, MDDI_REV_ENCAP_SZ);
-
- mddi_do_cmd(CMD_PERIODIC_REV_ENC);
+ writel(0x0004, MDDI_REV_RATE_DIV);
/* needs to settle for 5uS */
if (readl(MDDI_PAD_CTL) == 0) {
@@ -213,11 +254,11 @@
writel(0xA850F, MDDI_PAD_CTL);
writel(0x60006, MDDI_DRIVER_START_CNT);
- /* disable hibernate */
- mddi_set_auto_hibernate(0);
- mddi_do_cmd(CMD_IGNORE);
-
mddi_init_rev_encap();
+
+ /* disable hibernate */
+ mddi_do_cmd(CMD_HIBERNATE | 0);
+
return readl(MDDI_CORE_VER) & 0xffff;
}
@@ -234,8 +275,11 @@
n = mddi_init_regs();
dprintf(INFO, "mddi version: 0x%08x\n", n);
- mddi_get_caps(&client_caps);
- ASSERT(client_caps.length == 0x4a && client_caps.type == 0x42);
+ //mddi_get_caps(&client_caps);
+ //if(!(client_caps.length == 0x4a && client_caps.type == 0x42))
+ {
+ mddi_set_caps(&client_caps);
+ }
fb_cfg.width = client_caps.bitmap_width;
fb_cfg.stride = fb_cfg.width;
@@ -258,7 +302,7 @@
mlist = memalign(32, sizeof(mddi_llentry) * (fb_cfg.height / 8));
dprintf(INFO, "FB @ %p mlist @ %x\n", fb_cfg.base, (unsigned) mlist);
-
+
for(n = 0; n < (fb_cfg.height / 8); n++) {
unsigned y = n * 8;
unsigned pixels = fb_cfg.width * 8;
@@ -269,19 +313,19 @@
vs->client_id = 0;
vs->format = 0x5565; // FORMAT_16BPP;
vs->pixattr = PIXATTR_BOTH_EYES | PIXATTR_TO_ALL;
-
+
vs->left = 0;
vs->right = fb_cfg.width - 1;
vs->top = y;
vs->bottom = y + 7;
-
+
vs->start_x = 0;
vs->start_y = y;
-
+
vs->pixels = pixels;
vs->crc = 0;
vs->reserved = 0;
-
+
mlist[n].header_count = sizeof(mddi_video_stream) - 2;
mlist[n].data_count = pixels * 2;
mlist[n].reserved = 0;
diff --git a/platform/msm7k/mddi_hw.h b/platform/msm_shared/mddi_hw.h
similarity index 98%
rename from platform/msm7k/mddi_hw.h
rename to platform/msm_shared/mddi_hw.h
index 814ea0e..b47eadc 100644
--- a/platform/msm7k/mddi_hw.h
+++ b/platform/msm_shared/mddi_hw.h
@@ -29,7 +29,11 @@
#ifndef __PLATFORM_MSM7K_MDDI_HW_H
#define __PLATFORM_MSM7K_MDDI_HW_H
+#ifdef TARGET_MSM7630_SURF
+#define MSM_MDDI_BASE 0xAD600000
+#else
#define MSM_MDDI_BASE 0xAA600000
+#endif
/* see 80-VA736-2 C pp 776-787 */
diff --git a/platform/msm_shared/mmc.c b/platform/msm_shared/mmc.c
old mode 100755
new mode 100644
diff --git a/platform/msm_shared/nand.c b/platform/msm_shared/nand.c
old mode 100755
new mode 100644
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
old mode 100755
new mode 100644
index f08aa9c..6348d5a
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -3,6 +3,9 @@
INCLUDES += \
-I$(LOCAL_DIR)/include
+DEFINES += $(TARGET_XRES)
+DEFINES += $(TARGET_YRES)
+
OBJS += \
$(LOCAL_DIR)/uart.o \
$(LOCAL_DIR)/timer.o \
@@ -15,5 +18,6 @@
$(LOCAL_DIR)/jtag.o \
$(LOCAL_DIR)/nand.o \
$(LOCAL_DIR)/lcdc.o \
+ $(LOCAL_DIR)/mddi.o \
$(LOCAL_DIR)/mmc.o
diff --git a/target/msm7627_ffa/panel.c b/platform/qsd8k/panel.c
similarity index 62%
copy from target/msm7627_ffa/panel.c
copy to platform/qsd8k/panel.c
index c2b56a1..012c109 100644
--- a/target/msm7627_ffa/panel.c
+++ b/platform/qsd8k/panel.c
@@ -3,7 +3,7 @@
#include <debug.h>
#include <dev/gpio.h>
#include <kernel/thread.h>
-#include <platform/mddi.h>
+#include <mddi.h>
#define MDDI_CLIENT_CORE_BASE 0x108000
#define LCD_CONTROL_BLOCK_BASE 0x110000
@@ -139,6 +139,7 @@
#define WKREQ (SYSTEM_BLOCK1_BASE|0x00)
#define CLKENB (SYSTEM_BLOCK1_BASE|0x04)
#define DRAMPWR (SYSTEM_BLOCK1_BASE|0x08)
+#define CNT_DIS (SYSTEM_BLOCK1_BASE|0x10)
#define INTMASK (SYSTEM_BLOCK1_BASE|0x0C)
#define GPIOSEL (SYSTEM_BLOCK2_BASE|0x00)
@@ -147,9 +148,194 @@
unsigned int val;
};
+static struct init_table toshiba_480x800_init_table[] = {
+ { DPSET0, 0x4BEC0066 }, // # MDC.DPSET0 # Setup DPLL parameters
+ { DPSET1, 0x00000113 }, // # MDC.DPSET1
+ { DPSUS, 0x00000000 }, // # MDC.DPSUS # Set DPLL oscillation enable
+ { DPRUN, 0x00000001 }, // # MDC.DPRUN # Release reset signal for DPLL
+ { 0, 15 }, // wait_ms(15);
+ { SYSCKENA, 0x00000001 }, // # MDC.SYSCKENA # Enable system clock output
+ { CLKENB, 0x000000E9 }, // # SYS.CLKENB # Enable clocks for each module (without DCLK , i2cCLK)
+
+ { GPIO_BLOCK_BASE, 0x03FF0000 }, // # GPI .GPIODATA # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0
+ { GPIODIR, 0x0000024D }, // # GPI .GPIODIR # Select direction of GPIO port (0,2,3,6,9 output)
+ { SYSTEM_BLOCK2_BASE, 0x00000173 }, // # SYS.GPIOSEL # GPIO port multiplexing control
+ { GPIOPC, 0x03C300C0 }, // # GPI .GPIOPC # GPIO2,3 PD cut
+ { SYSTEM_BLOCK1_BASE, 0x00000000 }, // # SYS.WKREQ # Wake-up request event is VSYNC alignment
+ { GPIOIS, 0x00000000 }, // # GPI .GPIOIS # Set interrupt sense of GPIO
+ { GPIOIEV, 0x00000001 }, // # GPI .GPIOIEV # Set interrupt event of GPIO
+ { GPIOIC, 0x000003FF }, // # GPI .GPIOIC # GPIO interrupt clear
+ { GPIO_BLOCK_BASE, 0x00040004 }, // # GPI .GPIODATA # Release LCDD reset
+ { GPIO_BLOCK_BASE, 0x00080008 }, // # GPI .GPIODATA # eDRAM VD supply
+ { DRAMPWR, 0x00000001 }, // # SYS.DRAMPWR # eDRAM power up
+ { CLKENB, 0x0000A0EB }, // # enable eDRAM clock
+
+ { PWMCR, 0x00000000 }, // # PWM.PWMCR # PWM output enable
+ { 0, 1 }, // wait_ms(1);
+ { SPI_BLOCK_BASE, 0x00060399}, // # SPI .SSICTL # SPI operation mode setting
+ { SSITIME, 0x00000100 }, // # SPI .SSITIME # SPI serial interface timing setting
+ { CNT_DIS, 0x00000100 }, // # SPI .SSITIME # SPI serial interface timing setting
+ { SPI_BLOCK_BASE, 0x0006039B }, // # SPI .SSICTL # Set SPI active mode
+
+ { SSITX, 0x00000000 }, // # SPI.SSITX # Release from Deep Stanby mode
+ { 0, 2 }, // wait_ms(2);
+ { SSITX, 0x00000000 }, // # SPI.SSITX
+ { 0, 2 }, // wait_ms(2);
+ { SSITX, 0x00000000 }, // # SPI.SSITX
+ { 0, 2 }, // wait_ms(2);
+
+ { SSITX, 0x000800BA }, // # SPI.SSITX *NOTE 1 # Command setting of SPI block
+ { SSITX, 0x00000111 }, // # Display mode setup(1) : Normaly Black
+ { SSITX, 0x00080036 }, // # Command setting of SPI block
+ { SSITX, 0x00000100 }, // # Memory access control
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x0008003A }, // # Command setting of SPI block
+ { SSITX, 0x00000160 }, // # Display mode setup(2)
+ { SSITX, 0x000800B1 }, // # Command setting of SPI block
+ { SSITX, 0x0000015D }, // # RGB Interface data format
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800B2 }, // # Command setting of SPI block
+ { SSITX, 0x00000133 }, // # Drivnig method
+ { SSITX, 0x000800B3 }, // # Command setting of SPI block
+ { SSITX, 0x00000122 }, // # Booster operation setup
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800B4 }, // # Command setting of SPI block
+ { SSITX, 0x00000102 }, // # OP-amp capability/System clock freq. division setup
+ { SSITX, 0x000800B5 }, // # Command setting of SPI block
+ { SSITX, 0x0000011E }, // # VCS Voltage adjustment (1C->1F for Rev 2)
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800B6 }, // # Command setting of SPI block
+ { SSITX, 0x00000127 }, // # VCOM Voltage adjustment
+ { SSITX, 0x000800B7 }, // # Command setting of SPI block
+ { SSITX, 0x00000103 }, // # Configure an external display signal
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800B9 }, // # Command setting of SPI block
+ { SSITX, 0x00000124 }, // # DCCK/DCEV timing setup
+ { SSITX, 0x000800BD }, // # Command setting of SPI block
+ { SSITX, 0x000001A1 }, // # ASW signal control
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800BB }, // # Command setting of SPI block
+ { SSITX, 0x00000100 }, // # Dummy display (white/black) count setup for QUAD Data operation
+ { SSITX, 0x000800BF }, // # Command setting of SPI block
+ { SSITX, 0x00000101 }, // # Dummy display (white/black) count setup for QUAD Data operation
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800BE }, // # Command setting of SPI block
+ { SSITX, 0x00000100 }, // # wait_ms(-out FR count setup (A)
+ { SSITX, 0x000800C0 }, // # Command setting of SPI block
+ { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (A)
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800C1 }, // # Command setting of SPI block
+ { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (B)
+ { SSITX, 0x000800C2 }, // # Command setting of SPI block
+ { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (C)
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800C3 }, // # Command setting of SPI block
+ { SSITX, 0x00080132 }, // # wait_ms(-in line clock count setup (D)
+ { SSITX, 0x00000132 }, //
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800C4 }, // # Command setting of SPI block
+ { SSITX, 0x00080132 }, // # Seep-in line clock count setup (E)
+ { SSITX, 0x00000132 }, //
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800C5 }, // # Command setting of SPI block
+ { SSITX, 0x00080132 }, // # wait_ms(-in line clock count setup (F)
+ { SSITX, 0x00000132 }, //
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800C6 }, // # Command setting of SPI block
+ { SSITX, 0x00080132 }, // # wait_ms(-in line clock setup (G)
+ { SSITX, 0x00000132 }, //
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800C7 }, // # Command setting of SPI block
+ { SSITX, 0x00080164 }, // # Gamma 1 fine tuning (1)
+ { SSITX, 0x00000145 }, //
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800C8 }, // # Command setting of SPI block
+ { SSITX, 0x00000144 }, // # Gamma 1 fine tuning (2)
+ { SSITX, 0x000800C9 }, // # Command setting of SPI block
+ { SSITX, 0x00000152 }, // # Gamma 1 inclination adjustment
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800CA }, // # Command setting of SPI block
+ { SSITX, 0x00000100 }, // # Gamma 1 blue offset adjustment
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800EC }, // # Command setting of SPI block
+ { SSITX, 0x00080101 }, // # Total number of horizontal clock cycles (1) [PCLK Sync. VGA setting]
+ { SSITX, 0x000001FC }, //
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800CF }, // # Command setting of SPI block
+ { SSITX, 0x00000101 }, // # Blanking period control (1) [PCLK Sync. Table1 for VGA]
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800D0 }, // # Command setting of SPI block
+ { SSITX, 0x00080110 }, // # Blanking period control (2) [PCLK Sync. Table1 for VGA]
+ { SSITX, 0x00000104 }, //
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800D1 }, // # Command setting of SPI block
+ { SSITX, 0x00000101 }, // # CKV timing control on/off [PCLK Sync. Table1 for VGA]
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800D2 }, // # Command setting of SPI block
+ { SSITX, 0x00080100 }, // # CKV1,2 timing control [PCLK Sync. Table1 for VGA]
+ { SSITX, 0x00000128 }, //
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800D3 }, // # Command setting of SPI block
+ { SSITX, 0x00080100 }, // # OEV timing control [PCLK Sync. Table1 for VGA]
+ { SSITX, 0x00000128 }, //
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800D4 }, // # Command setting of SPI block
+ { SSITX, 0x00080126 }, // # ASW timing control (1) [PCLK Sync. Table1 for VGA]
+ { SSITX, 0x000001A4 }, //
+ { 0, 1 }, // wait_ms(1); // # Wait SPI fifo empty
+ { SSITX, 0x000800D5 }, // # Command setting of SPI block
+ { SSITX, 0x00000120 }, // # ASW timing control (2) [PCLK Sync. Table1 for VGA]
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+ { SSITX, 0x000800EF }, // # Command setting of SPI block
+ { SSITX, 0x00080132 }, // # Total number of horizontal clock cycles (2) [PCLK Sync. Table1 for QVGA ]
+ { SSITX, 0x00000100 }, //
+ { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
+
+ { BITMAP0, 0x032001E0 }, // MDC.BITMAP0 ); // Setup of PITCH size to Frame buffer1
+ { BITMAP1, 0x032001E0 }, // MDC.BITMAP1 ); // Setup of PITCH size to Frame buffer1
+ { BITMAP2, 0x014000F0 }, // MDC.BITMAP3 ); // Setup of PITCH size to Frame buffer2
+ { BITMAP3, 0x014000F0 }, // MDC.BITMAP4 ); // Setup of PITCH size to Frame buffer3
+ { BITMAP4, 0x014000F0 }, // MDC.BITMAP5 ); // Setup of PITCH size to Frame buffer4
+ { CLKENB, 0x0000A1EB }, // SYS.CLKENB ); // DCLK supply
+ { PORT_ENB, 0x00000001 }, // LCD.PORT_ENB ); // Synchronous port enable
+ { PORT, 0x00000004 }, // LCD.PORT ); // Polarity of DE is set to high active
+ { PXL, 0x00000002 }, // LCD.PXL ); // ACTMODE 2 set (1st frame black data output)
+ { MPLFBUF, 0x00000000 }, // LCD.MPLFBUF ); // Select the reading buffer
+ { HCYCLE, 0x000000FD }, // LCD.HCYCLE ); // Setup to VGA size
+ { HSW, 0x00000003 }, // LCD.HSW
+ { HDE_START, 0x00000007 }, // LCD.HDE_START
+ { HDE_SIZE, 0x000000EF }, // LCD.HDE_SIZE
+ { VCYCLE, 0x00000325 }, // LCD.VCYCLE
+ { VSW, 0x00000001 }, // LCD.VSW
+ { VDE_START, 0x00000003 }, // LCD.VDE_START
+ { VDE_SIZE, 0x0000031F }, // LCD.VDE_SIZE
+
+ { START, 0x00000001 }, // LCD.START ); // LCDC - Pixel data transfer start
+
+ { 0, 10 }, // wait_ms( 10 );
+ { SSITX, 0x000800BC }, // SPI.SSITX ); // Command setting of SPI block
+ { SSITX, 0x00000180 }, // Display data setup
+ { SSITX, 0x0008003B }, // Command setting of SPI block
+ { SSITX, 0x00000100 }, // Quad Data configuration - VGA
+ { 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty
+ { SSITX, 0x000800B0 }, // Command setting of SPI block
+ { SSITX, 0x00000116 }, // Power supply ON/OFF control
+ { 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty
+ { SSITX, 0x000800B8 }, // Command setting of SPI block
+ { SSITX, 0x000801FF }, // Output control
+ { SSITX, 0x000001F5 },
+ { 0, 1 }, // wait_ms( 1); // Wait SPI fifo empty
+ { SSITX, 0x00000011 }, // wait_ms(-out (Command only)
+ { SSITX, 0x00000029 }, // Display on (Command only)
+
+ //{ SYSTEM_BLOCK1_BASE, 0x00000002 }, // # wakeREQ -> GPIO
+
+ { 0, 0 }
+};
+
static struct init_table toshiba_480x640_init_table[] = {
{ DPSET0, 0x4BEC0066 }, // # MDC.DPSET0 # Setup DPLL parameters
- { DPSET1, 0x00000113 }, // # MDC.DPSET1
+ { DPSET1, 0x00000113 }, // # MDC.DPSET1
{ DPSUS, 0x00000000 }, // # MDC.DPSUS # Set DPLL oscillation enable
{ DPRUN, 0x00000001 }, // # MDC.DPRUN # Release reset signal for DPLL
{ 0, 14 }, // wait_ms(14);
@@ -169,7 +355,7 @@
{ DRAMPWR, 0x00000001 }, // # SYS.DRAMPWR # eDRAM power up
{ TIMER0CONTROL, 0x00000060 }, // # PWM.Timer0Control # PWM0 output stop
{ PWM_BLOCK_BASE, 0x00001388 }, // # PWM.Timer0Load # PWM0 10kHz , Duty 99 (BackLight OFF)
- //{PWM0OFF, 0x00000001 }, // # PWM.PWM0OFF
+ //{PWM0OFF, 0x00000001 }, // # PWM.PWM0OFF
#if 0
{ PWM0OFF, 0x00001387 }, // SURF 100% backlight
{ PWM0OFF, 0x00000000 }, // FFA 100% backlight
@@ -177,21 +363,21 @@
{ PWM0OFF, 0x000009C3 }, // 50% BL
{ TIMER1CONTROL, 0x00000060 }, // # PWM.Timer1Control # PWM1 output stop
{ TIMER1LOAD, 0x00001388 }, // # PWM.Timer1Load # PWM1 10kHz , Duty 99 (BackLight OFF)
- //{PWM1OFF, 0x00000001 }, // # PWM.PWM1OFF
+ //{PWM1OFF, 0x00000001 }, // # PWM.PWM1OFF
{ PWM1OFF, 0x00001387 },
{ TIMER0CONTROL, 0x000000E0 }, // # PWM.Timer0Control # PWM0 output start
{ TIMER1CONTROL, 0x000000E0 }, // # PWM.Timer1Control # PWM1 output start
{ PWMCR, 0x00000003 }, // # PWM.PWMCR # PWM output enable
- { 0, 1 }, // wait_ms(1);
+ { 0, 1 }, // wait_ms(1);
{ SPI_BLOCK_BASE, 0x00000799 }, // # SPI .SSICTL # SPI operation mode setting
{ SSITIME, 0x00000100 }, // # SPI .SSITIME # SPI serial interface timing setting
{ SPI_BLOCK_BASE, 0x0000079b }, // # SPI .SSICTL # Set SPI active mode
{ SSITX, 0x00000000 }, // # SPI.SSITX # Release from Deep Stanby mode
{ 0, 1 }, // wait_ms(1);
- { SSITX, 0x00000000 }, // # SPI.SSITX
+ { SSITX, 0x00000000 }, // # SPI.SSITX
{ 0, 1 }, // wait_ms(1);
- { SSITX, 0x00000000 }, // # SPI.SSITX
+ { SSITX, 0x00000000 }, // # SPI.SSITX
{ 0, 1 }, // wait_ms(1);
{ SSITX, 0x000800BA }, // # SPI.SSITX *NOTE 1 # Command setting of SPI block
{ SSITX, 0x00000111 }, // # Display mode setup(1) : Normaly Black
@@ -240,23 +426,23 @@
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800C3 }, // # Command setting of SPI block
{ SSITX, 0x0008010A }, // # wait_ms(-in line clock count setup (D)
- { SSITX, 0x0000010A }, //
+ { SSITX, 0x0000010A }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800C4 }, // # Command setting of SPI block
{ SSITX, 0x00080160 }, // # Seep-in line clock count setup (E)
- { SSITX, 0x00000160 }, //
+ { SSITX, 0x00000160 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800C5 }, // # Command setting of SPI block
{ SSITX, 0x00080160 }, // # wait_ms(-in line clock count setup (F)
- { SSITX, 0x00000160 }, //
+ { SSITX, 0x00000160 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800C6 }, // # Command setting of SPI block
{ SSITX, 0x00080160 }, // # wait_ms(-in line clock setup (G)
- { SSITX, 0x00000160 }, //
+ { SSITX, 0x00000160 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800C7 }, // # Command setting of SPI block
{ SSITX, 0x00080133 }, // # Gamma 1 fine tuning (1)
- { SSITX, 0x00000143 }, //
+ { SSITX, 0x00000143 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800C8 }, // # Command setting of SPI block
{ SSITX, 0x00000144 }, // # Gamma 1 fine tuning (2)
@@ -268,58 +454,58 @@
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800EC }, // # Command setting of SPI block
{ SSITX, 0x00080102 }, // # Total number of horizontal clock cycles (1) [PCLK Sync. VGA setting]
- { SSITX, 0x00000118 }, //
+ { SSITX, 0x00000118 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800CF }, // # Command setting of SPI block
{ SSITX, 0x00000101 }, // # Blanking period control (1) [PCLK Sync. Table1 for VGA]
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800D0 }, // # Command setting of SPI block
{ SSITX, 0x00080110 }, // # Blanking period control (2) [PCLK Sync. Table1 for VGA]
- { SSITX, 0x00000104 }, //
+ { SSITX, 0x00000104 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800D1 }, // # Command setting of SPI block
{ SSITX, 0x00000101 }, // # CKV timing control on/off [PCLK Sync. Table1 for VGA]
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800D2 }, // # Command setting of SPI block
{ SSITX, 0x00080100 }, // # CKV1,2 timing control [PCLK Sync. Table1 for VGA]
- { SSITX, 0x0000013A }, //
+ { SSITX, 0x0000013A }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800D3 }, // # Command setting of SPI block
{ SSITX, 0x00080100 }, // # OEV timing control [PCLK Sync. Table1 for VGA]
- { SSITX, 0x0000013A }, //
+ { SSITX, 0x0000013A }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800D4 }, // # Command setting of SPI block
{ SSITX, 0x00080124 }, // # ASW timing control (1) [PCLK Sync. Table1 for VGA]
- { SSITX, 0x0000016E }, //
+ { SSITX, 0x0000016E }, //
{ 0, 1 }, // wait_ms(1); // # Wait SPI fifo empty
{ SSITX, 0x000800D5 }, // # Command setting of SPI block
{ SSITX, 0x00000124 }, // # ASW timing control (2) [PCLK Sync. Table1 for VGA]
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800ED }, // # Command setting of SPI block
{ SSITX, 0x00080101 }, // # Total number of horizontal clock cycles (2) [PCLK Sync. Table1 for QVGA ]
- { SSITX, 0x0000010A }, //
+ { SSITX, 0x0000010A }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800D6 }, // # Command setting of SPI block
{ SSITX, 0x00000101 }, // # Blanking period control (1) [PCLK Sync. Table2 for QVGA]
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800D7 }, // # Command setting of SPI block
{ SSITX, 0x00080110 }, // # Blanking period control (2) [PCLK Sync. Table2 for QVGA]
- { SSITX, 0x0000010A }, //
+ { SSITX, 0x0000010A }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800D8 }, // # Command setting of SPI block
{ SSITX, 0x00000101 }, // # CKV timing control on/off [PCLK Sync. Table2 for QVGA]
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800D9 }, // # Command setting of SPI block
{ SSITX, 0x00080100 }, // # CKV1,2 timing control [PCLK Sync. Table2 for QVGA]
- { SSITX, 0x00000114 }, //
+ { SSITX, 0x00000114 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800DE }, // # Command setting of SPI block
{ SSITX, 0x00080100 }, // # OEV timing control [PCLK Sync. Table2 for QVGA]
- { SSITX, 0x00000114 }, //
+ { SSITX, 0x00000114 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800DF }, // # Command setting of SPI block
{ SSITX, 0x00080112 }, // # ASW timing control (1) [PCLK Sync. Table2 for QVGA]
- { SSITX, 0x0000013F }, //
+ { SSITX, 0x0000013F }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800E0 }, // # Command setting of SPI block
{ SSITX, 0x0000010B }, // # ASW timing control (2) [PCLK Sync. Table2 for QVGA]
@@ -331,23 +517,23 @@
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800E4 }, // # Command setting of SPI block
{ SSITX, 0x00080100 }, // # CKV timing control for using build-in osc
- { SSITX, 0x00000103 }, //
+ { SSITX, 0x00000103 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800E5 }, // # Command setting of SPI block
{ SSITX, 0x00080102 }, // # OEV timing control for using build-in osc
- { SSITX, 0x00000104 }, //
+ { SSITX, 0x00000104 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800E6 }, // # Command setting of SPI block
{ SSITX, 0x00000103 }, // # DCEV timing control for using build-in osc
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800E7 }, // # Command setting of SPI block
{ SSITX, 0x00080104 }, // # ASW timing setup for using build-in osc(1)
- { SSITX, 0x0000010A }, //
+ { SSITX, 0x0000010A }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800E8 }, // # Command setting of SPI block
{ SSITX, 0x00000104 }, // # ASW timing setup for using build-in osc(2)
-
-
+
+
{ CLKENB, 0x000001EF }, // # SYS.CLKENB # DCLK enable
{ START, 0x00000000 }, // # LCD.START # LCDC wait_ms( mode
{ WRSTB, 0x0000003F }, // # LCD.WRSTB # write_client_reg( strobe
@@ -360,11 +546,11 @@
{ ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable
{ 0, 10 }, // wait_ms(10);
{ ASY_DATA, 0x80000000 }, // # LCD.ASY_DATx # DUMMY write_client_reg(@*NOTE2
- { ASY_DATB, 0x80000000 }, //
- { ASY_DATC, 0x80000000 }, //
- { ASY_DATD, 0x80000000 }, //
- { ASY_CMDSET, 0x00000009 }, // # LCD.ASY_CMDSET
- { ASY_CMDSET, 0x00000008 }, // # LCD.ASY_CMDSET
+ { ASY_DATB, 0x80000000 }, //
+ { ASY_DATC, 0x80000000 }, //
+ { ASY_DATD, 0x80000000 }, //
+ { ASY_CMDSET, 0x00000009 }, // # LCD.ASY_CMDSET
+ { ASY_CMDSET, 0x00000008 }, // # LCD.ASY_CMDSET
{ ASY_DATA, 0x80000007 }, // # LCD.ASY_DATx # Index setting of SUB LCDD
{ ASY_DATB, 0x00004005 }, // # LCD driver control
{ ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable
@@ -414,7 +600,7 @@
{ 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty
{ SSITX, 0x000800B8 }, // Command setting of SPI block
{ SSITX, 0x000801FF }, // Output control
- { SSITX, 0x000001F5 },
+ { SSITX, 0x000001F5 },
{ 0, 1 }, // wait_ms( 1); // Wait SPI fifo empty
{ SSITX, 0x00000011 }, // wait_ms(-out (Command only)
{ SSITX, 0x00000029 }, // Display on (Command only)
@@ -447,7 +633,7 @@
switch(client_caps->manufacturer_name) {
case 0xd263: // Toshiba
dprintf(INFO, "Found Toshiba panel\n");
- _panel_init(toshiba_480x640_init_table);
+ _panel_init(toshiba_480x800_init_table);
break;
case 0x4474: //??
if (client_caps->product_code == 0xc065)
diff --git a/platform/qsd8k/platform.c b/platform/qsd8k/platform.c
index 9fb28ef..1ba0d8a 100644
--- a/platform/qsd8k/platform.c
+++ b/platform/qsd8k/platform.c
@@ -34,6 +34,9 @@
#include <dev/fbcon.h>
#include <kernel/thread.h>
#include <platform/debug.h>
+#include <mddi.h>
+
+static struct fbcon_config *fb_config;
void platform_init_interrupts(void);
void platform_init_timer();
@@ -63,7 +66,18 @@
void display_init(void)
{
struct fbcon_config *fb_cfg;
- fb_cfg = lcdc_init();
- fbcon_setup(fb_cfg);
+
+#if DISPLAY_TYPE_MDDI
+ fb_config = mddi_init();
+ ASSERT(fb_config);
+ fbcon_setup(fb_config);
+#endif
+
+#if DISPLAY_TYPE_LCDC
+ fb_config = lcdc_init();
+ ASSERT(fb_config);
+ fbcon_setup(fb_config);
+#endif
+
}
diff --git a/platform/qsd8k/rules.mk b/platform/qsd8k/rules.mk
index 7a1d434..63d61ac 100644
--- a/platform/qsd8k/rules.mk
+++ b/platform/qsd8k/rules.mk
@@ -17,6 +17,7 @@
$(LOCAL_DIR)/platform.o \
$(LOCAL_DIR)/interrupts.o \
$(LOCAL_DIR)/gpio.o \
+ $(LOCAL_DIR)/panel.o \
$(LOCAL_DIR)/acpuclock.o
LINKER_SCRIPT += $(BUILDDIR)/system-onesegment.ld
diff --git a/project/msm7627_ffa.mk b/project/msm7627_ffa.mk
index 5baefed..3943bb2 100644
--- a/project/msm7627_ffa.mk
+++ b/project/msm7627_ffa.mk
@@ -8,4 +8,4 @@
#DEFINES += WITH_DEBUG_DCC=1
#DEFINES += WITH_DEBUG_UART=1
-#DEFINES += WITH_DEBUG_FBCON=1
+DEFINES += WITH_DEBUG_FBCON=1
diff --git a/project/qsd8250_ffa.mk b/project/qsd8250_ffa.mk
index 358128d..fbc932c 100644
--- a/project/qsd8250_ffa.mk
+++ b/project/qsd8250_ffa.mk
@@ -8,4 +8,4 @@
#DEFINES += WITH_DEBUG_DCC=1
#DEFINES += WITH_DEBUG_UART=1
-#DEFINES += WITH_DEBUG_FBCON=1
+DEFINES += WITH_DEBUG_FBCON=1
diff --git a/target/msm7625_ffa/include/target/display.h b/target/msm7625_ffa/include/target/display.h
new file mode 100644
index 0000000..0b86812
--- /dev/null
+++ b/target/msm7625_ffa/include/target/display.h
@@ -0,0 +1,35 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef _TARGET_MSM7625_FFA_DISPLAY_H
+#define _TARGET_MSM7625_FFA_DISPLAY_H
+
+#define TARGET_XRES 480
+#define TARGET_YRES 800
+
+#endif
diff --git a/target/msm7625_surf/include/target/display.h b/target/msm7625_surf/include/target/display.h
new file mode 100644
index 0000000..45a558a
--- /dev/null
+++ b/target/msm7625_surf/include/target/display.h
@@ -0,0 +1,35 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef _TARGET_MSM7625_SURF_DISPLAY_H
+#define _TARGET_MSM7625_SURF_DISPLAY_H
+
+#define TARGET_XRES 800
+#define TARGET_YRES 480
+
+#endif
diff --git a/target/msm7627_ffa/include/target/display.h b/target/msm7627_ffa/include/target/display.h
new file mode 100644
index 0000000..d6e4a77
--- /dev/null
+++ b/target/msm7627_ffa/include/target/display.h
@@ -0,0 +1,35 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef _TARGET_MSM7627_FFA_DISPLAY_H
+#define _TARGET_MSM7627_FFA_DISPLAY_H
+
+#define TARGET_XRES 480
+#define TARGET_YRES 800
+
+#endif
diff --git a/target/msm7627_ffa/init.c b/target/msm7627_ffa/init.c
index 6c9ea7d..db58e21 100644
--- a/target/msm7627_ffa/init.c
+++ b/target/msm7627_ffa/init.c
@@ -65,12 +65,17 @@
.name = "system",
},
{
- .start = 800,
+ .start = 800,
+ .length = 8,
+ .name = "splash",
+ },
+ {
+ .start = 808,
.length = 40 /* 5MB */,
.name = "cache",
},
{
- .start = 840,
+ .start = 848,
.length = VARIABLE_LENGTH,
.name = "userdata",
},
diff --git a/target/msm7627_ffa/rules.mk b/target/msm7627_ffa/rules.mk
index 19c049a..92299f9 100755
--- a/target/msm7627_ffa/rules.mk
+++ b/target/msm7627_ffa/rules.mk
@@ -17,6 +17,9 @@
KEYS_USE_GPIO_KEYPAD := 1
DEFINES += DISPLAY_TYPE_MDDI=0
+DEFINES += DISPLAY_TYPE_LCDC=1
+
+DEFINES += DISPLAY_SPLASH_SCREEN=1
MODULES += \
dev/keys \
@@ -35,5 +38,4 @@
OBJS += \
$(LOCAL_DIR)/init.o \
$(LOCAL_DIR)/keypad.o \
- $(LOCAL_DIR)/atags.o \
- $(LOCAL_DIR)/panel.o
+ $(LOCAL_DIR)/atags.o
diff --git a/target/msm7627_surf/include/target/display.h b/target/msm7627_surf/include/target/display.h
new file mode 100644
index 0000000..36ccb77
--- /dev/null
+++ b/target/msm7627_surf/include/target/display.h
@@ -0,0 +1,35 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef _TARGET_MSM7627_SURF_DISPLAY_H
+#define _TARGET_MSM7627_SURF_DISPLAY_H
+
+#define TARGET_XRES 800
+#define TARGET_YRES 480
+
+#endif
diff --git a/target/msm7627_surf/panel.c b/target/msm7627_surf/panel.c
deleted file mode 100644
index c2b56a1..0000000
--- a/target/msm7627_surf/panel.c
+++ /dev/null
@@ -1,471 +0,0 @@
-/* Copyright 2007, Google Inc. */
-
-#include <debug.h>
-#include <dev/gpio.h>
-#include <kernel/thread.h>
-#include <platform/mddi.h>
-
-#define MDDI_CLIENT_CORE_BASE 0x108000
-#define LCD_CONTROL_BLOCK_BASE 0x110000
-#define SPI_BLOCK_BASE 0x120000
-#define I2C_BLOCK_BASE 0x130000
-#define PWM_BLOCK_BASE 0x140000
-#define GPIO_BLOCK_BASE 0x150000
-#define SYSTEM_BLOCK1_BASE 0x160000
-#define SYSTEM_BLOCK2_BASE 0x170000
-
-
-#define MDDICAP0 (MDDI_CLIENT_CORE_BASE|0x00)
-#define MDDICAP1 (MDDI_CLIENT_CORE_BASE|0x04)
-#define MDDICAP2 (MDDI_CLIENT_CORE_BASE|0x08)
-#define MDDICAP3 (MDDI_CLIENT_CORE_BASE|0x0C)
-#define MDCAPCHG (MDDI_CLIENT_CORE_BASE|0x10)
-#define MDCRCERC (MDDI_CLIENT_CORE_BASE|0x14)
-#define TTBUSSEL (MDDI_CLIENT_CORE_BASE|0x18)
-#define DPSET0 (MDDI_CLIENT_CORE_BASE|0x1C)
-#define DPSET1 (MDDI_CLIENT_CORE_BASE|0x20)
-#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24)
-#define DPRUN (MDDI_CLIENT_CORE_BASE|0x28)
-#define SYSCKENA (MDDI_CLIENT_CORE_BASE|0x2C)
-#define TESTMODE (MDDI_CLIENT_CORE_BASE|0x30)
-#define FIFOMONI (MDDI_CLIENT_CORE_BASE|0x34)
-#define INTMONI (MDDI_CLIENT_CORE_BASE|0x38)
-#define MDIOBIST (MDDI_CLIENT_CORE_BASE|0x3C)
-#define MDIOPSET (MDDI_CLIENT_CORE_BASE|0x40)
-#define BITMAP0 (MDDI_CLIENT_CORE_BASE|0x44)
-#define BITMAP1 (MDDI_CLIENT_CORE_BASE|0x48)
-#define BITMAP2 (MDDI_CLIENT_CORE_BASE|0x4C)
-#define BITMAP3 (MDDI_CLIENT_CORE_BASE|0x50)
-#define BITMAP4 (MDDI_CLIENT_CORE_BASE|0x54)
-
-
-#define SRST (LCD_CONTROL_BLOCK_BASE|0x00)
-#define PORT_ENB (LCD_CONTROL_BLOCK_BASE|0x04)
-#define START (LCD_CONTROL_BLOCK_BASE|0x08)
-#define PORT (LCD_CONTROL_BLOCK_BASE|0x0C)
-#define CMN (LCD_CONTROL_BLOCK_BASE|0x10)
-#define GAMMA (LCD_CONTROL_BLOCK_BASE|0x14)
-#define INTFLG (LCD_CONTROL_BLOCK_BASE|0x18)
-#define INTMSK (LCD_CONTROL_BLOCK_BASE|0x1C)
-#define MPLFBUF (LCD_CONTROL_BLOCK_BASE|0x20)
-#define HDE_LEFT (LCD_CONTROL_BLOCK_BASE|0x24)
-#define VDE_TOP (LCD_CONTROL_BLOCK_BASE|0x28)
-
-#define PXL (LCD_CONTROL_BLOCK_BASE|0x30)
-#define HCYCLE (LCD_CONTROL_BLOCK_BASE|0x34)
-#define HSW (LCD_CONTROL_BLOCK_BASE|0x38)
-#define HDE_START (LCD_CONTROL_BLOCK_BASE|0x3C)
-#define HDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x40)
-#define VCYCLE (LCD_CONTROL_BLOCK_BASE|0x44)
-#define VSW (LCD_CONTROL_BLOCK_BASE|0x48)
-#define VDE_START (LCD_CONTROL_BLOCK_BASE|0x4C)
-#define VDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x50)
-#define WAKEUP (LCD_CONTROL_BLOCK_BASE|0x54)
-#define WSYN_DLY (LCD_CONTROL_BLOCK_BASE|0x58)
-#define REGENB (LCD_CONTROL_BLOCK_BASE|0x5C)
-#define VSYNIF (LCD_CONTROL_BLOCK_BASE|0x60)
-#define WRSTB (LCD_CONTROL_BLOCK_BASE|0x64)
-#define RDSTB (LCD_CONTROL_BLOCK_BASE|0x68)
-#define ASY_DATA (LCD_CONTROL_BLOCK_BASE|0x6C)
-#define ASY_DATB (LCD_CONTROL_BLOCK_BASE|0x70)
-#define ASY_DATC (LCD_CONTROL_BLOCK_BASE|0x74)
-#define ASY_DATD (LCD_CONTROL_BLOCK_BASE|0x78)
-#define ASY_DATE (LCD_CONTROL_BLOCK_BASE|0x7C)
-#define ASY_DATF (LCD_CONTROL_BLOCK_BASE|0x80)
-#define ASY_DATG (LCD_CONTROL_BLOCK_BASE|0x84)
-#define ASY_DATH (LCD_CONTROL_BLOCK_BASE|0x88)
-#define ASY_CMDSET (LCD_CONTROL_BLOCK_BASE|0x8C)
-
-#define MONI (LCD_CONTROL_BLOCK_BASE|0xB0)
-
-#define Current (LCD_CONTROL_BLOCK_BASE|0xC0)
-#define LCD (LCD_CONTROL_BLOCK_BASE|0xC4)
-#define COMMAND (LCD_CONTROL_BLOCK_BASE|0xC8)
-
-
-#define SSICTL (SPI_BLOCK_BASE|0x00)
-#define SSITIME (SPI_BLOCK_BASE|0x04)
-#define SSITX (SPI_BLOCK_BASE|0x08)
-#define SSIRX (SPI_BLOCK_BASE|0x0C)
-#define SSIINTC (SPI_BLOCK_BASE|0x10)
-#define SSIINTS (SPI_BLOCK_BASE|0x14)
-#define SSIDBG1 (SPI_BLOCK_BASE|0x18)
-#define SSIDBG2 (SPI_BLOCK_BASE|0x1C)
-#define SSIID (SPI_BLOCK_BASE|0x20)
-
-
-#define I2CSETUP (I2C_BLOCK_BASE|0x00)
-#define I2CCTRL (I2C_BLOCK_BASE|0x04)
-
-
-#define TIMER0LOAD (PWM_BLOCK_BASE|0x00)
-#define TIMER0VALUE (PWM_BLOCK_BASE|0x04)
-#define TIMER0CONTROL (PWM_BLOCK_BASE|0x08)
-#define TIMER0INTCLR (PWM_BLOCK_BASE|0x0C)
-#define TIMER0RIS (PWM_BLOCK_BASE|0x10)
-#define TIMER0MIS (PWM_BLOCK_BASE|0x14)
-#define TIMER0BGLOAD (PWM_BLOCK_BASE|0x18)
-#define PWM0OFF (PWM_BLOCK_BASE|0x1C)
-#define TIMER1LOAD (PWM_BLOCK_BASE|0x20)
-#define TIMER1VALUE (PWM_BLOCK_BASE|0x24)
-#define TIMER1CONTROL (PWM_BLOCK_BASE|0x28)
-#define TIMER1INTCLR (PWM_BLOCK_BASE|0x2C)
-#define TIMER1RIS (PWM_BLOCK_BASE|0x30)
-#define TIMER1MIS (PWM_BLOCK_BASE|0x34)
-#define TIMER1BGLOAD (PWM_BLOCK_BASE|0x38)
-#define PWM1OFF (PWM_BLOCK_BASE|0x3C)
-#define TIMERITCR (PWM_BLOCK_BASE|0x60)
-#define TIMERITOP (PWM_BLOCK_BASE|0x64)
-#define PWMCR (PWM_BLOCK_BASE|0x68)
-#define PWMID (PWM_BLOCK_BASE|0x6C)
-#define PWMMON (PWM_BLOCK_BASE|0x70)
-
-
-#define GPIODATA (GPIO_BLOCK_BASE|0x00)
-#define GPIODIR (GPIO_BLOCK_BASE|0x04)
-#define GPIOIS (GPIO_BLOCK_BASE|0x08)
-#define GPIOIBE (GPIO_BLOCK_BASE|0x0C)
-#define GPIOIEV (GPIO_BLOCK_BASE|0x10)
-#define GPIOIE (GPIO_BLOCK_BASE|0x14)
-#define GPIORIS (GPIO_BLOCK_BASE|0x18)
-#define GPIOMIS (GPIO_BLOCK_BASE|0x1C)
-#define GPIOIC (GPIO_BLOCK_BASE|0x20)
-#define GPIOOMS (GPIO_BLOCK_BASE|0x24)
-#define GPIOPC (GPIO_BLOCK_BASE|0x28)
-
-#define GPIOID (GPIO_BLOCK_BASE|0x30)
-
-
-#define WKREQ (SYSTEM_BLOCK1_BASE|0x00)
-#define CLKENB (SYSTEM_BLOCK1_BASE|0x04)
-#define DRAMPWR (SYSTEM_BLOCK1_BASE|0x08)
-#define INTMASK (SYSTEM_BLOCK1_BASE|0x0C)
-#define GPIOSEL (SYSTEM_BLOCK2_BASE|0x00)
-
-struct init_table {
- unsigned int reg;
- unsigned int val;
-};
-
-static struct init_table toshiba_480x640_init_table[] = {
- { DPSET0, 0x4BEC0066 }, // # MDC.DPSET0 # Setup DPLL parameters
- { DPSET1, 0x00000113 }, // # MDC.DPSET1
- { DPSUS, 0x00000000 }, // # MDC.DPSUS # Set DPLL oscillation enable
- { DPRUN, 0x00000001 }, // # MDC.DPRUN # Release reset signal for DPLL
- { 0, 14 }, // wait_ms(14);
- { SYSCKENA, 0x00000001 }, // # MDC.SYSCKENA # Enable system clock output
- { CLKENB, 0x000000EF }, // # SYS.CLKENB # Enable clocks for each module (without DCLK , i2cCLK)
- { GPIO_BLOCK_BASE, 0x03FF0000 }, // # GPI .GPIODATA # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0
- { GPIODIR, 0x0000024D }, // # GPI .GPIODIR # Select direction of GPIO port (0,2,3,6,9 output)
- { SYSTEM_BLOCK2_BASE, 0x00000173 }, // # SYS.GPIOSEL # GPIO port multiplexing control
- { GPIOPC, 0x03C300C0 }, // # GPI .GPIOPC # GPIO2,3 PD cut
- { SYSTEM_BLOCK1_BASE, 0x00000000 }, // # SYS.WKREQ # Wake-up request event is VSYNC alignment
- { GPIOIS, 0x00000000 }, // # GPI .GPIOIS # Set interrupt sense of GPIO
- { GPIOIEV, 0x00000001 }, // # GPI .GPIOIEV # Set interrupt event of GPIO
- { GPIOIC, 0x000003FF }, // # GPI .GPIOIC # GPIO interrupt clear
- { GPIO_BLOCK_BASE, 0x00060006 }, // # GPI .GPIODATA # Release LCDD reset
- { GPIO_BLOCK_BASE, 0x00080008 }, // # GPI .GPIODATA # eDRAM VD supply
- { GPIO_BLOCK_BASE, 0x02000200 }, // # GPI .GPIODATA # TEST LED ON
- { DRAMPWR, 0x00000001 }, // # SYS.DRAMPWR # eDRAM power up
- { TIMER0CONTROL, 0x00000060 }, // # PWM.Timer0Control # PWM0 output stop
- { PWM_BLOCK_BASE, 0x00001388 }, // # PWM.Timer0Load # PWM0 10kHz , Duty 99 (BackLight OFF)
- //{PWM0OFF, 0x00000001 }, // # PWM.PWM0OFF
-#if 0
- { PWM0OFF, 0x00001387 }, // SURF 100% backlight
- { PWM0OFF, 0x00000000 }, // FFA 100% backlight
-#endif
- { PWM0OFF, 0x000009C3 }, // 50% BL
- { TIMER1CONTROL, 0x00000060 }, // # PWM.Timer1Control # PWM1 output stop
- { TIMER1LOAD, 0x00001388 }, // # PWM.Timer1Load # PWM1 10kHz , Duty 99 (BackLight OFF)
- //{PWM1OFF, 0x00000001 }, // # PWM.PWM1OFF
- { PWM1OFF, 0x00001387 },
- { TIMER0CONTROL, 0x000000E0 }, // # PWM.Timer0Control # PWM0 output start
- { TIMER1CONTROL, 0x000000E0 }, // # PWM.Timer1Control # PWM1 output start
- { PWMCR, 0x00000003 }, // # PWM.PWMCR # PWM output enable
- { 0, 1 }, // wait_ms(1);
- { SPI_BLOCK_BASE, 0x00000799 }, // # SPI .SSICTL # SPI operation mode setting
- { SSITIME, 0x00000100 }, // # SPI .SSITIME # SPI serial interface timing setting
- { SPI_BLOCK_BASE, 0x0000079b }, // # SPI .SSICTL # Set SPI active mode
-
- { SSITX, 0x00000000 }, // # SPI.SSITX # Release from Deep Stanby mode
- { 0, 1 }, // wait_ms(1);
- { SSITX, 0x00000000 }, // # SPI.SSITX
- { 0, 1 }, // wait_ms(1);
- { SSITX, 0x00000000 }, // # SPI.SSITX
- { 0, 1 }, // wait_ms(1);
- { SSITX, 0x000800BA }, // # SPI.SSITX *NOTE 1 # Command setting of SPI block
- { SSITX, 0x00000111 }, // # Display mode setup(1) : Normaly Black
- { SSITX, 0x00080036 }, // # Command setting of SPI block
- { SSITX, 0x00000100 }, // # Memory access control
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800BB }, // # Command setting of SPI block
- { SSITX, 0x00000100 }, // # Display mode setup(2)
- { SSITX, 0x0008003A }, // # Command setting of SPI block
- { SSITX, 0x00000160 }, // # RGB Interface data format
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800BF }, // # Command setting of SPI block
- { SSITX, 0x00000100 }, // # Drivnig method
- { SSITX, 0x000800B1 }, // # Command setting of SPI block
- { SSITX, 0x0000015D }, // # Booster operation setup
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800B2 }, // # Command setting of SPI block
- { SSITX, 0x00000133 }, // # Booster mode setup
- { SSITX, 0x000800B3 }, // # Command setting of SPI block
- { SSITX, 0x00000122 }, // # Booster frequencies setup
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800B4 }, // # Command setting of SPI block
- { SSITX, 0x00000102 }, // # OP-amp capability/System clock freq. division setup
- { SSITX, 0x000800B5 }, // # Command setting of SPI block
- { SSITX, 0x0000011F }, // # VCS Voltage adjustment (1C->1F for Rev 2)
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800B6 }, // # Command setting of SPI block
- { SSITX, 0x00000128 }, // # VCOM Voltage adjustment
- { SSITX, 0x000800B7 }, // # Command setting of SPI block
- { SSITX, 0x00000103 }, // # Configure an external display signal
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800B9 }, // # Command setting of SPI block
- { SSITX, 0x00000120 }, // # DCCK/DCEV timing setup
- { SSITX, 0x000800BD }, // # Command setting of SPI block
- { SSITX, 0x00000102 }, // # ASW signal control
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800BE }, // # Command setting of SPI block
- { SSITX, 0x00000100 }, // # Dummy display (white/black) count setup for QUAD Data operation
- { SSITX, 0x000800C0 }, // # Command setting of SPI block
- { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (A)
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C1 }, // # Command setting of SPI block
- { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (B)
- { SSITX, 0x000800C2 }, // # Command setting of SPI block
- { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (C)
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C3 }, // # Command setting of SPI block
- { SSITX, 0x0008010A }, // # wait_ms(-in line clock count setup (D)
- { SSITX, 0x0000010A }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C4 }, // # Command setting of SPI block
- { SSITX, 0x00080160 }, // # Seep-in line clock count setup (E)
- { SSITX, 0x00000160 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C5 }, // # Command setting of SPI block
- { SSITX, 0x00080160 }, // # wait_ms(-in line clock count setup (F)
- { SSITX, 0x00000160 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C6 }, // # Command setting of SPI block
- { SSITX, 0x00080160 }, // # wait_ms(-in line clock setup (G)
- { SSITX, 0x00000160 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C7 }, // # Command setting of SPI block
- { SSITX, 0x00080133 }, // # Gamma 1 fine tuning (1)
- { SSITX, 0x00000143 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800C8 }, // # Command setting of SPI block
- { SSITX, 0x00000144 }, // # Gamma 1 fine tuning (2)
- { SSITX, 0x000800C9 }, // # Command setting of SPI block
- { SSITX, 0x00000133 }, // # Gamma 1 inclination adjustment
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800CA }, // # Command setting of SPI block
- { SSITX, 0x00000100 }, // # Gamma 1 blue offset adjustment
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800EC }, // # Command setting of SPI block
- { SSITX, 0x00080102 }, // # Total number of horizontal clock cycles (1) [PCLK Sync. VGA setting]
- { SSITX, 0x00000118 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800CF }, // # Command setting of SPI block
- { SSITX, 0x00000101 }, // # Blanking period control (1) [PCLK Sync. Table1 for VGA]
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D0 }, // # Command setting of SPI block
- { SSITX, 0x00080110 }, // # Blanking period control (2) [PCLK Sync. Table1 for VGA]
- { SSITX, 0x00000104 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D1 }, // # Command setting of SPI block
- { SSITX, 0x00000101 }, // # CKV timing control on/off [PCLK Sync. Table1 for VGA]
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D2 }, // # Command setting of SPI block
- { SSITX, 0x00080100 }, // # CKV1,2 timing control [PCLK Sync. Table1 for VGA]
- { SSITX, 0x0000013A }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D3 }, // # Command setting of SPI block
- { SSITX, 0x00080100 }, // # OEV timing control [PCLK Sync. Table1 for VGA]
- { SSITX, 0x0000013A }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D4 }, // # Command setting of SPI block
- { SSITX, 0x00080124 }, // # ASW timing control (1) [PCLK Sync. Table1 for VGA]
- { SSITX, 0x0000016E }, //
- { 0, 1 }, // wait_ms(1); // # Wait SPI fifo empty
- { SSITX, 0x000800D5 }, // # Command setting of SPI block
- { SSITX, 0x00000124 }, // # ASW timing control (2) [PCLK Sync. Table1 for VGA]
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800ED }, // # Command setting of SPI block
- { SSITX, 0x00080101 }, // # Total number of horizontal clock cycles (2) [PCLK Sync. Table1 for QVGA ]
- { SSITX, 0x0000010A }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D6 }, // # Command setting of SPI block
- { SSITX, 0x00000101 }, // # Blanking period control (1) [PCLK Sync. Table2 for QVGA]
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D7 }, // # Command setting of SPI block
- { SSITX, 0x00080110 }, // # Blanking period control (2) [PCLK Sync. Table2 for QVGA]
- { SSITX, 0x0000010A }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D8 }, // # Command setting of SPI block
- { SSITX, 0x00000101 }, // # CKV timing control on/off [PCLK Sync. Table2 for QVGA]
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800D9 }, // # Command setting of SPI block
- { SSITX, 0x00080100 }, // # CKV1,2 timing control [PCLK Sync. Table2 for QVGA]
- { SSITX, 0x00000114 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800DE }, // # Command setting of SPI block
- { SSITX, 0x00080100 }, // # OEV timing control [PCLK Sync. Table2 for QVGA]
- { SSITX, 0x00000114 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800DF }, // # Command setting of SPI block
- { SSITX, 0x00080112 }, // # ASW timing control (1) [PCLK Sync. Table2 for QVGA]
- { SSITX, 0x0000013F }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800E0 }, // # Command setting of SPI block
- { SSITX, 0x0000010B }, // # ASW timing control (2) [PCLK Sync. Table2 for QVGA]
- { SSITX, 0x000800E2 }, // # Command setting of SPI block
- { SSITX, 0x00000101 }, // # Built-in oscillator frequency division setup [Frequency division ratio : 2 (60Hq)
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800E3 }, // # Command setting of SPI block
- { SSITX, 0x00000136 }, // # Built-in oscillator clock count setup
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800E4 }, // # Command setting of SPI block
- { SSITX, 0x00080100 }, // # CKV timing control for using build-in osc
- { SSITX, 0x00000103 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800E5 }, // # Command setting of SPI block
- { SSITX, 0x00080102 }, // # OEV timing control for using build-in osc
- { SSITX, 0x00000104 }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800E6 }, // # Command setting of SPI block
- { SSITX, 0x00000103 }, // # DCEV timing control for using build-in osc
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800E7 }, // # Command setting of SPI block
- { SSITX, 0x00080104 }, // # ASW timing setup for using build-in osc(1)
- { SSITX, 0x0000010A }, //
- { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
- { SSITX, 0x000800E8 }, // # Command setting of SPI block
- { SSITX, 0x00000104 }, // # ASW timing setup for using build-in osc(2)
-
-
- { CLKENB, 0x000001EF }, // # SYS.CLKENB # DCLK enable
- { START, 0x00000000 }, // # LCD.START # LCDC wait_ms( mode
- { WRSTB, 0x0000003F }, // # LCD.WRSTB # write_client_reg( strobe
- { RDSTB, 0x00000432 }, // # LCD.RDSTB # Read strobe
- { PORT_ENB, 0x00000002 }, // # LCD.PORT_ENB # Asynchronous port enable
- { VSYNIF, 0x00000000 }, // # LCD.VSYNCIF # VSYNC I/F mode set
- { ASY_DATA, 0x80000000 }, // # LCD.ASY_DATx # Index setting of SUB LCDD
- { ASY_DATB, 0x00000001 }, // # Oscillator start
- { ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable
- { ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable
- { 0, 10 }, // wait_ms(10);
- { ASY_DATA, 0x80000000 }, // # LCD.ASY_DATx # DUMMY write_client_reg(@*NOTE2
- { ASY_DATB, 0x80000000 }, //
- { ASY_DATC, 0x80000000 }, //
- { ASY_DATD, 0x80000000 }, //
- { ASY_CMDSET, 0x00000009 }, // # LCD.ASY_CMDSET
- { ASY_CMDSET, 0x00000008 }, // # LCD.ASY_CMDSET
- { ASY_DATA, 0x80000007 }, // # LCD.ASY_DATx # Index setting of SUB LCDD
- { ASY_DATB, 0x00004005 }, // # LCD driver control
- { ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable
- { ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable
- { 0, 20 }, // wait_ms(20);
- { ASY_DATA, 0x80000059 }, // # LCD.ASY_DATx # Index setting of SUB LCDD
- { ASY_DATB, 0x00000000 }, // # LTPS I/F control
- { ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable
- { ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable
-
- { VSYNIF, 0x00000001 }, // # LCD.VSYNCIF # VSYNC I/F mode OFF
- { PORT_ENB, 0x00000001 }, // # LCD.PORT_ENB # SYNC I/F output select
-
- /******************************/
-
- { VSYNIF, 0x00000001 }, // VSYNC I/F mode OFF
- { PORT_ENB, 0x00000001 }, // SYNC I/F mode ON
-
- { BITMAP1, 0x01E000F0 }, // MDC.BITMAP2 ); // Setup of PITCH size to Frame buffer1
- { BITMAP2, 0x01E000F0 }, // MDC.BITMAP3 ); // Setup of PITCH size to Frame buffer2
- { BITMAP3, 0x01E000F0 }, // MDC.BITMAP4 ); // Setup of PITCH size to Frame buffer3
- { BITMAP4, 0x00DC00B0 }, // MDC.BITMAP5 ); // Setup of PITCH size to Frame buffer4
- { CLKENB, 0x000001EF }, // SYS.CLKENB ); // DCLK supply
- { PORT_ENB, 0x00000001 }, // LCD.PORT_ENB ); // Synchronous port enable
- { PORT, 0x00000004 }, // LCD.PORT ); // Polarity of DE is set to high active
- { PXL, 0x00000002 }, // LCD.PXL ); // ACTMODE 2 set (1st frame black data output)
- { MPLFBUF, 0x00000000 }, // LCD.MPLFBUF ); // Select the reading buffer
- { HCYCLE, 0x0000010b }, // LCD.HCYCLE ); // Setup to VGA size
- { HSW, 0x00000003 }, // LCD.HSW
- { HDE_START, 0x00000007 }, // LCD.HDE_START
- { HDE_SIZE, 0x000000EF }, // LCD.HDE_SIZE
- { VCYCLE, 0x00000285 }, // LCD.VCYCLE
- { VSW, 0x00000001 }, // LCD.VSW
- { VDE_START, 0x00000003 }, // LCD.VDE_START
- { VDE_SIZE, 0x0000027F }, // LCD.VDE_SIZE
-
- { START, 0x00000001 }, // LCD.START ); // LCDC - Pixel data transfer start
-
- { 0, 10 }, // wait_ms( 10 );
- { SSITX, 0x000800BC }, // SPI.SSITX ); // Command setting of SPI block
- { SSITX, 0x00000180 }, // Display data setup
- { SSITX, 0x0008003B }, // Command setting of SPI block
- { SSITX, 0x00000100 }, // Quad Data configuration - VGA
- { 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty
- { SSITX, 0x000800B0 }, // Command setting of SPI block
- { SSITX, 0x00000116 }, // Power supply ON/OFF control
- { 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty
- { SSITX, 0x000800B8 }, // Command setting of SPI block
- { SSITX, 0x000801FF }, // Output control
- { SSITX, 0x000001F5 },
- { 0, 1 }, // wait_ms( 1); // Wait SPI fifo empty
- { SSITX, 0x00000011 }, // wait_ms(-out (Command only)
- { SSITX, 0x00000029 }, // Display on (Command only)
-
- { SYSTEM_BLOCK1_BASE, 0x00000002 }, // # wakeREQ -> GPIO
-
- { 0, 0 }
-};
-
-static void _panel_init(struct init_table *init_table)
-{
- unsigned n;
-
- dprintf(INFO, "panel_init()\n");
-
- n = 0;
- while (init_table[n].reg != 0 || init_table[n].val != 0) {
- if (init_table[n].reg != 0)
- mddi_remote_write(init_table[n].val, init_table[n].reg);
- else
- thread_sleep(init_table[n].val);//mdelay(init_table[n].val);
- n++;
- }
-
- dprintf(INFO, "panel_init() done\n");
-}
-
-void panel_init(struct mddi_client_caps *client_caps)
-{
- switch(client_caps->manufacturer_name) {
- case 0xd263: // Toshiba
- dprintf(INFO, "Found Toshiba panel\n");
- _panel_init(toshiba_480x640_init_table);
- break;
- case 0x4474: //??
- if (client_caps->product_code == 0xc065)
- dprintf(INFO, "Found WVGA panel\n");
- break;
- }
-}
-
-void panel_poweron(void)
-{
- gpio_set(88, 0);
- gpio_config(88, GPIO_OUTPUT);
- thread_sleep(1); //udelay(10);
- gpio_set(88, 1);
- thread_sleep(10); //mdelay(10);
-
- //mdelay(1000); // uncomment for second stage boot
-}
-
-void panel_backlight(int on)
-{}
diff --git a/target/msm7627_surf/rules.mk b/target/msm7627_surf/rules.mk
index b7c087a..701feaa 100644
--- a/target/msm7627_surf/rules.mk
+++ b/target/msm7627_surf/rules.mk
@@ -18,7 +18,7 @@
DEFINES += DISPLAY_TYPE_MDDI=0
DEFINES += DISPLAY_TYPE_LCDC=1
-DEFINES += DISPLAY_SPLASH_SCREEN=0
+DEFINES += DISPLAY_SPLASH_SCREEN=1
MODULES += \
dev/keys \
@@ -37,5 +37,4 @@
OBJS += \
$(LOCAL_DIR)/init.o \
$(LOCAL_DIR)/keypad.o \
- $(LOCAL_DIR)/atags.o \
- $(LOCAL_DIR)/panel.o
+ $(LOCAL_DIR)/atags.o
diff --git a/target/msm7630_surf/include/target/display.h b/target/msm7630_surf/include/target/display.h
new file mode 100644
index 0000000..7a3510b
--- /dev/null
+++ b/target/msm7630_surf/include/target/display.h
@@ -0,0 +1,35 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef _TARGET_MSM7630_SURF_DISPLAY_H
+#define _TARGET_MSM7630_SURF_DISPLAY_H
+
+#define TARGET_XRES 800
+#define TARGET_YRES 480
+
+#endif
diff --git a/target/msm8650a_st1x/include/target/display.h b/target/msm8650a_st1x/include/target/display.h
new file mode 100644
index 0000000..491c9b6
--- /dev/null
+++ b/target/msm8650a_st1x/include/target/display.h
@@ -0,0 +1,35 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef _TARGET_QSD8650A_ST1X_DISPLAY_H
+#define _TARGET_QSD8650A_ST1X_DISPLAY_H
+
+#define TARGET_XRES 800
+#define TARGET_YRES 480
+
+#endif
diff --git a/target/msm8660_surf/include/target/display.h b/target/msm8660_surf/include/target/display.h
new file mode 100644
index 0000000..6e5f470
--- /dev/null
+++ b/target/msm8660_surf/include/target/display.h
@@ -0,0 +1,35 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef _TARGET_QSD8660_SURF_DISPLAY_H
+#define _TARGET_QSD8660_SURF_DISPLAY_H
+
+#define TARGET_XRES 800
+#define TARGET_YRES 480
+
+#endif
diff --git a/target/qsd8250_ffa/include/target/display.h b/target/qsd8250_ffa/include/target/display.h
new file mode 100644
index 0000000..01b6fa8
--- /dev/null
+++ b/target/qsd8250_ffa/include/target/display.h
@@ -0,0 +1,35 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef _TARGET_QSD8250_FFA_DISPLAY_H
+#define _TARGET_QSD8250_FFA_DISPLAY_H
+
+#define TARGET_XRES 480
+#define TARGET_YRES 800
+
+#endif
diff --git a/target/qsd8250_ffa/init.c b/target/qsd8250_ffa/init.c
index b44014d..6887d6d 100644
--- a/target/qsd8250_ffa/init.c
+++ b/target/qsd8250_ffa/init.c
@@ -76,6 +76,11 @@
},
{
.start = DIFF_START_ADDR,
+ .length = 8 /* 1MB */,
+ .name = "splash",
+ },
+ {
+ .start = DIFF_START_ADDR,
.length = 40 /* 5MB */,
.name = "recovery",
},
diff --git a/target/qsd8250_ffa/rules.mk b/target/qsd8250_ffa/rules.mk
index 9f38935..1a639fc 100644
--- a/target/qsd8250_ffa/rules.mk
+++ b/target/qsd8250_ffa/rules.mk
@@ -17,6 +17,8 @@
KEYS_USE_GPIO_KEYPAD := 1
DEFINES += ENABLE_BATTERY_CHARGING=1
+DEFINES += DISPLAY_SPLASH_SCREEN=1
+DEFINES += DISPLAY_TYPE_MDDI=1
MODULES += \
dev/keys \
diff --git a/target/qsd8250_surf/include/target/display.h b/target/qsd8250_surf/include/target/display.h
new file mode 100644
index 0000000..aa7274b
--- /dev/null
+++ b/target/qsd8250_surf/include/target/display.h
@@ -0,0 +1,35 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef _TARGET_QSD8250_SURF_DISPLAY_H
+#define _TARGET_QSD8250_SURF_DISPLAY_H
+
+#define TARGET_XRES 800
+#define TARGET_YRES 480
+
+#endif
diff --git a/target/qsd8250_surf/init.c b/target/qsd8250_surf/init.c
index 0b3b0cd..dcddadb 100644
--- a/target/qsd8250_surf/init.c
+++ b/target/qsd8250_surf/init.c
@@ -76,6 +76,11 @@
},
{
.start = DIFF_START_ADDR,
+ .length = 8 /* 1MB */,
+ .name = "splash",
+ },
+ {
+ .start = DIFF_START_ADDR,
.length = 40 /* 5MB */,
.name = "recovery",
},
diff --git a/target/qsd8250_surf/rules.mk b/target/qsd8250_surf/rules.mk
index 9f38935..49ff8dd 100644
--- a/target/qsd8250_surf/rules.mk
+++ b/target/qsd8250_surf/rules.mk
@@ -17,6 +17,9 @@
KEYS_USE_GPIO_KEYPAD := 1
DEFINES += ENABLE_BATTERY_CHARGING=1
+DEFINES += DISPLAY_SPLASH_SCREEN=1
+DEFINES += DISPLAY_TYPE_LCDC=1
+
MODULES += \
dev/keys \
diff --git a/target/qsd8650a_st1x/include/target/display.h b/target/qsd8650a_st1x/include/target/display.h
new file mode 100644
index 0000000..491c9b6
--- /dev/null
+++ b/target/qsd8650a_st1x/include/target/display.h
@@ -0,0 +1,35 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef _TARGET_QSD8650A_ST1X_DISPLAY_H
+#define _TARGET_QSD8650A_ST1X_DISPLAY_H
+
+#define TARGET_XRES 800
+#define TARGET_YRES 480
+
+#endif