target: msm8952: add display support for SDM439 target
Add changes to enable display support for SDM439 device. This
includes enabling the required LDOs, GPIOs and adjusting the
register offsets for MDSS.
Change-Id: I3a26b0b4d30f9d5fcd5b1a5926d9de98b704300b
diff --git a/dev/pmic/pm8x41/include/pm8x41.h b/dev/pmic/pm8x41/include/pm8x41.h
index 65011ec..014834a 100644
--- a/dev/pmic/pm8x41/include/pm8x41.h
+++ b/dev/pmic/pm8x41/include/pm8x41.h
@@ -41,7 +41,7 @@
/* 1.5uA + 30uA boost */
#define PM_GPIO_PULL_UP_1_5_30 3
#define PM_GPIO_PULLDOWN_10 4
-#define PM_GPIO_PULL_RESV_2 5
+#define PM_GPIO_NO_PULL 5
#define PM_GPIO_OUT_CMOS 0x00
diff --git a/target/msm8952/oem_panel.c b/target/msm8952/oem_panel.c
old mode 100644
new mode 100755
index 19369f8..cb0e050
--- a/target/msm8952/oem_panel.c
+++ b/target/msm8952/oem_panel.c
@@ -849,12 +849,19 @@
* Update all data structures after 'panel_init' label. Only panel
* selection is supposed to happen before that.
*/
+ if (platform_is_sdm439() || platform_is_sdm429()) {
+ phy_db->pll_type = DSI_PLL_TYPE_12NM;
+ pinfo->lane_config = mdss_dsi_lane_config;
+ goto end;
+ }
+
if (platform_is_msm8956())
memcpy(panel_regulator_settings,
dcdc_regulator_settings_hpm, REGULATOR_SIZE);
else
memcpy(panel_regulator_settings,
dcdc_regulator_settings_lpm, REGULATOR_SIZE);
+end:
pinfo->pipe_type = MDSS_MDP_PIPE_TYPE_RGB;
return init_panel_data(panelstruct, pinfo, phy_db);
}
diff --git a/target/msm8952/regulator.c b/target/msm8952/regulator.c
index 74b6fe0..ee08d30 100644
--- a/target/msm8952/regulator.c
+++ b/target/msm8952/regulator.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -68,6 +68,22 @@
},
};
+static uint32_t ldo5[][11] = {
+ {
+ LDOA_RES_TYPE, 5,
+ KEY_SOFTWARE_ENABLE, 4, GENERIC_DISABLE,
+ KEY_MICRO_VOLT, 4, 0,
+ KEY_CURRENT, 4, 0,
+ },
+
+ {
+ LDOA_RES_TYPE, 5,
+ KEY_SOFTWARE_ENABLE, 4, GENERIC_ENABLE,
+ KEY_MICRO_VOLT, 4, 1800000,
+ KEY_CURRENT, 4, 150,
+ },
+};
+
static uint32_t ldo6[][11]=
{
{
@@ -105,14 +121,15 @@
void regulator_enable(uint32_t enable)
{
- if(platform_is_msm8956())
- {
+ if (platform_is_msm8956()) {
if (enable & REG_LDO1)
rpm_send_data(&ldo1[GENERIC_ENABLE][0], 36, RPM_REQUEST_TYPE);
- }
- else
- {
+ } else if (platform_is_sdm439() || platform_is_sdm429()) {
+ if (enable & REG_LDO5)
+ rpm_send_data(&ldo5[GENERIC_ENABLE][0],
+ 36, RPM_REQUEST_TYPE);
+ } else {
if (enable & REG_LDO2)
rpm_send_data(&ldo2[GENERIC_ENABLE][0], 36, RPM_REQUEST_TYPE);
}
@@ -126,14 +143,15 @@
void regulator_disable(uint32_t enable)
{
- if(platform_is_msm8956())
- {
+ if (platform_is_msm8956()) {
if (enable & REG_LDO1)
rpm_send_data(&ldo1[GENERIC_DISABLE][0], 36, RPM_REQUEST_TYPE);
- }
- else
- {
+ } else if (platform_is_sdm439() || platform_is_sdm429()) {
+ if (enable & REG_LDO5)
+ rpm_send_data(&ldo5[GENERIC_DISABLE][0],
+ 36, RPM_REQUEST_TYPE);
+ } else {
if (enable & REG_LDO2)
rpm_send_data(&ldo2[GENERIC_DISABLE][0], 36, RPM_REQUEST_TYPE);
}
diff --git a/target/msm8952/target_display.c b/target/msm8952/target_display.c
index e98b21d..bed0f4d 100644
--- a/target/msm8952/target_display.c
+++ b/target/msm8952/target_display.c
@@ -82,6 +82,10 @@
"msmgpio", 107, 3, 1, 0, 1
};
+static struct gpio_pin bkl_en_gpio = {
+"pm8953", 4, 3, 1, 0, 1
+};
+
#define VCO_DELAY_USEC 1000
#define GPIO_STATE_LOW 0
#define GPIO_STATE_HIGH 2
@@ -91,7 +95,9 @@
#define DSI0_BASE_ADJUST -0x4000
#define DSI0_PHY_BASE_ADJUST -0x4100
#define DSI0_PHY_PLL_BASE_ADJUST -0x3900
+#define DSI0_12NM_PHY_PLL_BASE_ADJUST -0x3F00
#define DSI0_PHY_REGULATOR_BASE_ADJUST -0x3C00
+#define DSI1_12NM_PHY_PLL_BASE_ADJUST -0x600
static void mdss_dsi_uniphy_pll_sw_reset_8952(uint32_t pll_base)
{
@@ -369,10 +375,25 @@
gcc_dsi_lp_clock_enable(flags);
- ret = mdss_dsi_pll_config(pinfo->mipi.pll_base,
- pinfo->mipi.ctl_base, pll_data);
- if (!ret)
- dprintf(CRITICAL, "Not able to enable master pll\n");
+ if (platform_is_sdm439() || platform_is_sdm429()) {
+ mdss_dsi_auto_pll_12nm_config(pinfo);
+
+ /*
+ * enable clock/data lane in DSI controller
+ * before enabling DSI PLL for 12nm PHY
+ */
+ if (pinfo->lane_config)
+ pinfo->lane_config(pinfo);
+
+ ret = mdss_dsi_auto_pll_12nm_enable(pinfo);
+ if (!ret)
+ dprintf(CRITICAL, "unable to ON 12nm PLL\n");
+ } else {
+ ret = mdss_dsi_pll_config(pinfo->mipi.pll_base,
+ pinfo->mipi.ctl_base, pll_data);
+ if (!ret)
+ dprintf(CRITICAL, "unable to ON master pll\n");
+ }
if (platform_is_msm8956() && pinfo->mipi.dual_dsi &&
!platform_is_msm8976_v_1_1()) {
@@ -412,6 +433,8 @@
reset_gpio.pin_id = 60;
bkl_gpio.pin_id = 98;
pinfo->mipi.use_enable_gpio = 0;
+ } else if (platform_is_sdm439() || platform_is_sdm429()) {
+ reset_gpio.pin_id = 60;
} else if ((hw_id == HW_PLATFORM_QRD) &&
(hw_subtype == HW_PLATFORM_SUBTYPE_POLARIS)) {
enable_gpio.pin_id = 19;
@@ -427,11 +450,28 @@
gpio_set_dir(enable_gpio.pin_id, 2);
}
- gpio_tlmm_config(bkl_gpio.pin_id, 0,
+ if (platform_is_sdm439() || platform_is_sdm429()) {
+ /* enable PM GPIO-4 for backlight enable */
+ struct pm8x41_gpio gpio_param = {
+ .direction = PM_GPIO_DIR_OUT,
+ .function = PM_GPIO_FUNC_HIGH,
+ .vin_sel = 0, /* VIN_0 */
+ .pull = PM_GPIO_NO_PULL,
+ .output_buffer = PM_GPIO_OUT_CMOS,
+ .out_strength = PM_GPIO_OUT_DRIVE_HIGH,
+ };
+
+ dprintf(SPEW, "%s: gpio=%d enable=%d\n", __func__,
+ bkl_en_gpio.pin_id, enable);
+
+ pm8x41_gpio_config(bkl_en_gpio.pin_id, &gpio_param);
+ } else {
+ gpio_tlmm_config(bkl_gpio.pin_id, 0,
bkl_gpio.pin_direction, bkl_gpio.pin_pull,
bkl_gpio.pin_strength, bkl_gpio.pin_state);
- gpio_set_dir(bkl_gpio.pin_id, 2);
+ gpio_set_dir(bkl_gpio.pin_id, 2);
+ }
gpio_tlmm_config(reset_gpio.pin_id, 0,
reset_gpio.pin_direction, reset_gpio.pin_pull,
@@ -556,7 +596,16 @@
int target_display_get_base_offset(uint32_t base)
{
- if(platform_is_msm8956() || platform_is_msm8937() ||
+ if (platform_is_sdm439() || platform_is_sdm429()) {
+ if (base == MIPI_DSI0_BASE)
+ return DSI0_BASE_ADJUST;
+ else if (base == DSI0_PHY_BASE)
+ return DSI0_PHY_BASE_ADJUST;
+ else if (base == DSI0_PLL_BASE)
+ return DSI0_12NM_PHY_PLL_BASE_ADJUST;
+ else if (base == DSI1_PLL_BASE)
+ return DSI1_12NM_PHY_PLL_BASE_ADJUST;
+ } else if (platform_is_msm8956() || platform_is_msm8937() ||
platform_is_msm8917()) {
if (base == MIPI_DSI0_BASE)
return DSI0_BASE_ADJUST;
@@ -578,6 +627,8 @@
if (platform_is_msm8956())
ldo_num |= REG_LDO1;
+ else if (platform_is_sdm439() || platform_is_sdm429())
+ ldo_num |= REG_LDO5; /* LDO23 is enable by default */
else
ldo_num |= REG_LDO2;
@@ -602,7 +653,7 @@
}
} else {
/*
- * LDO1, LDO2 and LDO6 are shared with other subsystems.
+ * LDO1, LDO2, LDO5 and LDO6 are shared with other subsystems.
* Do not disable them.
*/
regulator_disable(REG_LDO17);